UCC28781QRTWRQ1 [TI]
具有集成 SR 控制的汽车类高密度零电压开关 (ZVS) 反激式控制器 | RTW | 24 | -40 to 125;型号: | UCC28781QRTWRQ1 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有集成 SR 控制的汽车类高密度零电压开关 (ZVS) 反激式控制器 | RTW | 24 | -40 to 125 开关 控制器 |
文件: | 总82页 (文件大小:5322K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
UCC28781-Q1
ZHCSNG6 –NOVEMBER 2021
UCC28781-Q1 具有专用同步整流器栅极驱动
的零电压开关反激式控制器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准:
UCC28781-Q1 是一款零电压开关 (ZVS) 控制器,可
用于超高开关频率,从而充分减小变压器尺寸并实现高
功率密度。
– 温度等级1,TA:–40°C 至125°C
– 器件HBM ESD 分类等级2
– 器件CDM ESD 分类等级C2A
• 提供功能安全
该控制器采用直接同步整流器 (SR) 控制,可直接驱动
SR FET,充分提高效率并简化设计,因此无需独立
SR 控制器。(隔离式应用需要隔离式栅极驱动器
IC。)
– 可帮助进行功能安全系统设计的文档
• 开关频率:> 500 kHz
• 实现超过93% 的峰值效率
ZVS 采用自适应死区时间控制,可有效降低开关损耗
和 EMI。该设计使控制器在整个工作范围内具有极高
转换效率。
• 实现小于50mW 的待机功耗(基本系统)
• 零电压开关(ZVS) 自适应控制和死区时间优化
• EMI 频率抖动,无需权衡瞬态响应或可闻噪声
• 具有内部补偿的可编程自适应突发模式(ABM)
• 过热、过压、输出短路、过流、过功率和引脚故障
保护
可编程自适应突发模式 (ABM) 可灵活控制控制器进入
和退出待机模式的时机,从而降低轻负载和空载待机功
耗。ABM 还有助于减少纹波并有效降低可闻噪声。
• 自动恢复故障响应
• 4 mm × 4 mm 24 引脚QFN 封装
该控制器提供多种具有自动重启(重试)响应功能的保
护模式。
2 应用
器件信息
封装(1)
• 牵引逆变器
• 辅助偏置电源
• 便携式直流充电器
• 直流或交流充电(桩)站
• 直流/直流转换器
器件型号
封装尺寸
UCC28781-Q1
WQFN (24)
4.00mm × 4.00mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
CX
~
~
Isolated driver
(primary side)
VOUT
–
+
Isolated driver
(secondary side)
P13
P13
PGND
SWS
P13
VS
AGND
FB
XCD
REF
CC/CV
controller
T
简化版应用
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLUSEI6
UCC28781-Q1
ZHCSNG6 –NOVEMBER 2021
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes..........................................35
8 Application and Implementation..................................56
8.1 Application Information............................................. 56
8.2 Typical Application Circuit.........................................56
9 Power Supply Recommendations................................66
10 Layout...........................................................................67
10.1 Layout Guidelines................................................... 67
10.2 Layout Example...................................................... 70
11 Device and Documentation Support..........................75
11.1 Documentation Support.......................................... 75
11.2 支持资源..................................................................75
11.3 Trademarks............................................................. 75
11.4 Electrostatic Discharge Caution..............................75
11.5 术语表..................................................................... 75
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................7
6.4 Thermal Information....................................................7
6.5 Electrical Characteristics.............................................7
6.6 Typical Characteristics..............................................12
7 Detailed Description......................................................15
7.1 Overview...................................................................15
7.2 Functional Block Diagram.........................................17
7.3 Detailed Pin Description............................................18
Information.................................................................... 76
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
November 2021
*
Initial release.
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5 Pin Configuration and Functions
24
23
22
21
20
19
FLT
RTZ
RDM
IPC
1
2
3
4
5
6
18
17
16
15
14
13
XCD
XCD
SWS
PWMH
P13
Thermal
Pad
BUR
FB
S13
7
8
9
10 11 12
图5-1. RTW Package, 24-Pin WQFN (Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
The controller enters into the fault state if the FLT-pin voltage is pulled above 4.5 V or below 0.5 V. A
50-µA current source interfaces directly with an external NTC (negative temperature coefficient)
thermistor to AGND pin for remote temperature sensing. The current source is active during the run
state and inactive during the wait state. A 50-µs fault delay allows a filter capacitor to be placed on the
FLT pin without false triggering the 0.5-V OTP fault when the controller enters into a run state from a
wait state. Alternatively, a high-resistance voltage divider can be used to sense the bulk input
capacitor voltage for line-OVP detection, and a 750-µs fault delay helps to prevent false triggering the
4.5-V input line-OVP from a short-duration bulk capacitor voltage overshoot during line surge and
ESD strike events. When FLT-pin voltage is used for line-OVP detection, the external OTP can be
implemented on CS pin.
FLT
1
I
A resistor between this pin and AGND pin programs an adaptive delay for transition to zero voltage
from the turn-off edge of the PWMH signal to the turn-on edge of the PWML signal. Parasitic
capacitance between this pin and any other net, including AGND, must be minimized to avoid noise
coupling and its effect on the dead-time calculation.
RTZ
2
3
I
I
A resistor between this pin and AGND pin programs a synthesized demagnetization time used to
control the on-time of the PWMH signal to achieve zero voltage switching on the primary switch. The
controller applies a voltage on this pin that varies with the output voltage derived from the VS pin
signal. Parasitic capacitance between this pin and any other net, including AGND, must be minimized
to avoid noise coupling and its effect on the internal PWMH on-time calculation.
RDM
This pin is an intelligent power control (IPC) pin to optimize the converter efficiency. A 50-µA current
source directly interfaces with a resistor (RIPC) to AGND pin to program an increase in the peak
current level at very light load; the burst frequency can be further reduced, helping to achieve low
standby power and tiny-load power. If the IPC pin is connected to AGND without RIPC, the peak
current level in very light load is set to a minimum level for the output ripple or audible noise sensitive
designs. RIPC can also be connected between this pin and the CS pin or IPC pin can be directly
connected to CS pin, so the 50-µA IPC current can create an output voltage dependent offset voltage
on the CS pin for reducing output ripple in adaptive burst mode and improving light-load efficiency at
lower output voltage level of a wide output voltage range design.
IPC
4
I
This pin is used to program the burst threshold of the converter at light load. A resistor divider
between REF and AGND is used to set a voltage at BUR to determine the peak current level when
the converter enters adaptive burst mode (ABM). In addition, the Thevenin resistance on BUR is used
to activate offset voltages for smooth mode transitions. A 2.7-µA pull up current increases the peak
current threshold when the converter enters low-power mode (LPM) from ABM. A 5-µA pull down
current reduces the peak current threshold when the converter enters into high-power mode (adaptive
amplitude modulation, AAM) from ABM.
BUR
5
I
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表5-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
A current signal is coupled to this pin to close the converter regulation feedback loop. This pin
presents a 4.25-V output that is designed to have 0-µA to 75-µA current pulled out of the pin
corresponding to the converter operating from full-power to zero-power conditions. A 220-pF filter
capacitor between FB pin and REF pin is recommended to desensitize the feedback signal from noise
interference.
FB
6
I
This pin is a 5-V reference output that requires a 0.22-µF ceramic bypass capacitor to the AGND pin.
This reference is used to power internal circuits and can supply a limited external load current. Pulling
this pin low shuts down PWM action and initiates a VDD restart.
REF
7
8
O
G
Analog ground and the ground return of PWMH and RUN drivers. Return all analog control signals to
this ground.
AGND
This is the current-sense input pin. This pin couples to the current-sense resistor through a line-
compensation resistor to control the peak primary current in each switching cycle. An internal current
source on this pin, proportional to the converter’s input voltage, creates an offset voltage across the
line-compensation resistor to balance the over-power protection (OPP) threshold level across input
line. The CS pin can also provide an alternative OTP function, when the FLT pin is being used for the
line input-OVP. A small-signal diode in series with an NTC resistor is connected between PWMH pin
and CS pin to form the OTP detection. When PWMH is high, the NTC resistor and the line-
compensation resistor become a resistor divider from 5 V and creates a temperature dependent
voltage on CS pin. When CS pin voltage is higher than 1.2 V in PWMH on state for 2 consecutive
cycles, the OTP fault on CS pin is triggered.
CS
9
I
This output pin is high when the controller is in the run state. This output is low during start-up, wait,
and fault states. A 2.2-µs timer delays the initiation of PWML switching after this pin has gone high
and S13-pin voltage is above its 10-V power-good threshold. The pull-up driving capability of both
RUN and PWMH pins allows bias power management of a digital isolator through a common-cathode
small-signal diode, so the power consumption can be reduced in the wait state.
RUN
10
11
O
G
Low-side ground return of the PWML driver to the primary switch. The internal level shifter allows the
common return impedance to be eliminated and improves higher frequency operation by decoupling
the additional voltage spike on the current-sense resistor and layout parasitic inductance of the gate
driving loop. For a silicon (Si) power FET, this pin can be connected to the source for a smaller gate
driving loop. For a GaN power IC with a logic PWM input, this pin can be connected to AGND.
PGND
For a GaN-based gate-injection transistor (GIT), this pin can be directly connected to the separate
source pin of a GIT GaN device, which enhances the turn-off speed.
Primary switch gate driver output. The high-current capability (-0.5A/+1.9A) of PWML enables driving
of a silicon power MOSFET with higher capacitive loading, a GIT GaN with continuous on-state
current, or a GaN power IC with logic input. The maximum voltage level of PWML is clamped to the
P13 pin voltage.
PWML
S13
12
13
O
O
S13 is a switched bias-voltage source coupled to P13 through an internal 2.8-Ω switch controlled by
the RUN pin. When RUN is high, the S13 decoupling capacitor is charged up to 13 V by an internal
current limiter. The S13 pin voltage must increase above 10 V to initiate PWML switching. When RUN
is low, S13 is discharged by its load. The power-on delay of any device powered by S13 must be less
than 2 µs to be responsive to PWML. A 22-nF ceramic capacitor between S13 and the driver ground
is recommended. S13 can also perform power management on a PFC controller at the same time
through a diode, such that PFC can be disabled at very light-load condition.
P13 is a regulated 13-V bias-voltage source derived from VVDD. During VVDD startup, P13 pin is
connected to the VDD pin internally, so an external high-voltage depletion MOSFET, such as BSS126,
can provide controlled startup current to charge the VDD capacitor. After the initial startup, P13
recovers back to 13-V regulation. A 1-µF ceramic bypass capacitor is required from P13 to AGND. A
20-V Zener diode between P13 and AGND is recommended to protect this pin from overstress, such
as if the connection between this pin and the depletion MOSFET gate is fail-open or if line surge
energy is coupled to this pin.
P13
14
15
O
O
PWM output signal used to control the gate of a secondary-side synchronous rectifier (SR) MOSFET
through an external isolating gate driver. The driving capability is designed to bias a level-shifting
isolator through a small-signal diode, or can also transmit the signal to secondary-side driving circuitry
through a pulse transformer. The maximum voltage level of PWMH is clamped to REF.
PWMH
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表5-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
This sensing input is used to monitor the switch-node voltage as it nears zero volts in normal
operation for ZVS auto-tuning. The source of a high-voltage depletion-mode MOSFET, such as
BSS126, is coupled to this pin through a current-limiting resistor so only the useful switching
characteristic below 15 V is monitored. During start-up, this pin is connected to the VDD pin internally
to allow the depletion-mode MOSFET to provide start-up current. The external current-limit resistor
and a small bidirectional TVS across gate and source should be added to protect the VGS from
potential abnormal voltage stress. The resistor should be higher than 500 Ω and less than 820 Ω. The
clamping voltage of TVS should be less than the MOSFET voltage rating but greater than 15 V.
Moreover, the resistor and a 22-pF ceramic capacitor between the SWS pin and the bulk input
capacitor ground form a small sensing delay to help the internal detection circuit to identify the ZVS
characteristic correctly.
SWS
16
I
X-cap Discharge input pins with 2-mA maximum discharge current capability. A line zero-crossing
(LZC) threshold of 6.5 V on XCD is used to detect AC-line presence. When LZC is not detected within
an 84-ms test period, the discharge current is enabled for a maximum period of 300 ms followed by a
no-current blanking time of 700 ms. When AC-line recovers and LZC is detected again, the controller
can reset the fault state almost immediately and will attempt to restart without waiting to fully
discharge the bulk input capacitor. For the auto-recovery fault protections, if the controller is in 1.5-s
auto-recovery fault state, LZC can reset the timer and speed up the restart attempt. The two
redundant XCD pins help to provide the X-cap discharge function even when one pin is in fail-open
condition. To form the discharge path, an anode of two high-voltage diode rectifiers is connected to
each X-cap terminal, the two diode cathodes are connected together to a 26-kΩ high-voltage current-
limiting resistance, and the drain-to-source connection of a high-voltage depletion MOSFET couples
the resistance to the XCD pins. Two series 13-kΩ SMD resistors in 1206 size can be used as the
current limiting device, and share the potential transient voltage from the AC-line. A 600-V rated
MOSFET such as BSS126 is needed as the high voltage blocking device. The MOSFET gate is
connected to the P13 pin, so the XCD pins can obtain enough signal headroom for LZC detection. If
the X-cap discharge function is not needed, XCD pins must be connected to AGND pin to disable the
function, and the diode-resistor-MOSFET path must be removed.
XCD
17, 18
I
Controller bias power input. A ceramic capacitor with 10-µF or 15-µF capacitance is recommended,
and the minimum voltage rating is 25 V.
VDD
19
P
GTP1
GTP2
GTP3
20
21
22
G
G
G
Ground This Pin. This pin must be connected to AGND for proper operation of the device.
Ground This Pin. This pin must be connected to AGND for proper operation of the device.
Ground This Pin. This pin must be connected to AGND for proper operation of the device.
This voltage-sensing input pin is coupled to an auxiliary winding of the converter’s transformer via a
resistor divider. The pin and associated external resistors are used to monitor the output and input
voltages and switching edges of the converter at different moments within each switching cycle.
Parasitic capacitance between VS and any net, including AGND, must be minimized to avoid adverse
effects on output voltage sensing, edge detection, and the dead-time calculation.
VS
23
24
I
This pin is used to configure the controller to be optimized for gallium nitride (GaN) power FETs or
silicon (Si) power FETs on the primary side. Depending on the setting, it will optimize parameters of
the ZVS control loop, dead-time adjustment, and protection features. When pulled high to REF pin, it
is optimized for Si FETs. When pulled low to AGND, it is optimized for GaN FETs.
SET
I
Thermal
Pad
G
The thermal pad (TP) must be connected to AGND.
(1) I = input, O = output, I/O = input or output, FB = feedback, G = ground, P = power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
38
UNIT
VDD
SWS
38
–6
SWS (transient, negative pulse width of 20 ns max., duty cycle ≤
1%)
38
–10
VDD-SWS
38
3.6
7
–20
–0.3
–0.75
–1
CS
Input Voltage
VS
V
VS (transient, 100 ns max.)
PGND
7
4
–1
PGND (transient, 25 ns max.)
RTZ, BUR, SET, RDM, IPC, FLT, FB
XCD
5
7
–0.3
–0.3
–0.3
–0.3
30
7
REF, PWMH, RUN
Output Voltage
V
P13, S13, PWML
20
REF, P13, RTZ, RDM, IPC
S13 (average)
Self–limiting
15
VS
2
VS (transient, 100 ns max.)
2.5
Source Current
mA
FB
1
RUN (continuous)
PWML (continuous)
PWMH (continuous)
CS (transient, 30 ns max.)
RUN (continuous)
PWML (continuous)
PWMH (continuous)
SWS
5
50
10
1
8
50
10
Sink Current
mA
Self–limiting
XCD
25
0.3
FLT
Operating junction temperature, TJ
Storage temperature, Tstg
150
150
°C
°C
–40
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per AEC
Q100-011
±500
(1) AEC Q100-002 indicates that HBM stressing must be in accordance with the ANSI/ESDA/JEDC JS-001 specification.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
14
NOM
MAX
UNIT
V
VVDD
CVDD
CP13
CREF
TJ
Bias supply operating voltage
VDD capacitor
34
10
µF
µF
µF
°C
P13 bypass capacitor
1
REF bypass capacitor
Operating junction temperature
0.22
–40
140
6.4 Thermal Information
UCC28781-Q1
RTW (WQFN)
24 PINS
43.1
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
31.6
RθJB
ΨJT
Junction-to-board thermal resistance
20.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.5
20.3
ΨJB
RθJC(bot) Junction-to-case (bottom) thermal resistance
5.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Unless otherwise stated: VVDD = 20 V, RRDM = 115 kΩ, RRTZ = 140 kΩ, VBUR = 1.2 V, VSET = 0 V, RNTC = 50 kΩ, VVS = 4 V,
VSWS = 0 V, IFB = 0 μA, CPWML = 0 pF, CPWMH = 0 pF, CREF = 0.22 µF, CP13 = 1 µF, and -40⁰C < TJ = TA < 125⁰C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VDD INPUT
IRUN(STOP)
IRUN(SW)
IWAIT
Supply current, run state
Supply current, run state
Supply current, wait state
Supply current, start state
Supply current, fault state
No switching
0.88
2.45
465
150
2.2
3
2.66
3.55
658
301
630
mA
mA
µA
µA
µA
Switching, IVSL = 0 µA
IFB = -85 µA, IVDD only
VVDD = VVDD(ON) - 100 mV, VVS = 0 V
fault state
540
235
500
ISTART
IFAULT
VVDD increasing, VSWS - VVDD = 1 V,
VVDD = 16.5 V
IVDD(LIMIT)
VDD startup current limit during startup
1.2
2
2.53
mA
VVDD(ON)
VVDD(OFF)
VDD turnon threshold
VDD turnoff threshold
VVDD increasing
VVDD decreasing
16.2
9.94
17 17.91
V
V
10.6
11.17
2.98
Offset to power cycle for long output voltage
overshoot
VVDD(PCT)
P13 OUTPUT
VP13
Offset above VVDD(OFF), IFB = -85 µA
1.54
2.2
V
0 mA to 60 mA out of P13, run state,
VVDD = 20 V
P13 voltage level including load regulation
12.0
12.8
13.6
V
IP13(START)
IP13(MAX)
Max sink current of P13 pin during startup
Current sourcing limit of P13 pin
Line regulation of VP13
VP13 = 14 V
1.53
103.3
-6
2.2
133
2
3.04
160
8.7
mA
mA
mV
V
P13 shorted to AGND, VVDD = 20 V
VVDD = 15 V to 35 V
VR13(LINE)
VP13(OV)
Over voltage fault threshold above VP13
1.35
2
2.54
Dropout resistance of P13 regulator switch (VVDD - VP13) / 30 mA, VVDD = 11 V, 30
RP13
8.5
13
22.7
Ω
between VDD and P13 pins
mA out of P13
S13 OUTPUT
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Unless otherwise stated: VVDD = 20 V, RRDM = 115 kΩ, RRTZ = 140 kΩ, VBUR = 1.2 V, VSET = 0 V, RNTC = 50 kΩ, VVS = 4 V,
VSWS = 0 V, IFB = 0 μA, CPWML = 0 pF, CPWMH = 0 pF, CREF = 0.22 µF, CP13 = 1 µF, and -40⁰C < TJ = TA < 125⁰C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
RDS(on) of internal disconnect switch
between P13 and S13 pins
(VP13 - VS13) / 30 mA, VVDD = 11 V, 30
mA out of S13
RS13
2.1
2.8
3.82
10.7
Ω
VS13_OK
S13_OK threshold to enable switching
Current sourcing limit of S13 pin
VRUN = 5 V
9.63
10.2
V
IS13(MAX)
REF OUTPUT
VREF
S13 shorted to AGND, VVDD = 20 V
260.7
350 452.5
mA
REF voltage level
IREF = 0 A
4.9
14.3
-7
5
17
-3
5.13
20.3
1
V
IREF(MAX)
VR5(LINE)
Current sourcing limit of REF pin
Line regulation of VREF
REF shorted to AGND, VVDD = 20 V
VVDD = 12 V to 35 V
mA
mV
0 mA to 1 mA out of REF, Change in
VREF
VR5(LOAD)
Load regulation of VREF
-16
0.1
25
mV
VS INPUT
VVSNC
Negative clamp level
IVSL = -1.25 mA, voltage below ground
VVS decreasing
221
12.4
287
35
0
344
67.2
0.31
mV
mV
µA
VZCD
Zero-crossing detection (ZCD) level
Input bias current
IVSB
VVS = 4 V
-0.23
242.4
458.3
VVS(SM1)
VVS(SM2)
VS threshold voltage in SM1 startup mode
VS threshold voltage in SM2 startup mode
282 318.3
mV
mV
500
543
2.6
VS upper threshold out of low output voltage
mode (LV mode)
VVSLV(UP)
VVS increasing
VVS decreasing
2.41
2.49
V
VS lower threshold into low output voltage
mode (LV mode)
VVSLV(LR)
tZC
2.3
1.95
23
2.39
2.3
50
2.49
2.73
81
V
Zero-crossing timeout delay
µs
ns
Propagation delay from ZCD high to PWML
10% high
tD(ZCD)
VVS step from 4 V to -0.1 V
CS INPUT
767.4
650
801 836.4
727 788.7
600 651.8
mV
mV
mV
mV
mV
mV
mV
mV
IVSL = 0 μA, VVS ≥VVSLV(UP)
IVSL = -333 μA, VVS ≥VVSLV(UP)
IVSL = -666 μA, VVS ≥VVSLV(UP)
IVSL = -1.25 mA, VVS ≥VVSLV(UP)
IVSL = 0 mA, VVS ≤VVSLV(LR)
IVSL = -666 μA, VVS ≤VVSLV(LR)
IVSL = -1.25 mA, VVS ≤VVSLV(LR)
VCS increasing, IFB = -85 µA
Peak-power threshold on CS pin out of LV
mode
VCST(MAX)
570
537.2
593.7
540
570
612
628 663.9
570 609.5
540 584.7
153 200.1
VCST(MAX)_LV Peak-power threshold on CS pin in LV mode
511.2
120.7
VCST(MIN)
KLC
Minimum CS threshold voltage
Line-compensation current ratio
IVSL = -1.25 mA, IVSL / current out of CS
pin
21.6
78.4
29.3
25
96
36
29
113.6
42.7
A/A
mV
mV
(VBUR / KBUR-CST) < VCST < VCST(MAX)
IVSL > -646 μA, VVS ≥VVSLV(UP)
,
EMI dithering magnitude on CS pin out of LV
mode
(1)
VCST(EMI)
(VBUR / KBUR-CST) < VCST < VCST(MAX)
IVSL > -646 μA, VVS ≤VVSLV(LR)
,
VCST(EMI)_LV EMI dithering magnitude on CS pin in LV
(1)
mode
VCST(SM1)
VCST(SM2)
CS threshold voltage in SM1 startup mode
CS threshold voltage in SM2 startup mode
VVS < VVS(SM1)
177.5
470.4
171.2
94.4
200 222.9
500 531.4
190 216.1
mV
mV
ns
VVS < VVS(SM2)
VSET = 5 V, VCS = 1 V
VSET = 0 V, VCS = 1 V
tCSLEB
Leading-edge-blanking time
108
26
125
37
ns
Propagation delay of CS comparator high to
PWML 90 % low
tD(CS)
VCS step from 0 V to 1 V
10
20
ns
(VBUR / KBUR-CST) < VCST < VCST(OPP)
IVSL > -646 μA
,
(1)
fDITHER
EMI dithering frequency on CS pin
23
27
kHz
BUR INPUT and Low-power MODE
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Unless otherwise stated: VVDD = 20 V, RRDM = 115 kΩ, RRTZ = 140 kΩ, VBUR = 1.2 V, VSET = 0 V, RNTC = 50 kΩ, VVS = 4 V,
VSWS = 0 V, IFB = 0 μA, CPWML = 0 pF, CPWMH = 0 pF, CREF = 0.22 µF, CP13 = 1 µF, and -40⁰C < TJ = TA < 125⁰C
PARAMETER
TEST CONDITIONS
MIN
3.82
2.09
3.76
TYP
3.98
2.65
4.85
MAX UNIT
KBUR-CST
IBUR(LPM)
IBUR(AAM)
Ratio of VBUR to VCST
VBUR between 0.7 V and 2.4 V
4.09
3.16
5.81
V/V
µA
µA
Bias source current of VBUR offset in LPM
Bias sink current of VBUR offset in AAM
VCST > VBUR / KBUR-CST
First upper threshold of burst frequency in
ABM
fBUR(UP1)
fBUR(UP2)
30.7
41.8
34.4
51.2
38.5
58.9
kHz
kHz
Second upper threshold of burst frequency
in ABM
VVS = 2.2 V
fBUR(LR)
fLPM
Lower threshold of burst frequency in ABM
Burst frequency in low-power mode
21.3
23.3
24.5
25
28.1
26.9
kHz
kHz
IPC INPUT and SBP2 MODE
Highest programmable VCST range of SBP2
VCST_IPC(UP)
KIPC
VCST_IPC(LR)
VCST_IPC(MIN)
VIPC = 5 V
373.8
59.3
405 438.5
64
mV
by IPC pin
Ratio of the programmable IPC voltage to
VCST
VIPC between 1.8 V and 3.8 V
VIPC = 1 V
68.4 mV/V
Lowest programmable VCST range of SBP2
by IPC pin
247.5
128.1
273 307.7
154 191.5
mV
mV
Minimum VCST of SBP2 by grounding IPC
pin
VIPC = 0 V
IIPC(SBP2)
fSBP2(UP)
fSBP2(LR)
RUN
Bias source current of VIPC offset in SBP2
Upper threshold of burst frequency in SBP2
IFB = -85 µA
40.7
6
49
8.5
1.7
55.7
13.4
2
µA
kHz
kHz
Lower threshold of burst frequency in SBP2 VIPC = 2 V
1
VRUNH
RUN pin high-level
RUN pin low-level
IRUN = -0.2 mA
4.6
0.1
4.78
0.25
5
V
V
VRUNL
IRUN = 1 mA
0.3
VRUN = 2.3 V
VRUN = 3 V
33
14
44
20
52
25
mA
mA
ISRC(RUN)
RUN peak source current
Turn-on rise time of RUN pin, from 0 V to
2.5 V
tR(RUN)
CLOAD = 22 nF, VRUN from 0 V to 2.5 V
0.2
0.79
20
1
µs
ns
tF(RUN)
Turn-off fall time of RUN pin, 90 % to 10 % CLOAD = 10 pF
32
PWML
VPWMLH
VPWMLL
PWML pin high-level
IPWML = -1 mA
IPWML = 1 mA
VPWML = 0 V
12.1 12.85
0.002
13.6
0.1
0.8
2.8
6.1
1.9
V
V
PWML pin low-level
(1)
ISRC(PWML)
PWML peak source current
PWML peak sink current
PWML pull-up resistance
PWML pull-down resistance
0.25
1.2
3.1
0.5
0.5
1.9
4.3
1.1
A
(1)
ISNK(PWML)
VPWML = 13 V
IPWML = -20 mA
IPWML = 20 mA
A
RSRC(PWML)
RSNK(PWML)
Ω
Ω
Turn-on rise time of PWML pin, 10 % to 90
%
tR(PWML)
CLOAD = 1.5 nF
30
53
ns
tF(PWML)
Turn-off fall time of PWML pin, 90 % to 10 % CLOAD = 1.5 nF
9
4.7
20
7.43
180
ns
µs
tD(RUN-PWML) Delay from RUN high to PWML high
VS13 > 11 V
1.92
68
tON(MIN)
Minimum on-time of PWML in LPM
VSET = 5 V, IFB = -85 µA, VCS = 1 V
105
ns
PWMH
VPWMHH
VPWMHL
PWMH pin high-level
PWMH pin low-level
IPWMH = -1 mA
IPWMH = 1 mA
4.39
4.66
4.83
0.21
V
V
0.1 0.198
VPWMH = 2.5 V
VPWMH = 3.5 V
16.5
3.8
21
6
26.2
7.6
mA
mA
ISRC(PWMH)
PWMH peak source current
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Unless otherwise stated: VVDD = 20 V, RRDM = 115 kΩ, RRTZ = 140 kΩ, VBUR = 1.2 V, VSET = 0 V, RNTC = 50 kΩ, VVS = 4 V,
VSWS = 0 V, IFB = 0 μA, CPWML = 0 pF, CPWMH = 0 pF, CREF = 0.22 µF, CP13 = 1 µF, and -40⁰C < TJ = TA < 125⁰C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Turn-on rise time of PWMH pin, 10 % to 90
%
tR(PWMH)
CLOAD = 10 pF
8
24
29
28
ns
ns
ns
Turn-off fall time of PWMH pin, 90 % to 10
%
tF(PWMH)
CLOAD = 10 pF
22
18
Dead time between VS high and PWMH 10
% high
tD(VS-PWMH)
10
PROTECTION
VOVP
Over-voltage threshold
Over-current threshold
VVS increasing
VCS increasing
4.4
4.55
1.22
4.67
1.27
V
V
VOCP
1.14
Ratio of over-power threshold to peak-power VCST(OPP) / VCST(MAX) , and VCST(OPP)_LV
/
KOPP-PPL
0.72
0.75
0.78
V/V
threshold
VCST(MAX)_LV
IVSL(RUN)
IVSL(STOP)
KVSL
VS line-sense run current
VS line-sense stop current
VS line sense ratio
Current out of VS pin increasing
Current out of VS pin decreasing
IVSL(STOP) / IVSL(RUN)
313
255
365 408.6
305 336.4
µA
µA
0.72 0.836
0.9
70
A/A
kΩ
°C
RRDM(TH)
RRDM threshold for CS pin fault
Thermal-shutdown temperature
OPP fault timer
35
125
130
28.8
55
162
164
55
(1)
TJ(STOP)
Internal junction temperature
IFB = 0 A
tOPP
tBO
210
ms
ms
Brown-out detection delay time
IVSL < IVSL(STOP)
85.2
Maximum PWML on-time for detecting CS
pin fault
tCSF1
VSET = 5 V
1.6
2.05
2.5
µs
Maximum PWML on-time for detecting CS
pin fault
tCSF0
tFDR
RRDM < RRDM(TH) for VSET = 0 V
0.85
1.2
1.05
1.5
1.27
2.4
µs
s
Fault reset delay timer
OCP, OPP, OVP, SCP or CS pin fault
FLT INPUT
VNTCTH
RNTCTH
RNTCR
NTC shut-down voltage
FLT voltage decreasing
RNTC decreasing
0.47
8.9
0.5
9.91
23
0.52
11.18
26.4
0.1
V
NTC shut-down resistance
NTC recovery resistance
kΩ
kΩ
µA
V
RNTC increasing
21.2
-0.1
4.3
IFLT
Input bias current for VFLT at VIOVPTH
Shut-down voltage of input OVP
Hysteresis of input OVP
VFLT = 4.5 V
0
VIOVPTH
VIOVPR
FLT voltage increasing
FLT voltage increasing
4.5
74
4.67
87
57.7
14
mV
tFLT(NTC)
Delay time of NTC fault
50
100
µs
tFLT(IOVP)
VFLTZ
Delay time of input OVP fault
Clamp voltage of FLT pin
555
750
5.5
917
µs
V
IFLT = 150 µA
5.08
5.61
RTZ INPUT
ratio of tZ at IVSL = -200 µA to tZ at IVSL
-733 µA
=
KTZ
tZ compensation ratio
1.27
397.8
56.1
1.41
1.54
s/s
ns
ns
Maximum programmable dead time from
PWMH low to PWML high
tZ(MAX)
tZ(MIN)
478 592.8
70 89.1
RRTZ = 280 kΩ, IVSL = -1 mA, VSET = 5 V
Minimum programmable dead time from
PWMH low to PWML high
RRTZ = 78.4 kΩ, IVSL = -1 mA, VSET = 0
V
IVSL = -200 µA
IVSL = -450 µA
IVSL = -733 µA
152.2
129.2
109.7
175 212.7
150 190
125 147.2
ns
ns
ns
tZ
Dead time from PWMH low to PWML high
SWS INPUT
VSET = 5 V
VSET = 0 V
8.1
3.7
8.5
4.04
17
9.1
4.4
26
V
V
VTH(SWS)
SWS zero voltage threshold
tD(SWS-PWML) Time between SWS low to PWML 10 % high VSWS step from 5 V to 0 V
11.4
ns
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Unless otherwise stated: VVDD = 20 V, RRDM = 115 kΩ, RRTZ = 140 kΩ, VBUR = 1.2 V, VSET = 0 V, RNTC = 50 kΩ, VVS = 4 V,
VSWS = 0 V, IFB = 0 μA, CPWML = 0 pF, CPWMH = 0 pF, CREF = 0.22 µF, CP13 = 1 µF, and -40⁰C < TJ = TA < 125⁰C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
FB INPUT
IFB(SBP)
Maximum control FB current
Regulated FB voltage level
IFB increasing
64.2
4.02
7.4
75
4.25
8.3
87.1
4.53
9.6
µA
V
VFB(REG)
RFBI
FB input resistance
kΩ
A/s
dICOMP/dt(1)
Slope of internal ramp compensation current
0.192 0.214 0.236
Magnitude of internal ramp compensation
current
ICOMP
4
6.75
8
µA
RDM INPUT
tDM(MAX)
Maximum PWMH width with maximum
tuning
VSWS = 12 V
6.0
3.0
6.95
3.43
7.53
3.77
µs
µs
tDM(MIN)
XCD INPUT
VXCD(LR)
VXCD(UP)
IXCD(0)
Minimum PWMH width with minimum tuning VSWS = 0 V
XCD lower zero-crossing threshold
XCD upper zero-crossing threshold
5.9
6.8
6.62
7.5
0.3
0.4
7.2
7.9
V
V
Leakage current in XCD wait state
First-step XCD sense current
Second-step XCD sense current
Third-step XCD sense current
Fourth-step XCD sense current
Maximum XCD discharge current
Clamp voltage of XCD OVP
Dwell time for each XCD sense step
Maximum XCD discharge time
XCD wait time
VXCD = 15 V
VXCD = 15 V
VXCD = 15 V
VXCD = 15 V
VXCD = 15 V
VXCD = 15 V
IXCD = 20 mA
1.7
µA
mA
mA
mA
mA
mA
V
IXCD(1)
0.32
0.46
0.91
1.6
IXCD(2)
0.61 0.775
IXCD(3)
0.73
1.2
1.15
1.53
2
IXCD(4)
1.81
2.5
IXCD(MAX)
VXCD(OVP)
tXCD(STEP)
tXCD(MAX)
tXCD(WAIT)
1.65
23
26
30
9
12
14.6
ms
ms
ms
230.4
300 373.3
700 1071
(1) Ensured by design, not tested in production
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6.6 Typical Characteristics
VVDD = 20 V, RRDM = 115 kΩ, RRTZ = 140 kΩ, VSET = 0 V, and TJ = TA = 25 ⁰C (unless otherwise noted)
10
10
IRUN
IWAIT
1
IRUN(STOP)
IFAULT
0.1
0.01
1
IRUN(WAIT)
ISTART
ISTART
0.1
0.001
0
5
10
15
20
25
30
35
40
45
-50
-25
0
25
50
75
100
125
VVDD - Bias Supply Voltage (V)
TJ - Çꢀu‰ꢀŒꢁšµŒꢀ ~ö/•
图6-1. VDD Bias-Supply Current vs. VDD Bias-
图6-2. VDD Bias-Supply Current vs. Temperature
Supply Voltage
415
395
4
3
(VCST(MIN) - 0.15 V) / 0.15 V
2
IVSL(RUN)
375
(VCST(MAX) - 0.8 V) / 0.8 V
1
355
0
-1
-2
-3
-4
335
IVSL(STOP)
315
295
275
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
TJ - Çꢀu‰ꢀŒꢁšµŒꢀ ~ö/•
TJ - Çꢀu‰ꢀŒꢁšµŒꢀ ~ö/•
图6-3. VS Line-Sense Currents vs. Temperature
图6-4. Percentage Variation of Maximum and
Minimum CS Thresholds vs. Temperature
0.9
0.9
0.8
VCST(MAX) at 25öC
0.8
0.7
0.6
0.5
VCST(MAX)_LV at 25öC
VCST(MAX)_LV at -40öC
VCST(MAX)_LV at 125öC
VCST(MAX) at -40öC
VCST(MAX) at 125öC
0.7
0.6
0.5
0
200
400
600
800
1000
1200
1400
1600
0
200
400
600
800
1000
1200
1400
1600
IVSL - VS Line-Sense Current (mA)
IVSL - VS Line-Sense Current (mA)
图6-5. CS Peak-Power Threshold for VVS
>
图6-6. CS Peak-Power Threshold for VVS
<
VVSLV(UP) vs. VS Line-Sense Currents
VVSLV(LR) vs. VS Line-Sense Currents
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1.5
1.4
1.3
1.2
1.1
1
4.6
4.56
4.52
4.48
4.44
4.4
KTZ at 25öC
KTZ at -40öC
KTZ at 125öC
0.9
0
200
400
600
800
1000
1200
1400
1600
IVSL - VS Line-Sense Current (JA)
-50
-25
0
25
50
75
100
125
TJ - Çꢀu‰ꢀŒꢁšµŒꢀ ~ö/•
图6-7. tZ Compensation Ratio (KTZ) vs. VS Line-
图6-8. VS Over-Voltage Threshold vs. Temperature
Sense Currents
5.06
5.04
5.02
5
13.1
13
12.9
12.8
12.7
12.6
12.5
4.98
4.96
4.94
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
TJ - Çꢀu‰ꢀŒꢁšµŒꢀ ~ö/•
TJ - Çꢀu‰ꢀŒꢁšµŒꢀ ~ö/•
图6-9. REF Voltage vs. Temperature
图6-10. P13 Voltage vs. Temperature
25
23
21
19
17
15
13
11
9
7.6
7.4
7.2
7
VXCD(UP)
RNTCR
6.8
6.6
6.4
RNTCTH
VXCD(LR)
7
5
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
TJ - Çꢀu‰ꢀŒꢁšµŒꢀ ~ö/•
TJ - Çꢀu‰ꢀŒꢁšµŒꢀ ~ö/•
图6-12. XCD Thresholds vs. Junction Temperature
图6-11. FLT OTP Thresholds vs. Junction
Temperature
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2.4
2.3
2.2
2.1
2
1.9
1.8
-50
-25
0
25
50
75
100
125
TJ - Çꢀu‰ꢀŒꢁšµŒꢀ ~ö/•
图6-13. Max. XCD Discharge Current vs. Junction Temperature
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7 Detailed Description
7.1 Overview
The UCC28781-Q1 is a transition-mode zero-voltage-switching flyback (ZVSF) controller equipped with
advanced control schemes to enable significant size reduction of passive components for higher power density
and higher average efficiency. Its control law is optimized for Silicon (Si) and Gallium Nitride (GaN) power FETs
in a single-switch flyback configuration at high frequencies. In burst mode at very light loads the switching
frequency may increase up to 1.5 MHz.
The ZVSF control of the UCC28781-Q1 is capable of auto-tuning the on-time of a secondary-side synchronous
rectifier switch (QSR) by using a unique lossless ZVS-sensing network connected between the switch-node
voltage (VSW) and the SWS pin. The ZVSF controller is designed to adaptively achieve targeted full-ZVS or
partial-ZVS conditions for the primary-side main switch (QL) with minimum circulating energy over wide operating
conditions. Auto-tuning eliminates the risk of losing ZVS due to component tolerance, temperature, and input/
output voltage variations, since the QSR on-time is corrected cycle-by-cycle.
Dead-times between PWML (controls QL) and PWMH (controls QSR) are optimally adjusted to help minimize the
circulating energy required for ZVS as operating conditions change. Therefore, the overall system efficiency is
improved and more consistent in mass production of the soft-switching topology. The programming features of
the RTZ, RDM, BUR, IPC, and SET pins provide rich flexibility to optimize the power stage efficiency across a
range of output power and operating frequency levels.
The UCC28781-Q1 uses five different steady-state operating modes to maximize efficiency over wide load and
line ranges:
1. At higher load levels, adaptive amplitude modulation (AAM) adjusts the peak primary current.
2. In the medium-load range, adaptive burst mode (ABM) modulates the pulse count of each burst packet.
3. In the light-load range, low power mode (LPM) reduces the peak primary current of each two-pulse burst
packet.
4. During very light-load conditions, stand-by power mode 1 (SBP1) minimizes the power loss.
5. During no-load conditions, stand-by power mode 2 (SBP2) minimizes the power loss.
During the system transient events such as the output load step down and output voltage overshoots, VVDD may
be reduced close to the 10.5-V UVLO-off threshold. In such cases, a sixth non-steady-state mode called survival
mode (SM) is triggered to maintain VVDD above 13 V and to reduce the size of the hold-up VDD capacitor.
The switching frequency-dither function is active in AAM to help reduce conducted-EMI noise and allow EMI filter
size reduction. The 23-kHz dithering pattern and magnitude are designed to avoid audible noise, minimize
efficiency influence, and desensitize the effect of the output voltage feedback loop response effect on the EMI
attenuation. The dither function at low line can be programmed into disable mode based on the brown-in voltage
setting, so the option provides design flexibility to balance the worst-case low-line efficiency and EMI. The dither
fading feature smoothly disables the dither signal when the output load is close to the transition point between
AAM and ABM. The 23-kHz dither frequency is high enough to allow a higher control-loop bandwidth for
improved load transient response without distorting the dither signal and impairing EMI.
The unique burst mode control in ABM, LPM, and two SBP modes maximizes the light-load efficiency of the
ZVSF power stage while avoiding the concerns of conventional burst operation - such as high output ripple and
audible noise. The internal ramp compensation can stabilize the burst control loop without an external
compensation network. The burst control provides an enable signal through the RUN pin to dynamically manage
the static current of the SR gate-driver and also adaptively disables the drive signal of QSR. The internal drivers
of RUN and PWMH can supply and disconnect the 5-V bias voltage to a digital isolator through a small-signal
diode. The disconnect switch inside the S13 pin can directly control the 13-V bias voltage to a low-side GaN
driver. These power management functions with RUN, PWMH, and S13 pins can be used to minimize the
quiescent power consumed by those devices during burst off time, further improving the converter’s light-load
efficiency and reducing its stand-by power.
The S13 and IPC pins of the UCC28781-Q1 can be adapted to manage an upstream PFC stage to maximize the
light-load efficiency of higher power applications. The S13 pin can supply a 13-V bias voltage to the PFC
controller whenever the ZVSF controller is in the run state. The pin disconnects the bias voltage during the wait
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states of the burst mode operation. When the burst frequency is reduced in very light load conditions, the bias
voltage will decay below UVLO and shut down PFC controller, so the power loss from PFC can be eliminated.
The PWML output is a strong driver for a Si power MOSFET with high capacitive loading, a GaN-based gate
injection transistor (GIT) with continuous on-state current, or a GaN power IC with logic input. The maximum
voltage level of PWML is clamped at 13 V to balance the conduction loss reduction and gate charge loss of Si
MOSFET. A dedicated driver ground return pin (PGND) minimizes the parasitic impedance and noise coupling of
the PWML gate-drive loop to achieve faster switching speed and reduced turn-off loss of QL. The short 15-ns
propagation delay and narrow 110-ns minimum on-time enable more accurate ZVS control and higher switching
frequency operation.
During initial power up or VDD restart, the ZVSF stops switching, so UCC28781-Q1 starts up the VDD supply
voltage with an external high-voltage depletion-mode MOSFET between the ZVSF switch node and the SWS
pin. Fast startup is achieved with low stand-by power overhead, compared with using the conventional high-
voltage startup resistance to VDD. Moreover, the P13 pin biases the gate of the depletion-mode FET to also
allow this MOSFET to be used in lossless ZVS-sensing. This arrangement avoids additional sensing devices.
The enhanced switching control of UCC28781-Q1 mitigates excessive drain-to-source voltage stress on a
synchronous rectifier (SR) caused by temporary continuous conduction mode (CCM), so the power loss of an
SR snubber can be reduced for higher efficiency. Additional PWML timing controls can avoid premature QL turn-
on before the magnetizing current reaches to zero through an improved zero-crossing detection (ZCD) scheme
of the VS pin.
The UCC28781-Q1 also integrates more robust protection features tailored to maximize system reliability and
safety. These features include active X-capacitor discharge, internal soft start, brown in/out, output over-voltage
(OVP), input line over-voltage (IOVP), output over-power (OPP), system over-temperature (OTP), switch over-
current (OCP), output short-circuit protection (SCP), and pin faults. All fault responses are auto-recovery, which
means that the controller will attempt to restart after the shut-down time elapses.
The X-capacitor discharge function can actively discharge the residual voltage on X2 safety capacitors to a safe
level after AC-line voltage removal is detected through the XCD pins of UCC28781-Q1 and its external sensing
circuit. If the AC-line voltage recovers within 2 seconds after the line removal, the controller will reset the fault
state immediately and will attempt to restart without waiting to fully discharge the bulk input capacitor or VDD
capacitor. Grounding the two XCD pins disables this function and eliminates the sensing circuit. Unlike other
conventional flyback controllers, UCC28781-Q1 provides the design flexibility of using the X-capacitor discharge
function based on application power level as it is decoupled from VDD startup and brown-in/out detection
functions. Since those two functions are implemented on the SWS and VS pins, respectively, UCC28781-Q1
maintains the two functions even when the XCD-related components are fully removed.
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7.2 Functional Block Diagram
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7.3 Detailed Pin Description
7.3.1 BUR Pin (Programmable Burst Mode)
The voltage at the BUR pin (VBUR) sets a target peak current-sense threshold at the CS pin (VCST(BUR)) which
programs the onset of adaptive burst mode (ABM). VBUR also determines the clamped peak current level of
switching cycles in each burst packet. When VBUR is set higher, ABM will start at heavier output load conditions
with higher peak primary current, so the benefit is higher light-load efficiency but the side effect is larger burst-
mode output voltage ripple. Therefore, 50% to 60% of output load at high line is the recommended highest load
condition to enter ABM (Io(BUR)) for both Si and GaN-based designs. The gain between VBUR and VCST(BUR) is a
constant gain of KBUR-CST, so setting VCST(BUR) just requires properly selecting the resistor divider on the BUR
pin formed by RBUR1 and RBUR2. VBUR should be set between 0.7 V and 2.4 V. If VBUR is less than 0.7 V,
VCST(BUR) holds at 0.7 V / KBUR-CST. If VBUR is higher than 2.4 V, VCST(BUR) stays at 2.4 V / KBUR-CST
.
R
BUR1KBUR-CSTVCST (BUR)
4ì RBUR1VCST (BUR)
RBUR2
=
=
VREF - KBUR-CSTVCST (BUR) 5V - 4ìVCST (BUR)
(1)
In order to enhance the mode transition between ABM and LPM, a programmable offset voltage (ΔVBUR(LPM)) is
generated on top of the VBUR setting in ABM through an internal 2.7-μA current source (IBUR(LPM)), as shown in
图 7-1. In ABM, VBUR is set through the resistor voltage divider to fulfill the target average efficiency. On
transition from ABM to LPM, IBUR(LPM) is enabled in LPM and flows out of the BUR pin, so ΔVBUR(LPM) can be
programmed based on the Thevenin resistance on the BUR pin, which can be expressed as
(
//
)
(2)
IO
IBUR(LPM)
LPM
REF
ûVBUR(LPM)
RBUR1
VBUR
ûVBUR(AAM)
BUR
ABM
LPM
RBUR2
ABM
IBUR(AAM)
CBUR
Copyright © 2019, Texas Instruments Incorporated
图7-1. Hysteresis Voltage Generation on BUR Pin
When VBUR steps higher on transition into LPM, the initial peak magnetizing current in LPM is increased with
larger energy per switching cycle in each burst packet. This increases the output voltage which forces higher
feedback current to restore regulation. Higher feedback current causes UCC28781-Q1 to stay in LPM, forming a
hysteresis effect. If ΔVBUR(LPM) is designed too small, it is possible that mode toggling between LPM and ABM
can occur resulting in audible noise. For that situation, ΔVBUR(LPM) greater than 100 mV is recommended.
To minimize the effects of external noise coupling on VBUR, a filter capacitor on the BUR pin (CBUR) may be
needed. CBUR needs to be properly designed to minimize the delay in generating ΔVBUR during mode
transitions. It is recommended that CBUR should be sized small enough to ensure ΔVBUR(LPM) settles within 40
μs, corresponding to the burst frequency of 25 kHz in LPM (fLPM). Based on three RC time constants,
representing 95% of a settled steady-state value from a step response, the design guide for CBUR is expressed
as
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RBUR1 + RBUR2
CBUR Ç 40ms ì
3RBUR1RBUR2
(3)
In order to enhance the mode transition between ABM and AAM, a programmable offset voltage (ΔVBUR(AAM)) is
generated to lower the VBUR with an internal 5-μA pull-down current (IBUR(AAM)), as shown in 图 7-1. After
transition from ABM to AAM, IBUR(AAM) is enabled in AAM and flows into the BUR pin, so ΔVBUR(AAM) is also
programmed based on the Thevenin resistance on the BUR pin, which can be expressed as
(
//
)
(4)
When VBUR reduces after transition to AAM, the initial peak magnetizing current in AAM is reduced with less
energy per switching cycle, which forces controller to continu operating in AAM. If ΔVBUR(AAM) is too small, it is
possible that either mode toggling between ABM and AAM or low-frequency ABM burst packets less than 20 kHz
can occur and result in audible noise concern. For that situation, ΔVBUR(AAM) greater than 150 mV is
recommended. In some power stage designs, LPM in hard switching condition may cover a wider output load
current range, so the light-load efficiency in LPM may be lower than ABM with ZVS condition. Besides, the ABM-
to-AAM mode transition may be affected potentially when the load current condition of LPM-to-ABM transition is
too close to the load current condition of ABM-to-AAM transition.
In order to optimize the output load current range in LPM, lower VBUR(ABM), smaller ΔVBUR(LPM), larger ROPP
,
and smaller CCS help to reduce the peak magnetizing current in LPM. If the LPM energy needs to be further
reduced but VBUR in AAM is limited by the 0.7-V minimum programmable level, the optional application circuit in
图 7-2 can be considered. When the output load current is reduced, duty cycle of each burst packet becomes
smaller, so as the duty cycle of RUN-pin voltage. CBUR is discharged by the RUN driver through the small-signal
diode (DBUR) and the current limit resistor (RRUN). Proper selection of RRUN value can further reduce VBUR(ABM)
when the load current is reduced close to the transition point from ABM to LPM. One example BUR-pin setting is
RBUR1 = 182 kΩ, RBUR2 = 37.4 kΩ, CBUR = 330 pF, and RRUN = 20 kΩ.
IO
RUN
RRUN
REF
DBUR
VBUR
RBUR1
ûVBUR(AAM)
ûVBUR(LPM)
BUR
ABM
LPM
RBUR2
CBUR
图7-2. Optional Application Circuit to Reduce VBUR in LPM
7.3.2 FB Pin (Feedback Pin)
The FB pin usually connects to the collector of an optocoupler output transistor through an external current-
limiting resistor (RFB). A maximum of 20 kΩ for RFB is recommended. The feedback network of UCC28781-Q1 is
shown in 图 7-3. A high-quality ceramic by-pass capacitor between FB pin and REF pin (CFB) is required for
decoupling IFB from switching noise interference. A minimum of 220 pF is recommended for CFB . An internal 8-
kΩ resistor (RFBI) at the FB pin in conjunction with the external CFB forms an effective low-pass filter. 节 8
provides a detailed design guide on the secondary-side compensation network of VO feedback loop, to improve
the load transient response and also limit the IFB ripple of ABM mode within the recommended range.
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VO
Compensation
Network
REF
FB
CFB
IFB
IOPTO
VFB(REG)
RFBI
RFB
IFB
ICOMP
+
Internal Ramp
Compensation
-
OPTO
COUPLER
Regulator
RUN
Control
Law
Copyright © 2019, Texas Instruments Incorporated
图7-3. External Feedback Network Connected to the FB Pin
Depending on the operating mode, the controller interprets the current flowing out of the FB pin (IFB) to regulate
the output voltage. For AAM and LPM modes based on peak current control, IFB is converted into an internal
peak current-sense threshold (VCST) to modulate the amplitude of the current-sense signal on the CS pin. For
example, when the output voltage (VO) is lower than the regulation level set by the shunt regulator, the absolute
current level of IFB reduces, causing a higher VCST to increase more power to the output load. In ABM, the burst
control loop takes over the VO regulation, where VCST is clamped to VCST(BUR) and the ripple component of IFB
participates in the modulation of the burst off time.
图 7-4 illustrates the operating principle of the ABM. A burst of switching pulses raises the output voltage VO
which increases IFB. At the end of the burst, the load current discharges the output capacitor, which decreases
VO and IFB. UCC28781-Q1 injects a noise-free internal ramp compensation current (ICOMP) superimposed on IFB
in order to stabilize the ABM operation. When the RUN pin is high, ICOMP is reset to 0 μA. When the RUN pin
goes low, ICOMP is gradually increased to 6 μA with a positive slope of 0.214 A/s. The summation of IFB and
ICOMP is compared with ITH(FB) to trigger the next burst event. The magnitude and sharp slope of ICOMP help to
push switching ripple and high-frequency noise component of IOPTO away from ITH(FB)
.
IFB - ICOMP
ITH(FB)
0.214 A/s
ICOMP
6µA
IOPTO ≈ IFB
Vo
PWML
RUN
Copyright © 2019, Texas Instruments Incorporated
图7-4. Concept of Burst Control with an Internal Ramp Compensation
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7.3.3 REF Pin (Internal 5-V Bias)
The output of the internal 5-V regulator of the controller is connected to the REF pin. REF provides bias current
to most of the functional blocks within the UCC28781-Q1. It requires a high-quality ceramic by-pass capacitor
(CREF) to AGND to decouple switching noise and to reduce the voltage transients as the controller transitions
from wait state to run state. The minimum CREF value is 0.22 μF, and a high quality dielectric material should be
used, such as X7R.
The output short-circuit current (IS(REF)) of the REF regulator is self-limited to approximately 17 mA. 5-V bias is
only available after the under-voltage lock-out (UVLO) circuit enables the operation of UCC28781-Q1 when VVDD
reaches VVDD(ON)
.
This pin can be used to perform an external shutdown function. A small-signal switch can be used to pull this pin
voltage below the power-good threshold of 4.5V so the controller will stop switching, force a VDD restart cycle,
and turn off the REF current.
7.3.4 VDD Pin (Device Bias Supply)
The VDD pin is the primary bias for the internal 5-V REF regulator, internal 13-V P13 regulator, other internal
references, and the undervoltage lock-out (UVLO) circuit. As shown in 图 7-5, the UVLO circuit connected to the
VDD pin controls the internal power-path switches among VDD, P13, and SWS pins, in order to allow an
external depletion-mode MOSFET (QS) to be able to perform both VVDD startup and switch-node voltage (VSW
sensing for ZVS control after startup. During startup, SWS and P13 pins are connected to VDD pin allowing QS
to charge the VDD capacitor (CVDD) from the VSW
)
.
After the VDD startup completes, the ZVS discriminator block and switching logic are enabled. Then, the
transformer starts delivering energy to the output capacitor (CO) every switching cycle, so both output voltage
(VO) and auxiliary winding voltage (VAUX) increase.
As VAUX is high enough, the auxiliary winding takes over to power VVDD. The UVLO circuit provides a turn-on
threshold of VVDD(ON) at 17 V and turn-off threshold of VVDD(OFF) at 10.6 V. For fixed output voltage designs, the
wide VVDD range can accommodate lower values of VDD capacitor (CVDD) and support shorter power-on delays.
For a fixed output voltage design, the rectified VAUX is directly connected to the VDD pin. As VVDD reaches
VVDD(ON), the SWS pin is disconnected from the VDD pin by the internal power path switch, so the CVDD size has
to be sufficient to hold VVDD higher than VVDD(OFF) until the positive auxiliary winding voltage is high enough to
take over bias power delivery during VO soft start. Therefore, the calculation of minimum capacitance (CVDD(MIN)
)
needs to consider the discharging effect from the sink current of the UCC28781-Q1 during switching in its run
state (IRUN(SW)), the average operating current of driver (IDR), and the average gate charge current of half-bridge
FETs (IQg) throughout the longest duration of VO soft-start (tSS(MAX)) sequence.
I
+ I
DR
+ I × t
Qg
RUN SW
V
SS max
VDD off
C
=
(5)
VDD min
× V
VDD on
tSS(MAX) estimation should consider the averaged soft-start current (ISEC(SS)) on the secondary side of the
converter, load current on the output (IO(SS)) during start-up (if any), maximum output capacitance (CO(MAX)), and
a 0.7-ms time-out potentially being triggered in the startup sequence. Include 1 ms in the equation to be the
worst-case condition of the 0.7-ms timer.
C
× V
O
O max
− I
t
=
+ 1 ms
(6)
SS max
I
SEC SS
O SS
During the VO soft-start sequence, VCST reaches the maximum current threshold on the CS pin (VCST(MAX)) , so
ISEC(SS) at the minimum voltage of the input bulk capacitor (VBULK(MIN)) can be approximated as:
N
× V
V
BULK min
PS
CST max
2 × R
I
=
×
(7)
SEC SS
V
+ N × V + V
F
CS
BULK min
PS
O
where
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• RCS is the current sense resistor
• NPS is primary-to-secondary turns ratio
• VF is the forward voltage drop of the secondary rectifier
7.3.5 P13 and SWS Pins
The P13 pin provides a regulated voltage to the gate of the depletion-mode MOSFET (QS), enabling QS to serve
both VVDD start-up and loss-less ZVS-sensing from the high-voltage switch node (VSW) through the SWS pin.
During VVDD start-up, the UVLO circuit controls two power-path switches connecting SWS and P13 pins to VDD
pin with two internal current-limit resistors (RDDS and RDDH), as shown in 图 7-5. In this configuration, QS
behaves as a current source to charge the VDD capacitor (CVDD). RDDS is set at 5 kΩ when VVDD < 1.8 V to limit
the maximum fault current under a VDD short-to-GND condition. RDDS is reduced to 500 Ω when VVDD > 1.8 V to
allow VVDD to charge faster. The maximum charge current (ISWS) is affected by RDDS, the external series
resistance (RSWS) from SWS pin to QS, and the threshold voltage of QS (VTH(Qs)). ISWS can be calculated as
V
TH Qs
I
=
(8)
SWS
R
+ R
DDS
SWS
CVDD
UVLO
VDD
ISWS
RDDS
RSWS
SWS
P13
VSW
+
VTH(Qs)
-
CSWS
QS
RDDH
DSWS
CP13
DP13
Copyright © 2019, Texas Instruments Incorporated
图7-5. Operation of the VDD Startup Circuit
After VVDD reaches VVDD(ON), the two power-path switches open the connections between SWS, P13, and VDD
pins. At this point, a third power-path switch connects an internal 13-V regulator to the P13 pin for configuring QS
to perform loss-less ZVS sensing. Because the QS gate is fixed at 13 V, when the drain pin voltage of QS
becomes higher than the sum of QS threshold voltage (VTH(Qs)) and the 13-V gate voltage, QS turns off and the
source pin voltage of QS can no longer follow the drain pin voltage change. This gate control method makes QS
act as a high-voltage blocking device with the drain pin connected to VSW. When the controller is switching,
whenever VSW is lower than 13 V, QS turns on and forces the source pin voltage to follow VSW, becoming a
replica of the VSW waveform at the lower voltage level, as illustrated in 图7-6.
The limited window for monitoring the VSW waveform is sufficient for ZVS control of the UCC28781-Q1, since the
ZVS tuning threshold (VTH(SWS)) is set at 8.5 V for VSET = 5 V and set at 4 V for VSET = 0 V. The 8.5-V threshold
is the auto-tuning target of the internal adaptive ZVS control loop for realizing a partial-ZVS condition using Si
primary switches. On the other hand, performing full ZVS operation is more suitable with GaN primary switches.
Using a 4-V threshold helps to compensate for sensing delay between VSW and the SWS pin.
The internal 13-V regulator requires a high-quality ceramic by-pass capacitor (CP13) between the P13 pin and
AGND pin for noise filtering and providing compensation to the P13 regulator. The minimum CP13 value is 1 μF
and an X7R-type dielectric capacitor with 25-V rating or better is recommended. The controller enters a fault
state if the P13 pin is open or shorted to AGND during VVDD start-up, or if VP13 overshoot is higher than VP13(OV)
of 15 V in run state. The output short-circuit current of P13 regulator (IP13(MAX)) is self-limited to approximately
130 mA.
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Since the P13 pin interfaces to the external depletion-FET, during input surge or EFT testing the Cgd of the
depletion-FET can inject charge into the P13 pin and may cause an over-voltage stress. Under such condition it
is recommended to place an 18-V Zener diode (DP13) on the P13 pin to clamp its voltage below its abs-max
level.
During AAM and ABM if the negative magnetizing current is large enough, a GaN device may operate in the
reverse conduction condition before it turns on each switching cycle, so VSW may be around -5 V for a brief
inteval and it appears on the SWS pin. The SWS-pin design of UCC28781-Q1 can sustain –6 V (continuous)
and –10 V (transient) stress to enhance the robust operation of the GaN power stage.
During this interval, QS is in the on-state and its body diode may conduct for a short time when the voltage drop
across the on-state resistance of QS is high enough. The external RSWS can limit the forward current flowing
through the QS body diode, so the reverse recovery charge of the body diode can be significantly reduced. Too
high of RSWS value weakens the start-up charge current of CVDD and results in a longer start-up time. RSWS can
be expected be slightly higher than 500 Ω. A small back-to-back TVS across BSS126 gate-to-source should be
added to protect the gate-to-source voltage from potential abnormal voltage stress. Ensure that the TVS
clamping voltage is less than the BSS126 gate-to-source voltage rating but does not conduct below 15 V.
RSWS and a ceramic capacitor (CSWS) between the SWS pin and the bulk input capacitor ground form a small
sensing delay to help the internal detection circuit to identify the ZVS characteristic correctly. The delay is to
ensure that the ZCD detection on the VS pin happens earlier than the ZVS detection on the SWS pin, such that
the ZVS control can auto-tune the PWMH on-time in the proper direction. The minimum value of CSWS is 22 pF.
CVDD
VDD
VSW
VBULK+NPS(VO+VF)
RSWS
ZVS
Discriminator
SWS
P13
VSW
+
VTH(Qs)
-
CSWS
QS
VSWS
13V+VTH(Qs)
0V
13-V Regulator
DSWS
CP13
DP13
PWML
Copyright © 2019, Texas Instruments Incorporated
图7-6. ZVS Sensing by Reusing the VDD Startup Circuit
7.3.6 S13 Pin
As shown in Power Management Function for a GaN Power IC and PFC Controller , the S13 pin (switched 13-V
rail) is used to perform bias-power management for a primary-side GaN power IC, along with an example
application where it also powers a PFC controller. This configuration enables to minimize the power-loss
contribution to so-called "tiny-load" input power and stand-by power.
S13 is sourced by P13 through an internal 2.8-Ω switch controlled by the RUN pin. 图 7-8 illustrates the power-
up sequence of the S13 pin. When RUN is high, the S13 decoupling capacitor is charged up to 13 V and the
charge current is controlled by an internal soft-start current limiter. The S13-pin voltage must increase above the
10-V power-good threshold (VS13(OK)) in order to initiate PWML switching of each burst cycle. When RUN is low,
VS13 is discharged by the loading on S13. The power-on delay of the GaN power IC on the S13 pin must be less
than 2 µs to be responsive to PWML. If not, the VDD or P13 pin may be a more suitable bias supply for devices
with long power-on delay, but the wait-state power consumption will be compromised. A 22-nF ceramic capacitor
as CS13(ZVSF) is recommended. If the S13 pin is not used, it can be connected to the P13 pin in order to eliminate
the delay effect on PWML switching in every low-frequency burst cycle.
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PFC Controller
VCC
GaN + Driver
VCC
DS13
RS13
CS13(PFC)
UCC28781-Q1
CS13(ACF)
ROPP
S13
CS
COMP
GND
QIPC
RIPC
RCS
CIPC
IPC
RIPC2
DIPC
RIPC3
图7-7. Power Management Function for a GaN Power IC and PFC Controller
RUN
tD(RUN-PWML)
PWML
13V
VP13
VS13(OK)
10V
VS13
0V
S13_OK
IS13(OCP)
IS13
Copyright © 2019, Texas Instruments Incorporated
图7-8. Power-up Sequence of the S13 Pin
When the S13 pin supplies both the GaN power IC and a PFC controller at the same time, a low-voltage rectifier
diode (DS13) between the S13 pin and the PFC controller bias VCC pin is needed, so the local decoupling
capacitor for each powered device can be separated. The decoupling capacitor of the PFC controller (CS13(PFC)
)
is usually larger than the one for a GaN power IC, such that the bias voltage of the GaN power IC will discharge
more quickly without affecting the PFC bias voltage and PFC output voltage regulation. If the S13 pin supplies a
PFC controller only, the rectifier diode is not needed.
During start-up before VDD reaches the VVDD(ON) threshold, the S13 switch stays off, so the S13-pin loading will
not consume any of the charging current of VDD capacitor flowing from SWS pin to VDD pin, thereby enabling a
fast start-up sequence. Under this condition, the PFC controller will be off resulting in a lower PFC bus voltage
below 400 V.
7.3.7 IPC Pin (Intelligent Power Control Pin)
Under certain conditions, the IPC pin provides a 50-µA current from an internal source (IIPC(SBP2)) which is
controlled by logic as shown in 图 7-9. The voltage on the VS pin is sampled during the demagnetization time to
obtain an indication of the reflected output voltage (NVO). When the VS-pin voltage is lower than the 2.4-V lower
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LV mode threshold (VVSLV(LR)), the LOW_NVO logic signal is pulled high, and the current source is enabled
during the run state of all normal control modes (SBP1, SBP2, LPM, ABM, and AAM).
When the sampled VS-pin voltage is higher than the 2.5-V upper LV mode threshold (VVSLV(UP)), the LOW_NVO
logic signal becomes low. In the LOW_NVO = 0 V case, the 50-µA current source is enabled in the run state of
SBP2 mode only.
To minimize stand-by power, the 50-µA source is always disabled during the wait state of any control mode.
Additionally, if VVDD falls lower than the 13-V survival-mode threshold, the INT_STOP logic signal is pulled high
and the current source is disabled during survival mode operation, irrespective of the VVS level.
LOW_NVO
IIPC(SBP2)
INT_STOP
RUN
IPC
RIPC
SBP2
Copyright © 2019, Texas Instruments Incorporated
图7-9. Control Circuit Diagram to the IPC-Pin Current Source
The multi-function IPC pin can be programmed to obtain one or more of the following benefits:
1. Reduction of input power for special light-load and stand-by conditions
2. Improvement of light-load efficiency at lower output voltages, such as 5 V and 9 V
3. Reduction of burst-mode output ripple at lower output voltages
4. Reduction of the over-power limit at lower output voltages
5. Power management of a PFC controller, together with the S13 pin
To implement the benefit No. 1, connect a resistor RIPC from IPC pin to AGND pin. The 50-µA current source
establishes a voltage (VIPC) across RIPC to program an increase in the CS-pin peak primary current threshold at
very light loads. The transfer function between VIPC and the CS threshold (VCST_IPC) in SBP2 mode is illustrated
in 图7-10.
Proper sizing of RIPC to AGND can further reduce the burst frequency in SBP2 for so-called tiny-load power and
for stand-by power.
When VIPC is less than 0.9 V (or IPC is shorted to AGND), VCST_IPC threshold stays at the minimum level of 0.15
V. When VIPC is set between 0.9 V and 1.8 V, VCST_IPC is clamped at 0.27 V. For VIPC between 1.8 V and 3.8 V,
there is a linear programmable VCST_IPC range between 0.27 V and 0.4 V. When VIPC is greater than 3.8 V,
VCST_IPC remains clamped to 0.4 V. Be aware that high settings of VCST_IPC may, in some cases, introduce
higher output ripple in deep light-load condition or provoke audible noise.
VCST
VCST_IPC(UP)
VCST_IPC(LR)
0.4V
0.27V
VCST_IPC(MIN)
0.15V
VIPC
0V
0.9V
1.8V
3.8V
5V
Copyright © 2019, Texas Instruments Incorporated
图7-10. IPC Transfer Function to Program the SBP2 Peak Current Threshold
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Because the enable status of the IPC current source contains the very useful output voltage information from the
LOW_NVO logic state, the IPC pin can be used to further optimize power stage performance over a wide output
voltage range. To gain benefits No.2, No. 3, and No. 4 of the IPC function, connect RIPC between the IPC pin
and the CS pin, so that the current source can create additional CS-pin offset voltage on ROPP when VVS < 2.4 V.
With higher CS offset, the operating range of the VCST signal will be higher than the actual power stage peak
current. This forces the controller to operate in AAM mode for a wider actual output load range, and forces the
burst-mode threshold down to a lower power level.
图 7-11 shows the side effect of the IPC-to-CS connection if the RIPC setting is the same. Because the controller
enables 50 µA in the run state of SBP2, the lower peak magnetizing current of the IPC-to-CS connection makes
the SBP2 burst frequency higher and results in weakening the stand-by power improvement. Therefore, a higher
RIPC is needed to increase VCST_IPC to compensate the peak current change.
20 V / 100 W
5 V / 15 W
Hard Switching
(LPM, SBP1, SBP2)
Soft Switching
(AAM, ABM)
VCST
VCST
Soft Switching
(AAM, ABM)
50µA·ROPP
VCST(BUR)
PO
PO
IM(+)
IM(+)
RIPC to AGND
RIPC to CS
RIPC to AGND
RIPC to CS
PO
PO
15W
100W
Copyright © 2019, Texas Instruments Incorporated
图7-11. Effect of the CS-pin Offset Voltage from the IPC Pin
For benefit No. 5, the IPC pin can also be used to disable a PFC controller (if used) at all load conditions for
lower voltage outputs to further improve the light-load efficiency . As shown in Power Management Function for a
GaN Power IC and PFC Controller, the diode DIPC in series with RIPC is placed between IPC and CS pins, and
VIPC established at IPC is used to drive a small-signal switch QIPC to disable the PFC controller such as
UCC28056.
When VIPC is higher than its threshold voltage, QIPC can pull low the COMP pin voltage of a PFC controller, so its
switching is disabled. As a consequence, PFC output voltage drops from the typical 400-V regulation level to the
peak value of the AC line. This lowers the bulk voltage, which reduces the ZVS energy, which increases power
stage efficiency for low voltage outputs. Furthermore, the power loss of the PFC power stage is out of the
efficiency equation. One design example for those components are CS13(ZVSF) = 22 nF, CS13(PFC) = 0.22 µF, CIPC
= 10 nF, RIPC = 69.8 kΩ, RIPC2 = 10 MΩ, and RIPC3 = 20 kΩ. Choose QIPC with threshold voltage less than 1.5 V
to ensure that VIPC is sufficient to achieve low on-resistance (RDS(on)) even at very low burst frequencies.
7.3.8 RUN Pin (Driver and Bias Source for Isolator)
The RUN pin is a logic-level output signal which enables PWM switching when active high. When RUN is low, all
PWML and PWMH switching is disabled and the controller enters a low-current wait state.
In addition to enabling switching, RUN is capable of sourcing considerable current to bias an external gate driver
and perform a power management function on the primary side of a digital isolator. It generates a 5-V logic
output when the driver should be active, and pulls down to less than 0.5 V when the driver should be disabled.
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During the off-time of any burst mode, the RUN pin serves as a power-management function to dynamically
reduce the static bias current of the isolator/ driver, so light-load efficiency can be further improved and stand-by
power can be minimized.
As RUN goes high, while its voltage is less than 3 V, a 44-mA peak pull-up current is supplied from the internal
P13 regulator. With this current, the RUN driver can quickly charge the primary-side decoupling capacitor of a
digital isolator above its UVLO(ON) threshold. A Schottky diode can block discharge of this capacitor when RUN
goes low. When the RUN voltage goes above 3 V, P13 stops providing current and the pull-up is supplied from
the REF regulator, so the peak driving capability will be limited in order to avoid triggering the over-current
protection of the REF regulator. When RUN is low for a long burst off-time, the decoupling capacitor of the digital
isolator will be gradually discharged below its UVLO(OFF) threshold, so the isolator power loss can be
minimized.
There are three delays between RUN going high to the first PWML pulse going high in each burst packet. The
first delay is a fixed 2.2-μs delay time, intended to provide an appropriate "wake-up" time for the controller and
the gate driver to transition from a wait state to a run state. The second delay is gated by the 10-V power-good
threshold of the S13 pin. PWML will not go high until S13 voltage exceeds 10 V. The third delay is another 2.2-
μs timeout, tZC in the electrical table, intended to turn on the low-side switch of the first switching cycle per burst
packet around the valley point of DCM ringing by waiting for the zero-crossing detection (ZCD) on the auxiliary
winding voltage (VAUX). If ZCD is detected (on the VS input) before the tZC timeout elapses, PWML is
immediately driven. If no ZCD is detected, PWML is driven when tZC elapses. The first two delays can be
concurrent; the third delay is sequential.
Therefore, the minimum total delay time is 2.2 μs typically if VS13 > 10 V and ZCD is detected immediately after
the 2.2-μs wake-up time. If VS13 < 10 V, the total delay time with tolerance over temperature is listed as
tD(RUN-PWML) in the electrical table.
Digital
Isolator
Controller
RUN
PWMH
PWML
DRUN
VCC1
CRUN
PWMH
AGND
IN
V
CC1
V
GND
V
CC1(UVLO+)
V
RUN
图7-12. Power Management Circuit
图7-13. Power Management Waveform
7.3.9 PWMH and AGND Pins
The PWMH pin controls the gate of an SR MOSFET through an external isolating gate-driver. PWMH may also
be used to bias the primary-side of the gate-driver. The PWMH driver ground return is referenced to the AGND
pin. The maximum voltage level of PWMH is clamped to 5-V REF level. As PWMH goes high, when its voltage is
less than 3 V, up to 21-mA peak pull-up current may be supplied from the P13 regulator. When the PWMH
voltage goes above 3 V, the pull-up is supplied from the REF regulator instead, so the peak driving capability is
limited to less than 6 mA to avoid tripping the over-current protection of the REF regulator.
As shown in 图 7-12, since the RUN driver charges the decoupling capacitor of a digital isolator first through one
small-signal diode at the beginning of every burst cycle, the sourcing current of PWMH is sufficient to send the
control signal to the isolator and supply the continuous isolator operating current together with the RUN driver at
the same time through another small-signal diode. The high peak driving capability of PWMH provides the
flexibility of signal transmission through a digitally isolated gate-driver with opto-compatible input.
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It is prudent to choose an isolated gate-driver with minimal power-up delay on both input and output sides to
avoid missing several PWMH pulses for SR control.
AGND pin is the ground return for all the analog control signals, RUN driver, and PWMH driver. It is required to
implement a careful layout separation from other noisy ground return paths, such as PGND and power stage
ground. The thermal pad should be connected to the AGND pin directly and could be a Kelvin connection point
to the related external components. For details of the grounding layout guideline and noise decoupling
techniques, one can refer to the 节8.1 of this datasheet.
7.3.10 PWML and PGND Pins
The PWML pin is the primary-side switch gate-drive, for which ground return is referenced to the PGND pin. The
strong driver with 0.5-A peak source and 1.9-A peak sink capability can control either a silicon power MOSFET
with a higher gate-to-source capacitance, a cascode GaN, an E-mode gate-injection-transistor (GIT) GaN with
continuous on-state current, or a GaN power IC with logic PWM input.
The maximum voltage level of PWML is clamped to the P13 pin voltage. The 13-V clamped gate voltage
provides an optimal gate-drive for low on-state resistance and lower gate-driving loss. An external gate resistor
in parallel with a fast recovery diode can be used to further reduce the turn-on speed without compromising the
turn-off switching loss. Slower turn-on speed of the primary switch mitigates the voltage stress across the
secondary-side rectifier when the SR switch is disabled in deep light-load condition, and reduces the switching-
node dV/dt to a safe level for reducing stress on the high-voltage isolating SR driver. A decoupling capacitor
much larger than the PWML capacitive loading should be placed between P13 and PGND pins to decouple the
gate-drive loop to allow operation at higher switching frequency. The 15-ns propagation delay of the PWML
driver enables a higher frequency operation and more consistent ZVS switching.
图7-14 and 图 7-15 shows the example PWML driving network for a GIT GaN device and for a silicon MOSFET.
Resistor RG2 controls the turn-on speed. The turn-off speed can be maintained by the two fast recovery diodes,
DG1 and DG2. RG1 provides a continuous driving path to maintain the on state and low on-resistance (RDS(on)) of
a GIT GaN. CG avoids the small RG2 from affecting the on state current. PGND can be directly connected to the
separate source terminal of a GIT GaN to achieve a kelvin connection, so the driver loop parasitic inductance
can be decoupled.
QL
QL
RG
RG1
PWML
PGND
PWML
CG
RG2
AGND
AGND
PGND
DG2
DG
LStray
RCS
LStray
RCS
DG1
图7-14. Driving a GIT GaN Device
图7-15. Driving a Si MOSFET
An internal low-voltage level shifter is included between PGND and the ground return pin for analog control
signals (AGND), so PGND can be connected separately to the top of the current sense resistor (RCS) to achieve
a Kelvin connection. When hard switching condition occurs, the lumped parasitic capacitor on the switch node is
discharged, so a positive voltage spike is created across RCS. In soft switching condition, the negative
magnetizing current flowing through RCS can create a negative voltage spike on RCS. The level shifter is
designed to handle 5-V positive transient spike and -1-V negative stress between PGND pin and AGND pin.
7.3.11 SET Pin
Due to different capacitance non-linearity between Si and GaN power FETs as well as different propagation
delays of their drivers, the SET pin is provided to program critical parameters of UCC28781-Q1 for the two
different power stages.
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Firstly, this pin sets the zero-voltage threshold (VTH(SWS)) at the SWS input pin to be one of two different auto-
tuning targets for ZVS control. When SET pin is tied to AGND, VTH(SWS) is set at its low level of 4 V for realizing
full ZVS, which allows the low-side switch (QL) to be turned on when the switch-node voltage drops close to 0 V.
When SET pin is tied to REF pin, VTH(SWS) is set at 8.5 V for implementing partial ZVS, which makes QL turn on
at around 8.5 V.
Secondly, the SET pin also selects the current-sense leading-edge blanking time (tCSLEB) to accommodate
different delays of the gate drivers; 110 ns for VSET = 0 V and 190 ns for VSET = 5 V.
Thirdly, the minimum PWML on-time (tON(MIN)) in low-power mode and standby-power mode is 110 ns for VSET
0 V, and is 100 ns for VSET = 5 V.
=
Finally, the maximum PWML on-time to detect CS pin fault (tCSF) is adjusted. tCSF for VSET = 5 V (tCSF1) is set at
2 μs. tCSF for VSET = 0 V (tCSF0) depends on the value of RRDM. tCSF0 is configured to 2 μs when RRDM
RRDM(TH) and to 1 μs when RRDM < RRDM(TH)
≥
.
7.3.12 RTZ Pin (Sets Delay for Transition Time to Zero)
The dead-time between PWMH falling edge and PWML rising edge (tZ) serves as the wait time for VSW transition
from its high level down to the target ZVS point. Since the optimal tZ varies with VBULK, the internal dead-time
optimizer automatically extends tZ as VBULK is less than the highest voltage of the input bulk capacitor
(VBULK(MAX)). The circulating energy for ZVS can be further reduced, obtaining higher efficiency at low line
versus a fixed dead-time over a wide line voltage range. A resistor on the RTZ pin (RRTZ) programs the minimum
tZ (tZ(MIN)) at VBULK(MAX), which is the sum of the propagation delay of the synchronous rectifier driver (tD(DR)) and
the minimum resonant transition time of VSW falling edge (tLC(MIN)).
R
= K
× t
= K
× t
+ t
LC min
(9)
RTZ
RTZ
Z min
RTZ
D DR
where
• KRTZ is equal to 11.2 × 1011 (unit: F-1) for VSET = 0 V
• KRTZ is equal to 5.6 × 1011(unit: F-1) for VSET = 5 V
VSW
NPS(VO+VF)
VBULK(MAX)
IM
IM-
tD(DR)
tLC(MIN)
tZ(MIN)
PWMH
PWML
图7-16. RTZ Setting for the Falling-edge Transition of VSW
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As illustrated in 图 7-16, when PWMH turns off QSR after tD(DR) delay, the negative magnetizing current (iM-)
becomes an initial condition of the resonant tank formed by magnetizing inductance (LM) and the switch-node
capacitance (CSW). CSW is the total capacitive loading on the switch-node, including the junction capacitance
(COSS) of the primary switch, reflected secondary-side capacitance, intra-winding capacitance of the transformer,
the snubber capacitor, and parasitic capacitance of the PCB traces between switch-node and ground. Unlike a
conventional valley-switching flyback converter, the resonance of the Zconverter at high line does not begin at
the peak of the sinusoidal trajectory. The transition time of VSW takes less than half of the resonant period. The
following tLC(MIN) expression quantifies the transition time for RRTZ calculation, where an arccosine term
represents the initial angle at the beginning of resonance. As an example, the value of π minus the arccosine
term at VBULK(MAX) of 375 V, VO of 20 V, and NPS of 5 is around 0.585π, which is close to one quarter of the
resonant period.
NPS (VO +VF )
VBULK (MAX )
tLC(MIN ) = [
p
- cos-1(
)]ì LM CSW
(10)
7.3.13 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
The RRDM resistor provides the power stage information to the tDM optimizer for auto-tuning the on-time of
PWMH to achieve ZVS within a given tZ discharge time. The following equation calculates the resistance, based
on the knowledge of the primary magnetizing inductance (LM), auxiliary-to-primary turns ratio (NA/NP), the values
of the resistor divider (RVS1 and RVS2) from the auxiliary winding to VS pin, and the current sense resistor (RCS).
Among those parameters, LM contributes the most variation due to its typically wider tolerance. The optimizer is
equipped with wide enough on-time tuning range of PWMH to cover tolerance errors. Therefore, just typical
values are enough for the calculation.
N
× R
VS1
K
× L
CS
A
VS2
+ R
DM
R
M
R
=
×
(11)
RDM
N
× R
P
VS2
where
• KDM is equal to 5.0×109 (unit: F-1) for both VSET = 5 V and VSET = 0 V
7.3.14 XCD Pin
The XCD pin performs the X-capacitor discharge function in conjunction with the recommended external
detection circuit, shown in 图7-17.
备注
The XCD application circuit must be connected to an AC input but not to a DC input, in order to avoid
the thermal stress on those sensing components caused by enabling the discharge current
repetitively.
If the XCD function is not needed, directly shorting the two XCD pins to the AGND pin disables the XCD pin
function, so the controller wait-state current is further reduced. The external sensing circuit must be removed.
(see 图7-18)
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L
N
VHV
RXCD
QXCD
XCD
XCD
图7-18. Disable XCD Functions
图7-17. X-cap Discharge Circuit
To form the discharge path in the first circuit, the anode nodes of two high-voltage diode rectifiers are connected
to each X-cap terminal, the two diode cathodes are connected together to a 26-kΩ current limit resistance
(RXCD), and the drain-to-source of a high-voltage depletion MOSFET (QXCD) couples the resistance to XCD pins.
Since RXCD needs to sustain the high voltage drop from the XCD-pin current, two series 13-kΩ SMD resistors in
1206 size with 26-kΩ total resistance are required to meet the voltage de-rating. A 600-V rated MOSFET such
as BSS126 is needed as the high voltage blocking device. The MOSFET gate is connected to the P13 pin, so
the highest voltage level of the XCD pins is limited to the sum of the P13-pin voltage and the threshold voltage of
BSS126. The voltage level gives sufficient headroom over the 6.5-V line zero-crossing (LZC) threshold.
In case of single-fault event where one XCD pin is in fail-open condition, the redundant XCD pin helps to
maintain the X-cap discharge function. In case of the single-fault event of BSS126 involving its drain-to-source in
fail-short condition, an internal 26-V clamp helps to protect the XCD pin from exceeding its voltage rating. The
current-limiting resistance (RXCD) limits the fault current below the maximum clamping capability, however the
value of RXCD should avoid reducing the normal discharge current. A total resistance of 26 kΩ ±5% meets both
criteria. The internal clamping function can also help to dissipate some of the line surge energy accumulated on
the XCD pins in order to limit the pin voltage below its 30-V rating.
After the AC line is disconnected, X-capacitors in the EMI filters on the AC side of the diode-bridge rectifier must
have means to discharge its residual voltage to a safe level within a certain time. Typically a high voltage
discharge resistor bank is placed in parallel with the capacitor to form a discharge path. The value of the
resistance is chosen to discharge the capacitance within the required time period. However, if the capacitance is
large enough, the necessary lower value of discharge resistance will increase the standby power. The controller
provides an active X-capacitor discharge function with 2-mA maximum discharge current capability to reduce the
standby power. The discharge current is activated only when the detection criteria for the AC-line removal
condition is met. The 6.5-V line zero-crossing (LZC) threshold on XCD pins is used to detect AC-line presence.
When LZC is missing over an 84-ms detection timeout period, the discharge current is enabled for a maximum
period of 300 ms followed by a 700-ms blanking time with no current. To detect the zero crossing reliably, as well
as to save power consumption, a stair-case test current shown in 图 7-19 is generated within the 84-ms
detection time. The worst-case discharge current and timing are designed to discharge the X-capacitor up to 1
µF.
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IXCD(MAX)
IXCD(4)
IXCD(3)
IXCD(2)
IXCD(1)
IXCD(0)
tXCD(MAX)
7 x tXCD(STEP)
tXCD(WAIT)
Copyright © 2019, Texas Instruments Incorporated
图7-19. Step-current Profile into the XCD Pins for the X-cap Discharge Function
The four test current levels are designed to overcome the impact of leakage current from the bridge diode over a
wide line range. Without enough test current level in a 12-ms period, the diode leakage current will prevent the
XCD-pin voltage from reaching close to the 6.5-V LZC threshold. A higher AC line voltage or a higher diode
junction temperature requires a higher test current due to the increased diode leakage current. When the AC line
is connected, the four stair-case current levels and the 700-ms time out after the completion of LZC detection
helps to minimize the average current sink from AC main and thereby the static power loss. For the first three
current levels, every 12-ms time-out event commands the test current to increment. The last test current level
has to be sustained for 48 ms without LZC, before triggering the 2-mA discharge mode. Whenever LZC is
detected, any higher-level test-current steps are aborted and the 700-ms wait-state is initiated. 图 7-20 shows
the flow chart of X-capacitor discharge.
Note that the XCD-LATCH referenced in 图 7-20 is a latch that is set when loss of AC line is confirmed. When
set, this state allows X-capacitor discharge to proceed.
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VXCD > 4V
AFTER FIRST VVDD
STARTUP
Y
700ms
DONE
N
Disable XCD
700ms BLANK &
XCD_LATCH RESET
12ms LZC
DETECT
12ms
WAIT
LZC = 1
700ms
WAIT
(IXCD(0)
)
(IXCD(1)
)
12ms_DONE & LZC = 0
LZC = 1
12ms LZC
DETECT
12ms
WAIT
(IXCD(2)
)
LZC = 1
12ms_DONE & LZC = 0
12ms LZC
DETECT
12ms
WAIT
(IXCD(3)
)
LZC = 1
12ms_DONE & LZC = 0
48ms LZC
DETECT
48ms
WAIT
(IXCD(4)
)
700ms
DONE
48ms_DONE & LZC = 0
300ms
DISCHARGE
(IXCD(MAX)
700ms BLANK
(IXCD(0)
XCD_LATCH
SET
)
300ms_DONE
OR LZC = 1
)
700ms
WAIT
300ms
WAIT
Copyright © 2019, Texas Instruments Incorporated
图7-20. The State Diagram of the XCD-pin Function
Whenever any system protection is triggered, the converter switching is terminated and VVDD restart cycle
occurs between VVDD(ON) and VVDD(OFF). In this mode, the XCD pin function continues to operate, since the
internal circuitry is separately biased from VVDD instead of from VREF
.
Shorting the XCD pins to AGND disables the XCD function. After VVDD first reaches VVDD(ON), an 80-µA test
current is sourced out of the XCD pin in order to reliably identify the XCD-pin short with a low-impedance path to
the AGND pin. If XCD is shorted to AGND, any path to L and N must be open to prevent RXCD from overheating.
When VXCD is lower than 4 V before the RUN-pin first pulls high, the XCD function is disabled and the internal
circuit will stop sourcing current from VVDD
.
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7.3.15 CS, VS, and FLT Pins
The CS pin is the current-sense input. The internal peak current control loop limits the highest magnetizing
current, and 节7.4.4 in this datasheet describes the peak current change in different operating modes.
The VS pin is a multi-function sensing input, which detects the input voltage, the output voltage, and the zero-
current-detection (ZCD) through the auxiliary winding voltage, to optimize ZVSF performance and provide critical
protections.
The FLT pin is a dual-purpose fault detection pin for either over-temperature protection or input over-voltage
protection, depending on how the external circuit is configured.
The system protection functions of these three pins are introduced in 节7.4.12.
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7.4 Device Functional Modes
7.4.1 Adaptive ZVS Control with Auto-Tuning
图 7-21 shows the simplified block diagram explaining the ZVS control of UCC28781-Q1 controller. A high-
voltage sensing network provides a replica of the switch node voltage waveform (VSW) with a limited “visible”
lower voltage range that the SWS pin can handle. The ZVS discriminator identifies the ZVS condition and
determines the adjustment direction for the on-time of PWMH (tDM) by detecting if VSW reaches a predetermined
ZVS threshold, VTH(SWS), within tZ, where tZ is the targeted zero voltage transition time of VSW controlled by the
PWMH-to-PWML dead-time optimizer.
In 图 7-21, VSW of the current switching cycle in the dashed line has not reached VTH(SWS) after tZ expires. The
ZVS discriminator sends a TUNE signal to increase tDM for the next switching cycle in the solid line, such that the
negative magnetizing current (IM-) can be increased to bring VSW down to a lower level in the same tZ. After a
few switching cycles, the tDM optimizer settles and locks into ZVS operation of the low-side switch (QL). In
steady-state, there is a fine adjustment on tDM, which is the least significant bit (LSB) of the ZVS tuning loop.
This small change of tDM in each switching cycle is too small to significantly move the ZVS condition away from
the desired operating point. 图 7-22 demonstrates how fast the ZVS control can lock into ZVS operation. Before
the ZVS loop is settled, controller starts in a valley-switching mode as tDM is not long enough to create sufficient
IM-. Within 15 switching cycles, the ZVS tuning loop settles and begins toggling tDM with an LSB.
tD(PWML-H)
VCST
NP:NS
LK
IM / RCS
PWML
PWMH
VO
VBULK
IM
LM
RCo
CO
RO
tDM
SET
VS
RTZ
Adaptive ZVS Control
PWMH
PWML
Isolated Driver
(primary side)
Isolated Driver
(secondary side)
RDM
SET
tDM
Optimizer
Dead-Time Optimizer
(tD(PWML-H) and tZ)
QL
tZ
VSW
RCS
TUNE
tZ
VTH(SWS)
Peak Current
Loop
VCST
ZVS Discriminator
PWMH
PWML
SET
SWS
HV Sense
P13
图7-21. Block Diagram of Adaptive ZVS Control
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PWML
PWMH
1.2
0.8
IM (A)
0.4
0
18
12
VSWS (V)
6
VTH(SWS)
0
400
300
VSW (V)
200
100
0
5 µs/div
12
12
6
12
6
VSWS (V)
6
0
0
0
400
400
400
VSW (V)
200
200
0
200
0
0
图7-22. Auto-Tuning Process of Adaptive ZVS Control
7.4.2 Dead-Time Optimization
The dead-time optimizer in 图 7-21 controls the two dead-times: the dead-time between PWMH falling edge and
PWML rising edge (tZ), as well as the dead-time between PWML falling edge and PWMH rising edge
(tD(PWML-H)).
The adaptive control law for tZ utilizes the line feed-forward signal to extend tZ as VBULK reduces, as shown in 图
7-23. The VS pin senses VBULK through the auxiliary winding voltage (VAUX) when the primary side switch (QL) is
on. The auxiliary winding creates a line-sensing current (IVSL) out of the VS pin flowing through the upper resistor
of the voltage divider on VS pin (RVS1). Minimum tZ (tZ(MIN)) is set at VBULK(MAX) through the RTZ pin. When IVSL
is lower than 666 μA, tZ linearly increases and the maximum tZ extension is 140% of tZ(MIN)
.
140%
tZ(IVSL
)
tZ(MIN)
100%
IVSL
233 µA
666 µA
图7-23. tZ Control Optimized for Wide Input Voltage Range
The control law for tD(PWML-H) is adaptive with the slope variation of the switching node voltage, regardless of the
SET-pin voltage as shown in 图7-24.
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V
SW
UV
V
AUX
ZCD
Heavy load
Light load
PWML
PWMH
t
D(PWML-H)
(Heavy load)
t
D(PWML-H)
(Light load)
图7-24. tD(PWML-H) Control Optimized for GaN and Si FETs
7.4.3 EMI Dither and Dither Fading Function
The frequency dither function in AAM reduces the conducted EMI noise and results in EMI filter size reduction.
Conventionally, the dither carrier frequency is in the range of hundreds of Hz. However, when the control loop
bandwidth is pushed higher in order to improve the load transient response, the control loop will be able to
correct the disturbance from the dither signal, and weakens the EMI frequency spreading effectiveness. Even
though increasing the dither frequency to few kHz can reduce the influence of the control loop, the audible noise
issue will occur. For UCC28781-Q1, since itis able to run at a higher switching frequency in AAM, the dither
frequency can be optimized at 23 kHz, so as to avoid audible noise and desensitize the loop response effect on
the EMI attenuation.
UCC28781-Q1 enhances the response of the ZVS control loop, such that the ZVS performance can be
maintained in most switching cycles even under a strong EMI dither condition. A triangular dither signal is
superimposed on the feedback voltage signal VCST, The novel feed-forward control method is applied to allow
the ZVS loop to correct the timing error much faster, so ZVS can be maintained and the efficiency will not suffer.
Conventionally, the dither magnitude is fixed across the whole output voltage range. Since the higher output
voltage condition needs to deliver a higher output power, the EMI issue is typically more severe, so a stronger
dither signal is needed for more conducted EMI reduction. In the lower output voltage condition, the output ripple
specification is usually much tighter, so a strong dither signal may aggravate the output voltage ripple and create
the design tradeoff. For UCC28781-Q1, the two-level dither magnitude is adjusted automatically based on the
output voltage level, so the perturbed output ripple at the lower output voltage condition can be reduced to meet
a more stringent ripple requirement, and the strong dither can still be applied to the higher output voltage
condition for the better EMI performance. Specifically, when VVS is lower than 2.4 V during the demagnetization
time (the LOW_NVO logic signal is high), the peak-to-peak dither magnitude on CS pin is reduced to around 36
mV. When VVS is higher than 2.5 V, the peak-to-peak dither magnitude on CS pin is increased to around 98 mV.
Since the low-line efficiency usually determines the power stage thermal limit, the efficiency will drop further
when EMI dither is enabled. Since the bulk capacitor ripple voltage at low line is bigger than at high line and
AAM mode forces variable frequency operation, the line frequency causes nature dither frequency anyway even
without applying the internal EMI dither. Therefore, taking advantage of AAM mode, the dither function at low line
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can be disabled based on the brown-in voltage setting, so the option provides design flexibility to trade-off the
worst-case low-line efficiency and EMI. Specifically, when iVSL is higher than 646 μA, the EMI dither function is
enabled. When iVSL is lower than 580 μA, the EMI dither function is disabled. If the brown-in point is set at 75
Vac, this means that the EMI dither is disabled for 90 Vac and 115 Vac.
The dither fading feature allows the dither signal to be smoothly disabled, when the output load current is close
to the transition point between AAM and ABM. As shown in 图 7-25, VCST(MAX) and VCST(BUR) are used as the
two voltage-clamping targets to the perturbed VCST signal. When the VCST reaches VCST(MAX), the top of the
VCST ripple content is clipped by the internal clamp circuit, so the influence of the EMI dither on the peak power
capability can be eliminated. When the VCST reaches VCST(BUR), the bottom of the VCST ripple content is clipped
by an another internal clamp circuit, so the influence of the EMI dither on the ABM waveform is removed.
IO
IO(MAX)
IO(OPP)
IO(BUR)
VCST(MAX)
VCST(OPP)
VCST + VCST(EMI)
VCST
VBUR/4
FAULT_OPP
ABM
DITHER_EN
Copyright © 2019, Texas Instruments Incorporated
图7-25. Dither Fading Feature in AAM
7.4.4 Control Law Across Entire Load Range
The UCC28781-Q1 offers six modes of operation summarized in 表 7-1. Starting from heavier load, the AAM
mode forces PWML and PWMH into complementary switching with ZVS tuning enabled. ABM mode generates a
group of PWML and PWMH pulses as a burst packet, and adjusts the burst off-time to regulate the output
voltage. At the same time, the converter confines the burst frequency variation above 20 kHz by adjusting the
number of PWML and PWMH pulses per packet to mitigate audible noise and reduce burst output ripple. In
LPM, SBP1, and SBP2 modes, PWMH and the ZVS tuning loop are disabled, so the converter operates in
valley-switching mode. The survival mode is to maintain VVDD higher than VVDD(OFF) during a long interval of no
switching.
表7-1. Functional Modes
MODE
Adaptive
OPERATION
PWMH
ZVS
AAM
PWML and PWMH in complementary switching
Enabled
Yes
Amplitude
Modulation
ABM
LPM
Adaptive Burst
Mode
Variable fBUR > fBUR(LR), PWML and PWMH in
complementary switching
Enabled
Disabled
Yes
No
Low Power Mode
Fix fBUR ≈fLPM, valley-switching
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表7-1. Functional Modes (continued)
MODE
OPERATION
PWMH
ZVS
SBP1
SBP2
First StandBy
Power Mode
Variable fBUR between fSBP2(LR) and fSBP2(UP), valley-
switching
Disabled
No
Second StandBy Variable fBUR < fSBP2(UP) as VBUR < 0.9 V; Variable fBUR
Power Mode
<
Disabled
No
No
fSBP2(LR) as VBUR > 0.9 V; Both are in valley-switching
INT_STOP
Survival Mode
When VVDD < VVDD(OFF) + VVDD(PCT), a series of PWML
pulses followed by a long PWMH pulse is generated
Enabled in the last
switching cycle of
a survival-mode
burst packet
图 7-26 and 图 7-28 show the critical parameter changes among the five operating modes, where VCST is the
peak current threshold compared with the current-sense voltage from the CS pin, fSW is the switching frequency
of PWML, fBUR is the burst frequency, and NSW is the pulse number of PWML cycles per burst packet. 图 7-26
represents the control mode difference under the two VS-pin voltage ranges, when the IPC-pin voltage is less
than 0.9 V or IPC is connected to AGND. 图7-28 illustrates the modified control mode, when the IPC-pin voltage
setting is higher than 0.9 V. The following section explains the detailed operation of each mode. The following
section discusses VS-pin voltage and IPC-pin voltage effects.
SBP2 SBP1
LPM
SBP2 SBP1
LPM
VCST
VCST
ABM
AAM
ABM
AAM
VCST(OPP)
VCST(OPP)_LV
VCST(BUR)
VCST(BUR)
V
CST_IPC(MIN) =VCST(MIN)
=VCST(MIN)
PO
PO
Frequency
Frequency
fSW
fSW
fBUR(UP2)
fBUR(UP2)
fBUR(LR)
fBUR(UP1)
fBUR
fLPM
fSBP2(UP)
fBUR
fBUR(LR)
fLPM
fSBP2(UP)
PO
PO
NSW
NSW
9
5
4
2
4
2
PO
PO(BUR) PO(OPP)_LV
PO
PO(BUR)
PO(OPP)
图7-27. Control law for VVS < VVSLV(LR) (LOW_NVO
图7-26. Control law for VVS > VVSLV(UP) (LOW_NVO
= 1)
= 0)
Control Law Under Different Load Sweep Direction as VIPC > 0.9 V and VVS > VVSLV(UP)
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SBP2 SBP1
LPM
SBP2 SBP1
LPM
VCST
VCST
ABM
AAM
ABM
AAM
VCST(OPP)
VCST(OPP)
VCST(BUR)
VCST_IPC
VCST(MIN)
VCST(BUR)
VCST_IPC
VCST(MIN)
PO
PO
Frequency
Frequency
fSW
fSW
fBUR(UP2)
fBUR(UP2)
fBUR(UP1)
fBUR(UP1)
fBUR
fBUR(LR)
fBUR
fBUR(LR)
fLPM
fSBP2(UP)
fLPM
fSBP2(UP)
fSBP2(LR)
fSBP2(LR)
PO
PO
NSW
NSW
9
9
4
2
4
2
PO
PO
PO(BUR)
PO(OPP)
PO(BUR)
PO(OPP)
图7-28. Full Load to Light Load
图7-29. Light Load to Full Load
7.4.5 Adaptive Amplitude Modulation (AAM)
The switching pattern in AAM forces PWML and PWMH to alternate in a complementary fashion with dead-time
in between, as shown in 图 7-30. As the load current reduces, the negative magnetizing current (IM-) stays the
same, while the positive magnetizing current (IM+) reduces by the internal peak current loop to regulate the
output voltage. IM+ generates a current-feedback signal (VCS) on the CS pin through a current-sense resistor
(RCS) in series with QL source and a peak current threshold (VCST) in the current loop controls the peak current
variation. Due to the nature of transition-mode (TM) operation, lowering the peak current with lighter load
conditions results in higher switching frequency. When the load current increases to an over-power condition
(IO(OPP)) where VCST correspondingly reaches an OPP threshold (VCST(OPP)) of the peak current loop, the OPP
fault response will be triggered after a 160-ms timeout. The RUN signal stays high in AAM, so the half-bridge
driver remains active.
Heavy Load
IM
Light Load
0 A
IM-
PWML
PWMH
RUN
图7-30. PWM Pattern in AAM
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7.4.6 Adaptive Burst Mode (ABM)
As the load current reduces to IO(BUR) where VCS reaches the VCST(BUR) threshold, the control mode transitions
to ABM starts and VCS is clamped. The peak magnetizing current and the switching frequency (fSW) of each
switching cycle are fixed for a given input voltage level. VCST(BUR) is programmed by the BUR pin voltage (VBUR).
The PWM pattern of ABM is shown in 图 7-31. When RUN goes high, a delay time between RUN and PWML
(tD(RUN-PWML)) is given to allow both the gate driver and the UCC28781-Q1 controller time to wake up from a wait
state to a run state. The first PWML pulse turns on QL close to a valley point of the DCM ringing on the switch-
node voltage (VSW) by sensing the condition of zero crossing detection (ZCD) on the auxiliary winding voltage
(VAUX).
The following switching cycles operate in a ZVS condition, since PWMH is enabled. As the number of PWML
pulses (NSW) in the burst packet reaches its target value, the RUN pin pulls low after the ZCD of the last
switching cycle is detected, and forces the isolated gate driver and controller into a wait state for the quiescent
current reduction of both devices. In this mode, the minimum off-time of the RUN signal is 2.2 µs and the
minimum on-time of PWML is limited to the leading-edge blanking time (tCSLEB) of the peak current loop.
However, more grouped pulses means more risk of higher output ripple and higher audible noise. The following
equation estimates how burst frequency (fBUR) varies with output load and other parameters.
I
f
SW
O
f
=
×
(12)
BUR
I
N
O BUR
SW
As IO < IO(BUR), fBUR can become lower than the audible noise range if NSW is fixed. In ABM, NSW is modulated to
ensure fBUR stays above 20 kHz by monitoring fBUR in each burst period. As IO decreases, fBUR decreases and
reaches a predetermined low-level frequency threshold (fBUR(LR)) of 25 kHz. The ABM loop commands Nsw of
both PWML and PWMH to be reduced by one pulse to maintain fBUR above fBUR(LR). At the same time, the burst
frequency ripple on the output voltage reduces as NSW drops with the load reduction. As IO increases, fBUR
becomes higher and reaches a predetermined high-level frequency threshold (fBUR(UP)). The ABM loop
commands NSW to be increased by one pulse to push fBUR back below fBUR(UP)
.
The maximum NSW and the fBUR(UP) thresholds are modified based on the output voltage condition, i.e., the
positive VS-pin voltage level. When the VVS sampled at the PWMH falling edge is less than the 2.4-V threshold
(VVSLV(LR)), the maximum NSW is 5 pulses and the fBUR(UP2) is 50 kHz. When the sampled VVS is higher than the
2.5-V threshold (VVSLV(UP)), the maximum NSW is 9 pulses, the fBUR(UP2) is 50 kHz for NSW ≤3, and the fBUR(UP1)
is 34 kHz for NSW> 3. The IPC-pin voltage does not affect the parameters in ABM mode.
This algorithm maximizes the number of pulses in each burst packet to improve light-load efficiency, while also
limiting the burst output ripple and audible noise. As IO is close to the boundary between AAM and ABM, the two
burst packets with the maximum pulse count may start to bundle together. In order to mitigate the output ripple
and audible noise concerns, when the bundled burst packet appears two times within eight sequential burst
cycles, the 5-µA current sink into the BUR pin is enabled to reduce VBUR . The less energy per cycle with a lower
VBURwill force the control loop to transition from ABM to AAM smoothly in order to allow the peak current
increase to maintain the output voltage regulation.
tD(RUN-PWML)
VCST(BUR) / RCS
IM
0 A
ZCD
through Vaux
fSW
ZVS
tCSLEB
PWML
PWMH
fBUR
2.2 µs
RUN
图7-31. PWM Pattern in ABM
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7.4.7 Low Power Mode (LPM)
As NSW drops to two in ABM and the condition of fBUR less than fBUR(LR) is qualified under two consecutive burst
periods, the controller enters into LPM mode and disables PWMH. The purpose of LPM is to provide a soft peak
current transition between VCST(BUR) and VCST(MIN). LPM fixes NSW at two and sets fBUR equal to fLPM of 25 kHz.
In LPM mode, VCST is controlled to regulate the output voltage. At the start of each burst packet, after RUN pulls
high, tD(RUN-PWML) is used to wake up both the isolated gate driver and the controller. With PWMH disabled, the
two PWML pulses turn on QL close to valley-switching by sensing ZCD. When ZCD is detected again at the end
of the second pulse, the RUN pin goes low and the controller enters its low-power wait state. For LPM mode with
the SET pin connected to REF, the minimum on-time of PWML can be further reduced to tON(MIN), to allow the
peak magnetizing current to be reduced below the level limited by tCSLEB of the peak current loop. In this
condition, operation of the LPM control loop is changed from a current-mode control to a voltage-mode control,
so the on-time adjustment of PWML is not limited to tCSLEB. With this feature, before fBUR starts to fall below fLPM
and enters the audible frequency range of SBP mode, the peak current is low enough to limit the magnitude of
audible excitation.
tD(RUN-PWML)
VCST(BUR) / RCS
VCST(MIN) / RCS
IM
0 A
tON(MIN)
ZCD through VAUX
PWML
fBUR = fLPM
PWMH
RUN
图7-32. PWM Pattern in LPM
7.4.8 First Standby Power Mode (SBP1)
As VCST drops to VCST(MIN), UCC28781-Q1 enters into SBP1 mode and PWMH continues to stay disabled. The
purpose of SBP1 is to lower fBUR in order to minimize power loss. SBP1 fixes NSW at two and VCST to VCST(MIN)
,
while the burst off-time is adjusted to regulate the output voltage. As fBUR is well below fLPM, the switching-
related loss can be minimized. In addition, lowering fBUR forces both the isolated gate driver and controller to
remain in wait states longer to minimize the static power loss. The equivalent static current of the controller in
SBP can be represented as
2
I
= I
− I
×
+ t
× f
+ I
WAIT
(13)
VDD SBP
RUN
WAIT
D RUN − PWML
BUR
f
SW SBP
tD(RUN-PWML)
VCST(MIN) / RCS
IM
tON(MIN)
PWML
fBUR
PWMH
RUN
IVDD
IRUN
IWAIT
图7-33. PWM Pattern in SBP1
7.4.9 Second Standby Power Mode (SBP2)
When fBUR is below the 8.5-kHz upper burst frequency threshold (fSBP2(UP)), UCC28781-Q1 exits SBP1 mode
and enters into SBP2 mode. Compared with the SBP1 mode, the pulse count is doubled and VCST can be
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programmed by the IPC pin. The VCST programmable range in SBP2 is between 0.27 V and 0.4 V. The purpose
of SBP2 is to further lower fBUR in order to minimize standby power.
The fBUR condition to trigger the mode transition from SBP2 to SBP1 depends on the IPC pin voltage setting as
well. If VIPC is set lower than 0.9 V or the IPC pin is shorted to AGND, VCST is equal to VCST_IPC(MIN), and the
mode transition occurs when fBUR is increased above the same 8.5-kHz threshold. On the other hand, if VIPC is
set higher than 0.9 V, VCST is higher than 0.27 V, and the mode transition occurs when fBUR is increased above
the 1.7-kHz lower burst frequency threshold (fSBP2(LR)). The purpose of skipping the burst frequency range
between 1.7 kHz and 8.5 kHz is to avoid the most sensitive audible frequency range to the human ear. The
frequency skipping is only enabled, when the peak current is set higher by VIPC > 0.9 V.
SBP2 for VIPC < 0.9 V
SBP2 for VIPC ≥ 0.9 V
tD(RUN-PWML)
tD(RUN-PWML)
VCST_IPC / RCS
VCST(MIN) / RCS
IM
IM
tON(MIN)
PWML
PWMH
PWML
PWMH
RUN
IVDD
RUN
IVDD
IRUN
IRUN
IWAIT
IWAIT
Copyright © 2019, Texas Instruments Incorporated
图7-34. PWM Pattern in SBP2
7.4.10 Startup Sequence
图 7-35 shows the simplified block diagram related with the VDD startup function of UCC28781-Q1, and 图 7-36
addresses the startup sequence. 表7-2 describes specific startup waveform time periods.
DAUX
SWS
I
SWS
VDD
R
SWS
I
VDD
QDDS
RDDS
Q
S
V
AUX
V
SW
CSWS
D
UVLO
Q
DDP
SWS
C
VDD
N
AUX
P13
S13
R
DDP
13-V
Regulator
5-V
Regulator
Q
P13
I
P13
IREF
REF
C
P13
D
RUN
P13
Q
S13
CREF
C
S13
图7-35. Functional Startup Block Diagram
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V
V
VDD(BOOST)
VDD(ON)
V
VDD
V
P13
V
P13(OV)
13 V
V
VDD(OFF)
1.8 V
I
P13
I
P13(START)
I
VDD(LIMIT)
I
SWS
RUN
V
S13_OK
V
REF
V
REF_OK
V
S13
PWML
I
VSL
I
RUN
I
VDD
V
V
CST(SM2)
CST(SM1)
(F)
V
CST(MAX)
V
CST
V
O
(A)
(B)
(C)
(D)
(E)
(G)
(H)
(I) (J)
(K)
图7-36. Startup Timing Waveforms
表7-2. Startup Time Intervals
TIME
PERIOD
DESCRIPTION
The UVLO circuit commands the two internal power-path switches (QDDS and QDDP) to close the connections between SWS,
VDD, and P13 pins through two serial current-limiting resistors (RDDS and RDDP). The depletion-mode MOSFET (QS) starts
sourcing charge current (ISWS) safely from the high-voltage switch-node voltage (VSW) to the VDD capacitor (CVDD). Before
VVDD reaches 1.8 V, ISWS is limited by the high-resistance RDDS of 5 kΩ to prevent potential device damage if CVDD or VDD pin
is shorted to ground.
A
B
After VVDD rises above 1.8 V, RDDS is reduced to a smaller resistance of 0.5 kΩ. ISWS is increased to charge CVDD faster. The
maximum charge current during VDD startup can be quantified by Equation 8.
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表7-2. Startup Time Intervals (continued)
TIME
PERIOD
DESCRIPTION
As VVDD reaches VVDD(ON) of 17 V, the ULVO circuit turns-off QDDS to disconnect the source pin of QS to CVDD, and turns-off
QDDP to break the gate-to-source connection of QS, so QS loses its current-charge capability. VVDD then starts to drop, because
the 5-V regulator on REF pin starts to charge up the reference capacitor (CREF) to 5 V, for which the maximum charge current
(ISE(REF)) is self-limited at around 17 mA. After VREF is settled, the UVLO circuit turns-on another power-path switch (QP13), so
an internal 13-V regulator is connected to the P13 pin. The voltage on the P13 pin capacitor (CP13) starts to be discharged by
the regulator.
C
While discharging the recommended 1 µF on CP13 , the sink current of the 13-V regulator (IP13(START)) is self-limited at around
2.2 mA, so it takes longer than 10 μs to settle to 13 V. If VP13 reaches 13 V in less than 10 μs, the P13 pin open fault is
triggered to protect the device. Once VP13 has settled to 13 V without the fault event, RUN pin goes high and the controller
D
E
enters a run state with IVDD = IRUN
.
There is a minimum 2.2-μs delay from RUN going high to PWML starting to switch in order to wake-up the isolated gate driver
and UCC28781-Q1. In this interval, the 2.8-Ω power path switch between the P13 pin and the S13 pin is enabled, so the S13-
pin decoupling capacitor (CS13) is charged up and the charge current is supplied from CP13 and the P13 regulator. If 2.2-μs
delay is timed out before VS13 reaches to the 10-V power good threshold (VS13_OK), the PWML switching instance is further
delayed.
This is the soft-start region of peak magnetizing current. The first purpose is to limit the supply current if the output is short. The
second purpose is to push the switching frequency higher than the audible frequency range during repetitive startup situations.
At the beginning of VO soft-start, the peak current is limited by two VCST thresholds. The first VCST startup threshold (VCST(SM1)
)
is clamped at 0.2 V and the following second threshold (VCST(SM2)) is 0.5 V. When VCST = VCST(SM1), PWMH is disabled if the
F
sampled VS pin voltage (VVS) < 0.28 V, and the first five PWML pulses are forced to stay at this current level. After the sampled
VVS exceeds 0.28 V and the first five PWML pulses are generated, the peak current threshold changes from VCST(SM1) to
VCST(SM2). In case of the inability to build up VO with VCST(SM1) at the beginning of the VO soft-start due to excessively large
output capacitor and/or constant-current output load, there is an internal time-out of 0.7 ms to force VCST to switch to VCST(SM2)
.
When VVS rises above 0.5 V, VCST is allowed to reach VCST(MAX) , so the ramp rate of VO startup becomes faster. When PWML
is in a high state, IVDD can be larger than IRUN, because the 5-V regulator provides the line-sensing current pulse (IVSL) on the
VS pin to sense VBULK condition.
H
J
When VO gets close to the target regulation level, VCST starts to reduce from VCST(MAX)
.
K
VO and VCST settle, and the auxiliary winding takes over the VDD supply.
7.4.11 Survival Mode of VDD (INT_STOP)
When an output voltage overshoot occurs during step-down load transients, the VO feedback loop commands
the UCC28781-Q1 controller to stop switching quickly by increasing IFB, in order to prevent additional energy
from aggravating the overshoot. Since VVDD drops during this time, the typical way to prevent a controller from
shutting down is to oversize the VDD capacitor (CVDD) so as to hold VVDD above VVDD(OFF). Instead, the
controller is equipped with survival-mode operation to hold VVDD above VVDD(OFF) during a transient event.
Therefore, the size of CVDD can be significantly reduced and the PCB footprint for the auxiliary power can be
minimized. Specifically, there is a ripple comparator to regulate VVDD above a 13-V threshold, which is VVDD(OFF)
plus VVDD(PCT) in the electrical table. The ripple regulator is enabled when the VO feedback loop requests the
controller to stop switching due to VO overshoot.
The regulator initiates unlimited PWML pulses when VVDD drops lower than 13 V, and stops switching after VVDD
rises above 13 V. Since VVDD is lower than the reflected output voltage overshoot, most of the magnetizing
energy is delivered to the auxiliary winding and brings VVDD above 13 V quickly. After VO moves back to the
regulation level, VO feedback loop forces the controller to begin switching again by reducing IFB, and the PWML
and PWMH pulses are then controlled by the normal operating mode.
To prevent the controller from getting stuck in survival mode continuously or toggling between SBP and survival
mode at zero load, follow these guidelines for the auxiliary power delivery path to VDD.
• The normal VVDD level under regulated VO must be designed to be above the 13-V threshold by an
appropriate turns count for the auxiliary winding.
• CVDD should not be over-sized, but designed just large enough to hold VVDD > VVDD(OFF) under the longest VO
soft-start time.
• An auxiliary resistor in series with the auxiliary rectifier diode (DAUX) should not be too large of value,
because the lower series impedance can help the VDD capacitor to charge faster.
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• Ensure good coupling between the auxiliary winding (NAUX) and the secondary winding (NS) of the
transformer.
• Ensure that the DC resistance of the auxiliary winding is less than 0.1 ohm.
7.4.12 System Fault Protections
The UCC28781-Q1 provides extensive protections on different system fault scenarios. The protection features
are summarized in 表7-3.
表7-3. System Fault Protection
DELAY TO
ACTION
ACTION BY UCC28781-
Q1
PROTECTION
SENSING
THRESHOLD
VDD UVLO
Brown-in detection
VDD voltage
VS current
None
UVLO reset
V
VDD(OFF) ≤VVDD ≤VVDD(ON)
4 PWML pulses UVLO reset
I
I
VSL ≤IVSL(RUN)
VSL ≤IVSL(STOP)
Brown-out detection VS current
tBO (60ms) plus 3 UVLO reset
confirming PWML
pulses
Over-power
protection (OPP)
CS voltage
CS voltage
CS voltage
tOPP (160 ms)
tFDR restart (1.5s)
V
V
CST(OPP) ≤VCST ≤VCST(MAX)
CST ≤VCST(MAX)
Peak-power limit
(PPL)
Over-current
3 PWML pulses tFDR restart
VCS ≥VOCP
protection (OCP)
Output short-circuit CS, VS, and
protection (SCP) VDD voltages
tFDR restart
(1) VVDD = VVDD(OFF) & VCST ≥VCST(OPP) ; (2) VVDD
= VVDD(OFF) & VVS ≤VVS(SM2)
≤tOPP
Output over-voltage VS voltage
protection (OVP)
3 PWML pulses tFDR restart
VVS ≥VOVP
Over-temperature
protection on FLT
pin (OTP)
FLT voltage
CS voltage
FLT voltage
tFLT(NTC) (50 µs)
R
NTC ≤RNTCTH
UVLO reset until RNTC
RNTCR
≥
Over-temperature
protection on CS pin
(OTP)
2 PWMH pulses tFDR restart
VCS ≥VOCP
Input over-voltage
protection (IOVP)
tFLT(IOVP) (750 µs) UVLO reset until VFLT
VIOVPTH - VIOVPR
<
V
FLT ≥VIOVPTH
Thermal shutdown
Junction
3 PWML pulses UVLO reset
TJ ≥TJ(STOP)
temperature
7.4.12.1 Brown-In and Brown-Out
The VS pin senses the negative voltage level of the auxiliary winding during the on-time of the primary-side
switch (QL) to detect an under-voltage condition of the input DC or AC line. When the bulk voltage (VBULK) is too
low, UCC28781-Q1 stops switching and no VO restart attempt is made until the input line voltage is back into
normal range. As QL turns on with PWML, the negative voltage level of the auxiliary winding voltage (VAUX) is
equal to VBULK divided by primary-to-auxiliary turns ratio (NPA) of the transformer, which is NP / NA. During this
time, the voltage on VS pin is clamped to about 250 mV below AGND. As a result, VAUX can create a line-
sensing current (IVSL) out of the VS pin flowing through the upper resistor of the voltage divider on VS pin (RVS1).
With IVSL proportional to VBULK, it can be used to compare against two under-voltage thresholds, IVSL(RUN) and
IVSL(STOP)
.
The following discussion, equations, and figures involving brown-in and brown-out thresholds are based on AC-
line input conditions, but are generally applicable to DC input voltages as well. For an application using a DC
input, substitute VDC(BI) for VAC(BI), VDC(BO) for VAC(BO) and remove the √2 factor from each equation and figure
in this section.
The target brown-in AC voltage (VAC(BI)) can be programmed by the proper selection of RVS1. For every UVLO
cycle of VDD, there are at least four initial test pulses from PWML to check IVSLcondition. IVSL of the first test
pulse is ignored. If IVSL ≤ IVSL(RUN) is valid for the next three consecutive test pulses, the controller stops
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switching, the RUN pin goes low, and a new UVLO start cycle is initiated after VVDD reaches VVDD(OFF). On the
other hand, if IVSL > IVSL(RUN) occurs, VO soft start sequence is initiated.
VAC(BI )
2
VAC(BI ) 2
NA
RVS1
=
=
NPA ì IVSL(RUN ) NP 365
m
A
(14)
The brown-out AC voltage (VAC(BO)) is set internally by approximately 83% of VAC(BI), which provides enough
hysteresis to compensate for possible sensing errors through the auxiliary winding.
IVSL(STOP)
VAC(BO)
=
VAC(BI ) = 0.83ìVAC(BI )
IVSL(RUN )
(15)
A 60-ms timer (tBO) is used to bypass the effect of line ripple content on the IVSL sensing. Only when the IVSL ≤
IVSL(STOP) condition lasts longer than 60 ms (i.e. typically three line cycles of 50 Hz) and 3 additional switching
cycles verify the condition, the brown-out fault is triggered. If switching is interrupted, the brown-out fault will
remain pending without shut-down until the 3 verification cycles complete. The fault is reset after VVDD reaches
VVDD(OFF). 图 7-37 shows an example of the timing sequence of brown-out and brown-in protections for the case
of an actual input brown-out condition. An application with DC input that has considerable ripple on the bulk
voltage will behave similar to the AC-line bulk-ripple case.
图7-37. Timing Diagram of Brown-Out/Brown-In Response on AC Line Events
The tBO timer is started at the moment IVSL ≤ IVSL(STOP) is detected during the PWML on-time. The timer is
cleared when IVSL > IVSL(STOP) is detected. In the case of an overshoot voltage on the output, switching will stop
until the output voltage recovers to the regulation level. If the tBO timer is triggered by IVSL ≤ IVSL(STOP) while in
the valley of the bulk ripple voltage, and then switching is stopped the status of IVSL cannot be detected and
updated. The timer cannot be cleared without switching to sample IVSL, and the 60-ms timer may elapse even
though no brown-out condition exists. To prevent an unwarranted shut-down, the 3 additional switching cycles
sample the condition once switching does resume, to verify or dismiss the pending apparent brown-out fault. An
extended output overshoot condition longer than tBO can result from a sudden load drop combined with a drop in
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the regulation reference due to reduction of cable compensation. 图 7-38 shows an example of the timing
sequence for the case of an apparent brown-out cancelled by 3 verifying pulses.
图7-38. Timing Diagram of Brown-Out Response on Extended Output Overshoot
7.4.12.2 Output Over-Voltage Protection (OVP)
The VS pin is used to sense the positive voltage level of the auxiliary winding voltage (VAUX) to detect an over-
voltage condition of VO. When an OVP event is triggered, the auto-recovery version of OVP stops switching and
there is a 1.5-s fault recovery time (tFDR) before any VO restart attempt is made. As QL turns off, the settled VAUX
is equal to (VO+VF) x NAS, where NAS is the auxiliary-to-secondary turns ratio of the transformer, NA / NS, and VF
is the forward voltage drop of the secondary-side rectifier. The VS pin senses VAUX through a voltage divider
formed by RVS1 and RVS2. The pin voltage (VVS) is compared with an internal OVP threshold (VOVP). If VVS ≥
VOVP condition is qualified for three consecutive PWML pulses, the controller stops switching, brings RUN pin
low, and initiates the 1.5-s time delay. During this long delay time, only the UVLO-cycle of VVDD is active, and
there are no test pulses of PWML. After the 1.5-s timeout is completed and VVDD reaches the next VVDD(OFF), a
normal start sequence begins. The calculation of RVS2 is
RVS1 ìVOVP
RVS1 ì4.5V
RVS2
=
=
NAS ì(VO(OVP) +VF ) -VOVP (NA / NS )(VO(OVP) +VF ) - 4.5V
(16)
The long tFDR timer (1.5 s) helps to protect the power stage components from the large current stress during
every restart and allows some time for VO to discharge in the case of light-load or no-load, before attempting
restart.
7.4.12.3 Input Over Voltage Protection (IOVP)
The UCC28781-Q1 provides an input OVP function on the FLT pin. 图 7-39 shows the application circuit for the
input OVP sensing. A resistor divider senses the bulk capacitor voltage, and the IOVP fault is triggered when
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VFLT > 4.5 V for longer than 750 µs. The 750 µs delay helps to desensitize the abrupt bulk voltage spike during
the line surge condition, such that the output voltage will not drop accidentally. After the IOVP fault is asserted,
the switching will be terminated immediately and VVDD will restart. When VVDD reaches VVDD(ON) of the following
VDD cycle, the controller will check VFLT first before switching, to avoid the switching device from being exposed
to a high-voltage stress condition. The fault will be cleared when VFLT < 4.43 V.
If longer than 750 µs delay is required, a filter capacitor between the FLT pin and AGND pin can create
additional programmable delay. If the filter capacitor is too large, it may trigger the OTP fault on the FLT pin, if
the ramp up time for VFLT to rise above VNTCTH is longer than tFLT(NTC) after the RUN pin is pulled high. The
resistor divider design does not need to consider the offset voltage effect from the 50 µA current source out of
the FLT pin, because the controller will disable the current source once VFLT > 2.5 V.
The goal of the internal 5.5-V clamp device on the FLT pin is to protect the pin from exceeding the voltage limit
when one of the IOVP upper sensing resistor fails short. The maximum clamp current is 150 µA, so the resistor
divider design needs to consider this limitation.
VBULK
IFLT
RFLT1
VIOVP
RFLT2
INPUT OVP FAULT
OTP FAULT
œ
tFLT(IOVP) delay
(750µs)
(4.5V/4.43V)
FLT
+
VFLTZ
(5.5V)
RFLT3
CFLT
+
tFLT(NTC) delay
(50µs)
VNTCTH
(0.5V/1.15V)
œ
Copyright © 2019, Texas Instruments Incorporated
图7-39. Bulk Capacitor Voltage Sensing for Input OVP
7.4.12.4 Over-Temperature Protection (OTP) on FLT Pin
The UCC28781-Q1 uses an external NTC resistor (RNTC) tied to the FLT pin to program a thermal shutdown
temperature near the hotspot of the converter. The NTC shutdown threshold (VNTCTH) of 0.5 V with an internal
50-μA current source flowing through RNTC results in a 10-kΩ thermistor shutdown threshold. If the NTC
resistance stays lower than 10 kΩ for more than 50 μs, an OTP fault event is triggered. The 50-μs delay
(tFLT(NTC)) allows a filter capacitor (CFLT) to be placed between the FLT pin and the AGND pin, when the NTC
resistor is located far away from the controller but close to the hot spot. To avoid the OTP fault from false trigger
as RUN goes high, CFLT should be designed to allow VFLT increased above VNTCTH within tFLT(NTC). On the other
hand, if the NTC resistor is close to the controller and there is no potential noise coupling path to the sensing
traces, CFLT is not needed.
For auto-recovery mode, the 0.5-V threshold is increased to 1.15 V after the OTP fault, so the NTC resistance
has to increase above 23 kΩ to reset the OTP fault. This threshold change provides a safe temperature
hysteresis to help the hot-spot temperature cool down before the next VO restart attempt, reducing the thermal
stress to the components. If the FLT pin is not used, the pin can be left floating but can not be connected to REF
pin, since the line OVP will be falsely triggered.
The thermal issue in the heavy output load condition is the main design consideration for OTP, and the heavy
load operating mode, AAM, allows the controller to stay in the run state continuously, so the 50-μs delay allows
VFLT to trigger OTP. Based on the practical BUR-pin setting, 50% to 60% load is operated in AAM. The 50-μA
current source is disabled in the burst off time of the light load modes such as ABM, LPM, SBP1, and SBP2, in
order to save standby power. However, when the run state becomes shorter than the 50-μs in these modes but
the current source is disabled in the wait state, the OTP will not be able to trigger because there is not enough
time to detect the fault. Therefore, if certain design considerations still require the OTP to be armed in light load
modes, a second OTP configuration can be considered by reusing the 4.5-V threshold of input OVP. As shown in
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图 7-40, the upper NTC resistor and the lower resistor form a resistor divider from the REF pin to the FLT pin.
The 750-μs delay is independent to the wait state condition of controller, so the OTP fault can still be triggered
in the light load mode. This configuration provides auto-recovery mode only.
1st OTP Sensing
2nd OTP Sensing
REF
RNTC
FLT
FLT
RNTC
RFLT
CFLT
CFLT
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图7-40. Two Connections to Implement OTP on the FLT Pin
1.15 V
VNTC
0.5 V
tFLT(NTC)
tFLT(NTC)
OTP Fault
VVDD
VVDD(ON)
VVDD(OFF)
PWML
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图7-41. OTP Timing Diagram for a NTC between the FLT Pin and AGND Pin
7.4.12.5 Over-Temperature Protection (OTP) on CS Pin
In case the FLT pin is already used for the input OVP sensing, UCC28781-Q1 provides the third and fourth OTP
functions on the CS pin. The two configurations do not affect the current sense signal on the CS pin and the
OPP level, because the two sensing circuits are only biased after PWML is off. 图 7-42 shows the two
application circuits. For the third OTP configuration, when the PWMH pin is pulled high, RNTC and ROPP form a
resistor divider to create a temperature-dependent voltage signal on the CS pin. When the voltage exceeds the
1.2-V threshold sampled before the end of the demagnetization time (TDM) for two successive cycles, the OTP
fault will be triggered. The OTP sensing circuit will not affect the operation of the peak current loop, since the
PWMH is pulled low in the PWML on time duration. For auto-recovery mode, the long 1.5-s timer starts and the
controller stays in fault state without switching. This long recovery time provides a temperature hysteresis to help
the hot-spot temperature cool down before the next VO restart attempt. Compared with the first OTP
configuration on the FLT pin, this configuration allows the OTP armed in both AAM and ABM, so the OTP can
still be triggered at around 25% output load. Compared with the second OTP configuration from FLT pin, this
configuration supports both auto-recovery and latch-off modes.
The fourth configuration with a small-signal PMOS is the most comprehensive way to cover a wide output load
range and support both auto-recovery and latch-off modes at the same time. The RUN pin is used to bias the
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sensing circuit, and the PMOS gate is controlled by the PWML pin to only allow the detection to occur when
PWML is low.
3rd OTP Sensing
4th OTP Sensing
RUN
PWML
PWMH
QRUN
RNTC
RNTC
ROPP
ROPP
CS
CS
RCS
RCS
CCS
CCS
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图7-42. Two Connections to Implement OTP on the CS Pin
7.4.12.6 Programmable Over-Power Protection (OPP)
The over-power protection (OPP) allows operation in an over-power condition for a limited amount of time, so the
UCC28781-Q1 can support a power stage design with temporary peak power requirements. As shown in 图
7-43, when VCST is higher than the threshold voltage of the OPP curve (VCST(OPP)), a 160-ms timer starts. For
the auto-recovery mode, if VCST remains higher than VCST(OPP) continuously for 160 ms, the 1.5-s timer starts
and the controller stays in fault state without switching. This long recovery time reduces the average current
during a sustained over-power event. The system benefits includes the reduction of thermal stress in high
density adapters and the protection of its output cable.
The OPP function uses IVSL as a line feed-forward signal to vary VCST(OPP) depending on VBULK, in order to
make the OPP trigger point constant over a wide line voltage range. The UCC28781-Q1 allows programmability
of the OPP curve by adding a line-compensation offset voltage on the CS pin through a resistor (ROPP
)
connected between the CS pin and current-sense resistor (RCS). An internal current source flowing out of CS pin
creates the offset voltage on ROPP. This current level is equal to IVSL divided by a constant gain of KLC. As ROPP
increases, the OPP trigger point becomes lower at high line, so lower peak magnetizing current is allowed to run
continuously.
The OPP function uses VVS as an output voltage feed-forward signal to modify the line-dependent VCST(OPP)
curve into the two different sets, such that the OPP trigger point can be more consistent across a wide output
voltage range. The higher OPP threshold under VVS > 2.5 V contains two piece-wise linear regions, and the
lower OPP threshold under VVS < 2.4 V contains one piece-wise linear region.
The highest threshold of OPP curve (VCST(OPP1)) of 0.6 V helps to determine RCS value at VBULK(MIN)
.
VCST (OPP1)
RCS =
P
VBULK (MIN )tD(CST )
2
O(OPP)
-
VBULK (MIN )
h
DMAX
LM
(17)
where PO(OPP) is the output power that triggers OPP, and tD(CST) is the sum of all delays in the peak current loop
which contributes additional peak current overshoot. tD(CST) consists of propagation delay of the low-side driver,
current sense filter delay (ROPP x CCS), internal CS comparator delay (tD(CS)), and nonlinear capacitance delay of
QL. After RCS is determined, ROPP can be adjusted to keep a similar OPP point at highest line. Note that setting
the OPP trigger point too far away from the full power may introduce more challenge on the thermal design,
since the converter runs continuously with more power as long as the corresponding peak current is slightly less
than OPP threshold.
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VCST
VCST(MAX) for VVS > VVSLV(UP)
VCST(MAX)_LV for VVS < VVSLV(LR)
VCST(OPP) for VVS > VVSLV(UP)
VCST(OPP)_LV for VVS < VVSLV(LR)
0.8 V
0.655 V
0.628 V
0.6 V
0.57 V
0.54 V
0.491 V
0.471 V
0.4275V
0.405V
iVSL
233 µA 433 µA
966 µA
Copyright © 2019, Texas Instruments Incorporated
图7-43. VCST OPP curve across IVSL
tOPP Timer
tFDR Timer
160ms
1.5s
VVDD(ON)
VVDD
VVDD(OFF)
IO
VCST(MAX)
VCST(OPP)
VCST
VCST(SM2)
VCST(SM1)
PWML
VO
图7-44. Timing Diagram of OPP
7.4.12.7 Peak Power Limit (PPL)
The peak current threshold of the OPP curve is used to initiate the 160-ms timer, while the peak power limit
(PPL) determines the highest controllable peak current of the peak current loop, VCST(MAX). Regardless of VVS
,
the ratio between VCST(MAX) and VCST(OPP) is fixed at approximately 4/3. In other words, this feature provides the
highest short duration peak power (PO(MAX)) that the converter can deliver. The line-dependent PPL curve is able
to achieve a consistent peak power level over a wide input voltage range. As an example, to supply a highest
peak power of 150% of nominal rated load, choose an RCS value that ensures that the peak current threshold at
150% load and VBULK(MIN) must not be above VCST(MAX). Then, the threshold of the OPP power (PO(OPP)) can be
programmed to approximately 112% to support 150% peak power design, based on the following equation.
V
CST OPP1
0.6 V
0.8 V
P
=
× P
=
× P
O max
(18)
O OPP
O max
V
CST max
Additionally, before VO reaches steady-state regulation during VO soft-start, the highest VCST can also reach
VCST(MAX). The transformer maximum flux density must have sufficient design margin to the high-temperature
saturation limit of the core material at the peak current while in PPL.
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7.4.12.8 Output Short-Circuit Protection (SCP)
When a short-circuit is applied to the converter output, the peak current reaches the PPL limit and triggers the
160-ms OPP fault timer. During this event, the VDD recharge supply is lost due to the auxiliary winding voltage
being close to 0 V. Without additional short-circuit detection, if VVDD reaches VVDD(OFF) before the 160-ms
timeout, the 1.5-s recovery time for the OPP fault cannot be triggered but only a UVLO recycle is performed. To
remedy this scenario, as VVDD reaches VVDD(OFF), the UCC28781-Q1 checks two additional parameters to
identify the short-circuit event at the output, and triggers the fault response without waiting for 160 ms to expire.
Specifically, when VVDD reaches VVDD(OFF), if either VCST is greater than the OPP threshold (VCST(OPP)) or the
VS-pin voltage is less than 0.5 V, the 1.5-s recovery delay is initiated for auto-recovery mode. With this additional
layer of intelligence, the average load current during continued short-circuit event can be greatly reduced, and
thus also the thermal stress on the power supply.
7.4.12.9 Over-Current Protection (OCP)
The UCC28781-Q1 operates with cycle-by-cycle primary-peak current control. The normal operating range of the
CS pin threshold is between VCST(MIN) and VCST(MAX). If the voltage on CS exceeds the 1.2-V over-current level
at any instant after the internal leading edge blanking time (tCSLEB) and before the end of the transformer
demagnetization, for three consecutive PWML cycles, the device stops switching, RUN pin goes low, and the
OCP fault response is triggered. Similar to OVP, OPP, and SCP, only the UVLO-cycle of VDD is active and there
are no test PWML pulses at all. For auto-recovery, when VVDD reaches the next VDD(OFF) after the 1.5-s time-out
is completed a normal start sequence begins.
7.4.12.10 External Shutdown
The REF pin may be used as an external shutdown function by shorting this pin to AGND with a small-signal
control switch. This provides an additional design flexibility for the control function extension with external
circuitry. When the REF-pin voltage drops lower than its internal power good threshold (approximately 4.5 V), the
switching action will be terminated and VVDD will drop to VVDD(OFF), and the controller begins the UVLO restart
cycle.
As long as the REF pin is shorted to AGND continuously, the UVLO restart cycle will repeat and switching action
is inhibited until the external pull-down on REF is released. During the switch-short condition on REF, the falling
slope of VVDD will drop faster than normal case due to the 17-mA over-current limit of the REF regulator which
discharges the VDD capacitor faster than the normal IVDD currents in the run and wait states.
7.4.12.11 Internal Thermal Shutdown
The internal over-temperature shutdown threshold is higher than 125°C. If the junction temperature of the device
reaches this threshold, the device initiates a UVLO reset and restart fault cycle. If the temperature is still high at
the end of the UVLO cycle, the protection cycle repeats. This internal protection is not suitable as a substitute for
the NTC for hot-spot temperature protection. An NTC thermistor provides more accurate temperature sensing
and may be placed in a remote location for less compromise on PCB layout.
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7.4.13 Pin Open/Short Protections
As summarized in 表 7-4, UCC28781-Q1 strengthens the protections of several critical pins under "open" and
"short" conditions, such as CS, P13, RDM, and RTZ pins. The pin protections are all in auto-recovery modes. All
"short" conditions are defined as short-circuits to AGND.
表7-4. Protections for Open and Short of Critical Pins
DELAY TO
ACTION
PROTECTION
SENSING
CONDITION
> 2 μs (VSET = 5 V)
ACTION
PWML on-time at first PWML
pulse only
> 2 μs (VSET = 0 V, RRDM
RRDM(TH)
≥
CS pin short
none
tFDR restart (1.5 s)
)
> 1 μs (VSET = 0V, RRDM < RRDM(TH)
)
3 PWML
pulses
CS pin open
P13 pin open
CS voltage
P13 voltage at UVLOON
P13 voltage
tFDR restart (1.5 s)
UVLO reset
VCS ≥VOCP
none
VP13 drops to 14 V within 10 μs
P13 pin over
voltage
3 PWML
pulses
UVLO reset
V
P13 ≥VP13(OV) + VP13(REG)
RDM pin short
RDM pin open
RTZ pin short
RTZ pin open
RDM current at UVLOON
RDM current at UVLOON
RTZ current at UVLOON
RTZ current at UVLOON
VRDM = 0 V, self-limited IRDM
RDM = Open
none
none
none
none
UVLO reset
UVLO reset
UVLO reset
UVLO reset
VRTZ = 0 V, self-limited IRTZ
RTZ = Open
XCD pin over
voltage
XCD voltage
VXCD > VXCD(OVP)
UVLO reset
750 μs
7.4.13.1 Protections on CS pin Fault
UCC28781-Q1 identifies a fail-short event on the CS pin by monitoring the on-time pulse width of the first PWML
pulse after VVDD startup is completed. As shown in 图7-36, the normal first on-time pulse width should be limited
by the clamped VCST(SM1) level of 0.2 V and the rising slope of the current-loop feedback signal from the current-
sense resistor (RCS) to the CS pin. When the current feedback path is gone due to a CS pin short to GND, the
peak magnetizing current increases and potentially can damage the power stage. Therefore, a maximum on-
time of the first PWML pulse for VSET = 5 V, tCSF1 of 2 μs in the electrical table, is used to limit the first peak-
current stress of the silicon-based converter and then will trigger a CS pin short protection which initiates the
tFDR recovery of 1.5 s in auto-recovery mode.
Additionally, tCSF0 in the electrical table confines the maximum on-time of the first PWML pulse on the GaN-
based converter with VSET = 0 V. There are two corresponding values based on two predetermined ranges of the
RDM pin setting in order to provide the protection over a wider switching frequency range. Specifically, tCSF0 is
set at 2 μs with RRDM higher than the RRDM(TH) threshold of 55 kΩ, while tCSF0 is reduced to 1 μs under RRDM
<
RRDM(TH). Since a GaN-based converter is capable of operating at higher switching frequency with lower
magnetizing inductance (LM), it is possible that the peak current can be increased higher than a lower switching-
frequency design under the same VCST(SM1) level and same on-time of PWML. The RDM pin can provide a good
indication of the switching frequency range of a GaN power stage, since the lower LM requires smaller RRDM
setting. With a different tCSF0 setting, the CS pin fault adapts to a wide switching frequency range.
Unlike a CS pin short protection which senses only the first on-time pulse width of PWML only, CS pin open
protection monitors the fail-open condition cycle-by-cycle. An internal 4-μA current source out of the CS pin is
used to pull the CS pin voltage up to 3.3 V as the CS pin exhibits high impedance during a fail-open condition. If
the CS voltage is higher than the 1.2-V threshold of the OCP limit and lasts for three consecutive PWML pulses,
the CS pin open protection is triggered which initiates the 1.5-s recovery.
7.4.13.2 Protections on P13 pin Fault
As shown in 图 7-36, after VVDD reaches VVDD(ON), an internal 13-V regulator on the P13 pin should force VP13
back to the regulation level before PWML starts switching. If the recommended P13-pin capacitor (CP13) of 1 µF
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and the connection to the depletion-mode MOSFET (QS) are in place, the settling time of VP13 to 14 V is much
longer than 10 μs with a limited 1.9-mA sink current of the regulator (IP13(START)) to discharge CP13
.
The first fault scenario is that if CP13 is too small, or the P13 pin is open, the pin is not able to control QS correctly
for the high-voltage sensing function of ZVS control, so no switching action will be performed. When either two
situations happen, VP13 settles to 13 V very quickly instead. Therefore, after a 10-μs delay from the instant of
VVDD reaching VVDD(ON), UCC28781-Q1 checks if VP13 is below 14 V for the pin-fault detection, and then
performs one UVLO cycle of VDD directly without switching as the protection response.
The above protection is to prevent the controller from generating PWM signals. However, when the P13 pin is
open and disconnected from the QS gate, the source voltage of QS keeps increasing. To protect the P13-pin
open event, a small Zener diode (DP13) between QS gate to AGND should be used to limit the QS source
voltage. DP13 should be higher than VVDD(ON) , so as to prevent interference with normal VDD startup. A 20-V
Zener diode is recommended.
The second fault scenario is the over-voltage condition of P13 pin after the converter starts switching. When the
switch-node voltage (VSW) rises with a high dV/dt condition, there is a charge current flowing through the junction
capacitance of QS, and part of the current can charge up CP13. If the overshoot is too large, the voltage on the
SWS pin also increases due to the nature of depletion-mode MOSFET operation. UCC28781-Q1 detects the
overshoot event on P13 pin with a 15-V over-voltage threshold cycle-by-cycle. When VP13 is higher than 15 V for
three consecutive PWML pulses, the P13 over-voltage protection is triggered which performs one UVLO cycle of
VDD.
The third fault scenario is an P13 pin short event at the beginning of VDD startup, and QS is unable to charge up
the VDD capacitor to VDD(ON), so there is no chance to enable the controller.
7.4.13.3 Protections on RDM and RTZ pin Faults
Since RDM and RTZ pins are the critical programming pins for ZVS control, UCC28781-Q1 offers both open-
circuit and short-to-GND protections for those pins. At initial start-up when VVDD reaches VVDD(ON) and before
switching begins, a fixed voltage level is applied to each pin and the corresponding current level flowing out of
the pin is sensed to detect a pin-fault condition. As a result, too small of a current represents the pin-open state,
and too large of a current represents the pin-short state where the short-circuit current level is self-limited.
In general, maintain 2 kΩ< RRDM < 500 kΩand 20 kΩ< RRTZ < 1.1 MΩwith ample margins to avoid triggering
one of these faults. When a pin-fault condition is identified, no switching is allowed and one UVLO cycle of VDD
is triggered as the protection response. The normal start-up sequence will proceed on the next VDD cycle after
the fault condition is removed.
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8 Application and Implementation
备注
以下应用部分中的信息不属于 TI 元件规格,TI 不担保其准确性和完整性。TI 的客户负责确定元件是否
适合其用途,以及验证和测试其设计实现以确认系统功能。
8.1 Application Information
A typical application of a high-frequency zero-voltage switching flyback (ZVSF) converter, using the UCC28781-
Q1 controller, is to enable high-density DC-to-DC or AC-to-DC power supply design which complies with
stringent global and application-specific efficiency standards and high-density power packaging. Both Silicon (Si)
and Gallium Nitride (GaN) power MOSFETs may be used, with appropriate gate drivers for either (if necessary).
8.2 Typical Application Circuit
The following application circuit implements a 60-W, 15-V Si-based ZVSF power stage with the SET pin
connected to the REF pin.
Transformer
FDC
VO
VBULK
VDC
LK
CBULK
LM
NP
NS
CO
GND
QSR
DRUN
Isolated Driver
(primary side)
Isolated Driver
(secondary side)
VP13
CRUN
QS
DSWS
PWMH
RUN
QL
RSWS
PWML
VSWS
PGND
RBIAS1
CSWS
VRCS
DAUX
RCS
RBIAS2
CVDD1
NA
CC/CV
Controller
VP13
VS13
DP13
CVDD2
CP13
RVS1
RVS2
VS
XCD
GTP3 GTP2 GTP1
VDD
P13
S13
SWS
VSWS
XCD
VREF
RUN
RUN
UCC28781
PWMH
PWMH
PWML
PGND
PWML
PGND
BUR
SET
REF
FB RDM RTZ TP AGND FLT IPC
CS
ROPP
VRCS
VREF
CFB
CREF
CCS
RFB
图8-1. Typical Application Circuit
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8.2.1 Design Requirements for a 60-W, 15-V ZVSF Bias Supply Application with a DC Input
表8-1. Electrical Performance Specifications using Si FET(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CHARACTERISTICS
VIN
Input line voltage (DC)
50
400
47
500
V
VIN = 500 VDC, IO = 0 A
mW
mW
Input power at no-load,
VO = 15 V
PSTBY
VIN = 250 VDC, IO = 0 A
36
OUTPUT CHARACTERISTICS
VIN = 250 to 500 VDC, IO = 4.0 A to 0 A
VIN = 40 to 250 VDC, IO = 2.0 A to 0 A
14.7
15
15.3
V
VO
Output voltage
Full-load rated output current,
high input range
4
2
A
A
IO(FL_HI)
IO(FL_LO)
VIN = 250 to 500 VDC
Full-load rated output current,
low input range
VIN = 40 to 250 VDC
Output ripple voltage, peak to
peak, high input range
500 mVpp
300
VIN = 250 to 500 VDC, IO = 0 A to 4 A
VIN = 40 to 250 VDC, IO = 0 A to 2 A
350
200
VO_pp
Output ripple voltage, peak to
peak, low input range
PO(OPP)
tOPP
Over-power protection threshold VIN = 40 to 500 VDC
70
W
Over-power protection duration
VIN = 40 to 500 VDC, PO > PO(OPP)
160
ms
Output voltage transient deviation IO steps between 0 A and IO(FL_HI) at 100 Hz
at load-step
±1000 mVpp
ΔVO
SYSTEM CHARACTERISTICS
VIN = 500 VDC, IO = 4 A
0.932
0.937
0.905
0.919
0.808
0.835
25°C
ηFL
Full-load efficiency(2)
VIN = 250 VDC, IO = 2 A
VIN = 500 VDC
ηavg
4-point average efficiency(3)
VIN = 250 VDC
VIN = 500 VDC, IO = 10% of IO(FL_HI)
VIN = 250 VDC, IO = 10% of IO(FL_LO)
VIN = 90 to 264 VDC, VO = 20 V, IO = 0 to 3.25 A
η10%
Efficiency at 10% load
TAMB
Ambient operating temperature
range
(1) The performance listed in this table is based on the test results from a single board, using either DC input or AC input for their
respective results.
(2) Power losses from external input and output cables are not included in efficiency results.
(3) Average efficiency of four load points: IO = 100%, 75%, 50%, and 25% of IO(FL)
.
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8.2.2 Detailed Design Procedure
8.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
For off-line rectified-AC applications, the total input bulk capacitor (CBULK) should be sized to provide energy
from the peak of the minimum input AC-line rms voltage (VIN(MIN)) to the minimum allowable voltage (VBULK(MIN)
)
for the power conversion stage. Due to the transition-mode operation, too low of VBULK(MIN) selection results in
higher rms current at VIN(MIN) and affects the full-load efficiency, while too high of VBULK(MIN) enlarges the volume
of the bulk capacitor. This equation does not account for the hold-up time requirement over AC-line dips and
drop-outs.
VBULK (MIN )
P
1
O
ì[0.5+ ìarcsin(
)]
h
p
2 ìVIN (MIN )
(2ìVIN (MIN ) -VBULK (MIN )2 ) ì fLINE
CBULK (MIN )
=
2
(19)
For DC-input applications, the value of CBULK depends on the nature of the input:
• If the DC source is subject to brief interruptions (similar to dips and drop-outs of an AC-line), then the value of
CBULK is calculated in a similar manner as for CBULK(MIN) above. ΔtDC_drop represents the maximum expected
interruption time of the DC input.
P
O
× Δt
DC_drop
η
C
=
(20)
BULK MIN
2
2
V
− V
DC_IN MIN
BULK MIN
• If the DC source is consistently steady such as from a high-voltage battery, then the value of CBULK should be
sufficient to effectively by-pass the high-frequency primary switching current to avoid conducting significant
EMI noise back to the source.CBULK may be made up of more than one capacitor. Select standard values with
sufficient margin to the calculated CBULK(MIN) to allow for tolerance and aging.
8.2.2.2 Transformer Calculations
8.2.2.2.1 Primary-to-Secondary Turns Ratio (NPS
)
NPS is a ratio of primary winding turns to secondary winding turns and although each winding must have a whole
number of turns, the ratio of the two is not required to be a whole number. The choice of NPS influences the
design tradeoffs on the voltage ratings between primary and secondary switches, and the balance between the
magnetic core and winding loss of the transformer, which are explained in more detail as follows:
1. Maximum NPS (NPS(MAX)) is limited by the maximum derated drain-to-source voltage of QL (VDS_QL(MAX)). In
the expression below, ∆VCLAMP is the total voltage deviation above VBULK when the primary TVS or RCD
clamp absorbs the leakage inductance energy of the trasnformer when QL turns off. VO is the output voltage,
and VF is the forward voltage drop of the secondary rectifier.
VDS _QL(MAX ) -VBULK (MAX ) - DVCLAMP
NPS(MAX )
=
VO +VF
(21)
2. Minimum NPS (NPS(MIN)) is limited by the maximum derated drain-to-source voltage of the secondary rectifier
(VDS_SR(MAX)). In the expression for NPS(MIN), ∆VSPIKE should account for any additional voltage spike higher
than VBULK(MAX)/NPS that occurs when QSR is active and turns-off at non-zero current in AAM and ABM
modes.
VBULK(MAX )
NPS(MIN )
=
VDS _ SR(MAX ) -VO - DVSPIKE
(22)
3. The winding loss distribution between the primary and secondary side of the transformer is the final
consideration. As NPS increases, primary RMS current reduces, while secondary RMS current increases.
Conversely, as NPS decreases, primary RMS current increases, while secondary RMS current reduces.
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8.2.2.2.2 Primary Magnetizing Inductance (LM)
After NPS is chosen, LM can be estimated based on minimum switching frequency (fSW(MIN)) at VBULK(MIN)
,
maximum duty cycle (DMAX), and output power at highest nominal output voltage, nominal full-load current
(PO(FL)). The choice of fSW(MIN) should consider the expected range of switching frequency as bulk voltage
increases from minimum to maximum and as load falls from maximum to the burst mode threshold. KRES
represents the duty cycle loss to wait for the switch-node voltage transition from the reflected output voltage to
zero. Typically, fSW may extend to 200% to 300% fSW(MIN) or higher. A KRES value of 5% to 6% is used as an
initial estimate for GaN-based power stages, while ~10% is more appropriate for Si-based designs. The
selection of minimum switching frequency (fSW(MIN)) should consider the impact on full-load efficiency and EMI
filter design.
NPS (VO +VF )
VBULK(MIN ) + NPS (VO +VF )
DMAX
=
(23)
(24)
2
DMAX VBULK (MIN )
2
h
(1- KRES
fSW (MIN )
)
LM =
ì
2P
O(FL)
8.2.2.2.3 Primary Winding Turns (NP)
The number of turns on the primary winding (NP) of the transformer is determined by two design considerations:
1. The maximum flux density (BMAX) must be kept below the saturation limit (BSAT) of the chosen magnetic core
under the highest peak magnetizing current (IM+(MAX)) condition, the cross-sectional area (AE) of the core,
and highest core temperature. When IFB = 0 A, such as during VO soft-start or step-up load transient, the
peak magnetizing current reaches IM+(MAX), since VCST = VCST(MAX) in those conditions. IM+(MAX) can be
estimated based on the output power triggering an OPP fault (PO(OPP)) with VCST = VCST(OPP1) at VBULK(MIN)
.
2P
VCST (MAX )
VCST (OPP1)
O(OPP)
IM +(MAX )
=
DMAXVBULK (MIN )
h
(25)
LM IM +(MAX )
BMAX
=
< BSAT
NP AE
(26)
2. The AC flux density (ΔB) affects the core loss of the transformer. For a transition-mode ZVS flyback, the
core loss is usually highest at high line, since the switching frequency is highest, duty cycle is smallest, and
peak-to-peak magnetizing current swing is greatest for a given load condition. The following equation is the
ΔB calculation including the contribution of negative magnetizing current (IM-), used to put into the
Steinmetz equation for more accurate core loss estimation. For VBULK ≥NPS(VO+VF), IM- is calculated with
VBULK divided by the characteristic impedance of LM and the lumped time-related switch-node capacitance
(CSW). IM- is always a negative value. The expression of fSW is derived based on the triangular
approximation of the magnetizing current, which also considers the effect of IM- over wide DC or AC input
line conditions.
CSW
IM - = -
VBULK
LM
(27)
(28)
P
1
O(FL)
IIN
=
h
VBULK
NPS (VO +VF )
VBULK + NPS (VO +VF )
D =
(29)
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D2VBULK
2LM IIN - DLM IM - + DVBULK ì0.5
fSW
=
p
LM CSW
(30)
2P
O(FL)
2
IM +
=
+ IM -
h
LM fSW
(31)
(32)
LM (IM + - IM -
NP AE
)
DB =
For the ΔB calculation, remember that IM- is a negative value and that ΔB is a peak-to-peak flux swing. Core
loss is based on ½ of ΔB.
8.2.2.2.4 Secondary Winding Turns (NS)
After NP is chosen, NS can be calculated using the target NPS. NS and NP are adjusted to the nearest suitable
integers.
NP
NS =
NPS
(33)
Once NP and NS are finalized, the actual NPS is recalculated. With the new NPS value, 节 8.2.2.2.2 and follow-on
parameters are also recalculated to reflect the updated NPS parameter change.
8.2.2.2.5 Auxiliary Winding Turns (NA)
Turns of the auxiliary winding (NA) is an integer value usually chosen to provide a nominal VVDD that satisfies all
devices powered from VVDD, such as a gate driver, or the UCC28781-Q1. NA is determined by the following
design considerations:
1. VVDD must be lower than the maximum rating voltage of VDD pin (VVDD(MAX)) at maximum output voltage
and rectifier forward drop (VO(MAX) + VF). VVDD(MAX) is also limited by the lowest maximum voltage rating of
any other devices connected to the VDD pin. For designs with a fixed output voltage or a narrow output
range, the maximum Auxiliary winding turns (NA(max)) is given by the following equation.
VVDD(MAX )
NA(MAX )
=
NS
VO(MAX ) +VF
(34)
2. The nominal VVDD calculation must consider the impact on the stand-by power. Higher VVDD results in a
static loss increase with the total bias current of all devices connected to the VDD pin.
3. VVDD should be higher than the 13-V threshold voltage of survival mode (which is the sum of VVDD(off) and
V
VDD(PCT)) at the minimum sustained output voltage (VO(min)). ΔV here represents the voltage difference
between the nominal VVDD and the survival-mode threshold. A minimum of 3 V is a recommended design
margin for ΔV.
VVDD(OFF ) +VVDD(PCT ) + DV
NS
NA(MIN )
=
VO(MIN ) +VF
(35)
NA(min) must also accommodate the highest VVDD(off) threshold of other devices powered by VDD, if any. Select
an integer value for NA between the lowest NA(MAX) and the highest NA(MIN) with consideration of #2. For best
performance, design the DC resistance of the auxiliary winding to be < 0.1 Ω.
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8.2.2.2.6 Winding and Magnetic Core Materials
Besides the choice of AC flux density (ΔB) with LM and NP, the core loss of the transformer can also be
significantly reduced by proper selection of the magnetic core material. For converters operating at full-load
switching frequencies up to 250 kHz, ferrite materials such as Ferroxcube 3C97 or 3C98, for example, exhibit
low core-loss density. For converters operating at full-load switching frequencies over 400 kHz, materials such
as 3F36 from Ferroxcube and N49 from TDK/Epcos exhibit low core-loss density. Other ferrite materials with
equivalent or similar loss characteristics may also be used.
Litz wire is recommended for both primary and secondary windings, in order to reduce the RAC losses caused by
high-frequency proximity effect and skin effect of the windings. Choose a suitable insulation class for the
windings based on the expected and measured maximum operating temperature under sustained over-stress
conditions.
8.2.2.3 Calculation of ZVS Sensing Network
There are three components in the application circuit to help the depletion MOSFET (QS) perform ZVS sensing
safely: CSWS, RSWS, and DSWS. Design considerations and selection guidelines for the values of these
components are given here.
At the rising edge of the switch-node voltage, the fast dV/dt may couple through the drain-to-source capacitance
of QS (COSS(Qs)) and generate a charge current that flows into the circuit loading on the QS source pin. The result
may be a possible voltage overshoot on both the SWS pin and across the gate-to-source of QS (VGS(Qs)
)
because the gate is tied to P13. The SWS pin, having an absolute maximum voltage rating of 38 V, can handle
higher voltage stress than VGS(Qs). Therefore, carefully select a capacitor (CSWS) between the SWS pin and
GND to prevent the voltage overshoot from damaging the QS gate. Because COSS(Qs) and CSWS form a voltage
divider, the minimum CSWS (CSWS(min)) can be derived as
C
× V
V
+ N
V + V
PS O F
OSS Qs
BULK MAX
+ V
C
=
(36)
SWS min
P13
GS
MAX Qs
where
• VGS_MAX(Qs) is the de-rated maximum gate-to-source voltage of QS
• VP13 is the steady-state voltage level of 13 V
Without resistive damping, both the charge current on the rising edge of VSW and the discharge current on the
falling edge of VSW may oscillate with the parasitic series inductance within the ZVS sensing network resonating
with CSWS. Therefore, a series resistor (RSWS) between SWS pin and source-pin of QS is used to dampen any
high-frequency ringing, helping to obtain a cleaner sensing signal on the SWS pin and preventing any high-
frequency current from interfering with other noise-sensitive signals. RSWS can be expressed as:
LSWS
RSWS
>
CSWS + CDz
(37)
where
• LSWS is the lumped parasitic inductance including the packaging of QS and PCB traces of QS and CSWS
return path
• CDz is the junction capacitance of any zener diode applied across CSWS, if used (usually not necessary).
For most applications, use a resistor value slightly higher than 500 Ω. The resistor and a 22-pF ceramic
capacitor between the SWS pin and the bulk input capacitor ground form a small sensing delay to help the
internal detection circuit to identify the ZVS characteristic correctly.
Based on the above design guide, even though RSWS and CSWS may be sufficient to manage the voltage
overshoot in normal operation, a low-capacitance bi-directional TVS diode (DSWS) across BSS126 gate and
source is highly recommended to serve as a safety backup of the ZVS sensing network. Regular Zener diodes
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are not suitable due to high capacitance and slow clamping response. Ensure the clamping voltage of DSWS is
less than BSS126 voltage rating but greater than 15 V.
A general recommendation is to use a 50-V 22-pF C0G-type ceramic capacitor for CSWS, a 510-Ω chip resistor
for RSWS, and a bi-directional TVS diode with clamp voltage of 18 V for DSWS. Too large of RSWS or CSWS
introduces a sensing delay between the actual VSW and the SWS pin, causing the ZVS control to unnecessarily
extend tDM in order to pull down VSW earlier than expected before the end of tZ . As shown in 图 7-5, the larger
RSWS is, the smaller supply current to charge the VDD capacitor. If the reduced charge current (ISWS) is lower
than the total consumed current from the controller (ISTART) and from the external circuitry on the VDD and P13
pins, VVDD may not be able to reach VVDD(ON) and the controller can not initiate any switching event.
8.2.2.4 Calculation of BUR Pin Resistances
Referring back to 节 7.3.1, it is recommended that ABM is entered at no higher than 50% to 60% of full load.
Equation 1 and Equation 2, or Equation 1 and Equation 4, provide two equations for calculating two unknowns
for the BUR-pin resistor values. However, choose the target values of VCST(BUR), ΔVBUR(AAM), and ΔVBUR(LPM)
first. Because the ratio of IBUR(AAM) to IBUR(LPM) is fixed at 1.852 (5 µA / 2.7 µA), it is necessary to target
ΔVBUR(AAM) = 185 mV to ensure that ΔVBUR(LPM) = 100 mV, per guidance in 节7.3.1.
The procedure to determine the value of VCST(BUR) is quite complex and is not provided in this datasheet.
Instead, a soon-to-be-released UCC28781 Excel Calculator Tool automatically calculates this value based on
user input and determines the VBUR target voltage VBUR_tgt. Using this target value, it further determines the
appropriate values for RBUR2 and RBUR1 to meet the BUR pin targets based on user selections for the following
set of equations.
Expected values are used to determine recommended resistances, then actual resistances are selected from
standard value series and the resulting actual voltages are calculated from the selected resistor values. Actual
voltage results should be close to the targeted values.
Calculate expected ΔVBUR(LPM) value based on ΔVBUR(AAM) target value.
R
R
× R
+ R
BUR1
BUR1
BUR2
BUR2
∆ V
= I
×
(38)
BUR LPM
BUR LPM
Calculate the expected value for the parallel combination of RBUR1 with RBUR2
.
∆ V
BUR AAM
R
R
=
BUR2
I
(39)
BUR1
BUR AAM
Calculate the recommended value for RBUR1 and choose a standard 1% tolerance value for RBUR1_act that is
close to the recommended value.
∆ V
V
BUR AAM
REF
+ ∆ V
BUR AAM
R
=
×
(40)
BUR1_rec
I
V
BUR_tgt
BUR AAM
Calculate the recommended value for RBUR2 using RBUR1_act and choose a standard 1% tolerance value for
RBUR2_act that is close to the recommended value.
V
+ ∆ V
BUR_tgt
BUR AAM
+ ∆ V
BUR AAM
R
= R
×
(41)
BUR2_rec
BUR1
V
− V
BUR_tgt
REF
Calculate the actual values for VBUR, ΔVBUR(AAM), and ΔVBUR(LPM) using RBUR1_act and RBUR2_act
.
R
R
R
× R
+ R
BUR2
+ R
BUR1
BUR1
BUR2
BUR2
V
= V
×
− I
×
(42)
(43)
BUR_act
REF
BUR AAM
R
BUR1
BUR2
R
×
R
× R
BUR1
BUR2
∆ V
= I
BUR AAM
BUR AAM
+ R
BUR2
BUR1
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R
R
× R
+ R
BUR1
BUR1
BUR2
BUR2
∆ V
= I
×
(44)
BUR LPM
BUR LPM
Finally, verify that the total summation of the BUR voltage with hysteresis does not exceed the BUR-pin upper
clamp voltage of 2.4 V.
V
+ ∆ V
+ ∆ V ≤ 2.4 V
BUR LPM
(45)
BUR_act
BUR AAM
8.2.2.5 Calculation of Compensation Network
The UCC28781-Q1 integrates two control concepts to benefit high-efficiency operation: peak current-mode
control and burst-ripple control. The peak current loop in AAM can be analyzed based on linear control theory, so
the compensation target is to obtain enough phase margin and gain margin for the given small-signal
characteristic of a zero-voltage switching flyback converter. For transition-mode operation, the power stage can
be modeled as a voltage-controlled current source charging an output capacitor (CO) with an equivalent-series
resistance (RCo) and the output load (RO) as shown in 图 8-2. The first-order plant characteristic and high
switching frequency operation in AAM make the peak current loop easier to stabilize than when in ABM.
^
Equivalent Circuit of ZVSF
VO
^
^
KFVBULK
KEIFB
RCo
CO
RO
RE
HV (s)
Compensation
VO(REF)
^
IFB
图8-2. Small-Signal Model of ZVSF in AAM Loop
The adaptive burst mode (ABM) uses ripple-based control, so the linear control theory for AAM cannot be
applied. As illustrated in 图 7-4, the internal ramp compensation feature of the controller stabilizes the ABM
control loop, so the external compensation network can be simplified.
Optional
Compensation
VO
Controller
REF
FB
RDIFF
CDIFF
RBIAS1
CFB
IFB
IOPTO
RVo1
VFB(REG)
CTR
RFBI
ICOMP
RFB
IFB
ID
RBIAS2
Active Ripple
Compensation
Copto
RUN
Control
Law
RINT
CINT
ATL431
RVo2
图8-3. Compensation Network, Hv(s)
The transfer function from IFB to VO guides the pole/zero placement of the general secondary-side compensation
network in 图 8-3. In the primary-side control circuitry, two poles at ωFB and ωOPTO introduce phase-delay on
IFB. ωFB pole is formed by the external filter capacitor CFB and the parallel resistance of the internal RFBI and the
external current-limiting resistor (RFB). ωOPTO pole is formed by the parasitic capacitance of the optocoupler
output (COPTO) and the series resistance of RFBI and RFB. For CFB = 220 pF, RFBI = 8 KΩ, and RFB = 20 KΩ, the
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delay effect of ωFB pole located at 139 kHz is negligible. COPTO is in the range of a few nanoFarads contributed
by the Miller effect of the collector-to-base capacitance of the BJT in the optocoupler output, so ωOPTO pole is
located at less than 10 kHz.
If the control loop bandwidth needs to be designed at higher frequency for a faster transient response, the phase
delay effect of ωOPTO on the stability margin must be taken into account. Therefore, an RC network (RDIFF and
CDIFF) in parallel with RBIAS1 is used to compensate the phase-delay of the optocoupler, which introduces an
extra pole/zero pair located at ωP1 and ωZ1 respectively. The basic design guide is to place the ωZ1 zero close
to the ωOPTO pole, and to place ωP1 pole away from highest fBUR. On the other hand, if the stability margin and
transient response are sufficient to meet the requirements without RDIFF and CDIFF, then these two components
are optional for the controller.
IFB (s) CTR 1+ (s /
w
)
1
1+ (s /
P1) 1+ (s /
w
)
1
Z 0
Z1
=
VO (s) RBIAS1 (s /
w
Z 0 ) 1+ (s /
w
w
) 1+ (s /
w
)
FB
OPTO
(46)
(47)
(48)
(49)
(50)
(51)
1
w
=
=
=
Z 0
Z1
P1
(RVo1 + RINT )CINT
1
w
w
w
(RDIFF + RBIAS1)CDIFF
1
RDIFFCDIFF
1
=
OPTO
(RFB + RFBI )COPTO
1
w
=
FB
(RFBI / /RFB )CFB
The step-by-step design procedure of the compensator without RDIFF and CDIFF is:
1. RFB selection needs to consider both the output voltage regulation and compensation challenge on the low-
frequency pole at ωOPTO. RFB should be less than the maximum value of 28 kΩ to provide a sufficient
feedback current of 95 μA for the output voltage regulation in SBP2 mode, under the worst-case VFB(REG)
and RFBI. However, RFB = 28 kΩ and COPTO = 2 nF result in an ωOPTO pole located at 2.8 kHz. This low-
frequency pole may reduce phase margin at the cross-over frequency. If the control bandwidth is around this
frequency range, RFB value should be designed even lower to move the pole to a higher frequency.
VFB(REG) -VCE(OPTO)
IFB(SBP)
RFB(MAX )
=
- RFBI
(52)
2. RBIAS1 is determined based on a given current transfer ratio (CTR) of the optocoupler, ΔVO(ABM), and target
4~5 μA of ΔIFB as example. At collector currents less than 100 μA, the CTR of most optocouplers can be
as low as 10%, or 0.1 (used in this example), although some high performance devices can have higher
CTR.
CTR
0.1
5 μA
R
=
× ∆ V
=
× ∆ V
O ABM
(53)
BIAS1
O ABM
∆ I
FB
3. RINT selection is not designed for the small-signal compensation, but to resolve the slow large-signal
response of the shunt regulator. Specifically, after a step-down load change from heavy load to no load
occurs, the output voltage overshoot and the long settling time forces ATL431 to reduce the cathode voltage
continuously by the integrator configuration until the output voltage gets back to normal regulation level. If
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the load step-up transient happens before the output voltage is settled from the previous load step-down
event, the low voltage across ATL431 becomes the initial voltage level for the integrator to move to a new
steady-state. Because the time for ATL431 to move from lower voltage to a high voltage delays iFB reduction,
the controller response from SBP mode to AAM mode is delayed as well, which slows down the energy
delivery to the output and results in a large voltage undershoot.
To resolve this problem, RINT behaves like a current-limiting resistor for CINT, which slows down the
reduction of the cathode voltage of ATL431. RINT needs to be adjusted based on the voltage undershoot
requirement under the highest repetitive rate of load change.
8.2.3 Application Curves
100
98
96
94
92
90
88
86
84
82
80
100
98
96
94
92
90
88
86
84
82
80
ILOAD 4-A (max) Range
ILOAD 2-A (max) Range
ILOAD 4-A (max) Range
ILOAD 2-A (max) Range
0
50 100 150 200 250 300 350 400 450 500 550
DC Input Voltage (V)
0
50 100 150 200 250 300 350 400 450 500 550
DC Input Voltage (V)
图8-4. 4pt-Average Efficiency vs. DC Input Voltage 图8-5. 10%-Load Efficiency vs. DC Input Voltage
100
98
96
94
92
90
88
86
84
82
80
250
225
200
175
150
125
100
75
ILOAD 4-A (max) Range
ILOAD 2-A (max) Range
ILOAD 4-A (max) Range
ILOAD 2-A (max) Range
50
0
50 100 150 200 250 300 350 400 450 500 550
DC Input Voltage (V)
0
50 100 150 200 250 300 350 400 450 500 550
DC Input Voltage (V)
图8-6. Full-Load Efficiency vs. DC Input Voltage
图8-7. Average Switching Frequency at Full-Load
vs. DC Input Voltage
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9 Power Supply Recommendations
The UCC28781-Q1 controller is intended to control zero-voltage-switching flyback (ZVSF) converters in high-
efficiency, high DC input voltage applications, and can work in universal AC input range (85 VAC to 265 VAC, 47
Hz to 63 Hz) applications as well. An external depletion-mode MOSFET, connected between the switch node of
the converter and the SWS + P13 pins of this controller, is required to charge the VDD capacitor during start-up
and to perform ZVS sensing during normal operation.
When the VVDD reaches the UVLO turn-on threshold at 17 V, the VDD rail should be kept within the bias supply
operating voltage range listed in the Recommended Operating Conditions table. To avoid the possibility that the
device might stop switching, VVDD must not be allowed to fall below the UVLO turn-off threshold at 10.6 V.
The rectifier on the output winding must be a synchronous-rectifier (SR) MOSFET in order to generate the
negative magnetizing current necessary to achieve ZVS for high efficiency. The current rating of this SR
MOSFET should be appropriate for the peak current flowing during the demagnetization interval at maximum
loading. In addition to the output voltage plus reflected bulk voltage impressed across the SR during PWML on-
time, consideration for additional voltage spikes from various transient conditions should be made. Sources of
voltage spikes on the SR include: hard switching of the primary-side MOSFET and non-ZCS turn-off of the SR-
MOSFET.
Regardless of the cause of each of these spike sources, it is important to ensure that the peak voltage across
the SR does not exceed its maximum rating. This limitation can be accomplished in several ways:
• choose a MOSFET with a higher voltage rating
• add a snubber or voltage clamp across the SR, or
• investigate each cause and mitigate the associated spike separately
The simplest approach may be to include a TVS clamp across the rectifier.
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10 Layout
10.1 Layout Guidelines
The ZVSF converter designed with the UCC28781-Q1 virtually eliminates switching loss with minimum
circulating energy, so higher switching frequencies, efficiencies, and greater power densities can be achieved.
However, when designing for higher switching frequencies, good layout practices as discussed below should be
followed to ensure a reliable and robust design.
10.1.1 General Considerations
Designing for high power density requires consideration of noise coupling and thermal management. A four-layer
PCB structure is highly recommended to use inner layers to help reduce current-loop areas and provide heat-
spreading for surface-mount semiconductors.
• Provide internal-layer copper areas to improve heat dissipation of high-power SMDs, particularly for switching
MOSFETs and power diodes. Use multiple thermal-vias to conduct heat from outer pads to inner-layers and
supporting copper areas.
• To avoid capacitive noise coupling, do not cross outer-layer signals over copper areas that carry high-
frequency switching voltage.
• To avoid inductive noise coupling, keep switching current loops as small as possible, and do not run signal
tracks in parallel with such loops.
• Arrange the conducted-EMI filter components such that they do not allow switching noise to bypass them and
affect the input. Avoid running switching signals through the EMI filter area.
• Use multiple vias to connect high-current tracks and planes between layers.
图10-1 summarizes the critical layout guidelines, and more detail is further elaborated in the descriptions below.
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Keep control loop away
from dB/dt coupling of
transformer
Minimize the high di/dt switching loops to reduce EMI, voltage
stress on power devices, and noise coupling to control loop
Transformer
VO
FDC
VBULK
VDC
LK
CBULK
LM
NP
NS
CO
ROCP
Primary Power Ground
Shorten high dv/dt
traces for less EMI
and noise coupling;
run orthogonally
GND
QSR
Isolated Driver
Secondary
Power
Ground
DRUN
CRUN
across other traces
Isolated Driver
(primary side)
(secondary side)
VP13
QS
Keep signal and
power grounds
separate
DSWS
PWMH
RUN
CDIFF
QL
RSWS
Shorten VSWS trace
with dv/dt; keep away
from feedback loop
PWML
PGND
RBIAS1
VSWS
RDIFF
Shorten VAUX trace
with dv/dt; keep away
from feedback loop
CSWS
To CBULK
ground
VRCS
DAUX
RCS
Minimize high di/dt
switching loops
RBIAS2
Dedicate CSWS
return to RCS
ground node
CVDD1
NA
VP13
VS13
Keep compensator
DP13
CVDD2
CP13
CINT
RINT
away from dv/dt, di/
dt, and dB/dt noise
sources
RVS1
RVS2
VS
XCD
GTP3 GTP2 GTP1
VDD
P13
S13
SWS
RUN
Secondary Signal
Ground Plane
VSWS
RUN
XCD
VREF
UCC28781
PWMH
PWMH
Follow grounding
arrangements shown in
this schematic diagram
PWML
PGND
PWML
PGND
BUR
SET
REF
FB RDM RTZ TP AGND FLT IPC
CS
ROPP
To RCS
ground
VRCS
VREF
CFB
CREF
CCS
Primary Signal Ground Plane
RFB
Keep signal
components close
to IC to minimize
noise coupling
Minimize FB loop area, keep away from noise sources, and
route emitter return back to AGND in parallel with FB path
图10-1. Typical Schematic with Layout Considerations
10.1.2 RDM and RTZ Pins
Minimize stray capacitance to RDM and RTZ pins.
• Place RRDM and RRTZ as close as possible between the controller pins and AGND pin.
• Avoid putting a ground plane or any other tracks under RDM and RTZ pins to minimize parasitic capacitance.
This can be accomplished by putting cutouts and/or keepouts in the layers below these pins.
10.1.3 SWS Pin
Minimize potential stray noise coupling from SWS pin to noise-sensitive signals.
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• Keep some distance between SWS network and other connections.
• The RC damping network (RSWS, CSWS) and the TVS diode (DSWS) should be as close to the source pin of
QS as possible instead of SWS pin, so the gate-to-source pin of QS can be effectively protected.
• Keep the return path for di/dt current through CSWS and DSWS separate from the IC local GND and FB signal
return paths. Return CSWS back to the ground node at RCS, not at the IC.
10.1.4 VS Pin
Minimize stray capacitance at the VS pin to reduce the time-delay effect on ZVS control.
• Avoid putting a GND plane under the VS pin to reduce parasitic capacitance. This can be accomplished by
inserting a cutout in the plane (if any) below this pin's pad and the tracks and pads of components connected
to VS. Minimize the track length of the VS net.
• Do not run other tracks or planes over or under the VS net.
• Do not run other tracks or planes under RVS1 and RVS2
.
10.1.5 BUR Pin
The resistor divider (RBUR1 and RBUR2) and the filter capacitor (CBUR) on the BUR pin should to be as close to
the BUR pin and IC AGND as possible.
• It is recommended to provide shielding on the BUR-pin trace with ground planes to minimize the noise-
coupling effect on peak current variation during burst-mode operation. This can be accomplished by adding a
ground plane under the BUR traces and pins.
10.1.6 FB Pin
This pin can be noise-sensitive to capacitive coupling from the high dV/dt switch nodes, or the flux coupling from
magnetic components and high di/dt switching loops.
• Minimize the loop area for the PCB traces from the opto-coupler to the FB pin in order to avoid the possible
flux coupling effect. Run the opto-coupler emitter return track from AGND at the IC in parallel with the FB to
collector path, to minimize loop-area.
• Keep PCB traces away from the high dv/dt signals, such as the switch node of the converter (VSW), the
auxiliary winding voltage (VAUX), and the SWS-pin voltage (VSWS). If possible, it is recommended to provide
shielding for the FB trace with ground planes.
• The filter capacitor between FB pin and REF pin (CFB) needs to be as close to the two IC pins as possible.
• The current-limiting resistor of FB pin (RFB) should be as close to the FB pin as possible to enhance the noise
rejection of nearby capacitively-coupled noise sources.
10.1.7 CS Pin
The OPP-programming resistor (ROPP) and the filter capacitor (CCS) should be as close to the CS pin as
possible to improve the noise rejection of nearby capacitively-coupled noise sources, and to filter any ringing that
may be present during non-ZVS conditions.
10.1.8 AGND Pin
The AGND pin is the bias-power and signal-ground connection for the controller. The effectiveness of the filter
capacitors on the signal pins depends upon the integrity of this ground return.
• Place the decoupling capacitors for VDD, REF, CS, BUR, and P13 pins as close as possible to the device
pins and AGND pin with short traces.
• The device ground and power-stage ground should meet at the return pin of the current-sense resistor (RCS).
Try to ensure that high frequency, high current from the power stage does not flow through the signal ground.
• The thermal pad of the QFN package should be tied to the AGND pin with a short trace, and be connected to
the signal ground plane with multiple vias which becomes a low-impedance ground return of external
components to the AGND pin.
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10.1.9 PGND Pin
The PGND pin is the gate-drive return for the PWML signal. It is NOT a ground return; do not confuse it as a
power ground pin. It is not connected to AGND within the device.
• The PGND signal is normally connected to the source pin of the low-side switching device, and run in parallel
with PWML to minimize loop area.
• In certain cases, PGND may be connected to AGND at a location where PWML return currents do not create
ground noise to disturb control signals referenced to AGND.
• For the individual low-side GaN power IC with logic PWM input, it is recommended to connect PGND to the
bottom of the current sense resistor (RCS) directly.
10.1.10 Thermal Pad
The Thermal Pad (TP) is internally connected to the device substrate by an indeterminate impedance. Connect
this pad externally to AGND at the AGND pin and at other pins that may also be tied to AGND for the application.
This pad functions as a thermal dissipater for the device. Use multiple vias to connect this pad to other copper
planes and areas to help dissipate heat and to maintain the lowest GND impedance for signal integrity.
10.2 Layout Example
The layout techniques described in previous sections are applied to the layout of the 60-W high-density DC-to-
DC zero-voltage switching flyback converter. The schematic diagram of this converter is shown in the next three
figures, and the pcb layers are shown in the following four figures.
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3 ,
2 ,
1
8 ,
6 ,
7
5
,
3
2
1 A M T A 7 P 0 0 6 R 0 8 D P I
2
3
2
1
2
1
+
-
1
4
3
2
图10-2. Power Stage of the 60-W EVM
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R105
VDD
2.10k
(at C100)
C17
C10
VAUX
0.1uF
10uF
22µF
R106
2.10k
VDD
(at R104)
Wire Adds
Track Cut
U1
REF
R36
DNP
1.0M
19
23
22
16
R20
VDD
SWS
GTP2
FB
SWS
FB
REF
15.4k
D101
75V
(at U100)
R108
27.4k
21
6
VS
VS
C14
330pF
R30
20.0k
R23
6.98k
GTP3
OPTO_C
Wire Adds
D103
R109
1.00k
P13
C23
1µF
12
15
14
13
PWML
PWMH
P13
S13
PWML
SRDRV
CS
R14
191k
D102
27V
(at R101)
R110
10.0k
Q100
MMST3906-7-F
VAUX
R19
402
9
24
1
5
BUR
CS
BUR
RUN
QLSRC
39V
R13
39.2k
10
C21
C13
330pF
SET
FLT
RTZ
RDM
IPC
RUN
XCD
100pF
FLT
T rack Cut
R1
GND_P
17
18
XCD
XCD
3.32k
REF
C19
100pF
2
169kR8RTZ
93.1kR9RDM
IPC
RT1
47k
25
8
EP
AGND
GTP1
PGND
3
C100
R104
DNP DNP
R100
DNP
2200pF 2.21M
1.0M
4
CS
20
11
1.0M
GND_P
R17
0
7
4
3
REF
REF
R103
CS
0
1
V+
DNP
QLSRC
V-
C12
0.22uF
RUN
UCC28781-Q1
470k
U100
TLV7021DCKR
Track Cut
1000pF
681k
GND_P
GND_P
图10-3. ZVSF Controller of the 60-W EVM
SRDRV
SR_DRV
U2
D7
1
2
1
8
7
6
5
IN
VDD
OUT
VSS
VSS
VOUT
3
2
C8
10µF
VCCI
VCCI
GND
3
4
C11
RUN
VOUT
40V
R22
GND_S
UCC5304DWV
GND_P
TP5
VOUT_A
C25
0.015uF
R26
.0k
R25
150k
R27
U4
6
4
1
3
OPTO_C
22pF
C27
R29
R32
5.62k
10.0k
0 .01uF
TLP383(GR-TPL,E
GND_P
R31
30.0k
U3
ATL431AIDBZR
GND_S GND_S
图10-4. SR Drive and Feedback Circuits of the 60-W EVM
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图10-5. Top-Side Assembly and Top Layer of PCB
图10-6. Bottom-Side Assembly and Bottom Layer of PCB
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图10-7. Inner Layer 1 (Second Layer) of PCB
Inner Layer 2 (Third Layer) of PCB
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: UCC28781-Q1
PACKAGE OPTION ADDENDUM
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20-Nov-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
UCC28781QRTWRQ1
ACTIVE
WQFN
RTW
24
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
U28781Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
GENERIC PACKAGE VIEW
RTW 24
4 x 4, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224801/A
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PACKAGE OUTLINE
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
RTW0024B
4.15
3.85
A
B
4.15
3.85
PIN 1 INDEX AREA
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
(0.2) TYP
2X 2.5
EXPOSED
THERMAL PAD
12
7
20X 0.5
6
13
25
SYMM
2X
2.5
2.45±0.1
1
18
0.3
24X
0.18
19
0.5
24
PIN 1 ID
(OPTIONAL)
0.1
C A B
SYMM
0.05
C
24X
0.3
4219135/B 11/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
RTW0024B
(
2.45)
SYMM
24
19
24X (0.6)
1
18
24X (0.24)
(0.97)
25
SYMM
(3.8)
20X (0.5)
(R0.05)
TYP
13
6
(Ø0.2) TYP
VIA
7
12
(0.97)
(3.8)
LAND PATTERN EXAMPLE
SCALE: 20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219135/B 11/2016
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK-NO LEAD
RTW0024B
4X( 1.08)
(0.64) TYP
19
24
(R0.05) TYP
24X (0.6)
25
1
18
(0.64)
TYP
24X (0.24)
SYMM
(3.8)
20X (0.5)
13
6
7
12
METAL
TYP
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25:
78% PRINTED COVERAGE BY AREA UNDER PACKAGE
SCALE: 20X
4219135/B 11/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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