UCC28C57HDR [TI]

工业类 30V 低功耗电流模式 PWM 控制器，适用于 SiC，18.8V/15.5V UVLO，50% 占空比 | D | 8 | -40 to 125;


型号：	UCC28C57HDR
厂家：	TEXAS INSTRUMENTS
描述：	工业类 30V 低功耗电流模式 PWM 控制器，适用于 SiC，18.8V/15.5V UVLO，50% 占空比 \| D \| 8 \| -40 to 125 控制器
文件：	总57页 (文件大小：3471K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

UCCx8C5x 适用于Si 和SiC MOSFET 的

BiCMOS 低功耗电流模式PWM 控制器

VDD 绝对最大额定电压从 20V 增加至 30V，便于以理

想方式驱动 20V_gs、18V_gs或 15V_gsSiC MOSFET 的

1 特性

• 支持Si 和SiC MOSFET 应用的欠压锁定选项

• 30V VDD 绝对最大电压

• 1MHz 最大固定频率工作

• 50μA 启动电流，最大值75μA

• 低工作电流: 1.3mA（f_OSC= 52kHz）

• 35ns 快速逐周期过流限制

• 峰值驱动电流为±1A

栅极，同时可无需使用外部LDO。

器件性能改进

UCCx8C4x

UCCx8C5x

1.3mA

参数

52kHz 时的电源电流

启动电流（上限值）

VDD 绝对上限值

2.3mA

100µA

20V

75µA

30V

±2%

±1%

基准电压精度

• 轨到轨输出

– 25ns 上升时间

– 20ns 下降时间

• 精度为±1% 的2.5V 误差放大器基准

• 与UCCx8C4x 引脚对引脚兼容的可直接替代产品

• 提供功能安全

Si FET 的UVLO 和D_MAX

SiC FET 的UVLO 和D_MAX

最小封装选项

6 个选项

none

6 个选项

VSSOP (8)

UCCx8C5x 系列采用 8 引脚 VSSOP (DGK) 和 8 引脚

SOIC (D) 封装。

– 可帮助进行功能安全系统设计的文档

2 应用

器件信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

• 通用单端直流/直流或离线隔离式电源转换器

• 太阳能逆变器、电机驱动器、储能系统的辅助电源

• EV 充电站的隔离式电源

SOIC (8)

3.91mm × 4.90mm

UCC28C50、UCC28C51

UCC28C52、UCC28C53、

UCC28C54、UCC28C55、

UCC38C50、UCC38C51

UCC38C52、UCC38C53

UCC38C54、UCC38C55

VSSOP (8)

SOIC (8)

3.00mm × 3.00mm

3.91mm × 4.90mm

3 说明

UCCx8C5x 系列器件为高性能电流模式 PWM 控制

器，可驱动各种应用中的 Si 和 SiC MOSFET。

UCCx8C5x 系列是 UCCx8C4x 的更高效、更稳健的版

本。

UCC28C56H、UCC28C56L

UCC28C57H、

UCC28C57L、

UCC28C58、UCC28C59

除持续支持 Si MOSFET 的现有 UVLO 阈值

(UCCx8C50-55) 外，UCCx8C5x 系列还具有可确保

SiC MOSFET 可靠运行的新 UVLO 阈值

(UCC28C56-59)。

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

VIN

VOUT

VDD

OUT

VREF

UCC28C43

RT/CT

GND

COMP

简化版应用

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

Table of Contents

8.4 Device Functional Modes..........................................24

9 Application and Implementation..................................25

9.1 Application Information............................................. 25

9.2 Typical Application.................................................... 27

9.3 Power Supply Recommendations.............................41

9.4 Layout....................................................................... 41

10 Device and Documentation Support..........................44

10.1 Device Support....................................................... 44

10.2 Documentation Support.......................................... 44

10.3 接收文档更新通知................................................... 44

10.4 支持资源..................................................................44

10.5 Trademarks.............................................................45

10.6 静电放电警告.......................................................... 45

10.7 术语表..................................................................... 45

11 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 5

7.1 Absolute Maximum Ratings........................................ 5

7.2 ESD Ratings............................................................... 6

7.3 Recommended Operating Conditions.........................6

7.4 Thermal Information....................................................6

7.5 Electrical Characteristics.............................................7

7.6 Typical Characteristics................................................9

8 Detailed Description......................................................14

8.1 Overview...................................................................14

8.2 Functional Block Diagram.........................................15

8.3 Feature Description...................................................15

Information.................................................................... 45

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision B (February 2023) to Revision C (March 2023)

Page

• UCC28C56L、UCC38C53 和UCC38C55 器件的初始发行版........................................................................... 1

Changes from Revision A (October 2022) to Revision B (February 2023)

Page

• UCC28C50、UCC28C51、UCC28C52、UCC28C53、UCC28C54、UCC28C55、UCC28C57H、

UCC28C57L、UCC38C50、UCC38C51、UCC38C52 和UCC38C54 器件的初始版本...................................1

• Corrected Figure 8-5 Oscillator Synchronization Circuit ..................................................................................21

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Product Folder Links: UCC28C50 UCC28C51 UCC28C52 UCC28C53 UCC28C54 UCC28C55 UCC28C56H

UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

5 Device Comparison Table

UVLO

Junction

Temperature (T_J)

(°C)

Maximum

duty cycle

Turn on at 14.5 V

Turn off at 9 V

for off-line applications

Turn on at 8.4 V

Turn off at 7.6 V

for dc/dc applications

Turn on at 7 V

Turn off at 6.6 V

for battery applications

UCC28C52

UCC28C53

UCC28C50

UCC38C50

UCC28C51

UCC38C51

–40 to 125

0 to 85

100%

50%

UCC38C52

UCC38C53

UCC28C54

UCC28C55

–40 to 125

0 to 85

UCC38C54

UCC38C55

UVLO

Junction

Temperature (T_J)

(°C)

Turn on at 18.8 V

Turn off at 15.5 V

Suitable for HV applications

using GEN-I SiC MOSFET

Turn on at 18.8 V

Turn off at 14.5 V

Suitable for HV applications

using GEN-II SiC MOSFET

Turn on at 16 V

Turn off at 12.5 V

Suitable for HV applications

using GEN-III SiC MOSFET

Maximum

duty cycle

UCC28C56H

UCC28C57H

UCC28C56L

UCC28C57L

UCC28C58

UCC28C59

100%

50%

–40 to 125

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Product Folder Links: UCC28C50 UCC28C51 UCC28C52 UCC28C53 UCC28C54 UCC28C55 UCC28C56H

UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

6 Pin Configuration and Functions

COMP

VREF

VDD

OUT

GND

COMP

VREF

VDD

OUT

GND

RT/CT

Not to scale

图6-1. D Package 8-Pin SOIC (Top View)

图6-2. DGK Package, 8-Pin VSSOP (Top View)

表6-1. Pin Functions

TYPE

DESCRIPTION

(1)

NAME

NO.

This pin provides the output of the error amplifier for compensation. In addition, the COMP pin is frequently

used as a control port, by utilizing a secondary-side error amplifier to send an error signal across the

secondary-primary isolation boundary through an opto-isolator. The error amplifier is internally current limited

so the user can command zero duty cycle by externally forcing COMP to GND.

COMP

Primary-side current sense pin. The current sense pin is the noninverting input to the PWM comparator.

Connect to current sensing resistor. This signal is compared to a signal proportional to the error amplifier

output voltage. The PWM uses this to terminate the OUT switch conduction. A voltage ramp can be applied to

this pin to run the device with a voltage mode control configuration.

This pin is the inverting input to the error amplifier. FB is used to control the power converter voltage-feedback

loop for stability. The noninverting input to the error amplifier is internally trimmed to 2.5 V ± 1%.

GND

Ground return pin for the output driver stage and the logic level controller section.

—

The output of the on-chip drive stage. OUT is intended to directly drive a MOSFET. The OUT pin in the

UCCx8C50, UCCx8C52, UCCx8C53, UCC28C56H/L and UCC28C58 is the same frequency as the oscillator,

and can operate near 100% duty cycle. In the UCCx8C51, UCCx8C54, and UCCx8C55, UCC28C57H/L and

UCC28C59, the frequency of OUT is one-half that of the oscillator due to an internal T flipflop. This limits the

maximum duty cycle to < 50%. Peak currents of up to 1 A are sourced and sunk by this pin. OUT is actively

held low when VDD is below the turn-on threshold.

OUT

Fixed frequency oscillator set point. Connect timing resistor (R_RT) to VREF and timing capacitor (C_CT) to GND

from this pin to set the switching frequency. For best performance, keep the timing capacitor lead to the device

GND as short and direct as possible. If possible, use separate ground traces for the timing capacitor and all

other functions. The switching frequency (f_SW) of the UCCx8C50, UCCx8C52, UCCx8C53, UCC28C56H/L

and UCC28C58 gate drive is equal to f_OSC; the switching frequency of the UCCx8C51, UCCx8C54, and

RT/CT

I/O

UCCx8C55, UCC28C57H/L and UCC28C59 is equal to half of the f_OSC

Analog controller bias input that provides power to the device. Total VDD current is the sum of the quiescent

VDD current and the average OUT current. A bypass capacitor, typically 0.1 µF, connected directly to GND

with minimal trace length, is required on this pin. Additional capacitance at least 10 times greater than the gate

capacitance of the main switching FET used in the design and at least 10 times greater than the capacitance

on the VREF pin used in the design are also required on VDD.

VDD

5-V reference voltage. VREF is used to provide charging current to the oscillator timing capacitor through the

timing resistor. It is important for reference stability that VREF is bypassed to GND with a ceramic capacitor

connected as close to the pin as possible. A minimum value of 0.1 µF ceramic is required. Additional VREF

bypassing is required for external loads on VREF. No external voltage higher than specified VREF is allowed

to superimposed to VREF pin since VREF is an ouput.

VREF

(1) I = input, O = output, G = ground

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Product Folder Links: UCC28C50 UCC28C51 UCC28C52 UCC28C53 UCC28C54 UCC28C55 UCC28C56H

UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

MAX

UNIT

Input voltage

VDD

Input current

IVDD

Output drive current (peak)

Output energy (capacitive load), E_OUT

Analog input voltage

±1

µJ

COMP, CS, FB, RT/CT

OUT

6.3

–0.3

Output driver voltage

Reference voltage

VREF

Error amplifier output sink current

COMP

D package

DGK package

72.3

98.1

300

150

Total power dissipation at T_A= 25°C

°C/W

Lead temperature (soldering, 10 s), T_LEAD

Operating junction temperature, T_J

Storage temperature, T_stg

°C

–40

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) All voltages are with respect to GND pin. Currents are positive into and negative out of the specified terminals.

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Product Folder Links: UCC28C50 UCC28C51 UCC28C52 UCC28C53 UCC28C54 UCC28C55 UCC28C56H

UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

7.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2500

±1500

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

V_VDD

Input voltage

V_OUT

Output driver voltage

Average output driver current⁽¹⁾

Reference output current⁽¹⁾

I_OUT

200

–20

125

I_OUT(VREF)

UCC28C5x

UCC38C5x

–40

T_J

Operating junction temperature⁽¹⁾

°C

(1) TI recommends against operating the device under conditions beyond those specified in this table for extended periods of time.

7.4 Thermal Information

UCC28C5x, UCC38C5x

THERMAL METRIC⁽¹⁾

D (SOIC)

8 PINS

128.9

71.7

DGK (VSSOP)

8 PINS

176.4

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)Junction-to-case (top) thermal resistance

67.3

R_θJB

ψ_JT

Junction-to-board thermal resistance

72.3

98.1

Junction-to-top characterization parameter

Junction-to-board characterization parameter

23.4

11.1

71.5

91.5

ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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Product Folder Links: UCC28C50 UCC28C51 UCC28C52 UCC28C53 UCC28C54 UCC28C55 UCC28C56H

UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

7.5 Electrical Characteristics

V_VDD= 20V for UCC28C56H/L, UCC28C57H/L, and UCC28C58/9, V_VDD= 15 V for all other device options, R_RT= 10 kΩ,

C_CT= 3.3 nF, C_VDD= 0.1 µF and no load on the outputs, –40°C ≤T_J≤125°C for the UCC28C5x, 0°C ≤T_J≤85°C, for

the UCC38C5x (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

REFERENCE

V_VREF

VREF voltage, initial accuracy

Line regulation

T_J= 25°C, I_OUT= 1 mA

4.95

0.2

5.05

20 mV

25 mV

12 V ≤V_VDD≤25 V

Load regulation

1 mA to 20 mA

Temperature stability⁽²⁾

Total output variation⁽²⁾

VREF noise voltage⁽²⁾

Long term stability⁽²⁾

0.2

0.4 mV/°C

4.85

5.15

µV

10 Hz to 10 kHz, T_J= 25°C

1000 hours, T_J= 125°C

25 mV

55 mA

I_VREF

Output short circuit (source current)

OSCILLATOR

f_OSC

Initial accuracy⁽³⁾

T_J= 25°C

50.5

0.2%

55 kHz

Voltage stability

Temperature stability⁽²⁾

Amplitude

12 V ≤V_VDD≤25 V

T_J(MIN)to T_J(MAX)

2.5%

RT/CT pin peak-to-peak voltage

T_J= 25°C, V_RT/CT= 2 V

V_RT/CT= 2 V

1.9

7.7

7.2

8.4

Discharge current⁽⁴⁾

8.4

9.5

ERROR AMPLIFIER

V_FB

Feedback input voltage, initial accuracy V_COMP= 2.5 V, T_J= 25°C

Feedback input voltage, total variation V_COMP= 2.5 V

2.475

2.45

2.5 2.525

2.5

0.1

2.55

I_FB

Input bias current (source current)

Open-loop voltage gain

V_FB= 5 V

µA

A_VOL

2 V ≤V_OUT≤4 V

Unity gain bandwidth⁽²⁾

1.5

MHz

PSRR

Power supply rejection ratio

Output sink current

12 V ≤V_VDD≤25 V

V_FB= 2.7 V, V_COMP= 1.1 V

V_FB= 2.3 V, V_COMP= 5 V

Output source current

0.5

V_REF

–

VOH

VOL

High-level COMP voltage

Low-level COMP voltage

V_FB= 2.7 V, R_COMP= 15 kΩCOMP to GND

V_FB= 2.7 V, R_COMP= 15 kΩCOMP to VREF

0.2

0.1

1.1

CURRENT SENSE

A_CS

V_CS

PSRR

I_CS

Gain^{(5) (1)}

2.85

0.9

3.15 V/V

Maximum input signal

Power supply rejection ratio^{(2) (5)}

Input bias current (source current)

CS to output delay

V_FB< 2.4 V

1.1

µA

12 V ≤V_VDD≤25 V

0.1

t_D

COMP to CS offset

V_CS= 0 V

1.15

OUTPUT

V_OUT(low)R_DS(on)pulldown

V_OUT(high)R_DS(on)pullup

I_SINK= 200 mA

5.5

I_SOURCE= 200 mA

T_J= 25°C, C_OUT= 1 nF

t_RISE

t_FALL

Rise time

Fall time

UNDERVOLTAGE LOCKOUT

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Product Folder Links: UCC28C50 UCC28C51 UCC28C52 UCC28C53 UCC28C54 UCC28C55 UCC28C56H

UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

V_VDD= 20V for UCC28C56H/L, UCC28C57H/L, and UCC28C58/9, V_VDD= 15 V for all other device options, R_RT= 10 kΩ,

C_CT= 3.3 nF, C_VDD= 0.1 µF and no load on the outputs, –40°C ≤T_J≤125°C for the UCC28C5x, 0°C ≤T_J≤85°C, for

the UCC38C5x (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

13.5

7.8

TYP

14.5

8.4

MAX UNIT

UCCx8C52, UCCx8C54

15.5

UCCx8C53, UCCx8C55

UCCx8C50, UCCx8C51

6.5

7.5

VDD_ON

Start threshold⁽⁶⁾

UCC28C56H, UCC28C57H

UCC28C56L, UCC28C57L

UCC28C58, UCC28C59

17.6

14.8

18.8

17.2

UCCx8C52, UCCx8C54

UCCx8C53, UCCx8C55

UCCx8C50, UCCx8C51

UCC28C56H, UCC28C57H

7.6

8.2

7.1

6.1

6.6

VDD_OFF

Minimum operating voltage⁽⁶⁾

15.5

UCC28C56L, UCC28C57L

UCC28C58, UCC28C59

UCCx8C52, UCCx8C54

UCCx8C53, UCCx8C55

UCCx8C50, UCCx8C51

UCC28C56H, UCC28C57H

UCC28C56L, UCC28C57L

UCC28C58, UCC28C59

13.95

14.5

12.5

5.5

0.9

0.5

3.3

4.3

3.5

5.4

0.8

0.4

VDD_Hyst

VDD_ON- VDD_OFF

2.6

3.65

2.8

PWM

D_MAX

D_MIN

UCCx8C52, UCCx8C53, UCCx8C50,V_FB< 2.4 V

94%

96%

UCC28C56H, UCC28C56L, UCC28C58,VFB < 2.4

Maximum duty cycle

Minimum duty cycle

UCCx8C54, UCCx8C55, UCCx8C51,V_FB< 2.4 V

47%

48%

UCC28C57H, UCC28C57L, UCC28C59,VFB < 2.4

V_FB> 2.6 V

CURRENT SUPPLY

I_START-UPStart-up current

µA

V_VDD= VDD_ON–0.5 V

I_VDD

Operating supply current

V_FB= V_CS= 0 V

1.3

(1) For UCC28C56H/L, UCC28C57H/L and UCC28C58/9 adjust V_VDDto a value above the start threshold before setting it to 20 V. For all

other device options, adjust V_VDDto a value above the start threshold before setting it to 15.5 V

(2) Specified by design. Not production tested.

(3) Output frequencies of the UCCx8C51, UCCx8C54, and the UCCx8C55, UCC28C57H/L and the UCC28C59 are half the oscillator

frequency.

(4) Oscillator discharge current is measured with R_RT= 10 kΩto VREF.

(5) Parameter measured at trip point of latch with V_FB= 0 V. Gain is defined as A_CS= ΔV_COMP/ ΔV_CS, 0 V ≤V_CS≤900 mV.

(6) VDD_ON, VDD_OFFand V_REFare tracking each other in the same direction. (Minimum VDD_OFFis due to minimum VDD_ON.)

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UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

7.6 Typical Characteristics

9.5

1000

Group 1, VDD = 12 V

Group 2, VDD = 20 V

100

8.5

220 pF

470 pF

7.5

1 nF

2.2 nF

4.7 nF

-50

-25

100

125

R_RTTiming Resistance (kW)

100

Temperature (C)

D001

Group 2: UCC28C56H/L,

UCC28C57H/L, and

UCC28C58/9

Group 1: UCCx8C50 to

UCCx8C55

图7-1. Oscillator Frequency vs Timing Resistance

and Capacitance

图7-2. Oscillator Discharge Current vs

Temperature

100

1.8

1.6

1.4

1.2

200

180

Group 1, VDD = 12 V

Group 2, VDD = 20 V

160

140

GAIN

120

100

0.8

0.6

0.4

0.2

PHASE

MARGIN

-50

-25

100

125

Temperature (C)

100

1 k 10 k 100 k 1 M 10 M

V_CS= 0 V

f -- Frequency -- Hz

Group 2: UCC28C56H/L,

UCC28C57H/L, and

UCC28C58/9

Group 1: UCCx8C50 to

UCCx8C55

图7-3. Error Amplifier Frequency Response

图7-4. COMP to CS Offset Voltage vs Temperature

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UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

5.05

5.04

5.03

5.02

5.01

2.55

2.54

2.53

2.52

2.51

2.5

Group 1, VDD = 12 V

Group 2, VDD = 20 V

Group 1, VDD = 12 V

Group 2, VDD = 20 V

4.99

4.98

4.97

4.96

4.95

2.49

2.48

2.47

2.46

2.45

-50

-25

100

125

-50

-25

100

125

Temperature (C)

Group 2: UCC28C56H/L,

UCC28C57H/L, and

UCC28C58/9

Group 2: UCC28C56H/L,

UCC28C57H/L, and

UCC28C58/9

Group 1: UCCx8C50 to

UCCx8C55

Group 1: UCCx8C50 to

UCCx8C55

图7-5. Reference Voltage vs Temperature

图7-6. Error Amplifier Reference Voltage vs

Temperature

200

-35

Group 1, VDD = 12 V

Group 2, VDD = 20 V

-37

-39

-41

-43

-45

-47

-49

-51

-53

-55

150

100

--50

--100

--150

--200

-50

-25

100

125

Temperature (C)

--50

--25

25 50

Temperature (°C)

100

125

Group 2: UCC28C56H/L,

UCC28C57H/L, and

UCC28C58/9

Group 1: UCCx8C50 to

UCCx8C55

图7-8. Error Amplifier Input Bias Current vs

Temperature

图7-7. Reference Short-Circuit Current vs

Temperature

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UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

9.0

UVLO

8.8

8.6

UVLO

8.4

8.2

8.0

7.8

UVLO

OFF

7.6

7.4

7.2

7.0

UVLO

OFF

--50

--25

100

125

--50

--25

25 50

Temperature (°C)

100

125

Temperature (°C)

UCCx8C52 and UCCx8C54

UCCx8C53 and UCCx8C55

图7-9. Undervoltage Lockout vs Temperature

图7-10. Undervoltage Lockout vs Temperature

7.3

7.2

UVLO

7.1

7.0

6.9

6.8

6.7

6.6

6.5

UVLO

OFF

6.4

6.3

UCC28C56H and UCC28C57H

--50

--25

100

125

Temperature (°C)

图7-12. Undervoltage Lockout vs Temperature

UCCx8C50 and UCCx8C51

图7-11. Undervoltage Lockout vs Temperature

UVLO_ON

UVLO_OFF

-50

-25

100

125

Temperature (C)

UCC28C56L and UCC28C57L

UCC28C58 and UCC28C59

图7-13. Undervoltage Lockout vs Temperature

图7-14. Undervoltage Lockout vs Temperature

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Product Folder Links: UCC28C50 UCC28C51 UCC28C52 UCC28C53 UCC28C54 UCC28C55 UCC28C56H

UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

2.1

Group 1 (No Load, V_DD= 12 V)

Group 2 (No Load, V_DD= 20 V)

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1-nF Load

No Load

200

400

600

Frequency (kHz)

800

1000

1200

-50

-25

100

125

Temperature (C)

Group 2: UCC28C56H/L,

UCC28C57H/L, and

UCC28C58/9

图7-15. Supply Current vs Oscillator Frequency

Group 1: UCCx8C50 to

UCCx8C55

图7-16. Supply Current vs Temperature

100

CT = 220 pF

(1 nF)

CT = 1 nF

500

1000

1500

2000

2500

--50

--25

100

125

f -- Frequency -- kHz

-- Temperature -- °C

图7-18. Maximum Duty Cycle vs Oscillator

图7-17. Output Rise Time and Fall Time vs

Frequency

Temperature

100

--50

--25

100

125

--50

--25

100

125

Temperature (°C)

图7-19. Maximum Duty Cycle vs Temperature

图7-20. Maximum Duty Cycle vs Temperature

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UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

1.05

Group 1, VDD = 12 V

Group 2, VDD = 20 V

1.03

1.01

0.99

0.97

0.95

-50

-25

100

125

Temperature (C)

Group 2: UCC28C56H/L,

UCC28C57H/L, and

UCC28C58/9

--50

--25

100

125

Group 1: UCCx8C50 to

UCCx8C55

-- Temperature -- °C

图7-22. Current Sense to Output Delay Time vs

图7-21. Current Sense Threshold Voltage vs

Temperature

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Product Folder Links: UCC28C50 UCC28C51 UCC28C52 UCC28C53 UCC28C54 UCC28C55 UCC28C56H

UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

8 Detailed Description

8.1 Overview

The UCCx8C5x series of control integrated circuits provide the features necessary to implement AC-DC or

DC‑to-DC fixed-frequency current-mode control schemes with a minimum number of external components.

Protection circuitry includes undervoltage lockout (UVLO) and current limiting. Internally implemented circuits

include a start-up current of less than 75 µA, a precision reference trimmed for accuracy at the error amplifier

input, logic to ensure latched operation, a pulse-width modulation (PWM) comparator that also provides current-

limit control, and an output stage designed to source or sink high-peak current. The output stage, suitable for

driving N-channel MOSFETs, is low when it is in the OFF state. The oscillator contains a trimmed discharge

current that enables accurate programming of the maximum duty cycle and dead time limit, making this device

suitable for high-speed applications.

Major differences between members of this series are the UVLO thresholds, acceptable ambient temperature

range, maximum duty cycle and frequency. Typical UVLO thresholds of 14.5 V (ON) and 9 V (OFF) on the

UCCx8C52 and UCCx8C54 devices make them ideally suited to off-line AC-DC applications. The corresponding

typical thresholds for the UCCx8C53 and UCCx8C55 devices are 8.4 V (ON) and 7.6 V (OFF), making them

ideal for use with regulated input voltages used in DC-DC applications. The UCCx8C50 and UCCx8C51 feature

a start-up threshold of 7 V and a turnoff threshold of 6.6 V (OFF), which makes them suitable for battery-

powered applications. The UCC28C56H/L, UCC28C57H/L, UCC28C58 and UCC28C59 can operate with higher

UVLO thresholds to reliably drive SiC MOSFETs in high-voltage applications. The UCC28C56H and

UCC28C57H operate with start threshold of 18.8 V (ON) and stop threshold of 15.5 V (OFF). The UCC28C56L

and UCC28C57L operate with start threshold of 18.8V (ON) and stop threshold of 14.5 V (OFF). The UCC28C58

and UCC28C59 operate with start threshold of 16 V (ON) and stop threshold of 12.5 V (OFF). The UCCx8C50,

UCCx8C52, UCCx8C53, UCC28C56H/L and UCC28C58 devices can operate with duty cycles approaching

100%. The UCCx8C51, UCCx8C54, UCCx8C55, UCC28C57H/L and UCC28C59 devices can operate from 0%

to 50% duty cycle, by the addition of an internal toggle flip-flop, which blanks the output off every other clock

cycle. The UCC28C5x series is specified for operation from –40°C to 125°C, and the UCC38C5x series is

specified for operation from 0°C to 85°C. The switching frequency (fSW) of the UCCx8C50, UCCx8C52,

UCCx8C53, UCC28C56H/L and UCC28C58 gate drive is equal to f_OSC; the switching frequency of the

UCCx8C51, UCCx8C54, UCCx8C55, UCC28C57H/L and UCC28C59 is equal to half of the f_OSC

The UCC28C5x and UCC38C5x series devices are drop-in replacement for BiCMOS UCCx8C4x family and pin-

to-pin compatibile with the bipolar UC284x, UC384x, UC284xA, and UC384xA families. The new series offers

improved performance when compared to older bipolar devices and other competitive BiCMOS devices with

similar functionality. These improvements generally consist of tighter specification limits that are a subset of the

older product ratings. In new designs, these improvements can reduce the component count or enhance circuit

performance when compared to theolder generation devices.

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Product Folder Links: UCC28C50 UCC28C51 UCC28C52 UCC28C53 UCC28C54 UCC28C55 UCC28C56H

UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

8.2 Functional Block Diagram

VDD

UVLO

VREF

VREF Good

Logic

RT/CT

Osc

OUT

GND

( NOTE)

2.5V

E/A

PWM

Latch

COMP

PWM

Comparator

Toggle flip-flop used only in UCCx8C51, UCCx8C54, UCCx8C55, UCC28C57H/L, and UCC28C59

8.3 Feature Description

The BiCMOS design allows operation at high frequencies that were not feasible in the predecessor bipolar

devices. First, the output stage has been redesigned to drive the external power switch in approximately half the

time of the earlier devices. Second, the internal oscillator is more robust, with less variation as frequency

increases. This faster oscillator makes this device suitable for high speed applications and the trimmed

discharge current enables precise programming of the maximum duty cycle and dead-time limit. In addition, the

current sense to output delay is kept the same 45 ns (typical) as UCCx8C4x. Such a delay time in the current

sense results in superior overload protection at the power switch. The reduced start-up current of this device

minimizes steady state power dissipation in the startup resistor, and the low operating current maximizes

efficiency while running, increasing the total circuit efficiency, whether operating off-line, DC input, or battery

operated circuits. These features combine to provide a device capable of reliable, high-frequency operation.

表8-1. Improved Key Parameters

PARAMETER

UCCx8C4x

2.3 mA

100 µA

20 V

UCCx8C5x

1.3 mA

75 µA

Supply current at 52 kHz

Start-up current, maximum

V_VDDabsolute maximum

Reference voltage accuracy

30 V

± 1%

± 2%

UVLO and Dmax for Si FETs

UVLO and Dmax for SiC FETs

6 options

No options

VSSOP (8)

6 options

Smallest package option

VSSOP (8)

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UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

8.3.1 Detailed Pin Description

8.3.1.1 COMP

The error amplifier in the UCC28C5x family has a unity-gain bandwidth of 1 MHz. The COMP terminal can both

source and sink current. The error amplifier is internally current-limited, so that one can command zero duty

cycle by externally forcing COMP to GND.

8.3.1.2 FB

FB is the inverting input of the error amplifier. The noninverting input to the error amplifier is internally trimmed to

2.5 V ± 1%. FB is used to control the power converter voltage-feedback loop for stability. For best stability, keep

FB lead length as short as possible and FB stray capacitance as small as possible.

8.3.1.3 CS

The UCC28C5x current sense input connects directly to the PWM comparator. Connect CS to the MOSFET

source current sense resistor. The PWM uses this signal to terminate the OUT switch conduction. A voltage

ramp can be applied to this pin to run the device with a voltage mode control configuration or to add slope

compensation. To prevent false triggering due to leading edge noises, an RC current sense filter may be

required. The gain of the current sense amplifier is typically 3 V/V.

8.3.1.4 RT/CT

The internal oscillator uses a timing capacitor (C_CT) and a timing resistor (R_RT) to program the oscillator

frequency and maximum duty cycle. The operating frequency can be programmed based the curves in 图 7-1,

where the timing resistor can be found once the timing capacitor is selected. It is best for the timing capacitor to

have a flat temperature coefficient, typical of most COG or NPO type capacitors. For this converter, 15.4 kΩand

1000 pF were selected for R_RTand C_CTto operate at 110-kHz switching.

8.3.1.5 GND

GND is the signal and power returning ground. TI recommends separating the signal return path and the high

current gate driver path so that the signal is not affected by the switching current.

8.3.1.6 OUT

The high-current output stage of the UCCx8C5x to drive the external power switch has been kept the same as

the earlier devices UCC28C4x. To drive a power MOSFET directly, the totem-pole OUT driver sinks or source up

to 1 A peak of current. The OUT of the UCCx8C50, UCCx8C52, UCCx8C53 UCC28C56H/L and UCC28C58

devices switch at the same frequency as the oscillator and can operate near 100% duty cycle. In the UCCx8C51,

UCCx8C54, and UCCx8C55, UCC28C57H/L and UCC28C59, the switching frequency of OUT is one-half that of

the oscillator due to an internal T flip-flop. This limits the maximum duty cycle in the UCCx8C51, UCCx8C54,

and UCCx8C55, UCC28C57H/L and UCC28C59 to < 50%.

The UCCx8C5x family houses unique totem pole drivers exhibiting a 10-Ω impedance to the upper rail and a

5.5‑Ω impedance to ground, typically. This reduced impedance on the low-side switch helps minimize turn-off

losses at the power MOSFET, whereas the higher turnon impedance of the high-side is intended to better match

the reverse recovery characteristics of many high-speed output rectifiers. Transition times, rising and falling

edges, are typically 25 nanoseconds and 20 nanoseconds, respectively, for a 10% to 90% change in voltage.

A low impedance MOS structure in parallel with a bipolar transistor, or BiCMOS construction, comprises the

totem-pole output structure. This more efficient utilization of silicon delivers the high peak current required along

with sharp transitions and full rail-to-rail voltage swings. Furthermore, the output stage is self-biasing, active low

during under-voltage lockout type. With no VDD supply voltage present, the output actively pulls low if an

attempt is made to pull the output high. This condition frequently occurs at initial power-up with a power

MOSFET as the driver load.

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UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

8.3.1.7 VDD

VDD is the power input connection for this device. In normal operation, power VDD through a current limiting

resistor. The absolute maximum supply voltage is 30 V (extended from 20 V of UCCx8C4x) to facilitate more

designs and applications. The voltage level of 30 V, including any transients that may be present, cannot be

exceeded, device damage is likely if otherwise. Because of this limitation, the UCCx8C5x devices match the

predecessor bipolar devices, which could survive up to 30 V on the input bias pin. Because no internal clamp is

included in the device, the VDD pin must be protected from external sources which could exceed the 30 V level.

If containing the start-up and bootstrap supply voltage from the auxiliary winding N_Abelow 30 V under all line

and load conditions can not be achieved, use a zener protection diode from VDD to GND. Depending on the

impedance and arrangement of the bootstrap supply, this may require adding a resistor, R_VDD, in series with the

auxiliary winding to limit the current into the zener as shown in 图 8-1. Ensure that over all tolerances and

temperatures, the minimum zener voltage is higher than the highest UVLO upper turn-on threshold. To prevent

noise related problems, filter VDD with a ceramic bypass capacitor to GND. The VDD pin must be decoupled as

close to the GND pin as possible.

N_P

N_A

N_S

R_START

D_BIAS

Input

R_VDD

VDD

GND

OUT

C_VCC

C_VDDbp

0.1 mF

D_ZCLAMP

R_CS

图8-1. VDD Protection

Although nominal VDD operating current is only 1.3 mA, the total supply current is higher, depending on the OUT

current. Total VDD current is the sum of quiescent VDD current and the average OUT current. Knowing the

operating frequency and the MOSFET gate charge (Q_g), average OUT current can be calculated from 方程式1.

I_OUT= Q_g× f_SW

(1)

8.3.1.8 VREF

VREF is the voltage reference for the error amplifier and also for many other internal circuits in the IC. The 5-V

reference tolerance is ±1% for the UCC28C5x family. The high-speed switching logic uses VREF as the logic

power supply. The reference voltage is divided down internally to 2.5 V ±1% and connected to the error

amplifier's noninverting input for accurate output voltage regulation. The reference voltage sets the internal bias

currents and thresholds for functions such as the oscillator upper and lower thresholds along with the

overcurrent limiting threshold. The output short-circuit current is 55 mA (maximum). To avoid device over-heating

and damage, do not pull VREF to ground as a means to terminate switching. For reference stability and to

prevent noise problems with high-speed switching transients, bypass VREF to GND with a ceramic capacitor

close to the IC package. A ceramic capacitor with a minimum value of 0.1 µF is required. Additional VREF

bypassing is required for external loads on the reference. An electrolytic capacitor may also be used in addition

to the ceramic capacitor.

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UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

8.3.2 Undervoltage Lockout

Six sets of UVLO thresholds are available with turn-on and turnoff thresholds of: (14.5 V and 9 V), (8.4 V and 7.6

V), (7 V and 6.6 V), (18.8 V and 15.5 V), (18.8 V and 14.5V) and (16 V and 12.5V), respectively. The first set is

primarily intended for off-line and 48-V distributed power applications, where the wider hysteresis allows for

lower frequency operation and longer soft-starting time of the converter. The second set of UVLO option is ideal

for high frequency DC-DC converters typically running from a 12-VDC input. The third set is for battery powered

and portable applications. The fourth to sixth UVLO sets are suitable to drive SiC MOSFETs in high voltage

applications. 表8-2 shows the maximum duty cycle and UVLO thresholds by device.

表8-2. UVLO Options

MAXIMUM

DUTY CYCLE (%)

UVLO ON

(V)

UVLO OFF

(V)

DEVICE

NUMBER

100

14.5

8.4

UCCx8C52

UCCx8C53

UCCx8C50

UCC28C56H

7.6

6.6

15.5

18.8

100

18.8

14.5

12.5

UCC28C56L

UCC28C58

UCCx8C54

UCCx8C55

UCCx8C51

UCC28C57H

UCC28C57L

UCC28C59

14.5

8.4

7.6

6.6

18.8

15.5

14.5

12.5

During UVLO the IC draws less than 75 µA of supply current. Once crossing the turnon threshold the IC supply

current increases to a maximum of 2mA, typically 1.3 mA. This low start-up current allows the power supply

designer to optimize the selection of the startup resistor value to provide a more efficient design. In applications

where low component cost overrides maximum efficiency, the low run current of 1.3 mA (typical) allows the

control device to run directly through the single resistor to (+) rail, rather than requiring a bootstrap winding on

the power transformer, along with a rectifier. The start and run resistor for this case must also pass enough

current to allow driving the primary switching MOSFET, which may be a few milliamps in small devices.

< 2

< 0.075

OFF

Operating Voltage (V)

图8-2. UVLO ON and OFF Profile

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UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

8.3.3 ±1% Internal Reference Voltage

The BiCMOS internal reference of 2.5 V has an enhanced design, and uses production trim to allow initial

accuracy of ±1% at room temperature and ±2% over the full temperature range. This reference voltage can be

used to eliminate an external reference in applications that do not require the extreme accuracy afforded by the

additional device. This reference voltage is useful for non-isolated DC-DC applications, where the control device

is referenced to the same common as the output. It is also applicable in off-line designs that regulate on the

primary side of the isolation boundary by looking at a primary bias winding, or from a winding on the output

inductor of a buck-derived circuit.

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UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

8.3.4 Current Sense and Overcurrent Limit

An external series resistor (R_CS) senses the current and converts this current into a voltage that becomes the

input to the CS pin. The CS pin is the noninverting input to the PWM comparator. The device compares the CS

input with a signal proportional to the error amplifier output voltage. The gain of the current sense amplifier is

typically 3 V/V. The peak I_SENSEcurrent is determined using 方程式2

V_CS

I_SENSE

R_CS

(2)

The typical value for V_CSis 1 V. A small RC filter (R_CSFand C_CSF) may be required to suppress switch transients

caused by the reverse recovery of a secondary side diode or equivalent capacitive loading in addition to parasitic

circuit impedances. The time constant of this filter should be considerably less than the switching period of the

converter.

Error

Amplifier

2 R

COMP

1 V

PWM

Comparator

I_SENSE

R_CSF

C_CSF

R_CS

GND

图8-3. Current-Sense Circuit Schematic

Cycle-by-cycle pulse width modulation performed at the PWM comparator essentially compares the error

amplifier output to the current sense input. This is not a direct volt-to-volt comparison, as the error amplifier

output network incorporates two diodes in series with a resistive divider network before connecting to the PWM

comparator. The two-diode drop adds an offset voltage that enables zero duty cycle to be achieved with a low

amplifier output. The 2R/R resistive divider facilitates the use of a wider error amplifier output swing that can be

more symmetrically centered on the 2.5-V noninverting input voltage.

The 1-V Zener diode associated with the PWM comparator input from the error amplifier is not an actual diode in

the device design, but an indication that the maximum current sense input amplitude is 1 V (typical). When this

threshold is reached, regardless of the error amplifier output voltage, cycle-by-cycle current limiting occurs, and

the output pulse width is terminated within 35 ns (typical). The minimum value for this current limit threshold is

0.9 V with a 1.1-V maximum. In addition to the tolerance of this parameter, the accuracy of the current sense

resistor, or current sense circuitry, must be taken into account. It is advised to factor in the worst case of primary

and secondary currents when sizing the ratings and worst-case conditions in all power semiconductors and

magnetic components.

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UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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8.3.5 Reduced-Discharge Current Variation

The oscillator design for the UCC28C5x controllers incorporates a trimmed discharge current to accurately

program maximum duty cycle and operating frequency. In its basic operation, a timing capacitor (C_CT) is charged

by a current source, formed by the timing resistor (R_RT) connected to the device reference voltage (VREF). The

oscillator design incorporates comparators to monitor the amplitude of the timing capacitor voltage. The

exponentially shaped waveform charges up to a specific amplitude representing the oscillator upper threshold of

3 V. After the controller reaches this level, an internal current sink to ground turns on and the capacitor begins to

discharge. This discharge continues until the oscillator lower threshold has reached 0.7 V at which point the

current sink is turned off. Next, the timing capacitor starts charging again and a new switching cycle begins.

VDD_ON

VDD_OFF

VREF

R_RT

C_CT

RT/CT

GND

t_ON

t_PERIOD

t_OFF

8.4 mA

图8-4. Oscillator Circuit

While the device discharges the timing capacitor, resistor R_RTcontinues attempting to charge C_CT. It is the exact

ratio of these two currents, the discharging versus the charging current, which specifies the maximum duty cycle.

During the discharge time of C_CT, the device output is always off. This represents an ensured minimum off time

of the switch, commonly referred to as dead-time. To program an accurate maximum duty cycle, use the

information provided in Maximum Duty Cycle vs Oscillator Frequency for maximum duty cycle versus oscillator

frequency. Any number of maximum duty cycles can be programmed for a given frequency by adjusting the

values of R_RTand C_CT. After selecting the value of R_RT, find the oscillator timing capacitance using the curves in

Oscillator Frequency vs Timing Resistance and Capacitance. However, because resistors are available in more

precise increments, typically 1%, and capacitors are only available in 5% accuracy, it might be more practical to

select the closest capacitor value first and then calculate the timing resistor value.

8.3.6 Oscillator Synchronization

Synchronization is best achieved by forcing the timing capacitor voltage above the oscillator internal upper

threshold. A small resistor is placed in series with C_CTto GND. This resistor serves as the input for the sync

pulse which raises the C_CTvoltage above the oscillator internal upper threshold. The PWM is allowed to run at

the frequency set by R_RTand C_CTuntil the sync pulse appears. This scheme offers several advantages including

having the local ramp available for slope compensation. The UCC28C5x oscillator must be set to a lower

frequency than the sync pulse stream, typically 20 percent with a 0.5-V pulse applied across the resistor.

VREF

R_RT

C_CT+ SYNC

C_CT

RT/CT

GND

SYNC

C_CT

50 ꢀ

图8-5. Oscillator Synchronization Circuit

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UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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8.3.7 Soft-Start Timing

The soft-start timing is the technique to gradually power up the converter in a well-controlled fashion by slowly

increasing the effective duty cycle starting at zero and gradually rising. Following start-up of the PWM, the error

amplifier inverting input is low, commanding the error amplifier’s output to go high. The output stage of the

amplifier can source 1 mA typically, which is enough to drive most high impedance compensation networks, but

not enough for driving large loads quickly. Soft-start timing is achieved by charging a fairly large value, >1-µF,

capacitor (C_SS) connected to the error amplifier output through a PNP transistor as shown in 图8-6

VREF

R_SS

COMP

Z_F

2N2907

C_SS

Z_I

To VOUT

图8-6. Soft-Start Implementation

The limited charging current of the amplifier into the capacitor translates into a dv/dt limitation on the error

amplifier output. This directly corresponds to some maximum rate of change of primary current in a current mode

controlled system as one of the PWM comparator inputs gradually rises. The values of R_SSand C_SSmust be

selected to bring the COMP pin up at a controlled rate, limiting the peak current supplied by the power stage.

After the soft-start interval is complete, the capacitor continues to charge to VREF, effectively removing the PNP

transistor from the circuit consideration. Soft-start timing offers a different, frequently preferred function in current

mode controlled systems than it does in voltage mode control. In current mode, soft start controls the rising of

the peak switch current. In voltage mode control, soft start gradually widens the duty cycle, regardless of the

primary current or rate of ramp-up.

The purpose of resistor R_SSand the diode is to remove the soft-start capacitor from the error amplifier path

during normal operation, after the soft-start period completes and the capacitor charges fully. The optional diode

in parallel with the resistor forces a soft-start period each time the PWM goes through UVLO condition that

forces VREF to go low. Without the diode, the capacitor remains charged during a brief loss of supply or brown-

out, and the device does not emable a soft-start function upon re-application of VDD.

8.3.8 Enable and Disable

There are several ways to enable or disable the UCC28C5x devices, depending on which type of restart is

required. The two basic techniques use external transistors to either pull the error amplifier output low (< 2 V_BE

)

or pull the current sense input high (> 1.1 V). Application of the disable signal causes the output of the PWM

comparator to be high. The PWM latch is reset dominant so that the output remains low until the next clock cycle

after the shutdown condition at the COMP or CS pin is removed. Another choice for restart without a soft-start

period is to pull the current sense input above the cycle-by-cycle current limiting threshold. A logic level P-

channel FET from the reference voltage to the current sense input can be used.

COMP

DISABLE

图8-7. Disable Circuit

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UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

8.3.9 Slope Compensation

With current mode control, slope compensation is required to stabilize the overall loop with duty cycles

exceeding 50%. Although not required, slope compensation also improves stability in applications using below a

50% maximum duty cycle. Slope compensation is introduced by injecting a portion of the oscillator waveform to

the actual sensed primary current. The two signals are summed together at the current sense input (CS)

connection at the filter capacitor. To minimize loading on the oscillator, it is best to buffer the timing capacitor

waveform with a small transistor whose collector is connected to the reference voltage.

VREF

0.1 µF

R_RT

RT/CT

C_CT

R_RAMP

R_CSF

I_SENSE

R_CS

C_CSF

图8-8. Slope Compensation Circuit

8.3.10 Voltage Mode

In certain applications, voltage mode control may be a preferred control strategy for a variety of reasons. Voltage

mode control is easily executable with any current mode controller, especially the UCC28C5x family members.

Implementation requires generating a 0-V to 0.9-V sawtooth shaped signal to input to the current sense pin (CS)

which is also one input to the PWM comparator. This is compared to the divided down error amplifier output

voltage at the other input of the PWM comparator. As the error amplifier output is varied, it intersects the

sawtooth waveform at different points in time, thereby generating different pulse widths. This is a straightforward

method of linearly generating a pulse whose width is proportional to the error voltage.

Implementation of voltage mode control is possible by using a fraction of the oscillator timing capacitor (C_CT

)

waveform. This value can be divided down and fed to the current sense pin as shown in 图 8-9. The oscillator

timing components must be selected to approximate as close to a linear sawtooth waveform as possible.

Although exponentially charged, large values of timing resistance and small values of timing capacitance help

approximate a more linear shaped waveform. A small transistor is used to buffer the oscillator timing

components from the loading of the resistive divider network. Due to the offset of the oscillator’s lower timing

threshold, a DC blocking capacitor is added.

VREF

R_RT

2N2222

RT/CT

C_CT

图8-9. Current Mode PWM Used as a Voltage Mode PWM

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UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

8.4 Device Functional Modes

8.4.1 Normal Operation

During normal operating mode, the controller can be used in peak current mode or voltage mode control. When

the converter is operating in peak current mode, the controller regulates the converter's peak current and duty

cycle. When used in voltage mode control, the controller regulates the power converter's duty cycle. The

regulation of the system's peak current and duty cycle can be achieved with the use of the integrated error

amplifier and external feedback circuitry.

8.4.2 UVLO Mode

During the system start-up, VDD voltage starts to rise from 0 V. Before the VDD voltage reaches its

corresponding turn-on threshold, the IC is operating in UVLO mode. During UVLO mode operation, the VREF

pin voltage is not generated. When VDD is above 1 V and below the turn-on threshold, the VREF pin is actively

pulled low. This behavior allows VREF to be used as a logic signal to indicate UVLO mode. If the bias voltage to

VDD drops below the UVLO-OFF threshold, the PWM switching stops and VREF returns to 0 V. The device can

be restarted by applying a voltage greater than the UVLO-ON threshold to the VDD pin.

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UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

9 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The UCC28C5x controllers are peak current mode pulse width modulators. These controllers have an onboard

amplifier and can be used in isolated and nonisolated power supply designs. The onboard totem pole gate driver

is capable of delivering 1 A of peak current. This high-speed PWM is capable of operating at switching

frequencies up to 1 MHz. Since UCCx8C5x can be used to directly substitute UCCx8C4x by drop-in, the design

steps are the same as those for UCCx8C4x. The same design example, including the layout, of UCCx8c4x is re-

used for UCCx8C5x as shown below. 图9-1 shows a typical off-line application using UCC38C44.

D50

12 V

OUT

R10

C52

C55

C12

AC Input

R56

BR1

100 V_AC– 240 V_AC

EMI Filter

Required

L50

R11

D51

C1A

C18

5 V

OUT

R12

RT1

C53

C54

R55

SEC

COMMON

R50

UCC38C44

R16

COMP REF

IC2

R57

C50

IC2

VCC

OUT

R53

R52

C13

C51

R50

RT/CT GND

IC3

R54

图9-1. Typical Off-Line Application

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UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

图 9-2 shows a forward converter with synchronous rectification. This application provides 48 V to 3.3 V at 10 A

with over 85% efficiency, and uses the UCC38C42as the secondary-side controller and UCC3961 as the

primary-side startup control device.

4.7uH

3r3V

C18

1nF

4700pF

C21

0.1uF

C17

R20

4700pF

C19

R21

C20

470uF

VinP

10k

470uF

PWRGND

32.4k

C25

0.047uF

R27

4.7

R26

4.7

470uF

1.2k

1.5k

R19

BAR74

76.8k

2.4k

TPS2832

VinN

R28

BAR74

100

BOOT

0.33

5.1k

PGND HIDR

C26

OVS

UVS

S_T

BTLO

LODR

4.7

2uF

C22

R23

402

10nF

V_CC

UCC3961

4.7nF

V_DD

OUT

PGND

R10

R16

21.5k

0.22uF

C24

0.1uF

1uF

C23

680pF

C13

R_T

COMP

REF

V_CC

R11

R22

100

C16

R17

20k

46.4k

0.22uF

REF

AGND

5.6nF

0.1uF

UCC38C4x

V_S

R15

50k

OUT

GND

C15

1uF

C14

1uF

100pF

470pF

RT/CT

R24

20k

BZX84C15LT1

C12

3300pF

R14

R18

7.5k

20k 40%

C11

R12

200

R25

20k

1500pF

C10

2.7nF

R13

300

图9-2. Forward Converter with Synchronous Rectification Using the UCC38C42 as the Secondary-Side

Controller

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UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

9.2 Typical Application

A typical application for the UCC28C42 controller in an off-line flyback converter is shown in 图 9-3. The

UCC28C52 controller can be used as drop-in replacement for UCC28C42.The controller uses an inner current

control loop that contains a small current sense resistor which senses the primary inductor current ramp. This

current sense resistor transforms the inductor current waveform to a voltage signal that is input directly into the

primary side PWM comparator. This inner loop determines the response to input voltage changes. An outer

voltage control loop involves comparing a portion of the output voltage to a reference voltage at the input of an

error amplifier. When used in an off-line isolated application, the voltage feedback of the isolated output is

accomplished using a secondary-side error amplifier and adjustable voltage reference, such as the TL431. The

error signal crosses the primary to secondary isolation boundary using an opto-isolator whose collector is

connected to the VREF pin and the emitter is connected to FB. The outer voltage control loop determines the

response to load changes.

D_CLAMP

= 85 VAC

to 265VAC

C_SNUB

10nF

R_SNUB

50kꢀ

D_OUT

D_BRIDGE

V_OUT

12V,

N_S

180µF

N_P

N_A

R_START

420k ꢀ

C_OUT

2200µF

C_SS

R_VDD

22 ꢀ

D_BIAS

C_VDD

120µF

R_SS

L_P=1. 5 mH

N_P:N_S=10

N_P:N_A=10

UCC28C42

COMP VREF

R_COMPp

10kꢀ

C_COMPp

10nF

VDD

OUT

GND

R_G

10 ꢀ

R_RT

15.4k ꢀ

Q_SW

RT/CT

D_ZC_VDDbpC_VREF

18V 0.1µF

R_BLEEDER

10kꢀ

R_CS

0. 75 ꢀ

1µF

C_CT

1000pF

R_LED

1.3 kꢀ

R_TLbias

1 kꢀ

C_RAMP

10nF

R_CSF

3. 8kꢀ

R_RAMP

24.9 kꢀ

OPTO-

COUPLER

10V

R_FBU

9. 53kꢀ

R_P

Not Populated

C_CSF

100pF

R_FBG

4. 99kꢀ

R_COMPzC_COMPz

88. 7kꢀ 0. 01µF

R_OPTO

1k ꢀ

TL431

R_FBB

2. 49kꢀ

图9-3. Typical Application Design Schematic

9.2.1 Design Requirements

表 9-1 shows a typical set of performance requirements for an off-line flyback converter capable of providing

48 W at 12-V output voltage from a universal AC input. The design uses peak primary current control in a

continuous current mode PWM converter.

表9-1. Design Parameters

PARAMETER

Input Voltage

TEST CONDITIONS

MIN

NOM

115/230

50/60

MAX

265

UNIT

V_RMS

V_IN

f_LINE

V_OUT

V_RIPPLE

I_VOUT

f_SW

Line Frequency

Output Voltage

11.75

12.25

100

_VOUT(min)≤I_VOUT≤I_VOUT(max)

Output Ripple Voltage

Output Current

mVpp

Switching Frequency

110

kHz

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English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

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表9-1. Design Parameters (continued)

PARAMETER

Efficiency

TEST CONDITIONS

MIN

NOM

MAX

UNIT

85%

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9.2.2 Detailed Design Procedure

This procedure outlines the steps to design an off-line universal input continuous current mode (CCM) flyback

converter. See 图9-3 for component names referred to in the design procedure.

9.2.2.1 Input Bulk Capacitor and Minimum Bulk Voltage

Bulk capacitance may consist of one or more capacitors connected in parallel, often with some inductance

between them to suppress differential-mode conducted noise. The value of the input capacitor sets the minimum

bulk voltage;. Setting the bulk voltage lower by using minimal input capacitance results in higher peak primary

currents leading to more stress on the MOSFET switch, the transformer, and the output capacitors. Setting the

bulk voltage higher by using a larger input capacitor results in higher peak current from the input source and the

capacitor itself is physically larger. Compromising between size and component stresses determines the

acceptable minimum input voltage. The total required value for the primary-side bulk capacitance (C_IN) is

selected based upon the power level of the converter (P_OUT), the efficiency target (η), the minimum input

voltage (V_IN(min)), and is chosen to maintain an acceptable minimum bulk voltage level (V_BULK(min)), using 方程式

V_{BULK (min )}

2 × P × F0.25 + × arcsin F

2 × V

IN(min )

C_IN

k2 × V_I²_{N(min )}F V_B²_{ULK (min )}o × f_{LINE (min )}

(3)

where

• V_IN(min)is the RMS value of the minimum AC input voltage (85 VRMS) whose minimum line frequency is

denoted as f_LINE(min), equal to 47 Hz

Based on 方程式 3, to achieve a minimum bulk voltage of 75 V, assuming 85% converter efficiency, the bulk

capacitor must be larger than 126 µF. this design uses a value of 180 µF, with consideration for component

tolerances and efficiency estimation.

9.2.2.2 Transformer Turns Ratio and Maximum Duty Cycle

The transformer design begins with selecting a suitable switching frequency for the given application. The

UCC28C42 is capable of switching up to 1 MHz but considerations such as overall converter size, switching

losses, core loss, system compatibility, and interference with communication frequency bands generally

determine an optimum frequency that should be used. For this off-line converter, the switching frequency (f_SW) is

selected to be 110 kHz as a compromise to minimize the transformer size and the EMI filter size, and still have

acceptable losses.

The transformer primary to secondary turns ratio (N_PS) can be selected based on the desired MOSFET voltage

rating and the secondary diode voltage rating. Because the maximum input voltage is 265 VRMS, the peak bulk

input voltage can be calculated as shown in 方程式4.

V_{BULK (max )}= ¾2 × V

N 375 V

IN(max )

(4)

To minimize the cost of the system, a readily available 650-V MOSFET is selected. Derating the maximum

voltage stress on the drain to 80% of its rated value and allowing for a leakage inductance voltage spike of up to

30% of the maximum bulk input voltage, the reflected output voltage must be less than 130 V as shown in 方程

式5.

V_REFLECTED= 0.8ì V_DS(rated)-1.3ì V_BULK(max)= 130.2V

(

)

(5)

The maximum primary to secondary transformer turns ratio (N_PS) for a 12 V output can be selected as

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V_REFLECTED

N_PS

= 10.85

V_OUT

(6)

A turns ratio of N_PS= 10 is used in the design example.

The auxiliary winding is used to supply bias voltage to the controller. Maintaining the bias voltage above the VDD

minimum operating voltage after turnon is required for stable operation. The minimum VDD operating voltage for

the controller selected for this design is 10 V. The auxiliary winding is selected to support a 12 V bias voltage so

that it is above the minimum operating level but maintains a low level of losses in the IC. The primary to auxiliary

turns ratio (N_PA) can be calculated from 方程式7:

V_OUT

N_PA= N_PS

= 10

V_BIAS

(7)

The output diode experiences a voltage stress that is equal to the output voltage plus the reflected input voltage:

V_{BULK max}

;

V_DIODE

+ V_OUT= 49.5 V

N_PS

(8)

TI recommends a Schottky diode with a rated blocking voltage greater than 60 V to allow for voltage spikes due

to ringing. The forward voltage drop (V_F) of this diode is estimated to be equal to 0.6 V

To avoid high peak currents, the flyback converter in this design operates in continuous conduction mode. Once

N_PSis determined, the maximum duty cycle (D_MAX) can be calculated using the transfer function for a CCM

flyback converter:

V_OUT+ V_F

V_BULK

D_MAX

= l

p × l

N_PS

1 F D_MAX

;

min

(9)

N_PSì V

+ V_F

(

)

OUT

D_MAX

= 0.627

V_BULK(min)+ N_PSì V

+ V_F

(

)

(10)

Because the maximum duty cycle exceeds 50%, and the design is an off-line (AC-input) application, the

UCC28C42 is best suited for this application.

9.2.2.3 Transformer Inductance and Peak Currents

For this design example, the transformer magnetizing inductance is selected based upon the CCM condition. An

inductance value that allows the converter to stay in CCM over a wider operating range before transitioning into

discontinuous current mode is used to minimize losses due to otherwise high currents and also to decrease the

output ripple. The design of the transformer in this example sizes the inductance so the converter enters CCM

operation at approximately 10% load and minimum bulk voltage to minimize output ripple.

The inductor (L_P) for a CCM flyback can be calculated using 方程式11.

_;o²× l

N_PS× V_OUT

min

kV_BULK

min

V_BULK

_;+ N_PS× V_OUT

L_P=

0.1 × P × f_SW

(11)

where

• P_INis estimated by dividing the maximum output power (P_OUT) by the target efficiency (η)

• f_SWis the switching frequency of the converter

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For the UCC28C42 the switching frequency is equal to the oscillator frequency and is set to 110 kHz. Selecting

f_SWto be 110 kHz provides a good compromise between size of magnetics, switching losses, and places the first

harmonic below the 150-kHz lower limit of EN55022. Therefore, the transformer inductance must be

approximately 1.8 mH. A 1.5 mH inductance is chosen as the magnetizing inductance, L_P, value for this design.

Based on calculated inductor value and the switching frequency, the current stress of the MOSFET and output

diode can be calculated.

The peak current in the primary-side MOSFET of a CCM flyback can be calculated as shown in 方程式12.

N_PS× V_OUT

;

V_{BULK (min )}

2 × L_m

V_{BULK min}+ N × V_OUT

;

I_PK

+ n

MOSFET

N_PS× V_OUT

f_SW

V_{BULK min}

;

V_{BULK min}+ N × V_OUT

;

(12)

The MOSFET peak current is 1.36 A. The RMS current of the MOSFET is calculated to be 0.97 A as shown in 方

程式13. Therefore, IRFB9N65A is selected to be used as the primary-side switch.

D_MAX²× I_PK

× V_{BULK (min )}

MOSFET

V_{BULK (min )}

L_P× f_SW

D_MAX

²o

MOSFET

I_{RM S}

× l

p F F

G + kD_MAX× I_PK

MOSFET

L_P× f_SW

(13)

The output diode peak current is equal to the MOSFET peak current reflected to the secondary side.

I_PK

= N_PS× I_PK

= 13.634 A

MOSFET

DIODE

(14)

The diode average current is equal to the total output current (4 A) combined with a required 60-V rating and

13.6-A peak current requirement, a 48CTQ060-1 is selected for the output diode.

9.2.2.4 Output Capacitor

The total output capacitance is selected based upon the output voltage ripple requirement. In this design, 0.1%

voltage ripple is assumed. Based on the 0.1% ripple requirement, the capacitor value can be selected using 方程

式15.

N_PS× V_OUT

I_OUT

V_{BULK min}+ N × V_OUT

;

C_OUT

= 1865 JF

0.001 × V_OUT× f_SW

(15)

To design for device tolerances, a 2200-µF capacitor was selected.

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9.2.2.5 Current Sensing Network

The current sensing network consists of the primary-side current sensing resistor (R_CS), filtering components

R_CSFand C_CSF, and optional R_P. Typically, the direct current sense signal contains a large amplitude leading

edge spike associated with the turnon of the main power MOSFET, reverse recovery of the output rectifier, and

other factors including charging and discharging of parasitic capacitances. Therefore, C_CSFand R_CSFform a low-

pass filter that provides immunity to suppress the leading edge spike. For this converter, C_CSFis chosen to be

100 pF.

Without R_P, R_CSsets the maximum peak current in the transformer primary based on the maximum amplitude of

the CS pin, which is specified to be 1 V. To achieve 1.36-A primary side peak current, a 0.75-Ω resistor is

chosen for R_CS

The high current sense threshold of CS helps to provide better noise immunity to the system but also results in

higher losses in the current sense resistor. These current sense losses can be minimized by injecting an offset

voltage into the current sense signal using R_P. R_Pand R_CSFform a resistor divider network from the current

sense signal to the reference voltage of the controller (V_VREF) which adds an offset to the current sense voltage.

This technique still achieves current mode control with cycle-by-cycle over-current protection. To calculate

required offset value (V_OFFSET), use 方程式16.

R_CSF

V_OFFSET

× V_REF

R_CSF+ R_P

(16)

After adding the R_Presistance, adjust the R_CSvalue accordingly.

9.2.2.6 Gate Drive Resistor

R_Gis the gate driver resistor for the power switch (Q_SW). The selection of this resistor value must be done in

conjunction with EMI compliance testing and efficiency testing. Using a larger resistor value for R_Gslows down

the turnon and turnoff of the MOSFET. A slower switching speed reduces EMI but also increases the switching

loss. A tradeoff between switching loss and EMI performance must be carefully performed. For this design, a

10‑Ωresistor was chosen for the gate drive resistor.

9.2.2.7 VREF Capacitor

A precision 5-V reference voltage performs several important functions. The reference voltage is divided down

internally to 2.5 V and connected to the error amplifier’s noninverting input for accurate output voltage

regulation. Other duties of the reference voltage are to set internal bias currents and thresholds for functions

such as the oscillator upper and lower thresholds. Therefore, the reference voltage must be bypassed with a

ceramic capacitor. A 1-µF, 16-V ceramic capacitor was selected for this converter. Placement of this capacitor on

the physical printed-circuit board layout must be as close as possible to the respective VREF and GND pins.

9.2.2.8 RT/CT

RT/CT is the oscillator timing pin. For fixed frequency operation, set the timing capacitor charging current by

connecting a resistor from VREF to RT/CT. Set the frequency by connecting timing capacitor from RT/CT to

GND. For the best performance, keep the timing capacitor lead to GND as short and direct as possible. If

possible, use separate ground traces for the timing capacitor and all other functions.

The controller's oscillator allows for operation to 1 MHz. The device uses an external resistor to set the charging

current for the external capacitor, which determines the oscillator frequency. TI recommends timing resistor

values from 1 kΩto 100 kΩand timing capacitor values from 220 pF to 4.7 nF. The UCCx8C5x oscillator is true

to the curves of the original BiCMOS devices at lower frequencies, yet extends the frequency programmability

range to at least 1 MHz. This programmability allows the device to offer pin-to-pin capability where required, yet

capable of extending the operational range to the higher frequencies.

See 图7-1 for component values for setting the oscillator frequency.

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UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

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9.2.2.9 Start-Up Circuit

At start-up, the IC gets its power directly from the high-voltage bulk, through a high-voltage resistor (R_START).

The selection of the start-up resistor is the tradeoff between power loss and start-up time. The current flowing

through R_STARTat the minimum input voltage must be higher than the VDD current under UVLO conditions (100

µA at its maximum value). A resistance of 420-kΩ was chosen for R_START, providing 250 µA of start-up current

at low-line conditions. The start-up resistor is physically comprised of two 210-kΩ resistors in series to meet the

high voltage requirements and power rating at high-line.

After VDD is charged up above the UVLO-ON threshold, the UCC28C42 starts to consume full operating current.

The VDD capacitor is required to provide enough energy to prevent its voltage from dropping below the UVLO-

OFF threshold during start-up, before the output is able to reach its regulated level. A large bulk capacitance

would hold more energy but would result in slower start-up time. In this design, a 120-µF capacitor is chosen to

provide enough energy and maintain a start-up time of approximately 7 seconds. For faster start-up, the bulk

capacitor value may be decreased or the R_STARTresistor modified to a lower value.

9.2.2.10 Voltage Feedback Compensation

Feedback compensation, also called closed-loop control, can reduce or eliminate steady state error, reduce the

sensitivity of the system to parametric changes, change the gain or phase of a system over some desired

frequency range, reduce the effects of small signal load disturbances and noise on system performance, and

create a stable system from an unstable system. A system is stable if its response to a perturbation is that the

perturbation eventually dies out. A peak current mode flyback uses an outer voltage feedback loop to stabilize

the converter. To adequately compensate the voltage loop, the open-loop parameters of the power stage must

be determined.

9.2.2.10.1 Power Stage Poles and Zeroes

The first step in compensating a fixed frequency flyback is to verify if the converter is continuous conduction

mode (CCM) or discontinuous conduction mode (DCM). If the primary inductance (L_P) is greater than the

inductance for DCM or CCM boundary mode operation, called the critical inductance (L_Pcrit), then the converter

operates in CCM:

L_P> L_Pcrit, then CCM

(17)

;

R_OUT× N_PS

L_Pcrit

× l

2 × f_SW

V + V_OUT× N_PS

(18)

For the entire input voltage range, the selected inductor has a value larger than the critical inductor. Therefore,

the converter operates in CCM and the compensation loop requires design based on CCM flyback equations.

The current-to-voltage conversion is done externally with the ground-referenced R_CSand the internal 2R/R

resistor divider which sets up the internal current sense gain, A_CS= 3. The exact value of these internal resistors

is not critical but the IC provides tight control of the resistor divider ratio, so regardless of the actual resistor

value variations their relative value to each other is maintained.

The DC open-loop gain (G_O) of the fixed-frequency voltage control loop of a peak current mode control CCM

flyback converter shown in 方程式 19 is approximated by first using the output load (R_OUT), the primary to

secondary turns ratio (N_PS), and the maximum duty cycle (D) as calculated in 方程式20.

R_OUT× N_PS

R_CS× A_CS

G_O=

;

1 F D

;

+ 2 × M + 1

R_L

(19)

In 方程式 19, D is calculated with 方程式 20, τ_Lis calculated with 方程式 21, and M is calculated with 方程式

22.

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N_PS× V_OUT

D =

;

V_BULKmin+ N_PS× V_OUT

(20)

(21)

(22)

2 × L_P× f_SW

R_L=

;

R_OUT× N_PS

V_OUT× N_PS

V_BULKmin

M =

For this design, a converter with an output voltage (V_OUT) of 12 V, and 48 W relates to an output load (R_OUT

)

equal to 3 Ω at full load. With a maximum duty cycle of 0.627, a current sense resistance of 0.75 Ω, and a

primary to secondary turns-ratio of 10, the open-loop gain calculates to 3.082 or 9.776 dB.

A CCM flyback has two zeroes that are of interest. The ESR and the output capacitance contribute a left-half

plane zero (ω_ESRz) to the power stage, and the frequency of this zero (f_ESRz), are calculated with 方程式 23 and

方程式24.

X_ESRz

R_ESR× C_OUT

(23)

(24)

f_ESRz

2 × N × R_ESR× C_OUT

The f_ESRzzero for an output capacitance of 2200 µF and a total ESR of 43 mΩis located at 1.682 kHz.

CCM flyback converters have a zero in the right-half plane (RHP) in their transfer function. A RHP zero has the

same 20 dB per decade rising gain magnitude with increasing frequency just like a left-half plane zero, but it

adds a 90° phase lag instead of lead. This phase lag tends to limit the overall loop bandwidth. The frequency

location (f_RHPz) of the RHP zero (ω_RHPz) is a function of the output load, the duty cycle, the primary inductance

(L_P), and the primary to secondary side turns ratio (N_PS).

;

R_OUT× 1 F D × N_PS

X_RHPz

L_P× D

(25)

;

R_OUT× 1 F D × N_PS

f_RHPz

2 × N × L_P× D

(26)

The right-half plane zero frequency increases with higher input voltage and lighter load. Generally, the design

requires consideration of the worst case of the lowest right-half plane zero frequency and the converter must be

compensated at the minimum input and maximum load condition. With a primary inductance of 1.5 mH, at 75-V

DC input, the RHP zero frequency (f_RHPz) is equal to 7.07 kHz at maximum duty cycle, full load.

The power stage has one dominate pole (ω_P1) which is in the region of interest, located at a lower frequency

(f_P1); which is related to the duty cycle, the output load, and the output capacitance, and calculated with 方程式

28. There is also a double pole placed at half the switching frequency of the converter (f_P2) calculated with 方程

式30. For this example, pole f_P1is located at 40.37 Hz and f_P2is at 55 kHz.

;

1 F D

+ 1 + D

R_L

X_P1

R_OUT× C_OUT

(27)

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UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

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;

1 F D

+ 1 + D

R_L

f_P1

2 × N × R_OUT× C_OUT

(28)

(29)

X_P2= N × f_SW

f_SW

f_P2

(30)

9.2.2.10.2 Slope Compensation

Slope compensation is the large signal subharmonic instability that can occur with duty cycles that may extend

beyond 50% where the rising primary side inductor current slope may not match the falling secondary side

current slope. The subharmonic oscillation would result in an increase in the output voltage ripple and may even

limit the power handling capability of the converter.

The target of slope compensation is to achieve an ideal quality coefficient (Q_P), equal to 1 at half of the switching

frequency. The Q_Pis calculated with 方程式31.

Q_P=

;

N × M_C× 1 F D F 0.5

(31)

where

• D is the primary side switch duty cycle

• M_Cis the slope compensation factor, which is defined with 方程式32

S_e

M_C= + 1

S_n

(32)

where

• S_eis the compensation ramp slope

• S_nis the inductor rising slope

The optimal goal of the slope compensation is to achieve Q_P= 1; upon rearranging 方程式 32 the ideal value of

slope compensation factor is determined:

+ 0.5

M_ideal

1 F D

(33)

For this design to have adequate slope compensation, M_Cmust be 2.193 when D reaches it maximum value of

0.627.

The inductor rising slope (S_n) at the CS pin is calculated with 方程式34.

INmin

× R_CS

S_n=

= 0.038

L_P

(34)

The compensation slope (S_e) is calculated with 方程式35.

;

S_e= M_CF 1 × S_n= 44.74

(35)

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UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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The compensation slope is added into the system through R_RAMPand R_CSF. The C_RAMPis an AC-coupling

capacitor that allows the voltage ramp of the oscillator to be used without adding an offset to the current sense;

select a value to approximate a high-frequency short circuit, such as 10 nF, as a starting point and make

adjustments if required. The R_RAMPand R_CSFresistors form a voltage divider from the oscillator charge slope

and this proportional ramp is injected into the CS pin to add slope compensation. Choose the value of R_RAMPto

be much larger than the R_RTresistor so that it does not load down the internal oscillator and result in a frequency

shift. The oscillator charge slope is calculated using the peak-to-peak voltage of the RT/CT sawtooth waveform

(V_OSCpp) equal to 1.9 V, and the minimum ON time, as shown in 方程式37.

t_ONmin

f_SW

(36)

V_OSCpp

1.9 V

S_OSC

= 333

t_ONmin

5.7 Js

(37)

To achieve a 44.74-mV/µs compensation slope, R_CSFis calculated with 方程式 38. In this design, R_RAMPis

selected as 24.9 kΩ, a 3.8-kΩresistor was selected for R_CSF

R_RAMP

R_CSF

S_OSC

S_e

F 1

(38)

9.2.2.10.3 Open-Loop Gain

Once the power stage poles and zeros are calculated and the slope compensation is determined, the power

stage open-loop gain and phase of the CCM flyback converter can be plotted as a function of frequency. The

power stage transfer function can be characterized with 方程式39.

: ;

s f

: ;

s f

X_RHPz

l1 +

p × l1 F

X_ESRz

: ;

H_OPENs = G₀×

: ;

s f

X_P1

: ;

s f

: ;²

s f

1 +

X_P2× Q_P

;

X_P2

(39)

(40)

The bode for the open-loop gain and phase can be plotted by using 方程式40.

: ;

:ꢀ

: ;ꢀ;

Gain_OPENs = 20 × log H_OPENs

See 图9-4 and 图9-5.

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UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

-45

-5

-90

-10

-15

-20

-135

-180

-25

100 1000

frequency (Hz)

10000

100000

100 1000

frequency (Hz)

10000

100000

D002

D001

图9-5. Converter Open-Loop Bode Plot - Phase

图9-4. Converter Open-Loop Bode Plot - Gain

9.2.2.10.4 Compensation Loop

The design of the compensation loop involves selecting the appropriate components so that the required gain,

poles, and zeros can be designed to result in a stable system over the entire operating range. There are three

distinct portions of the loop: the TL431, the opto-coupler, and the error amplifier. Each of these stages combines

with the power stage to result in a stable robust system.

For good transient response, the bandwidth of the finalized design must be as large as possible. The bandwidth

of a CCM flyback, f_BW, is limited to ¼ of the RHP zero frequency, or approximately 1.77 kHz using 方程式41.

f_RHPz

f_BW

(41)

The gain of the open-loop power stage at f_BWcan be calculated using 方程式 40 or can be observed on the

Bode plot (图9-4) and is equal to –19.55 dB and the phase at f_BWis equal to –58°.

The secondary side portion of the compensation loop begins with establishing the regulated steady state output

voltage. To set the regulated output voltage, a TL431 adjustable precision shunt regulator is ideally suited for use

on the secondary side of isolated converters due to its accurate voltage reference and internal op-amp. The

resistors used in the divider from the output terminals of the converter to the TL431 REF pin are selected based

upon the desired power consumption. Because the REF input current for the TL431 is only 2 µA, selecting the

resistors for a divider current (I_{FB_REF}) of 1 mA results in minimal error. The top divider resistor (R_FBU) is

calculated:

V_OUTF REF_TL431

R_FBU

I_{FB_REF}

(42)

The TL431 reference voltage (REF_TL431) has a typical value of 2.495 V. A 9.53-kΩ resistor is chosen for R_FBU

To set the output voltage to 12 V, 2.49 kΩis used for R_FBB

REF_TL431

R_FBB

× R_FBU

V_OUTF REF_TL431

(43)

For good phase margin, a compensator zero (f_COMPz) is required and should be placed at 1/10th the desired

bandwidth:

f_BW

f_COMPz

(44)

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UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

X_COMPz= 2 × N × f_COMPz

(45)

With this converter, f_COMPzshould be set at approximately 177 Hz. A series resistor (R_COMPz) and capacitor

(C_COMPz) placed across the TL431 cathode to REF sets the compensator zero location. Setting C_COMPzto

0.01 µF, R_COMPzis calculated:

R_COMPz

X_COMPz× C_COMPz

(46)

Using a standard value of 88.7 kΩfor R_Zand a 0.01 µF for C_Zresults in a zero placed at 179 Hz.

In 图 9-3, R_TLbiasprovides cathode current to the TL431 from the regulated voltage provided from the Zener

diode (D_REG). For robust performance, 10 mA is provided to bias the TL431 by way of the 10-V Zener and a 1-

kΩresistor is used for R_TLbias

The gain of the TL431 portion of the compensation loop is calculated with 方程式47.

: ;

G_TL431s = lR_COMPz

p ×

s(f) × C_ZCOMPz

R_FBU

(47)

A compensation pole is required at the frequency of right half plane zero or the ESR zero, whichever is lowest.

Based previous the analysis, the right half plane zero (f_RHPz) is located at 7.07 kHz and the ESR zero (f_ESRz) is

at 1.68 kHz; therefore, for this design, the compensation pole must be put at 1.68 kHz. The opto-coupler

contains a parasitic pole that is difficult to characterize over frequency so the opto-coupler is set up with a pull-

down resistor (R_OPTO) equal to 1 kΩ, which moves the parasitic opto-coupler pole further out and beyond the

range of interest for this design.

The required compensation pole can be added to the primary side error amplifier using R_COMPpand C_COMPp

Choosing R_COMPpas 10 kΩ, the required value of C_COMPpis determined using 方程式48.

C_COMPp

= 9.46 nF

2 × N × f_ESRz× R_COMPp

(48)

A 10-nF capacitor is used for C_COMPpsetting the compensation pole at 1.59 kHz.

Adding a DC gain to the primary-side error amplifier may be required to obtain the required bandwidth and helps

to adjust the loop gain as needed. Using 4.99 kΩ for R_FBGsets the DC gain on the error amplifier to 2. At this

point the gain transfer function of the error amplifier stage (G_EA(s)) of the compensation loop can be

characterized using 方程式49.

R_COMPp

: ;

G_EAs = l

p × F

1 + s f × C_COMPp× R_COMPp

: ;

R_FBG

(49)

Using an opto-coupler whose current transfer ratio (CTR) is typically at 100% in the frequency range of interest

so that CTR = 1, the transfer function of the opto-coupler stage (G_OPTO(s)) is found using 方程式50.

CTR × R_OPTO

G_OPTO(s) =

R_LED

(50)

The bias resistor (R_LED) to the internal diode of the opto-coupler and the pull-down resistor on the opto emitter

(R_OPTO) sets the gain across the isolation boundary. R_OPTOhas already been set to 1 kΩ but the value of R_LED

has not yet been determined.

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UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

The total closed loop gain (G_TOTAL(s)) is the combination of the open-loop power stage (H_o(s)), the opto gain

(G_OPTO(s)), the error amplifier gain (G_EA(s)), and the gain of the TL431 stage (G_TL431(s)), as shown in 方程式51.

: ; : ;ꢀ

ꢀ

: ;ꢀ

ꢀ

: ;ꢀ

ꢀ

: ;ꢀ

ꢀ

G_TOTALs = H_OPENs × G_OPTOs × G_EAs × G_TL431s

(51)

The required value for R_LEDcan be selected to achieve the desired crossover frequency (f_BW). By setting the

total loop gain equal to 1 at the desired crossover frequency and rearranging 方程式 51, the optimal value for

R_LEDcan be determined, as shown in 方程式52.

ꢀ

: ;ꢀ : ;ꢀ

ꢀ

: ;ꢀ

ꢀ

R_LEDQ H_OPENs × CTR × C_OPTO× G_EAs × G_TL431s

(52)

A 1.3-kΩresistor suits the requirement for R_LED

Based on the compensation loop structure, the entire compensation loop transfer function is written as 方程式

53.

R_COMPp

CTR × R_OPTO

: ;

G_CLOSEDs = H_OPENs × l

p × l

p × F

R_LED

R_FBG

1 + ks × C_COMPp× R_COMPp

R_COMPz+ @

s × C_COMPz

× n

R_FBU

(53)

The final closed-loop bode plots are show in 图9-6 and 图9-7. The converter achieves a crossover frequency of

approximately 1.8 kHz and has a phase margin of approximately 67°.

TI recommends checking the loop stability across all the corner cases including component tolerances to ensure

system stability.

-45

-90

-135

-180

-20

-40

100 1000

frequency (Hz)

10000

100000

100 1000

frequency (Hz)

10000

100000

D0014

D003

图9-7. Converter Closed-Loop Bode Plot –Phase

图9-6. Converter Closed-Loop Bode Plot –Gain

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UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

9.2.3 Application Curves

图9-8. Primary Side MOSFET Drain to Source

图9-9. Primary Side MOSFET Drain to Source

Voltage at 120-V AC Input (100 V/div)

Voltage at 240-V AC Input (100 V/div)

CH1: Output Voltage AC Coupled, 200 mV/div

CH4: Output Current, 1 A/div

图9-11. Output Voltage Ripple at Full Load (100

mV/div)

图9-10. Output Voltage During 0.9-A to 2.7-A Load

Transient

图9-12. Output Voltage Behavior at Full Load Start-up (5 V/div)

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UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

9.3 Power Supply Recommendations

The absolute maximum supply voltage is 30 V for UCC28C52 , including any transients that may be present. If

this voltage is exceeded, device damage is likely.

Because no clamp is included in the device, the supply pin must be protected from external sources which could

exceed the 30-V level.

To prevent false triggering due to leading edge noises, an RC current sense filter may be required on CS. Keep

the time constant of the RC filter well below the minimum on-time pulse width.

To prevent noise problems with high-speed switching transients, bypass VREF to ground with a ceramic

capacitor close to the IC package. A minimum of 0.1-µF ceramic capacitor is required. Additional VREF

bypassing is required for external loads on the reference. An electrolytic capacitor may also be used in addition

to the ceramic capacitor.

9.4 Layout

9.4.1 Layout Guidelines

9.4.1.1 Precautions

Careful layout of the printed board is a necessity for high-frequency power supplies. As the device-switching

speeds and operating frequencies increase, the layout of the converter becomes increasingly important.

This 8-pin device has only a single ground for the logic and power connections. This forces the gate-drive

current pulses to flow through the same ground that the control circuit uses for reference. Thus, the interconnect

inductance must be minimized as much as possible. One implication is to place the device (gate driver) circuitry

close to the MOSFET it is driving. This can conflict with the need for the error amplifier and the feedback path to

be away from the noise generating components.

The single most critical item in a PWM controlled printed-circuit board layout is the placement of the timing

capacitor. While both the supply and reference bypass capacitor locations are important, the timing capacitor

placement is far more critical. Any noise spikes on the C_CTwaveform due to lengthy printed circuit trace

inductance or pick-up noise from being in proximity to high power switching noise causes a variety of operational

problems. Dilemmas vary from incorrect operating frequency caused by pre-triggering the oscillator due to noise

spikes to frequency jumping with varying duty cycles, also caused by noise spikes. The placement of the timing

capacitor must be treated as the most important layout consideration. Keep PC traces as short as possible to

minimize added series inductance.

9.4.1.2 Feedback Traces

Try to run the feedback trace as far from the inductor and noisy power traces as possible. You would also like the

feedback trace to be as direct as possible and somewhat thick. These two sometimes involve a trade-off, but

keeping it away from EMI and other noise sources is the more critical of the two. If possible, run the feedback

trace on the side of the PCB opposite of the inductor with a ground plane separating the two.

9.4.1.3 Bypass Capacitors

When using a low value ceramic bypass capacitor, it must be placed as close to the VDD pin of the device as

possible. This eliminates as much trace inductance effects as possible and give the internal device rail a cleaner

voltage supply. Using surface mount capacitors also reduces lead length and lessens the chance of noise

coupling into the effective antenna created by through-hole components.

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UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

9.4.1.4 Compensation Components

For best stability, external compensation components must be placed close to the IC. Keep FB lead length as

short as possible and FB stray capacitance as small as possible. TI recommends surface mount components

here as well for the same reasons discussed for the filter capacitors. These must not be placed very close to

traces with high switching noise.

9.4.1.5 Traces and Ground Planes

Make all of the power (high current) traces as short, direct, and thick as possible. It is good practice on a

standard PCB board to make the traces an absolute minimum of 15 mils (0.381 mm) per ampere. The inductor,

output capacitors, and output diode must be as close to each other possible. This helps reduce the EMI radiated

by the power traces due to the high switching currents through them. This also reduces lead inductance and

resistance as well, which in turn reduces noise spikes, ringing, and resistive losses that produce voltage errors.

The grounds of the IC, input capacitors, output capacitors, and output diode, if applicable, must be connected

close together directly to a ground plane. It would also be a good idea to have a ground plane on both sides of

the PCB. This reduces noise as well by reducing ground loop errors as well as by absorbing more of the EMI

radiated by the inductor. For multi-layer boards with more than two layers, a ground plane can be used to

separate the power plane, where the power traces and components are, and the signal plane, where the

feedback and compensation and components are, for improved performance. On multi-layer boards the use of

vias is required to connect traces and different planes. It is good practice to use one standard via per 200 mA of

current if the trace conducts a significant amount of current from one plane to the other.

Arrange the components so that the switching current loops curl in the same direction. Due to the way switching

regulators operate, there are two power states. One state when the switch is ON and one when the switch is

OFF. During each state there is a current loop made by the power components that are currently conducting.

Place the power components so that during each of the two states the current loop is conducting in the same

direction. This prevents magnetic field reversal caused by the traces between the two half-cycles and reduces

radiated EMI.

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UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

9.4.2 Layout Example

MOSFET Heatsink

TO-220FP Bo om View

Track To

<= Bulk Cap

Track To

Transformer =>

Track To

<= Bulk Cap +

22AWG

Jumper

Wire

GND

OUT

VDD

RT/CT

C_VDD

VREF

COMP

Aux Cap

22AWG Jumper Wires

PCB Bo om-side View

图9-13. UCCx8C4x Layout Example

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UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

10 Device and Documentation Support

10.1 Device Support

10.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

10.2 Documentation Support

10.2.1 Related Documentation

For related documentation see the following:

UC384x Provides Low-Cost Current-Mode Control (SLUA143)

10.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

10.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

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UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L,

UCC28C57H, UCC28C57L, UCC28C58, UCC28C59, UCC38C50, UCC38C51, UCC38C52, UCC38C53,

UCC38C54, UCC38C55

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ZHCSPH5C –JUNE 2022 –REVISED MARCH 2023

10.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

10.6 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

10.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Product Folder Links: UCC28C50 UCC28C51 UCC28C52 UCC28C53 UCC28C54 UCC28C55 UCC28C56H

UCC28C56L UCC28C57H UCC28C57L UCC28C58 UCC28C59 UCC38C50 UCC38C51 UCC38C52

UCC38C53 UCC38C54 UCC38C55

English Data Sheet: SLUSER8

PACKAGE OPTION ADDENDUM

www.ti.com

26-Mar-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

UCC28C50DGKR

UCC28C50DR

UCC28C51DGKR

UCC28C51DR

UCC28C52DGKR

UCC28C52DR

UCC28C53DGKR

UCC28C53DR

UCC28C54DGKR

UCC28C54DR

UCC28C55DGKR

UCC28C55DR

UCC28C56HDR

UCC28C56LDR

UCC28C57HDR

UCC28C57LDR

UCC28C58DR

UCC28C59DR

UCC38C50DR

UCC38C51DR

ACTIVE

VSSOP

SOIC

DGK

2500 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

-40 to 125

0 to 85

2C50

Samples

NIPDAU

28C50

2C51

VSSOP

SOIC

DGK

28C51

2C52

VSSOP

SOIC

DGK

28C52

2C53

VSSOP

SOIC

DGK

28C53

2C54

VSSOP

SOIC

DGK

28C54

2C55

VSSOP

SOIC

DGK

28C55

28C56H

28C56L

28C57H

28C57L

28C58

28C59

38C50

38C51

SOIC

0 to 85

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

26-Mar-2023

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

UCC38C52DR

UCC38C53DGKR

UCC38C53DR

UCC38C54DR

UCC38C55DR

ACTIVE

SOIC

VSSOP

SOIC

DGK

2500 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

Level-2-260C-1 YEAR

Level-1-260C-UNLIM

0 to 85

38C52

Samples

NIPDAU

3C53

38C53

38C54

38C55

SOIC

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

26-Mar-2023

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF UCC28C50, UCC28C51, UCC28C52, UCC28C53, UCC28C54, UCC28C55, UCC28C56H, UCC28C56L, UCC28C57H, UCC28C57L,

UCC28C58, UCC28C59 :

Automotive : UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1, UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-

Q1, UCC28C58-Q1, UCC28C59-Q1

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

7-Jul-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

UCC28C50DGKR

UCC28C50DR

VSSOP

SOIC

DGK

2500

330.0

12.4

5.3

6.4

5.3

6.4

5.3

6.4

5.3

6.4

5.3

6.4

5.3

6.4

3.4

5.2

3.4

5.2

3.4

5.2

3.4

5.2

3.4

5.2

3.4

5.2

1.4

2.1

1.4

2.1

1.4

2.1

1.4

2.1

1.4

2.1

1.4

2.1

8.0

12.0

UCC28C51DGKR

UCC28C51DR

VSSOP

SOIC

DGK

UCC28C52DGKR

UCC28C52DR

VSSOP

SOIC

DGK

UCC28C53DGKR

UCC28C53DR

VSSOP

SOIC

DGK

UCC28C54DGKR

UCC28C54DR

VSSOP

SOIC

DGK

UCC28C55DGKR

UCC28C55DR

VSSOP

SOIC

DGK

UCC28C56HDR

UCC28C56LDR

UCC28C57HDR

UCC28C57LDR

SOIC

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

7-Jul-2023

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

UCC28C58DR

UCC28C59DR

UCC38C50DR

UCC38C51DR

UCC38C52DR

UCC38C53DGKR

UCC38C53DR

UCC38C54DR

UCC38C55DR

SOIC

VSSOP

SOIC

2500

330.0

12.4

6.4

5.3

6.4

5.2

3.4

5.2

2.1

1.4

2.1

8.0

12.0

DGK

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

7-Jul-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

UCC28C50DGKR

UCC28C50DR

UCC28C51DGKR

UCC28C51DR

UCC28C52DGKR

UCC28C52DR

UCC28C53DGKR

UCC28C53DR

UCC28C54DGKR

UCC28C54DR

UCC28C55DGKR

UCC28C55DR

UCC28C56HDR

UCC28C56LDR

UCC28C57HDR

UCC28C57LDR

UCC28C58DR

UCC28C59DR

VSSOP

SOIC

DGK

2500

367.0

35.0

VSSOP

SOIC

DGK

VSSOP

SOIC

DGK

VSSOP

SOIC

DGK

VSSOP

SOIC

DGK

VSSOP

SOIC

DGK

SOIC

Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

7-Jul-2023

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

UCC38C50DR

UCC38C51DR

UCC38C52DR

UCC38C53DGKR

UCC38C53DR

UCC38C54DR

UCC38C55DR

SOIC

VSSOP

SOIC

2500

367.0

35.0

DGK

Pack Materials-Page 4

PACKAGE OUTLINE

D0008A

SOIC - 1.75 mm max height

SCALE 2.800

SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE

.228-.244 TYP

[5.80-6.19]

.004 [0.1] C

PIN 1 ID AREA

6X .050

[1.27]

.189-.197

[4.81-5.00]

NOTE 3

.150

[3.81]

4X (0 -15 )

8X .012-.020

[0.31-0.51]

.150-.157

[3.81-3.98]

NOTE 4

.069 MAX

[1.75]

.010 [0.25]

C A B

.005-.010 TYP

[0.13-0.25]

4X (0 -15 )

SEE DETAIL A

.010

[0.25]

.004-.010

[0.11-0.25]

0 - 8

.016-.050

[0.41-1.27]

DETAIL A

TYPICAL

(.041)

[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

SEE

DETAILS

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

6X (.050 )

[1.27]

(.213)

[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED

METAL

EXPOSED

METAL

.0028 MAX

[0.07]

.0028 MIN

[0.07]

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

6X (.050 )

[1.27]

(.213)

[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

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UCC28C57HDR [TI]

相关型号：

UCC28C57HQDRQ1

UCC28C57L

UCC28C57L-Q1

UCC28C57LDR

UCC28C57LQDRQ1

UCC28C58

UCC28C58DR

UCC28C59

UCC28C59-Q1

UCC28C59DR

UCC28C59QDRQ1

UCC29001