UCC29002DR/1 [TI]
温度范围为 -40°C 至 105°C 的高级 8 引脚负载共享控制器 | D | 8 | -40 to 105;
| 型号： | UCC29002DR/1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 温度范围为 -40°C 至 105°C 的高级 8 引脚负载共享控制器 | D | 8 | -40 to 105 控制器 信息通信管理 光电二极管 电源管理电路 电源电路 |
| 文件： | 总19页 (文件大小：269K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLUS495C − SEPTEMBER 2001 − REVISED JULY 2003
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FEATURES
DESCRIPTION
D
D
D
D
D
D
D
D
High Accuracy, Better Than 1% CurrentShare
Error at Full Load
The UCC39002 is an advanced, high performance and
low cost loadshare controller that provides all
necessary functions to parallel multiple independent
power supplies or dc-to-dc modules. Targeted for high
reliability applications in server, workstation, telecom
and other distributed power systems, the controller is
suitable for N+1 redundant systems or high current
applications where off-the-shelf power supplies need to
be paralleled.
High-Side or Low-Side (GND Reference)
Current-Sense Capability
Ultra-Low Offset Current Sense Amplifier
Single Wire Load Share Bus
Full Scale Adjustability
Intel SSI LoadShare Specification Compliant
Disconnect from Load Share Bus at Stand-By
The BiCMOS UCC39002 is based on the automatic
master/slave architecture of the UC3902 and UC3907
load share controllers. It provides better than 1%
current share error between modules at full load by
Load Share Bus Protection Against Shorts to
GND or to the Supply Rail
D
8-Pin MSOP Package Minimizes Space
Lead-Free Assembly
using
a
very low offset post-package-trimmed
D
current-sense amplifier and a high-gain negative
feedback loop. And with the amplifier’s common mode
range of 0-V to the supply rail, the current sense resistor
can be placed in either the GND return path or in the
positive output rail of the power supply.
SYSTEM CONFIGURATIONS
D
D
D
Modules With Remote Sense Capability
Modules With Adjust Input
Modules With Both Remote Sense and Adjust
Input
D
In Conjunction With the Internal Feedback E/A
of OEM Power Supply Units
TYPICAL LOW-SIDE CURRENT SENSING APPLICATION
V+
R
ADJ
S+
UCC39002
LOAD
1
2
3
4
CS−
CSO
8
7
6
5
POWER
SUPPLY
WITH
REMOTE
SENSE
CS+
VDD
GND
LS
EAO
ADJ
S−
V−
R
SENSE
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Copyright 2002, Texas Instruments Incorporated
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ꢜ ꢠ ꢝ ꢜꢕ ꢖꢪ ꢘꢗ ꢛ ꢣꢣ ꢡꢛ ꢙ ꢛ ꢚ ꢠ ꢜ ꢠ ꢙ ꢝ ꢥ
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SLUS495C − SEPTEMBER 2001 − REVISED JULY 2003
DESCRIPTION (continued)
During transient conditions while adding or removing power supplies, the UCC39002 protects the system by
keeping the load share bus disconnected from the remaining supplies. By disabling the adjust function in case
a short of the load share bus occurs to either GND or the supply rail, it also provides protection for the system
against erroneous output voltage adjustment.
The UCC39002 also meets Intel’s SSI (Server System Infrastructure) loadshare specifications of a single-line
load share bus and scalable load share voltage for any level of output currents.
The UCC39002 family is offered in 8-pin MSOP (DGK), SOIC (D), and PDIP (P) packages.
}w
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, current limited (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 15 V
DD
Supply voltage, voltage source (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 13.5 V
DD
Input voltage, current sense amplifier (V
, V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V
+ 0.3 V
CS+ CS−
DD
Current sense amplifier output voltage (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V
Load share bus voltage (V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V
CSO
DD
DD
LS
ZENER
ADJ
ADJ
Supply current (I
Adjust pin input voltage (V
Adjust pin sink current (I
+ I
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
DD
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
+1 V < V
≤ V
EAO
ADJ DD
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 mA
Operating junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead Temperature, T (Soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
J
Storage temperature range T
stg
sol
‡
§
All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal.
PDIP (P) PACKAGE
(TOP VIEW)
SOIC (D) OR MSOP (DGK) PACKAGE
(TOP VIEW)
CS−
CS+
VDD
GND
CSO
LS
1
2
3
4
8
7
6
5
CS−
CS+
VDD
GND
CSO
LS
8
7
6
5
1
2
3
4
EAO
ADJ
EAO
ADJ
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
= T
J
SOIC−8
(D)
MSOP−8
(DGK)
PDIP−8
(P)
†
†
−40°C to 105°C
0°C to 70°C
UCC29002D
UCC39002D
UCC29002DGK
UCC39002DGK
UCC29002P
UCC39002P
†
The D and DGK packages are available taped and reeled. Add R suffix to device type (e.g.
UCC39002DR) to order quantities of 2,500 devices per reel.
2
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electrical characteristics V
= 12 V, 0°C < T < 70°C for the UCC39002, −40°C < T < 105°C for the
A A
DD
UCC29002, T = T (unless otherwise noted)
A
J
general
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3.5
UNITS
mA
Supply current
LS with no load,
IDD = 6 mA
ADJ = 5 V
2.5
VDD clamp voltage
13.50
14.25
15.00
V
undervoltage lockout
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
4.575
0.550
UNITS
(1)
Start-up voltage
4.175
0.200
4.375
0.375
V
Hysteresis
current sense amplifier
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
µV
T
V
= 25_C
V
IC
= 0.5 V or 11.5 V,
A
CSO
−100
100
= 5 V
V
IO
Input offset voltage
Over-temperature variation
±10
90
µV/_C
A
V
Gain
75
75
dB
CMRR
Common mode rejection ratio
Input bias current (CS+, CS−)
90
I
−0.6
0.6
µA
BIAS
0.1 V ≤ ([CS+] − [CS−]) ≤ 0.4 V,
V
V
High-level output voltage (CSO)
Low-level output voltage (CSO)
10.7
0.00
11.0
0.10
11.8
OH
I
= 0 mA
OUT_CSO
−0.4 V ≤ ([CS+] − [CS−]) ≤ 0.1 V,
= 0 mA
V
0.15
OL
I
OUT_CSO
I
I
High-level output current (CSO)
Low-level output current (CSO)
V
= 10 V
−1
−1.5
1.5
2
OH
CSO
CSO
mA
V
= 1 V
1
OL
(2)
Gain bandwidth product
GBW
MHz
load share driver (LS)
PARAMETER
TEST CONDITIONS
MIN
0
TYP
MAX
10
UNITS
V
V
Input voltage range
RANGE
V
V
V
= 1 V
0.995
9.995
0.00
1
1.005
CSO
CSO
CSO
Output voltage
OUT
= 10 V
= 0 V,
10 10.005
V
V
V
Low-level output voltage
High-level output voltage
Output current
I
= 0 mA
0.10
−1.7
0.15
OL
OUT_LS
(2)
V
DD
OH
I
0.5 V ≤ V ≤ 10 V
LS
−1
−10
0.3
−1.5
−20
0.5
OUT
SC
mA
V
I
Short circuit current
V
LS
= 0 V,
V
= 10 V
CSO
V
Driver shutdown threshold
V
CS−
− V
CS+
0.7
SHTDN
load share bus protection
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
V
= 2 V,
= 2 V,
V
V
= V ,
DD
CSO
EAO
LS
0
5
5
10
= 5 V
ADJ
V = 0 V,
LS
I
Adjust amplifier current
µA
ADJ
V
CSO
V
EAO
= 2 V,
= 2 V,
0
10
V
ADJ
= 5 V
(1) Enables the load share bus at start-up.
(2) Ensured by design. Not production tested.
3
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electrical characteristics V
= 12 V, 0°C < T < 70°C for the UCC39002, −40°C < T < 105°C for the
A A
DD
UCC29002, T = T (unless otherwise noted) (continued)
A
J
error amplifier
PARAMETER
TEST CONDITIONS
MIN
3.50
TYP
MAX
UNITS
V
V
OH
High-level output voltage
Transconductance
I
= 0 mA
OUT_EAO
3.65
14
3.80
g
M
I
= ± 50 µA
mS
EAO
− V = 0.4 V,R
CSO EAO
I
High-level output current
V
= 2.2 kΩ
0.70
0.85
1.00
mA
OH
LS
ADJ buffer
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
mV
(2)
V
Input offset voltage
V
= 1.5 V,
= 5.0 V,
ADJ
V
V
= 0 V,
= 0 V
−60
5
IO
ADJ
EAO
I
Sink current
V
0
3.60
3.45
3.35
10
4.30
4.45
4.55
µA
SINK
EAO
T
A
= 25_C
3.95
3.95
3.95
V
ADJ
= 5.0 V,
LS = floating
V
EAO
= 2.0 V
0_C ≤ T ≤ 70_C
I
Sink current
mA
A
SINK
−40_C ≤ T ≤ 105_C
A
(1) Enables the load share bus at start-up.
(2) Ensured by design. Not production tested.
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Adjust amplifier output. This is the buffered output of the error amplifier block to adjust output
voltage of the power supply being controlled. This pin must always be connected to a voltage
ADJ
5
O
equal to or greater than V
+ 1 V.
EAO
CS−
CS+
CSO
EAO
GND
LS
1
2
8
6
4
7
3
I
I
Current sense amplifier inverting input.
Current sense amplifier non-inverting input.
O
O
−
Current sense amplifier output.
Output for load share error amplifier. (Transconductance error amplifier.)
Ground. Reference ground and power ground for all device functions.
Load share bus. Output of the load share bus driver amplifier.
Power supply providing bias to the device.
I/O
I
VDD
4
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SLUS495C − SEPTEMBER 2001 − REVISED JULY 2003
typical high-side current sensing application
R
SENSE
V+
S+
R
ADJ
UCC39002
1
2
3
4
CS−
CSO
8
7
6
5
POWER SUPPLY
WITH
REMOTE SENSE
CS+
VDD
GND
LS
EAO
ADJ
S−
V−
R
SENSE
V+
S+
R
ADJ
UCC39002
1
2
3
4
CS−
CS+
VDD
GND
CSO
8
7
6
5
POWER SUPPLY
WITH
REMOTE SENSE
LS
LOAD
EAO
ADJ
S−
V−
R
SENSE
V+
S+
R
ADJ
UCC39002
1
2
3
4
CS−
CS+
VDD
GND
CSO
8
7
6
5
POWER SUPPLY
WITH
REMOTE SENSE
LS
EAO
ADJ
S−
V−
UDG−01078
5
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SLUS495C − SEPTEMBER 2001 − REVISED JULY 2003
functional block diagram
8
CSO
Current Sense
Amp
Disconnect Switch
Load Share
Bus Driver
CS−
1
2
+
+
CS+
Enable
and
Bias OK
7
6
5
LS
V
BIAS
Load Share Bus
100 kΩ
Receiver
+
VDD
GND
3
4
Error Amp
+
g
EAO
ADJ
13.5 V
to
15 V
M
3 V
3 V
Adjust Amp
Start Up
and
Adjust
Logic
+
Fault
Protection
500 Ω
UDG−02086
FUNCTIONAL DESCRIPTION
differential current sense amplifier (CS+, CS−, CSO)
The UCC39002 features a high-gain and high-precision amplifier to measure the voltage across a low-value
current sense resistor. Since the amplifier is fully uncommitted, the current sense gain is user programmable.
The extremely low input offset voltage of the UCC39002 current sense amplifier makes it suitable to measure
current information across a low value sense resistor. Furthermore, the input common mode range includes
ground and the positive supply rail of the UCC39002 (V ). Accordingly, the current sense resistor can be
DD
placed in the ground return path or in the positive output rail of the power supply V as long as V ≤ V .
O
O
DD
load share bus driver amplifier (CSO)
This is a unity-gain buffer amplifier to provide separation between the load share bus voltage and the output
of the current sense amplifier. The circuit implements an ideal diode with virtually 0 V forward voltage drop by
placing the diode inside the feedback loop of the amplifier. The diode function is used to automatically establish
the role of the master module in the system. The UCC39002 which is assigned to be the master uses the load
share bus driver amplifier to copy its output current information on to the load share bus.
All slave units, with lower output current levels by definition, have this “ideal diode” reversed biased
(V
< V ). Consequently, the V
and V signals will be separated. That allows the error amplifier of the
CSO
LS
CSO LS
UCC39002 to compare its respective module’s output current to the master module’s output current and make
the necessary corrections to achieve a balanced current distribution.
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SLUS495C − SEPTEMBER 2001 − REVISED JULY 2003
FUNCTIONAL DESCRIPTION
Since the bus is always driven by a single load share bus driver amplifier, the number of modules (n) are limited
by the output current capability of the amplifier according to:
100 kW I
OUT,MIN
n +
V
LS,FULL_SCALE
(1)
where 100 kΩ is the input impedance of the LS pin as shown in the block diagram, I
is given in the data
OUT,MIN
sheet and V
is the maximum voltage on the load share bus at full load.
LS,FULL_SCALE
Note that the number of parallel units can be increased by reducing the full scale bus voltage, i.e. by reducing
the current sense gain.
load share bus receiver amplifier (LS)
The load share bus receiver amplifier is a unity gain buffer monitoring the load share bus voltage. Its primary
purpose is to ensure that the load share bus is not loaded by the internal impedances of the UCC39002.
error amplifier (EAO)
As pictured in the block diagram, the UCC39002 employs a transconductance also called g type error
M
amplifier. The g amplifier was chosen because it requires only one pin, the output to be accessible for
M
compensation.
The purpose of the error amplifier is to compare the average, per module current level to the output current of
the respective module controlled by the UCC39002. It is accommodated by connecting the buffered V voltage
LS
to its non−inverting input and the V
signal to its inverting input. If the average per module current,
CSO
represented by the load share bus is higher than the module’s own output current, an error signal will be
developed across the compensation components connected between the EAO pin and ground. The error signal
is than used by the adjust amplifier to make the necessary output voltage adjustments to ensure equal output
currents among the parallel operated power supplies.
In case the UCC39002 assumes the role of the master load share controller in the system or it is used in
conjunction with a stand alone power module, the measured current signal on V
is approximately equal to
CSO
the V voltage. To avoid erroneous output voltage adjustment, the input of the error amplifier incorporates a
LS
typically 25 mV offset to ensure that the inverting input of the error amplifier is biased higher than the
non−inverting input. Consequently, when the two signals are equal, there will be no adjustment made and the
initial output voltage set point is maintained.
adjust amplifier output (ADJ)
A current proportional to the error voltage V
on pin 6 is sunk by the ADJ pin. This current flows through the
EAO
adjust resistor R
and changes the output voltage of the module controlled by the UCC39002. The amplitude
ADJ
of the current is set by the 500-Ω internal resistor between ground and the emitter of the amplifier’s open
collector output transistor according to Figure 1. The adjust current value is given as:
V
EAO
I
+
ADJ
500 W
(2)
At the master module V
voltage of the master module remains at its initial output voltage set point at all times.
is 0 V, thus the adjust current must be zero as well. This ensures that the output
EAO
Furthermore, at insufficient bias level, during a fault or when the UCC39002 is disabled, the non-inverting input
of the adjust amplifier is pulled to ground to prevent erroneous adjustment of the module’s output voltage by
the load share controller.
7
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SLUS495C − SEPTEMBER 2001 − REVISED JULY 2003
FUNCTIONAL DESCRIPTION
enable function (CS+, CS−)
The two inputs of the current sense amplifier are also used for implementing an ENABLE function. During
normal operation CS− = CS+ and the internal offset added between the CS− voltage and the inverting input of
the enable comparator ensures that the UCC39002 is always enabled. By forcing the CS− pin approximately
0.5-V above the CS+ pin, the UCC39002 can be forced into a disable mode. While disabled, the UCC39002
disconnects itself from the load share bus and its adjust current is zero.
CS+
2
+
ENABLE
0.5 V
CS− 1
UDG−02087
Figure 1. Enable Comparator
fault protection
Accidentally, the load share bus might be shorted to ground or to the positive bias voltage of the UCC39002.
These events might result in erroneous output voltage adjustment. For that reason, the load share bus is
continuously monitored by a window comparator as shown in Figure 2.
+
V
DD
− 0.7 V
LS
7
8
FAULT
+
R
CSO
2R
UDG−02088
Figure 2. Fault Protection Comparators
The FAULT signal is handled by the start up and adjust logic which pulls the non-inverting input of the adjust
amplifier low when the FAULT signal is asserted.
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SLUS495C − SEPTEMBER 2001 − REVISED JULY 2003
FUNCTIONAL DESCRIPTION
start up and adjust logic
The start up and adjust logic responds to unusual operating conditions during start up, fault and disable. Under
these circumstances the information obtainable by the error amplifier of the UCC39002 is not sufficient to make
the right output voltage adjustment, therefore the adjust amplifier is forced to certain known states. Similarly,
the driver amplifier of UCC39002 is disabled during these conditions.
During start up, the load share driver amplifier is disabled by the disconnect switch and the adjust amplifier is
forced to sink the maximum current through the adjust resistor. This operating mode ensures that the module
controlled by the UCC39002 will be able to engage in sharing the load current since its output will be adjusted
to a sufficiently high voltage. Both the load share driver and the adjust amplifiers revert to normal operation as
soon as the measured current exceeds 80% of the average per module current level represented by the bus
voltage.
In case of a fault shorting the load share bus to ground or to the bias of the UCC39002 the load share bus driver
and the adjust amplifiers are disabled. The same action takes place when the UCC39002 is disabled using the
CS+ and CS− pins or when the bias voltage is below the minimum operating voltage.
bias and bias OK circuit (VDD)
The UCC39002 is built on a 15-V, high performance BiCMOS process. Accordingly the maximum voltage across
the V
and GND pins (pin 3 and 4 respectively) is limited to 15 V. The recommended maximum operating
DD
voltage is 13.5 V which corresponds to the tolerance of the on-board 14.2-V Zener clamp circuit. In case the
bias voltage could exceed the 13.5-V limit, the UCC39002 should be powered through a current limiting resistor.
The current into the V
pin must be limited to 10 mA as listed in the absolute maximum ratings table.
DD
V
VDD
3
4
BIAS
(Internal Bias)
14.2 V
4.375 V
+
Bias_OK
GND
UDG−02089
Figure 3. V
Clamp and Bias Monitor
DD
The UCC39002 does not have an undervoltage lockout circuit. The bias OK comparator works as an enable
function with a 4.375-V threshold. While V < 4.375 V the load share control functions are disabled. While this
DD
might be inconvenient for some low voltage applications it is necessary to ensure high accuracy. The load share
accuracy is dependent on working with relatively large signal amplitudes on the load share bus. If the internal
offsets, current sense error and ground potential difference between the UCC39002 controllers are comparable
in amplitude to the load share bus voltage, they can cause significant current distribution error in the system.
The maximum voltage on the load share bus is limited approximately 1.7-V below the bias voltage level (V
)
DD
which would result in an unacceptably low load share bus amplitude therefore poor accuracy at low V
levels.
DD
To circumvent this potential design problem, the UCC39002 won’t operate below the above mentioned 4.375-V
bias voltage threshold. If the system does not have a suitable bias voltage available to power the UCC39002,
it is recommended to use an inexpensive charge pump which can generate the bias voltage for all the
UCC39002s in the load share system.
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SLUS495C − SEPTEMBER 2001 − REVISED JULY 2003
FUNCTIONAL DESCRIPTION
The maximum V
of the UCC39002 is 15 V. For higher-voltage applications, use the application solution as
DD
recommended in Figure 4. A Zener clamp on the VDD pin is provided internally so the device can be powered
from higher voltage rails using a minimum number of external components.
LOAD CURRENT DIRECTION
R
SENSE
VOUT+
SNS+
R
ADJ
POWER SUPPLY
OUTPUT
LOAD
SNS−
VOUT−
R
BIAS
SYSTEM
GROUND
UCC39002
CS− CSO 8
1
2
3
LS BUS
TO OTHER
UCC39002
DEVICES
CS+
VDD
LS 7
UDG−01077
EAO 6
ADJ 5
C
C
R
BIAS
COMP
4
GND
COMP
Figure 4. High Voltage Application
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SLUS495C − SEPTEMBER 2001 − REVISED JULY 2003
DESIGN PROCEDURE
The following is a practical step-by-step design procedure on how to use the UCC39002 to parallel power
modules for load sharing.
paralleling the power modules
D
D
D
D
V
I
= nominal output voltage of the modules to be paralleled
= maximum output current of each module to be paralleled
OUT
OUT(max)
∆V
= maximum output voltage adjustment range of the power modules to be paralleled
ADJ
N = number of modules
NOTE: The power modules to be paralleled must be equipped with true remote sense or access
to the feedback divider of the module’s error amplifier.
A typical high side application for a single module is shown in Figure 5 and is repeated for each module to be
paralleled.
R
SENSE
0.005 Ω
V+
P1
R15
274 Ω
C13 1 nF
V−
TP11
TP12
R16 16.2 kΩ
R13
274 Ω
U1
UCC39002
1
2
CS− CSO
8
7
R18
1 kΩ
R
ADJUST
82 Ω
CS+
LS
V+
Load
C12
1 nF
TP13
R
EAO
475 Ω
V−
Q1
SB2
3
VDD EAO 6
GND ADJ 5
C11
0.47 µF
R19
47 kΩ
R14
16.2 kΩ
C
47 µF
EAO
S+
4
S1
S−
UDG−02078
Load Share Bus
Figure 5. Typical High-Side Application for Single Power Module
In Figure 5, P1 represents the output voltage terminals of the module, S1 represents the remote sense terminals
of the module, and a signal on the SB2 terminal will enable the disconnect feature of the device. The load share
bus is the common bus between all of the paralleled load share controllers. VDD must be decoupled with a good
quality ceramic capacitor returned directly to GND.
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SLUS495C − SEPTEMBER 2001 − REVISED JULY 2003
DESIGN PROCEDURE
measuring the modules’ loop
Using the configuration in Figure 6, measure the unity gain crossover frequency of the power modules to be
paralleled. A typical resultant bode plot is shown in Figure 7.
+
+
+
VOUT
DC−DC Module
Load
V
IN
50 Ω
+
SENSE
XFRMR
Source
Out
Channel
A
Channel
B
Network Analyzer
UDG−02079
Figure 6. Unity Gain Crossover Frequency Measurement Connection Diagram
40
30
20
10
0
−10
UNITY GAIN
CROSSOVER
−20
FREQUENCY
f
= 40 Hz
CO
−30
−40
1
10
100
1000
f − Frequency − Hz
Figure 7. Power Module Bode Plot
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SLUS495C − SEPTEMBER 2001 − REVISED JULY 2003
DESIGN PROCEDURE
the sense resistor
Selection of the sense resistor is limited by its voltage drop at maximum module output current. This voltage
drop should be much less than the voltage adjustment range of the module:
I
R
tt D V
OUT(max)
SENSE
ADJ(max)
(3)
Other limitations for the sense resistor are the desired minimum power dissipation and available component
ratings.
the CSA gain
The gain of the current sense amplifier is configured by the compensation components between Pin 1, CS−,
and Pin 8, CSO, of the load share device. The voltage at the CSO pin is limited by the saturation voltage of the
internal current sense amplifier and must be at least two volts less than VDD:
V
t VDD * 2 V
CSO(max)
(4)
The maximum current sense amplifier gain is equal to:
V
CSO
A
+ ǒR
Ǔ
CSA
I
SENSE
OUT(max)
(5)
Referring to Figure 5, the gain is equal to R16/R15 and a high-frequency pole, configured with C13, is used for
noise filtering. This impedance is mirrored at the CS+ pin of the differential amplifier as shown.
The current sense amplifier output voltage, V
, serves as the input to the unity gain LS bus driver. The module
CSO
with the highest output voltage forward biases the internal diode at the output of the LS bus driver and determine
the voltage on the load share bus, V . The other modules act as slaves and represent a load on the I of
LS
VDD
the module due to the internal 100-kΩ resistor at the LS pin. This increase in supply current for the master
module is equal to N(V /100 kΩ).
LS
ADJUST
determining R
The Sense+ terminal of the module is connected to the ADJ pin of the load-share controller. By placing a resistor
between this ADJ pin and the load, an artificial Sense+ voltage is created from the voltage drop across R
ADJUST
due to the current sunk by the internal NPN transistor. The voltage at the ADJ pin must be maintained at
approximately 1 V above the voltage at the EAO pin. This is necessary in order to keep the transistor at the
output of the internal adjust amplifier from saturating. To fulfill this requirement, R
the following equation:
is first calculated using
ADJUST
* ǒI
Ǔ
ƪ
ƫ
DV
R
500 W
ADJ(max)
OUT(max)
SENSE
R
w ƪV
ƫ
ADJUST
) ǒI
Ǔ* 1 V
* DV
R
OUT
ADJ(max)
OUT(max)
SENSE
(6)
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SLUS495C − SEPTEMBER 2001 − REVISED JULY 2003
DESIGN PROCEDURE
Also needed for consideration is the actual adjust pin current. The maximum sink current for the ADJ pin,
, is 6 mA as determined by the internal 500-Ω emitter resistor and 3-V clamp. The value of adjust resistor,
I
R
ADJmax
ADJUST
, is based upon the maximum adjustment range of the module, ∆V
. This adjust resistor is
ADJmax
determined using the following formula:
* ǒI
Ǔ
ƫ
ƪ
DV
R
ADJ(max)
OUT(max)
SENSE
R
w
ADJUST
I
ADJ(max)
(7)
By selecting a resistor that meets both of these minimum requirements, the ADJ pin will be at least 1 V greater
than the EAO voltage and the adjust pin sink current will not exceed its 6 mA maximum.
error amplifier compensation
The total load-share loop unity-gain crossover frequency, f , should be set at least one decade below the
CO
measured crossover frequency of the paralleled modules previously measured, f
(See Figure 7)
CO(module).
Compensation of the transconductance error amplifier is accomplished by placing the compensation resistor,
R
, and capacitor, C
, between EAO and GND. The values of these components is determined using
EAO
EAO
equations (8) and (13).
g
M
ǒ
Ǔ ǒA Ǔ ǒA
Ǔ
ǒf
Ǔ
ǒA
Ǔ
+ ǒ Ǔ A
C
EAO
CSA
V
ADJ
PWR CO
p f
CO
(8)
Where:
D
D
D
D
D
D
g
f
is the transconductance of the error amplifier, typically 14 mS,
is equal to the desired crossover frequency in Hz of the load share loop, typically f
equals R16/R15,
M
(module)/10,
CO
CO
A
CSA
A is the voltage gain, equal to R
/R
,
V
SENSE LOAD
A
is the gain associated with the adjust amplifier, equal to R
/500 Ω,
ADJ
ADJUST
A
(f ) is the measured gain of the power module at the desired load share crossover frequency,
converted from dB to V/V
PWR CO
R16
R15
A
+
CSA
(9)
R
SENSE
A +
V
R
LOAD
(10)
R
ADJUST
A
+
ADJ
500 W
(11)
(12)
ǒf Ǔ + from power moduleȀs Bode plot (Fig. 7)
A
PWR CO
Once the C
capacitor is determined, R
is selected to achieve the desired loop response:
EAO
EAO
1
R
+
EAO
ǒ
Ǔ ǒf
Ǔ
ƪ2p C
ƫ
EAO
CO
(13)
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SLUS495C − SEPTEMBER 2001 − REVISED JULY 2003
DESIGN PROCEDURE
references
For further details, refer to the following document:
D
Reference Design, 48-V , 12-V
Modules”, Texas Instruments Literature No. SLUA270
Loadshare System Using UCC39002 with Three DC/DC PH-100S4
IN
OUT
For a more complete description of general load sharing toics, refer to the following documents.
D
D
Application Note, The UC3902 Load Share Controller and Its Performance in Distributed Power Systems,
TI Literature No. SLUA128
Application Note, UC3907 Load Share IC Simplifies Parallel Power Supply Design, TI Literature No.
SLUA147
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SLUS495C − SEPTEMBER 2001 − REVISED JULY 2003
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
0.020 (0,51)
0.014 (0,35)
0.050 (1,27)
0.010 (0,25)
8
5
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
4
0.010 (0,25)
0°− 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
0.069 (1,75) MAX
0.004 (0,10)
0.004 (0,10)
PINS **
8
14
16
DIM
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/E 09/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
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SLUS495C − SEPTEMBER 2001 − REVISED JULY 2003
MECHANICAL DATA
DGK (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,38
0,25
M
0,65
8
0,25
5
0,15 NOM
3,05
2,95
4,98
4,78
Gage Plane
0,25
0°−ā6°
1
4
0,69
3,05
2,95
0,41
Seating Plane
0,10
0,15
0,05
1,07 MAX
4073329/B 04/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-187
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SLUS495C − SEPTEMBER 2001 − REVISED JULY 2003
MECHANICAL DATA
P (PDIP)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.430 (10,92)
MAX
0.010 (0,25)
M
0.015 (0,38)
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
18
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