UCC3585N_技术文档

UCC2585

UCC3585

PRELIMINARY

Low Voltage Synchronous Buck Controller

FEATURES

DESCRIPTION

• Resistor Programmable 1.25V to 4.5V The UCC2585/UCC3585 synchronous Buck controller provides flexible

V_OUT

high efficiency power conversion for output voltages as low as 1.25V with

guaranteed ±1% DC accuracy. Output currents are only limited by the

choice of external logic level MOSFETs. With an input voltage range of

2.5V to 6.0V it is the ideal choice for 3.3V only, battery input, or other low

voltage systems. Applications include local microprocessor core voltage

power supplies for desktop and Notebook computers, and high speed GTL

bus regulation. Its fixed frequency oscillator is capable of providing practical

PWM operation to 700kHz.

• 2.5V to 6V Input Supply Range

• 1% DC Accuracy

• High Efficiency Synchronous

Switching

• Drives P-channel (High Side) and

N-channel (Low Side) MOSFETs

With its low voltage capability and inherent “always on” operation, the

UCC2585/UCC3585 causes VOUT to track VIN once VIN has exceeded

the threshold voltage of the external P channel MOSFET. Tracking can be

tailored for any application with a single resistor or disabled by connecting

TRACK to VIN. For dual supply rail microprocessors this feature negates

the need for external diodes to insure supply voltage tracking between the

+3.3V and lower voltage microprocessor core supplies.

• Lossless Programmable Current Limit

• Logic Compatible Shutdown

• Programmable Frequency

• Start-up Voltage Tracking Protects

Dual Rail Microprocessors

(continued)

TYPICAL APPLICATION DIAGRAM

VIN

C8

0.47µF

R3

27.4k

R1

10k

+

15 VIN

CLSET

8

R5

3

C1

C2

Q1

IRF7404

150µF 150µF

1

2

4

ENB

PDRV 12

C7

147pF

R2

549k

L1 4.7µF

COMP

VFB

ISENSE 11

NDRV 14

VOUT

R6

3

Q2

IRF7401

+

C11

C9

C10

220µF

10 SD

TRACK

N/C

6

9

C4

3.2N

R10

36k

R12

32k

3

SS

C5

0.22µF

16 CT

PWRGND 13

C6

470pF

7

ISET

GND

5

R11

82k

R4

100k

RTN

UDG-98024

07/99

UCC2585

UCC3585

CONNECTION DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

Analog Pins

DIL-16, SOIC-16, SSOP-16 (TOP VIEW)

J, N, D, and M Packages

Minimum and Maximum Forced Voltage

(Reference to GND) . . . . . . . . . . . . . . . . . . . –0.3V to +6.3V

Digital Pins

Minimum and Maximum Forced Voltage

(Reference to GND) . . . . . . . . . . . . . . . . . . . . .–0.3V to 6.3V

Power Driver Output Pins

Maximum forced current . . . . . . . . . . . . . . . . . . . . . . . . . ±1.0A

Operating Junction Temperature. . . . . . . . . . –55°C to +125°C

Storage Temperature. . . . . . . . . . . . . . . . . . . –65°C to +150°C

ENB

COMP

SS

16 CT

1

2

3

4

5

6

7

8

15 VIN

14 NDRV

13 PWRGND

12 PDRV

11 ISENSE

10 SD

Note: Unless otherwise indicated, voltages are reference to

ground and currents are positive into, negative out of, the spec-

ified terminals. Pulsed is defined as a less than 10% duty cycle

with a maximum duration of 500ns.

VFB

GND

TRACK

ISET

APPLICATIONS

• Low Voltage Microprocessor Power such as PowerPC

603 and 604

CLSET

9

N/C

• High Power 5V or 3.3V to 1.25V–4.5V Regulators

• GTL Bus Termination

DESCRIPTION (cont.)

The UCC2585/UCC3585 drives a complementary pair of secutive faults, or latch-off after fault detection, allowing

power MOSFET transistors, P-channel on the high side, maximum application flexibility. The current limit thresh-

and N-channel on the low side to step down the input old is programmed with a single resistor selected to

voltage at up to 90% efficiency.

match system MOSFET characteristics.

A programmable two-level current limiting function is pro- The UCC2585/UCC3585 also includes undervoltage

vided by sensing the voltage drop across the high side P lockout, a logic controlled enable, and softstart functions.

channel MOSFET. This circuit can be configured to pro- The UCC2585/UCC3585 is offered in the 16 pin surface

vide pulse-by-pulse limiting, timed shutdown after 7 con- mount and through hole packages.

2

UCC2585

UCC3585

ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications hold for T_A= 0°C to 70°C for the

UCC3585, and T_A= –40°C to 85°C for the UCC2585. T_A= T_J. VIN = 3.3V, ENB, I_SENSE= V_IN, V_FB= 1.25V, COMP = 1.5V,

C_T= 330pF, R_ISET= 100k, RTRACK = 10k, RCLSET = 10k.

PARAMETER

Input Supply Section

TEST CONDITIONS

MIN

TYP

MAX UNITS

Supply Current – Total (Active)

Supply Current – Shutdown

VIN Turn On Threshold (UVLO)

VIN Turn On Hysteresis

Voltage Amplifier Section

Input Voltage (Internal Reference)

Open Loop Gain

2.3

10

3.5

25

mA

µA

V

ENABLE = 0V

2.35

450

2.60

550

mV

T_A= 0°C to 70°C, VIN = 3.0V to 3.6V, Note 1

VIN = 3.0V to 3.6V, IND/MIL Temp, Note 1

COMP = 0.5 to 2.5V

1.238 1.250 1.262

1.228 1.250 1.273

V

65

80

dB

V

Output Voltage High

I(COMP) = –50µA

3.00

3.25

0.10

Output Voltage Low

I(COMP) = 50µA

0.25

V

Output Source Current

Output Sink Current

–100 –175

µA

mA

0.4

1.0

Oscillator/PWM Section

Initial Accuracy

T_J= 25°C

405

390

1.8

450

2.1

0.4

495

510

2.4

kHz

V

Initial Accuracy

Over Temperature

CT Ramp Peak to Valley

CT Ramp Valley Voltage

PWM Maximum Duty Cycle

PWM Minimum Duty Cycle

PWM Delay to Outputs

Tracking Current

0.3

V

COMP = 3V, Measured on PDRV

COMP = 0.2V, Measured on PDRV

COMP = 2.5V

100

%

0

%

45

12

ns

µA

V

Measured on TRACK, V_TRACK= 1.6V

Measured on ENABLE (Note 3)

Measured on ENABLE

10

15

Enable High Threshold

Enable Low Threshold

Softstart Charge Current

Current Limit Section

Pulse to Pulse Threshold

CLSET Current

2.8

0.5

–14

V

SS = 0V

–10

–18

µA

Measured Between V_INand I_SENSE

100

11

8

125

14

150

16

mV

µA

V

SD Sink Current

SD = 2V

13

18

SD Source Current

SD = 2V

–100 –140

Restart Threshold

Measured on SDOWN

0.40

0.55

0.90

Output Driver Section (PDRV, NDRV)

Pull Up Resistance

–100mA (Source) T_A= 25°C

100mA (Sink) T_A= 25°C

Note 2

6

4

Ω

Pull Down Resistance

Deadtime Delay

150

200

250

ns

Note 1. Measured on COMP with the Error Amp in a Unity Gain (voltage follower) configuration.

Note 2. 50% point of PDRV Rise to NDRV Rise and 50% point of NDRV Fall to PDRV Fall.

Note 3. Enable High Threshold = V –0.5.

IN

3

UCC2585

UCC3585

BLOCK DIAGRAM

TRACK

6

ISET

7

CLSET

8

UVLO

2V

PRECISION

BIAS SET

CURENT

LIMIT ADJ

10µA

VIN 15

TRACK

CURRENT

LIMIT

1.25V

11 ISENSE

12 PDRV

UVLO

DRIVER

1.25V

REF

ENABLE

ENB

1

TRACK

VIN

–0.8V

ANTI

SHOOT THRU

PWM

COMP

VFB

2

4

R

Q

D

PWM

LATCH

10µA

DRIVER

S

Q

1.25V

UVLO

14 NDRV

SS

NC

3

9

REVERSE

SOFTSTART COMPLETE

PRECISION

BIAS

13 PWRGND

OVER CURRENT COUNTER

SHUTDOWN TIMER

SOFTSTART COMPLETE

REVERSE

CLK

OSCILLATOR

H = NO OVERCURRENT

CURRENT

LOGIC

REVERSE

10µA

DISABLE DRIVERS

16

5

GND

10

L = NO SHUTDOWN

H = LATCHED SHUTDOWN

CAP = TIMED SHUTDOWN

CT

SD

UDG-98008

PIN DESCRIPTIONS

Use capacitor values greater than 100pF in order to mini-

mize the effects of stray capacitance. The oscillator is ca-

pable of reliable operation in excess of 1MHz.

CLSET: CLSET is used to program the pulse by pulse

and overcurrent shutdown levels for the UCC1585. A re-

sistor is connected between CLSET and VIN to set the

thresholds. The threshold follows the following relation-

ship:

ENB: A LOGIC1 (V_IN–0.5V) on this input will activate the

Output drivers. A logic zero (0.5V) will prevent switching

of the output drivers. Do not allow ENB to remain be-

tween these levels steady state.

1.25

• R_CLSET

R_ISET

lcl =

RDS(on)

GND: Reference level for the IC. All voltages and cur-

rents are with respect to GND.

COMP: Output of the Voltage type error amplifier. Loop

compensation components are connected between

COMP and VFB.

ISENSE: ISENSE performs two functions. The first is to

monitor the voltage dropped across the high side P chan-

nel MOSFET switch while it is conducting. This informa-

tion is used to detect over current conditions by the

current limit circuitry. The second function of ISENSE is

to measure current through the lowside N-channel

MOSFET. When the current flow through this MOSFET is

drain to source, (i.e. reversed), this FET is turned off for

the remainder of the switching cycle.

CT: A high quality ceramic capacitor connected between

this pin and ground sets the PWM oscillator frequency by

the following relationship:

1

F =

(6700 • CT )

4

UCC2585

UCC3585

PIN DESCRIPTIONS (cont.)

ISET: A resistor is connected between ISET and ground SS: A low leakage capacitor connected between SS and

to program precision bias for many of the GND will provide a softstart function for the converter.

UCC2585/UCC3585 circuit blocks. Allowable resistor val- The voltage on this capacitor will slowly charge on start-

a

up via an internal current source. The output of the Volt-

age error amplifier (COMP) tracks this voltage thereby

limiting the controller duty ratio.

ues are 90kΩ to 110kΩ. 1.25V is provided to ISET via a

buffered version the internal bandgap voltage reference.

The resultant current is 1.25V / R_ISET.This current is mir-

rored directly over to CLSET to program the over current

thresholds. A second use for this current is to set a basis

for the charging current of the oscillator.

NDRV: High current driver output for the low side

MOSFET switch. A 3Ω to 10Ω series resistor between

NDRV and the MOSFET gate may be inserted to reduce

PDRV: High current driver output for the high side P ringing on this pin. In some layout situations, a low V_Fdi-

ode may be required from this pin to ground to keep the

pin from ringing more than 0.5V below ground.

channel MOSFET switch. A 3Ω to 10Ω series resistor be-

tween PDRV and the MOSFET gate may be inserted to

reduce ringing on this pin. In some layout situations, a

low V_Fdiode may be required from this pin to ground to

keep the pin from ringing more than 0.5V below ground.

TRACK: A resistor is connected between TRACK and

output voltage of the converter to set the start-up profile

of the power converter. Certain dual supply rail micropro-

cessors require that a maximum voltage differential be-

tween the supply rails is not exceeded. Failure to do so

results in large currents in the microprocessor through

the ESD (electrostatic discharge) protection devices. This

can result in chip failure. The UCC2585/UCC3585 is de-

signed such that it is “normally on” before V_INreaches

the 2.0V (nom.) UVLO threshold. That is, the high side P

channel MOSFET switch driver output is actively held low

allowing the MOSFET to conduct current to the output as

soon as V_INis high enough to exceed the gate turn on

threshold. The resistor from TRACK to V_OUTsets the

voltage level on VOUT at which the P channel MOSFET

is turned off. The tracking cutoff voltage follows the fol-

lowing relationship:

PWRGND: High current return path for the MOSFET

drivers. PWRGND and GND should be terminated to-

gether as close to the IC package as possible.

SD: This pin can configure current limit to operate in any

one of three different ways.

1) A forced voltage of less than 250mV on SD inhibits the

shutdown function causing pulse by pulse limiting.

2) A capacitor from SD to GND provides a control-

ler-converter shutdown timeout after 7 consecutive

overcurrent signals are received by the current limit cir-

cuitry. An interval 10µA (typ) current source discharges

the SD capacitor to the 0.5V (typ) restart threshold. The

shutdown time is given by:

V_OUT(max)=1.25V +12µ A• R

(

)

TRACK

[

]

C_SD• V −0.5

(

)

IN

T_SHUT

=

,

10 µ A

This is necessary for very low output voltage applications

(< 2.0V), where overvoltage may occur if the Pchannel

MOSFET is not disabled before the UVLO threshold is

reached. For applications with V_OUTgreater than 2.0V,

TRACK can be disabled by tying TRACK to V_IN.

where C_SDis the value of the capacitor from SD to GND,

and VIN is the chip supply voltage (on pin 15). At this

point, a softstart cycle is initiated, and a 100µA current

(typ) quickly recharges SD to VIN. During softstart, pulse

by pulse limiting is enabled, and the 7 cycle count is de-

layed until softstart is complete (i.e. charged to approxi-

mately VIN volts).

VFB: Inverting input to the Voltage type error amplifier.

The common mode input range for VFB extends from

GND to 1.5V.

VIN: Supply voltage for the UCC2585/UCC3585.Bypass

with a 0.1µF ceramic capacitor (minimum) to supply the

switching transient currents required by the external

MOSFET switches.

3) A forced voltage of greater than 1V on SD will cause

the UCC2585/UCC3585 to latch OFF after 7 overcurrent

signals are received. After the controller is latched off, SD

must drop below 250mV to restart the controller.

5

UCC2585

UCC3585

APPLICATION INFORMATION

V_OUT

V_IN

1.8

Some of today’s microprocessors require very low oper-

ating voltages. In some cases, as low as 1.8V of supply

voltage are required in addition to already available 3.3V

system voltage. Following is an illustration of a design

using the UCC3585 as the power controller.

δ =

=

=0.545

3.3

2) Select the output inductor to meet ripple current re-

quirements. For this design, the allowable ripple current in

the output inductor is selected to be 10% of the full load

output current.

The design criteria are as follows:

• Input Voltage (V_IN) 3.3V DC

(V_IN− V_OUT)• δ

L1=

= 4.6 µH

F_S• 0.1• I_OUT

• Output Voltage (V_OUT) 1.8V DC

A Pulse Engineering SMT inductor (PE-53682) is 4.7µH

has a DC resistance (R_L1) of 8.3mΩ and will dissipate

0.1W under full load operation.

• Output Ripple Voltage (V_OUT) 18mV

• Output Current (I_OUT) 3.5A DC

Other features include

• Output Tracking

The resulting ∆I_OUTis now:

(V_IN−V_OUT

4.7 • 10^{− 6}

)

δ

∆ I_OUT

=

•

=0.5 A

• Switching Frequency (F_S) 350kHz

• 100% Surface Mount

F^S

3) Next, the output capacitors are determined based

The first few steps in the design are to define the power upon the output ripple criteria. Assuming the ripple is lim-

stage (Schematic Fig. 1).

ited by the equivalent series resistance, or ESR, of the

capacitors and not the impedance of the capacitors at the

switching frequency, then the output capacitor selection is

based upon ESR, size and voltage considerations.

1) The normal operating duty cycle (δ) of the regulator is

approximately

VIN

C8

0.47µF

R3

27.4k

R1

10k

+

15 VIN

CLSET

8

R5

3

C1

C2

Q1

IRF7404

150µF 150µF

1

2

4

ENB

PDRV 12

ISENSE 11

NDRV 14

C7

147pF

R2

549k

L1 4.7µF

COMP

VFB

VOUT

R6

3

Q2

IRF7401

+

C11

C9

C10

220µF

10 SD

TRACK

N/C

6

9

C4

3.2N

R10

36k

R12

32k

3

SS

C5

0.22µF

16 CT

PWRGND 13

C6

470pF

7

ISET

GND

5

R11

82k

R4

100k

RTN

UDG-98024

Figure 1. Application circuit schematic.

6

UCC2585

UCC3585

APPLICATION INFORMATION (cont.)

∆V_OUT

0.018

and a body diode turn OFF switching time (t_OFF2) of

59ns. In this topology, the N Channel MOSFET, Q2, is

turned OFF prior to the turn ON of Q1, so when Q2 is

turned OFF, current is being re-routed from the channel

of the device into the intrinsic body diode. Therefore Q2’s

intrinsic body diode incurs switching loss during the turn

OFF interval.

ESR =

=

=0.026Ω

∆ I_OUT

0.5

A 220µF, 6.3V Sprague 594D capacitor has an ESR of

75mΩ. Three of these in parallel will result in an overall

ESR of 25mΩ. (C9, C10, and C11 in Fig. 1). Since the

output ripple current is so low, the capacitor’s ripple cur-

rent rating of 1.45A is not a concern.

The conduction loss in Q2 is:

To check the assumption that the capacitor’s impedance

at the switching frequency is dominated by the ESR and

not the capacitor’s capacitance value, calculate the im-

pedance and compare it to the ESR.

P_DQ2_ON=I_DQ2 _RMS²• R_DSQ2=0.2W

ON

The gate drive losses will be

P_DQ2_GATE=Q_G• V_IN• F_S=55mW

2

1

And the body diode turn OFF loss:

1

ZC =

=

= 2mΩ

2π • F^S• C 2π • 350k • 220 µ

P_DQ2 _{D _OFF}

=

• V_IN• I_D• T_{OFF 2}• F_S=0.13W

PK

The ESR of the capacitor is 37 times that of the imped-

ance of the capacitor at the switching frequency, so the

earlier assumption was valid.

2

The total power loss for Q2 is the sum of these three:

P_DQ2_TOTAL=0.4W

4) Before selecting the switching MOSFETs, the current

that will be flowing through them must first be deter-

mined.

7) Thus far the power loss in the two MOSFETs and the

output inductor total 1.0W. The average input current is:

V_OUT• I_OUT+P_LOSS

∆ I_OUT

I_IN

=

= 2.2A

I_D=I_OUT

+

=3.8 A

AVG

PK

V_IN

2

The RMS of this current in Q1 is

The peak to peak ripple in the input capacitors is the

peak current less the average input current during Q1’s

ON time, and equal to the average input current during

Q1’s OFF time. The RMS value of this current is then:

I_DQ1_RMS=I_D

δ = 2.8 A

PK

And in Q2

I_DQ2_RMS=I_D

1−δ = 2.5 A

PK

I_{IN_CAP}

= (I_D−I_IN)²• δ +(I_IN)²• (1−δ) =1.9 A

PK AVG AVG

RMS

5) Since this regulator must be able to operate from a

3.3V source, the MOSFETs used must have a gate

threshold level of no more than 2V.

8) After the input capacitor’s input ripple current is

known, select the input capacitors. Again, Sprague 594D

Solid Tantalum capacitors are chosen. A single 150µF,

10V capacitor has a ripple current rating of 1.35A RMS.

Two in parallel (C1 and C2) will have a combined capabil-

ity of 2.7A, and a total ESR of 40mΩ. The losses in the

capacitors are:

For Q1, an IRF7404 is selected. It has an R_DS(on)of

0.04Ω, a total gate charge (Q_G1) of 50nC, and a turn

OFF (t_OFF1) time of 65ns. The conduction loss in Q1 will

be:

P_DQ1_ON=I_DQ1_RMS²• R_DSQ1=0.593W

ON

2

P_{DIN_CAP}=I_{IN_CAP}

• ESR =0.14W

The gate drive losses will be

RMS

Adding the capacitor loss to that previously found, the to-

tal losses are now 2.1W.

P_DQ1_GATE=Q_G• V_IN• F_S=58mW

1

And finally the turn OFF losses are estimated

1

9) The overall efficiency of the power train is then

P_DQ1_OFF

=

• V_IN• I_DQ1_PK• T_OFF1• F_S=0.14W

V_OUT• I_OUT

2

E_FF

=

=0.84

V_OUT• I_OUT+ 2.1

The total power loss for Q1 is the sum of these three:

P_DQ1_TOTAL=0.5W

The losses are dominated by the MOSFETs Q1 and Q2.

One way to improve the efficiency would be to reduce the

conduction loss in Q1, either by choosing a device with a

6) Q2 has been selected to be an IRF7401, which has an

_DS(ON)of 0.03Ω, and a total gate charge (Q_G2) of 48nC

R

7

UCC2585

UCC3585

APPLICATION INFORMATION (cont.)

lower R_DS(on)or by paralleling it with another MOSFET. 11) The voltage divider is next determined to give us the

The conduction losses in Q2 may be improved by the proper output voltage. First select one of the divider re-

same technique, but will prove detrimental in switching sistors R11 = 82k. The other resistor becomes:

losses. To lower the switching losses, Q2 may be paral-

V_OUT

R10 =R11•

−R11=36k

leled with a Schottky diode. In this manner, the switching

loss may be absorbed by the Schottky, instead of the

MOSFET.

V_REF

12) The equation for the error amplifier in this configura-

tion is:

10) After the power stage design is completed, attention

is given to the feedback loop. The LC filter gain is de-

scribed by the equation (10A) below: (where ω= j2πf)

1

+R2

_J2π • f • C7

K_EA

=

R10

Where C_OUTis the combined capacitance of C9, C10,

and C11 and R_ESRis the ESR of the capacitors.

For a gain of 5 and a zero at 2kHz

There will be a double pole at:

1

R2=15 • R10 =180k

and

F_P=

= 2.8kHz

2π L1• C_OUT

1

2π • fp • R2

C7 =

= 440pF

and a zero at the point where the impedance of the out-

put capacitors equals the ESR:

The overall voltage loop gain now has a crossover at

34kHz with a phase margin of about 73 degrees.

1

F_Z

=

=9.6kHz

2π • R_ESR• C_OUT

13) Select the R_ISETresistor, R3, to be 100k. (The range

of value should be between 90k and 110k.) Then choos-

ing the current limit trip point to be 130% of I_OUT, the cur-

rent limit set resistor is then found by the relationship

The modulator gain is given by

V_IN

K_PWM

=

=1.65

V_RAMP

1.3 • I_OUT

R3 =

• R_{DS on}Q1• R_ISET= 27.2k

( )

where V_RAMPis the peak to peak amplitude of the oscil-

lator ramp found on the CT pin. The overall open loop

gain is shown in Fig. 2.

1.25

Note that the R_DS(on)value used should include the ef-

fects of temperature.

100

10

0

80

AMPLIFIER GAIN

60

40

20

0

-10

-20

-30

-40

OVERALL LOOP GAIN

-20

-40

-60

10

100

1000

10000

100000

10

100

1000

FREQUENCY (Hz)

10000

100000

FREQUENCY (Hz)

Figure 2. Modulator and filter frequency response.

Figure 3. Error amp and closed loop frequency

response.

1+ω • R_ESR• C_OUT

(10A) KLC =

L1

1+ω ²• L1• C_OUT+ω R_L1• C_OUT+R_ESR• C_OUT

+

R_LOAD

8

UCC2585

UCC3585

APPLICATION INFORMATION (cont.)

14) During normal power on of the UCC3585, the gate of

Q1 is held low (Q1 turned ON) until the V_CCinput to the

IC reaches the 2V Under Voltage Lockout (UVLO) volt-

age. At UVLO, the UCC3585 wakes up and switching be-

gins on Q1 and Q2. With a 1.8V output however, the

output will reach 2V before regulation begins! This is

where the tracking function comes into use. By selecting

an appropriate resistive divider from the output, we can

select the point below UVLO at which Q1 will be shut off.

Upon reaching UVLO, the UCC3585 will then begin to

regulate normally.

180

135

90

ERROR AMP

OVERALL LOOP

45

0

With a 1.8V nominal output voltage, select the tracking

turn off point to be 1.6V.

10

100

1000

10000

100000

FREQUENCY (Hz)

1.6 −1.25

R3 =

= 29k Ω

Figure 4. Error amp and closed loop frequency

response.

12µ

Note that the tracking function ONLY makes a difference

below UVLO. If V_OUTwere to be 2V or above, then the

tracking pin should be tied to V_IN.

POWER ON PROFILE

15) A capacitor on the SD pin will allow the converter to

shutdown in the event seven consecutive over current

pulses occur. If a timing shutdown interval of 1ms is cho-

sen as the shutdown time, T_SD, then the value of the ca-

pacitor is:

WITHOUT "TRACK AND HOLD"

2.0

1.5

1.0

POWER ON

PROFILE WITH

"TRACK AND HOLD"

T_SD

C4=

=3.2nF

0.5

1

(V_IN– 0.5 )•

+

I_CHGI_DICHG

1.0

1.5

2.0

VIN (V)

2.5

Where I_CHGand I_DISCHGare 100µA and 10µA respect-

fully.

Figure 5. Power on profile.

16) The next step is to find the value of timing capacitor.

T_S

C6 =

= 476pF

6000

80

60

40

20

A 470pF capacitor will result in a switching frequency of

354kHz.

17) The softstart capacitor is selected for a 5ms startup

time. Knowing that a 10µA current source will charge the

capacitor to 2.5V, the softstart capacitor is given by:

T_SS• I_CHG

5m • 10 µ

C5 =

=

= 20nF

V_SS

2.5

1.2

1.4

1.6

1.8

2.0

VTR (V)

Figure 6. Tracking resistor value as a function of turn

off voltage.

UNITRODE CORPORATION

7 CONTINENTAL BLVD. • MERRIMACK, NH 03054

TEL. (603) 424-2410 • FAX (603) 424-3460

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Machines Corporation

9

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型号：	UCC3585N
厂家：	TEXAS INSTRUMENTS
描述：	Low Voltage Synchronous Buck Controller 16-PDIP 0 to 85 控制器
文件：	总10页 (文件大小：142K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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