UCC3882DWG4 [TI]
IC,SMPS CONTROLLER,CURRENT-MODE,BICMOS,SOP,28PIN,PLASTIC;
| 型号： | UCC3882DWG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC,SMPS CONTROLLER,CURRENT-MODE,BICMOS,SOP,28PIN,PLASTIC 信息通信管理 |
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UCC2882/-1
UCC3882/-1
Average Current Mode Synchronous Controller With 5-Bit DAC
DESCRIPTION
FEATURES
The UCC3882 combines high precision reference and voltage
monitoring circuitry with average current mode PWM synchro-
nous rectification controller circuitry to power high-end micropro-
cessors with a minimum of external components. The UCC3882
converts 5V or 12V to an adjustable output ranging from 1.8VDC
to 2.05VDC in 50mV steps and 2.1VDC to 3.5VDC in 100mV
steps with 1% DC system accuracy.
• Combined DAC/Voltage Monitor and PWM
with Synchronous Rectification Functions
• 5-Bit Digital-to-Analog (DAC) Converter
• 1% DAC/Reference Combined Accuracy
• Compatible with 5V and 12V Systems and
12V-only Systems
The DAC output voltage is directly compatible with Intel’s 5-bit
VID code (Table 1) which covers 1.3V to 2.05V in 50mV steps
and 2.1V to 3.5V in 100mV steps. The accuracy of the DAC/ref-
erence combination is better than 1%. Undervoltage lockout cir-
cuitry assures the correct logic states at the outputs during
power up and power down. The overvoltage and undervoltage
comparators monitor the system output voltage and indicate
when it rises above or falls below its designed value by more
than 9%. A second overvoltage comparator digitally forces
GATEHI off and GATELO on when the system output voltage ex-
ceeds its designed value by more than 17.5%.
• Low Offset Current Sense Amplifier
• Programmable Oscillator Frequency Practical
to 700kHz
• Foldback Current Limiting
• Overvoltage and Undervoltage Fault Windows
• 2Ω Totem Pole Outputs with Programmable
Dead Times to Eliminate Cross-Conduction
• Chip Disable Function
(continued)
BLOCK DIAGRAM
UDG-97047-1
03/99
UCC2882/-1
UCC3882/-1
CONNECTION DIAGRAM
ABSOLUTE MAXIMUM RATINGS
VDRVHI, GATEHI (Note 1) . . . . . . . . . . . . . . . . . –0.3V to 20V
VDRVLO, GATELO. . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 15V
All other pins referenced to GND . . . . . . . . . . . . . –0.3V to 5.3V
VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15V
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature. . . . . . . . . . . . . . . . . . . –55°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C
DIL-28, SOIC-28 (Top View)
N, DW or PW Packages
VSNS
PWRGD
N/C
1
2
3
4
5
6
7
8
9
28 GND
27 D0
26 D1
Currents are positive into, negative out of the specified terminal.
Consult Packaging Section of Databook for thermal limitations
and considerations of packages.
CAM
CAO
25 N/C
24 D2
Note 1: 20V at no load. Derate to 18.5V when used with capaci-
tive loads of greater than 1000pF in series with less than 20 Ω.
ISOUT
IS+
23 D3
22 D4
IS–
21 VREF
20 COMMAND
19 VDRVHI
18 GATEHI
17 EN
VIN
VDRVLO 10
GATELO 11
PGND 12
RT 13
16 COMP
15 VFB
CT 14
DESCRIPTION (continued)
For all of the parts, grounding the EN pin disables the nally programmed with RT and CT. The foldback circuit
GATEHI and GATELO outputs, shutting down the power reduces the converter short circuit current limit to 50% of
supply. For the 2882 and 3882 only, programming a DAC its nominal value when the converter is short-circuited,
output voltage below 1.8V, or programming all of the VID minimizing component stress and dissipation during ab-
pins high also disables the GATEHI and GATELO out- normal conditions. The gate drivers are low impedance
puts. For the “–1" option parts, the GATEHI and GATELO totem pole output stages capable of driving large exter-
outputs are switching, and the power supply output volt- nal MOSFETs. Cross conduction is eliminated internally
age regulates at the programmed DAC output voltage for by programming the dead time between turn-off and turn
all VID codes.
on of the external high side and synchronous MOSFETs.
The voltage and current amplifiers have 2.5MHz This device is available in a 28-pin wide body surface
gain-bandwidth product to satisfy high performance sys- mount package. The UCC2882 is specified for operation
tem requirements. The internal current sense amplifier from –25°C to +85°C and the UCC3882 is specified for
permits the use of a low value current sense resistor, operation from 0°C to 70°C.
minimizing power loss. The oscillator frequency is exter-
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VIN = VDRVHI = VDRVLO = 12V, VSNS = 3.5V, VD0 = VD1
= VD2 = VD3 = VD4 = 0V, RT = 13k, CT = 1.8nF, EN = Open, 0°C < TA < 70°C, TA = TJ.
PARAMETER
Undervoltage Lockout
TEST CONDITIONS
MIN
TYP
MAX UNITS
VIN UVLO Turn-on Threshold
VIN UVLO Turn-off Threshold
UVLO Threshold Hysteresis
Supply Current
10.5
10
10.8
700
12
V
V
9.5
300
500
mV
lIN
EN = 0V
7
mA
2
UCC2882/-1
UCC3882/-1
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VIN = VDRVHI = VDRVLO = 12V, VSNS = 3.5V, VD0 = VD1
= VD2 = VD3 = VD4 = 0V, RT = 13k, CT = 1.8nF, EN = Open, 0°C < TA < 70°C, TA = TJ.
PARAMETER
DAC/Reference
TEST CONDITIONS
MIN
–1
TYP
MAX UNITS
COMMAND Voltage Accuracy
D0-D4 Voltage High
D0-D4 Input Bias Current
OVP Comparator
Trip Point
10.8V < VIN < 13.2V, IREF = 0mA (Note 1)
DX Pin Floating
1
%
V
5
5.2
–20
DX Pin Tied to GND
–120
10
–70
µA
% Over COMMAND Voltage (Note 2)
% Over COMMAND Voltage (Note 2)
17
20
25
%
Hysteresis
mV
OV Comparator
Trip Point
5
9
12
470
–5
%
mV
Ω
Hysteresis
20
PWRGD On Resistance
UV Comparator
Trip Point
% Over COMMAND Voltage (Note 2)
VEN = 2.5V
–12
–80
–9
20
%
Hysteresis
mV
Enable Pin
Pull Up Current
–50
0
–20
µA
Voltage Error Amplifier
Input Offset Voltage
Input Bias Current
Open Loop Gain
VCM = 3V
–10
10
mV
µA
dB
VCM = 3V
–0.5
0.5
2.05V < VCOMP < 3.05V
10.8V < VIN < 15V
90
85
Power Supply Rejection Ratio
Output Sourcing Current
Output Sinking Current
Current Sense Amplifier
Gain
dB
VVFB = 2V, VCOMMAND = VCOMP = 2.5V
VVFB = 3V, VCOMMAND = VCOMP = 2.5V
–1.6
1
–0.8
17
mA
mA
15
3
16
60
80
–4
4
V/V
dB
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Output Sourcing Current
Output Sinking Current
Current Amplifier
Input Offset Voltage
Input Bias Current
Open Loop Gain
0V < VCM < 4.5V
10.8V < VIN < 15V
dB
VIS– = 2V, VISOUT = VIS+ = 2.5V
VIS– = 3V, VISOUT = VIS+ = 2.5V
–3
mA
mA
VCM = 3V
1
–0.1
90
3
mV
µA
dB
V
VCM = 3V
1V < VCAO < 2.5V
Output Voltage High
Power Supply Rejection Ratio
Output Sourcing Current
Output Sinking Current
Oscillator
10.8V < VIN < 15V
80
–7
17
dB
mA
mA
VCAM = 2V, VCAO = VCOMP = 2.5V
VCAM = 3V, VCAO = VCOMP = 2.5V
Initial Accuracy
TA = 25°C
324
300
360
360
1.67
1
396
420
kHz
kHz
V
0°C < TA < 70°C
Valley to Peak Voltage
Frequency Change With Voltage
Output Section (GATEHI and GATELO)
Output Low Voltage
10.8V < VIN < 15V
%
IGATE = –100mA
0.2
11.8
20
V
V
Output High Voltage
IGATE = 100mA
Rise Time
CGATE = 3.3nF, RSERIES = 10Ω
CGATE = 3.3nF, RSERIES = 10Ω
80
80
ns
ns
Fall Time
15
3
UCC2882/-1
UCC3882/-1
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VIN = VDRVHI = VDRVLO = 12V, VSNS = 3.5V, VD0 = VD1
= VD2 = VD3 = VD4 = 0V, RT = 13k, CT = 1.8nF, EN = Open, 0°C < TA < 70°C, TA = TJ.
PARAMETER
Turn On Delay
TEST CONDITIONS
MIN
TYP
MAX UNITS
GATEHI Turn Off to GATELO Turn On
GATELO Turn Off to GATEHI Turn On
Foldback Current Limit
150
135
ns
ns
Clamp Level
VCOMMAND = VSNS
1.37
0.71
17
V
V
VFB = VCOMMAND – 100mV (Note 3)
VSNS = 0
VFB = VCOMMAND – 100mV (Note 3)
VCOMMAND = 2.3V
System Short Circuit Current Limit
14.4
22
A
VFB = 0V (Note 4)
Note 1: This test measures the combined errors of the COMMAND voltage and the voltage amplifier offset voltage. Applies to all
DAC codes from 1.8V to 3.5V.
Note 2: This percentage is measured with respect to the ideal COMMAND voltage programmed by the D0 - D4 pins.
Note 3: This voltage is measured with respect to the COMMAND voltage.
Note 4: The calculation of this parameter assumes an offchip sense resistor value of 0.005Ω. This test encompasses all sources
of error from the IC.
PIN DESCRIPTIONS
CAM: This pin is the inverting input to the current ampli- CT: This pin is used with RT to program the internal
fier. The average load current feedback from the ISOUT PWM oscillator frequency. Use a high quality capacitor
pin is applied through a resistor to this pin. The current for best oscillator accuracy. See the Applications Section
loop compensation network is also connected to this pin for programming the oscillator.
(see CAO below).
D0-D4: These are the digital input control codes for the
CAO: This pin is the current amplifier output. The current DAC (See Table 1). The DAC is comprised of two ranges
loop compensation network is connected between this set by D4 and with D0 representing the least significant
pin and the CAM pin. The voltage on this pin is the input bit (LSB) and D3, the most significant bit (MSB). A bit is
to the PWM comparator and regulates the output voltage set low by being connected to GND; a bit is set high by
of the system. The voltage at this output ranges from be- floating it, or connecting it to a 5V source. Each control
low 0.5V (forcing 0% duty cycle) to above 2.5V forcing pin is pulled up to approximately 5V by an internal pull
maximum duty cycle. A 3V clamp circuit prevents the up.
CAO voltage from rising excessively past the oscillator
peak voltage, for excellent transient response.
EN: This input is used to disable the GATEHI and
GATELO outputs, resulting in disabling the power supply.
COMP: This pin is the voltage error amplifier output volt- Pulling EN to GND causes the GATEHI and GATELO
age. The system voltage compensation network is ap- outputs to be held low, while floating the pin or pulling it
plied between COMP and VFB. A 1.37V clamp above up to 5V ensures normal operation. EN is pulled up to 5V
COMMAND is used to force the power supply into cur- internally.
rent limit mode when the output is short circuited. See
the Applications Section for programming current limit.
GATEHI: This output provides a low impedance totem
pole driver to drive the high-side external MOSFET. A se-
COMMAND: This pin is the output of the 5-bit digi- ries resistor between this pin and the gate of the external
tal-to-analog (DAC) converter and is the non-inverting in- MOSFET is recommended to prevent gate drive ringing
put of the voltage error amplifier. The voltage on this pin and overshoot. Good layout techniques should be used
sets the switching regulator output voltage. The COM- to prevent GATEHI from ringing more than 0.3V below
MAND voltage is set by the DAC input pins D0-D4, ac- PGND. The VDRVHI pin provides the power for the
cording to Table 1. The COMMAND source impedance is GATEHI pin. GATEHI is disabled during UVLO and
overvoltage conditions. For the 2882/3882 only, GATEHI
is also disabled when the COMMAND voltage is pro-
grammed between 1.3 and 1.75V, or where the D0-D4
pins are all logic high levels, indicating no processor
present.
typically 1.2kΩ and must therefore drive only high imped-
ance inputs if accuracy is to be maintained. Bypass
COMMAND with a 0.01µF, low ESR, low ESL capacitor
for best circuit noise immunity.
4
UCC2882/-1
UCC3882/-1
PIN DESCRIPTIONS (continued)
GATELO: This output provides a low impedance totem VDRVHI: This pin supplies power to the high side output
pole driver to drive the low-side synchronous external driver, GATEHI. Connect VDRVHI to an 18V or lower
MOSFET. A series resistor between this pin and the gate source for power supplies converting 12VDC to lower
of the external MOSFET is recommended to prevent gate voltages, and to a 12V source for systems for power sup-
drive ringing and overshoot. Good layout techniques plies converting 5VDC. This pin should be bypassed di-
should be used to prevent GATELO from ringing more rectly to PGND using a low ESR capacitor.
than 0.3V below PGND. The VDRVLO pin provides the
VDRVLO: This pin supplies power to the low side output
power for GATELO. GATELO is disabled during UVLO
driver, GATELO. VDRVLO is typically connected to a 12V
conditions. For the 2882/3882 only, GATELO is also dis-
source, but may be connected to a 5V source for driving
abled when the COMMAND voltage is programmed be-
logic level MOSFETs. This pin should be bypassed di-
tween 1.3 and 1.75V, or where the D0-D4 pins are all
rectly to PGND using a low ESR capacitor.
logic high levels, indicating no processor present.
VIN: This pin supplies power to the chip. Connect VIN to
a stable voltage source that is at least 10.8V above GND.
GND: Ground reference for the device. All voltages, with
the exception of the GATE voltages, are measured with
The GATEHI, GATELO and PWRGD outputs will be held
respect to GND. Bypass capacitors on VIN, VREF, VSNS
low until VCC exceeds the upper undervoltage lockout
and COMMAND should be connected directly to the
threshold. This pin should be bypassed directly to GND.
ground plane near GND.
VFB: This pin is the inverting input to the error amplifier.
This input is connected to COMP through a feedback
IS-: This pin is the inverting input to the current sense
amplifier and is connected to the low side of the average
network and to the power supply output through a resis-
current sense resistor.
tor or a divider network.
IS+: This pin is the non-inverting input to the current
VREF: This pin provides an accurate 5V reference and is
sense amplifier and is connected to the high side of the
internally short circuit current limited. VREF powers the
average current sense resistor.
D/A Converter and also provides a threshold voltage for
ISOUT: This pin is the output of the current sense ampli- the UVLO comparator. For best reference stability, by-
fier. The voltage on this pin is equal to the voltage across pass VREF directly to GND with a low ESR, low ESL ca-
the sense resistor multiplied by 16 and biased up by the
COMMAND voltage. This voltage is used for Average
Current mode control and for current limiting.
pacitor of at least 0.01µF.
VSNS: This pin is connected to the system output volt-
age through a low pass R-C filter. When the voltage on
VSNS rises above or falls below the COMMAND voltage
by 9%, the PWRGD output is driven low to reset the mi-
croprocessor. When the voltage on VSNS rises above
the COMMAND voltage by 17.5%, the OVP comparator
disables the GATEHI output and enables the GATELO
output, forcing 0% duty cycle on the power supply. This
pin is also used by the foldback current limiting circuitry
to indicate when the output voltage has been short cir-
cuited. VSNS should be decoupled very closely to the IC
with a capacitor to GND. The OV and UV comparators’
hysteresis is typically 20mV, requiring good layout and fil-
tering techniques to insure that noise and ground-bounce
do not inadvertently trip the OV and UV comparators. It is
recommended that an R-C filter set to approximately
Fs/10 be used to filter noise from the system output,
where Fs is the oscillator frequency.
PGND: This pin provides a dedicated ground for the out-
put gate drivers. The GND and PGND pins should be
connected externally using a short PC board trace or
plane. Decouple VDRVHI and VDRVLO to PGND with
low ESR capacitor of at least 0.1µF.
PWRGD: This pin is an open drain output which is driven
low to reset the microprocessor when VSNS rises above
or falls below its nominal value by 9%. The on resistance
of the open-drain switch will be no higher than 470Ω.
This output should be pulled up to a logic level voltage
and should be programmed to sink 1mA or less.
RT: This pin is used with CT to program the internal
PWM oscillator frequency. It is also used to program the
delay times between the external MOSFET turn on and
turn off periods, which eliminates cross conduction in
those MOSFETs. See the Applications Section for pro-
gramming the oscillator and for controlling cross conduc-
tion.
5
UCC2882/-1
UCC3882/-1
DAC INFORMATION
The 5-bit Digital-to-Analog Converter (DAC) is pro- GATELO are disabled at certain DAC codes, as shown
grammed according to Table 1.The COMMAND voltage in Table 1. Disabling the gate drives disables the power
is always active as long as the UCC3882 VIN pin is supply. For the 2882 -1 and 3882 -1, the GATEHI and
above the undervoltage lockout voltage. For the GATELO drives are enabled for all DAC codes. For a
2882/3882 only, the output gate drives GATEHI and given code, the power supply output regulates at the cor-
responding COMMAND voltage.
Digital Command
Command
Voltage
1.300
1.350
1.400
1.450
1.500
1.550
1.600
1.650
1.700
1.750
1.800
1.850
1.900
1.950
2.000
2.050
GATEHI/GATELO
Status
Digital Command
Command
Voltage
2.000
2.100
2.200
2.300
2.400
2.500
2.600
2.700
2.800
2.900
3.000
3.100
3.200
3.300
3.400
3.500
GATEHI/GATELO
Status
D4 D3 D2 D1 D0
D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Note 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Note 1
Note 1
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Table 1. Programming the Command Voltage for the UCC3882
APPLICATION INFORMATION
This IC is intended to be used in a high performance only part of the solution. The power supply designer
®
power supply to power the Pentium II or a similar pro- must also understand intrinsic delays involving MOSFET
cessor. Figure 1 shows a typical power supply application turn on, turn off, rise and fall times in order to insure that
circuit which converts +5V to lower voltages required by there is no cross conduction.
®
the Pentium II Processor.
It is recommended that a value between 10kΩ and 15kΩ
Synchronous Switching Delay Time
be used for RT, which minimizes the delay and can result
in the highest efficiency operation. A higher value of RT
will result in a larger delay between the MOSFET Gate
transitions. RT should be between 10kΩ minimum and
50kΩ maximum.
Figure 2 shows that the fundamental difference between
a Buck and a Synchronous Buck regulator is the use of a
MOSFET rather than a Schottky diode as the low side or
free-wheeling switch.
Programming the Oscillator
In order to maintain safe and efficient operation of a Syn-
chronous Buck regulator, both MOSFETs, Q1 and Q2,
should never be turned on at the same time. Having both
MOSFETs on at the same time results in cross conduc-
tion, which can result in excessively high power dissipa-
tion in one or both MOSFETs. The UCC3882 has a built
in delay between the turn OFF of one MOSFET and the
turn ON of the other MOSFET. This delay is a controlled
delay between the GATEHI and GATELO drive outputs
and is programmable by the selection of the resistor RT.
Controlling the delay between the gate drive outputs is
The first step in programming the oscillator is choosing
the value of RT as described above. The second step is
to program the frequency according to the curves shown
in Figure 3, by choosing the appropriate capacitor value.
For convenience, values are shown in Table 1 for nominal
frequencies from 100kHz to 700kHz using standards re-
sistors and capacitor values.
6
UCC2882/-1
UCC3882/-1
APPLICATION INFORMATION (continued)
Using an External Schottky Diode in Parallel With the
Low Side MOSFET
FREQUENCY
(kHz)
100
RT
CT
(kΩ)
14.7
11.0
10.5
11.3
12.7
10.7
11.0
(pF)
5600
3900
2700
1800
1200
1200
1000
The purpose of using a synchronous buck regulator is to
substitute a low voltage drop MOSFET in place of a
Schottky diode as the low side switch. An external
Schottky diode may still be required however, in order to
reduce the losses due to the reverse recovery of the
low-side MOSFET body diode. Figure 4 illustrates the ef-
fects on power losses due to the non-ideal nature of a
typical MOSFET body diode. IRM is the peak recovery
current of the body diode of Q2 and ILOUT is the current
of the output inductor. Using a parallel Schottky diode
can reduce these losses and increase circuit efficiency.
The size of the diode should be increased as a function
of load current, input voltage, and operating frequency.
The diode should be as close to the lower MOSFET, Q2,
as possible, to reduce stray inductance.
200
300
400
500
600
700
Table 2. Programming Standard Frequencies
An excessively long delay time between gate drive sig-
nals, or a delay time that is too small, will result in a inef-
ficient power supply design. The third step in
programming the oscillator is to observe the actual circuit
waveforms to insure that the delay is optimal. The de-
signer should vary RT and CT accordingly to adjust the
delay time and to program the proper oscillator fre-
quency.
UDG-97048-1
®
Figure 1. Application circuit - Pentium II power supply.
7
UCC2882/-1
UCC3882/-1
APPLICATION INFORMATION
Choosing RSENSE to Set the Current Limit
800
700
600
500
400
300
200
100
0
RSENSE is chosen to limit the maximum (short circuit)
current of the power supply. The short circuit current
equation for the UCC3882 is:
1.0nF
1.2nF
1.37V
ISC =
1.8nF
2.7nF
2.2n
RSENSE •16
and therefore, the value of the sense resistor, for a cho-
sen short circuit current is:
3.9nF
1.37V
5.6nF
RSENSE =
ISC •16
10
15
20
25
RT [kW]
The short circuit current limit does vary slightly as a func-
tion of the switching regulator’s output inductor value and
operating frequency because a high value of ripple cur-
rent will reduce the average short circuit current limit.
Figure 5 shows the variation in Isc given common values
for the UCC3882. The UCC3882 is nominally configured
so that a 0.005mΩ resistor will set the current limit to ap-
proximately 17A.
Figure 3. Programming UCC3882 oscillator
frequency.
Choosing VDRVLO, VDRVHI and VIN
The UCC3882 requires a nominal 12V input supplied at
VIN. VDRVLO and VDRVHI can be set to any voltage
less than 18.5V, and may be set individually. A power
supply deriving its power from +5V should use +12V at
the VDRVHI pin, but may use either +5V or +12V de-
pending on the drive requirements of the synchronous
low-side MOSFET. A power supply deriving its power
from +12V should use +18V at VDRVHI in order to pro-
vide adequate voltage (6V) gate drive to the high-side
MOSFET. VIN must be less than +15V.
The UCC3882 incorporates short circuit current foldback,
as shown in Figure 6. When the output of the power sup-
ply is short circuited, the output voltage falls. When the
output voltage reaches 1/2 of its nominal voltage (COM-
MAND/2) then the output current is reduced. This feature
reduces the amount of current in the MOSFETs and ca-
pacitors, and insures high reliability.
Input Capacitors
The input capacitors are chosen primarily based on their
switching frequency RMS current handling capability and
their voltage rating. The input capacitors must handle vir-
tually all of the RMS current at the switching frequency,
even if the circuit does not have an input inductor. The
switching current in the input capacitors appears as
shown in Figure 7.
Aluminum or tantalum capacitors can be used. The
amount of RMS current in an Electrolytic capacitor has a
strong impact on the reliability and lifetime of the capaci-
tor. Other factors which affect the life of an input capaci-
tor are internal heat rise, external airflow, the amount of
time that the circuit operates at maximum current and
the operating voltage. The curves in Figure 8 show the
RMS current handled by the total input capacitance in
typical VRM circuits powered from 5V or from 12V.
UDG-97049
Figure 2. Buck vs. synchronous buck regulator.
8
UCC2882/-1
UCC3882/-1
APPLICATION INFORMATION (continued)
100
80
60
40
20
0
0
20
40
60
80
100
% SHORT CIRCUIT CURRENT
Figure 6. Short circuit foldback reduces stress on
circuit components by reducing short circuit current.
UDG-97051
Figure 4. Effects of reverse recovery in a
synchronous rectifier.
UDG-96216
6.5
400kHz, 3mH
Figure 7. Input capacitors current waveform.
6
5.5
5
VIN 5V, VOUT 1.8V
10.0
VIN 5V, VOUT 2.8V
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
VIN 12V, VOUT 2.8V
VIN 12V, VOUT 1.8V
4.5
200kHz, 3mH
300kHz, 1.5mH
400kHz, 1.5mH
200kHz, 1.5mH
{
4
13
14
15
16
17
18
19
20
Choose the type and number of input capacitors based on
these curves by choosing the input voltage and nominal
output voltage. Example: For a 5V input, 1.8V output power
supply with a load of 15 Amperes, the input capacitors
should be chosen for 7.5 Amperes RMS current.
SHORT CIRCUIT CURRENT (A)
Figure 5. Short circuit current limit vs. RSENSE for
various frequency and inductor values.
10 11 12 13 14 15 16 17 18 19 20
LOAD CURRENT (A)
Figure 8. Load current vs RMS current for input
®
capacitors - Pentium II Family.
9
UCC2882/-1
UCC3882/-1
APPLICATION INFORMATION (continued)
Demonstration Kit Design and Performance
• Short Circuit Current = 17A Nominal
A demonstration circuit was built based on the UCC3882
and utilizing an Intel VRM 8.1 form factor connector. The
schematic is shown in Figure 9 and the Bill of Materials
in Table 3. The circuit is configured for the following oper-
ating parameters:
• Output Voltage: 1.8V to 2.8V Configured by VID Code
• Airflow: 100 LFM
• Temperature: 0 to 60°C
• Regulation: Per Intel VRM 8.1 DC-DC Converter
Design Guidelines
• Switching Frequency = 225kHz
• Rated Output Current = 15A
Figures 12 - 14 show the performance of the circuit.
REF
U1
DESCRIPTION
PACKAGE
Unitrode UCC3882 DAC/PWM
Sanyo 6MV1500GX, 1500µF, 6.3V, Aluminum Electrolytic
Sanyo 6MV1500GX, 1500µF, 6.3V, Aluminum Electrolytic
Sanyo 6MV1500GX, 1500µF, 6.3V, Aluminum Electrolytic
Sprague/Vishay 595D475X0016A2B, 4.7uF 16V Tantalum
Sanyo 6MV1500GX, 1500µF, 6.3V, Aluminum Electrolytic
Sanyo 6MV1500GX, 1500µF, 6.3V, Aluminum Electrolytic
Sanyo 6MV1500GX, 1500µF, 6.3V, Aluminum Electrolytic
Sanyo 6MV1500GX, 1500µF, 6.3V, Aluminum Electrolytic
Sanyo 6MV1500GX, 1500µF, 6.3V, Aluminum Electrolytic
0.10µF Ceramic
SOIC-28 WIDE
10x20mm Radial Can
10x20mm Radial Can
10x20mm Radial Can
SPRAGUE Size A
10x20mm Radial Can
10x20mm Radial Can
10x20mm Radial Can
10x20mm Radial Can
10x20mm Radial Can
1206 SMD
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
C17
C18
C19
C20
CT
0.10µF Ceramic
1206 SMD
0.01µF Ceramic
0603 SMD
0.01µF Ceramic
0603 SMD
0.01µF Ceramic
0603 SMD
0.10µF Ceramic
1206 SMD
68pF NPO Ceramic
0603 SMD
1000pF Ceramic
0603 SMD
220pF NPO Ceramic
0603 SMD
Sanyo 6MV1500GX, 1500µF, 6.3V, Aluminum Electrolytic
3900pF Ceramic
10x20mm Radial Can
0603 SMD
J1
AMP 532956-7 40 Pin Connector
Toroid T51-52C, 5 Turns #16AWG, 1.6µH
International Rectifier IRL3103, 30V, 56A
International Rectifier IRL3103D1, 30V, 56A
5mΩ, PCB Resistor
40 Pin
L1
Toroid
Q1
TO-220AB, layed down
TO-220AB, layed down
Copper Trace
0603 SMD
Q2
R01
R02
R03
R05
R06
R07
R08
R09
R10
10kΩ, 5%, 1/16 Watt
5.62kΩ, 1%, 1/16 Watt
0603 SMD
365kΩ, 1%, 1/16 Watt
0603 SMD
100kΩ, 5%, 1/16 Watt
0603 SMD
5.6kΩ, 5%, 1/16 Watt
0603 SMD
10kΩ, 5%, 1/16 Watt
0603 SMD
3.3Ω, 5%, 1/16 Watt
0603 SMD
3.3Ω, 5%, 1/16 Watt
0603 SMD
Table 3. Bill of materials.
10
UCC2882/-1
UCC3882/-1
APPLICATION INFORMATION (continued)
UDG-97140
®
Figure 9. Reference design - UCC3882 5-bit synchronous rectifier PWM controller for the Intel Pentium II
processor.
11
UCC2882/-1
UCC3882/-1
APPLICATION INFORMATION (continued)
Figure 10. Demo board.
Figure 11a. COMP silkscreen.
Figure 11b. COMP side.
Figure 11c. GND layer.
Figure 11d. PWR layer.
Figure 11e. Solder side.
Figure 11f. Drill drawing.
12
UCC2882/-1
UCC3882/-1
APPLICATION INFORMATION (cont.)
5.00%
3.00%
1.00%
-1.00%
-3.00%
-5.00%
0
2
4
6
8
10
12
14
16
LOAD CURRENT (A)
Figure 14. Load regulation.
Figure 12. Transient response to 15.2A step load
channel 2 scale is 50mV/A.
95%
90%
85%
80%
75%
70%
65%
60%
55%
50%
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
EFFICIENCY
POWER
DISSIPATION
0.0
5.0
10.0
15.0
DC LOAD CURRENT (A)
Figure 13. UCC3882 demo kit efficiency.
Pentium® II is a registered trademark of Intel Corporation.
UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460
13
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