UCC3952DP-3G4_技术文档

U

C

3

S

9

i

5

n

2

g

-

l

1

e

,

Ć

U

C

L

3

i

9

5

i

2

u

-

m

2

,

Ć

U

n

C

B

3

a

9

5

e

2

r

-

y

3

,

U CC 39 52 -4

i

C

e

l

t

h

I

o

t

P

r

o

t

e

c

t

o

n

I

C

SLUS400D – AUGUST 2000

PW PACKAGE

(TOP VIEW)

D

Protects Sensitive Lithium-Ion Cells From

Overcharging and Over-Discharging

D

Dedicated for One-Cell Applications

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

TCLK

NC

PACK+

CBPS

NC

PACK–

D

Integrated Low-Impedance MOSFET Switch

and Sense Resistor

BNEG

D

Precision Trimmed Overcharge and

Overdischarge Voltage Limits

D

Extremely Low Power Drain

3-A Current Capacity

Overcurrent and Short-Circuit Protection

Reverse Charger Protection

Thermal Protection

description

DP PACKAGE

(TOP VIEW)

The UCC3952 monolithic BiCMOS lithium–ion

battery protection circuit increases the useful

operating life of a one-cell rechargeable battery

pack. Cell protection features include internally

trimmed charge and discharge voltage limits,

discharge current limit with a delayed shutdown,

and an ultra-low-current sleep mode state when

the cell is discharged. Additional features include

an on-chip MOSFET for reduced external compo-

nent count and a charge pump for reduced power

losses while charging or discharging a low-cell-

voltage battery pack. This protection circuit

requires one external capacitor and can operate

and safely shut down in a short circuit condition.

TCLK

NC

PACK+

CBPS

NC

1

2

3

4

5

6

7

8

16

15

14

NC

SUB

13 SUB

12

11

10

9

SUB

BNEG

PACK–

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

P

R

O

d

D

U

t

C

s

T

I

O

c

N

o

D

A

T

A

t

i

n

s

f

p

o

e

r

m

a

i

t

c

i

a

o

t

n

i

s

c

u

r

t

e

h

n

e

t

a

s

m

o

f

o

p

T

u

e

b

x

l

i

a

c

s

a

t

i

o

n

d ate.

Ins tr u men ts

r

o

u

c

n

f

o

r

m

o

c

i

f

i

o

n

p

e

r

t

e

r

s

f

s

t

a

s

n

d

g

a

r

d

w

a

r

a

n

t

y

.

P

r

o

d

u

p a r a m e t e r s .

c

t

i

o

n

p

r

o

c

e

s

i

n

g

d

o

e

s

n

o

t

n

e

c

e

s

a

r

i

l

y

i

n

c

l

u

d

e

t

e

t

i

n

o

f

l

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

U C C 3 9 5 2 - 1 , U C C 3 9 5 2 - 2 , U C C 3 9 5 2 - 3 , U C C 3 9 5 2 - 4

S in g le ĆC e ll L ith i u mĆI on Ba tte r y Pr o te c tio n IC

SLUS400D – AUGUST 2000

application diagram

+

PACK

1

2

3

4

5

6

7

8

TCLK

N/C

16

15

3 kΩ

+

CBPS

0.1µF

BNEG

NC 14

CHARGER

13

12

11

10

9

–

PACK

LOAD

–

PACK

BNEG

AVAILABLE OPTIONS

PACKAGES

T

A

TSSOP–16 (PW)

SOIC–16 (DP)

UCC3952PW–1

UCC3952PW–2

UCC3952PW–3

UCC3952PW–4

UCC3952DP–1

UCC3952DP–2

UCC3952DP–3

UCC3952DP–4

–20°C to 70 °C

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

U C C 3 9 5 2 - 1 , U C C 3 9 5 2 - 2 , U C C 3 9 5 2 - 3 , U C C 3 9 5 2 - 4

Si n gl e ĆCe ll L ith iu m ĆIo n Ba tte r y P r ot ect i on I C

SLUS400D – AUGUST 2000

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage (PACK+ to BNEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Maximum forward voltage (PACK+ to PACK–) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V

Maximum reverse voltage (where PACK+ to BNEG = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –8 V

Maximum cell continuous charge current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 A

Junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C

J

Storage Temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Data Book for thermal limitations and

considerations of packages. All voltages are referenced to GND.

electrical characteristics, T = –20°C to 70°C, all voltages are with respect to BNEG (unless

A

otherwise stated)

state transition threshold

PARAMETER

TEST CONDITIONS

MIN

4.15

4.20

4.25

4.30

3.85

3.90

3.95

4.00

2.25

2.55

10

TYP

4.20

4.25

4.30

4.35

3.90

3.95

4.00

4.05

2.35

2.65

25

MAX UNITS

4.25

UCC3952–1

UCC3952–2

UCC3952–3

UCC3952–4

UCC3952–1

UCC3952–2

UCC3952–3

UCC3952–4

4.30

V

(OV)

Normal to overcharge voltage

V

4.35

4.40

3.95

4.00

Overcharge to normal recovery

voltage

V

(OVR)

4.05

4.10

V

Normal to undercharge

2.45

2.75

40

V

(UV)

(UVR)

d(OD)

Undercharge to normal recovery

Overcharge delay time

t

ms

short circuit protection

PARAMETER

TEST CONDITIONS

PACK+ = 3.7 V

MIN

3.0

1

TYP

MAX UNITS

I

t

Discharge current limit

6.0

3.0

A

(THLD)

Discharge current delay

PACK+ = 3.7 V, I = 6 A

I

ms

MΩ

d(DLY)

R

Discharge current reset resistance

PACK+ = 3.7 V

7.5

(RESET)

bias

PARAMETER

Supply current

TEST CONDITIONS

MIN

TYP

5

MAX UNITS

I

V

< V

(OV)

8

24

µA

DD

(UV)

(PACK)

I

Operating supply current in overvoltage

Shutdown current

11

DD(OV)

(OV)

(PACK)

I

= 2.0 V

2.5

(SD)

(PACK)

Minimum cell voltage when all circuits are fully

functional

V

1.7

V

s

(min)

t (OV)

d

Overvoltage delay time

1

2

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

U C C 3 9 5 2 - 1 , U C C 3 9 5 2 - 2 , U C C 3 9 5 2 - 3 , U C C 3 9 5 2 - 4

S in g le ĆC e ll L ith i u mĆI on Ba tte r y Pr o te c tio n IC

SLUS400D – AUGUST 2000

electrical characteristics, T = –20°C to 70°C, all voltages are with respect to BNEG (unless

A

otherwise stated) (continued)

FET switch

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNITS

PACK+ > V

OV

(SWITCH)

Battery overcharged state switch permits discharge

,

I

= 1 mA to 2 A,

100

400

mV

current only.

V

Voltage at PACK–

(PACK–)

PACK+ = 2.5V,

I

= –1 mA to –2 A,

(SWITCH)

–600

–100

50

mV

Battery overdischarged state switch permits charge

current only.

PACK+ = 2.5 V,

In normal mode (when not in OV or UV). This value

includes package and bondwire resistance.

R

Series resistance of the device

75

mΩ

ON

thermal shutdown

PARAMETER

Thermal shutdown temperature (see Note 2)

TEST CONDITIONS

MIN

TYP

MAX UNITS

T

(SD)

135

°C

NOTE 2: This parameter is ensured by design and is not production tested.

detailed description

pin descriptions

BNEG

Connect the negative terminal of the battery to this pin.

PACK+

Connect to the positive terminal of the battery. This pin is available to the user.

CBPS

This power supply bypass pin is connected to PACK+ through an internal 3-kΩ resistor. An external 0.1-µF

capacitor must be connected between this pin and BNEG.

PACK–

The negative terminal of the battery pack (negative terminal available to the user). The internal FET switch

connects this terminal to the BNEG terminal to give the battery pack user appropriate access to the battery. In

an overcharged state, only discharge current is permitted. In an overdischarged state, only charge current is

permitted.

SUB (DP Package Only)

Do not connect. These pins must be electrically isolated from all other pins. The SUB pins may be soldered to

an isolated copper pad for heatsinking. However, most applications do not require heatsinking.

TCLK

Production test mode pin. This pin is used to provide a high-frequency clock to the IC during production testing.

In an application, this pin is left unconnected or tied to BNEG.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

U C C 3 9 5 2 - 1 , U C C 3 9 5 2 - 2 , U C C 3 9 5 2 - 3 , U C C 3 9 5 2 - 4

Si n gl e ĆCe ll L ith iu m ĆIo n Ba tte r y P r ot ect i on I C

SLUS400D – AUGUST 2000

APPLICATION INFORMATION

PACK+ 16

CBPS 15

3k

V

UV

V

UVR

4–1

MUX

T

DEL

OV

STATE

MACHINE

LOGIC

V

1SEC

OVR

THRESHOLD

COMPARATOR

TCLK

N/C

1

2

3

4

5

6

7

8

9

V

OV

1.5V

T

SEL

DEL

UV

10mS

CLK

BNEG

PACK–

SYSTEM

CLOCK

GENERATOR

TDLS

1mS

SETD

V

PUMP

50mV

2MΩ

RST

THERMAL

SHUTDOWN

PACK– 10

PACK– 11

PACK– 12

13

PACK–

NC 14

Figure 1. Detailed Block Diagram

battery voltage monitoring

The battery cell voltage is sampled every 8 ms by connecting a resistor divider across it and comparing the

resulting voltage to a precision internal reference voltage. Under normal conditions (cell voltage is below

overvoltage threshold and above undervoltage threshold), the UCC3952 consumes less than 10 µA of current

and the internal MOSFET is fully turned on with the aid of a charge pump.

When the cell voltage falls below the undervoltage threshold for two consecutive samples, the IC disconnects

the load from the battery pack and enters a super-low-power mode. The pack remains in this state until it detects

the application of a charger, at which point charging is enabled. The requirement of two consecutive readings

below the undervoltage threshold filters out momentary drops in cell voltage due to load transients, preventing

nuisance trips.

If the cell voltage exceeds the overvoltage threshold for 1 second, charging is disabled; however, discharge

current is still allowed. This feature of the IC is explained further in the controlled charge/discharge mode section

of this document.

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

U C C 3 9 5 2 - 1 , U C C 3 9 5 2 - 2 , U C C 3 9 5 2 - 3 , U C C 3 9 5 2 - 4

S in g le ĆC e ll L ith i u mĆI on Ba tte r y Pr o te c tio n IC

SLUS400D – AUGUST 2000

APPLICATION INFORMATION

overcurrent monitoring and protection

Discharge current is continuously monitored via an internal sense resistor. In the event of excessive current,

an overcurrent condition is declared if the high current (over 3 A) persists for over 1 ms. This delay allows for

charging of the system bypass capacitors without tripping the overcurrent protection. A 0.1-µF capacitor on the

CBPS pin provides momentary holdup for the IC to assure proper operation in the event that a hard short

suddenly pulls the cell voltage below the minimum operating voltage.

Once an overcurrent condition has been declared, the internal MOSFET turns off. To return the device to normal

operation, the UCC3952 requires a load impedance greater than 7.5 MΩ across PACK+ to PACK–. This

impedance is typically achieved by removing the battery pack from the system. At this point, the pack returns

to its normal state of operation.

controlled charge/discharge mode

When the chip senses an overvoltage condition, it prevents any additional charging, but allows discharge. This

is accomplished by activating a linear control loop, which controls the gate of the MOSFET based on the

differential voltage across its drain-to-source terminals. The linear loop attempts to regulate the differential

voltage across the MOSFET to 100 mV. When a light load is applied to the part, the loop adjusts the impedance

of the MOSFET to maintain 100 mV across it. As the load increases, the impedance of the MOSFET is

decreased to maintain the 100-mV control. At heavy loads (still below the overcurrent limit), the loop does not

maintain regulation and drives the gate of the MOSFET to the battery voltage (not the charge-pump output

voltage). The MOSFET R

in the overvoltage state is higher than RDS(on) during normal operation. The

DS(on)

voltage drop (and associated power loss) across the internal MOSFET in this mode of operation is still

significantly lower than the typical solution of two external back-to-back MOSFETs, where the body diode is

conducting.

When the chip senses an undervoltage condition, it disconnects the load from the battery pack and shuts itself

down to minimize current drain from the battery. Several circuits remain powered and detect placement of the

battery pack into a charger. Once the charger presence is detected, the linear loop is activated and the chip

allows charging current into the battery. This linear control mode of operation is in effect until the battery voltage

reaches a level of V

, at which time normal operation is resumed.

UVR

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

24-Feb-2006

PACKAGING INFORMATION

Orderable Device

UCC3952DP-1

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

D

16