UCC5350MCDWV [TI]

具有米勒钳位或分离输出以及 8V 或 12V UVLO 的 3kVrms、5A/5A 单通道隔离式栅极驱动器 | DWV | 8 | -40 to 125;


型号：	UCC5350MCDWV
厂家：	TEXAS INSTRUMENTS
描述：	具有米勒钳位或分离输出以及 8V 或 12V UVLO 的 3kVrms、5A/5A 单通道隔离式栅极驱动器 \| DWV \| 8 \| -40 to 125 栅极驱动驱动器
文件：	总60页 (文件大小：1975K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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UCC5310, UCC5320, UCC5350, UCC5390

ZHCSGC2F –JUNE 2017–REVISED JANUARY 2019

UCC53x0 单通道隔离式栅极驱动器

1 特性

3 说明

•

特性选项

UCC53x0 是一系列单通道隔离式栅极驱动器，用于驱

动 MOSFET、IGBT、SiC MOSFET 和 GaN FET

(UCC5350SBD)。UCC53x0S 提供分离输出，可分别

控制上升和下降时间。UCC53x0M 将晶体管的栅极连

接到内部钳位，以防止米勒电流造成假接通。

UCC53x0E 的 UVLO2 以 GND2 为基准，以获取真实

的 UVLO 读数。

–

分离输出 (UCC53x0S)

以 GND2 为基准的 UVLO (UCC53x0E)

米勒钳位选项 (UCC53x0M)

•

8 引脚 D（4mm 爬电）和

DWV（8.5mm 爬电）封装

•

60ns（典型值）传播延迟

100kV/μs 最低 CMTI

UCC53x0 采用 4mm SOIC-8 (D) 或 8.5mm SOIC-8

(DWV) 封装，可分别支持高达 3kV_RMS和 5kV_RMS的

隔离电压。凭借这些各种不同的选项，UCC53x0 系列

非常适合电机驱动器和工业电源。

隔离层寿命达 40 年以上

3V 至 15V 输入电源电压

高达 33V 的驱动器电源电压

–

8V 和 12V UVLO 选项

与光耦合器相比，UCC53x0 系列的部件间偏移更低，

传播延迟更小，工作温度更高，并且 CMTI 更高。

•

输入引脚具有负 5V 电压处理能力

安全相关认证：

–

7000V_PK隔离 DWV（计划）和 4242V_PK隔离

D（符合 DIN V VDE V 0884-11:2017-01 和

DIN EN 61010-1 标准）

器件信息⁽¹⁾

最低拉电流和灌

电流

可订购部件号

说明

–

5000V_RMSDWV 和 3000V_RMSD

隔离等级长达 1 分钟（符合 UL 1577 标准）

UCC5310MC

UCC5320SC

2.4A 和 1.1A

2.4A 和 2.2A

米勒钳位

分离输出

符合 GB4943.1-2011

D 和 DWV 标准的 CQC 认证（计划）

UVLO 以 IGBT 发射极为基

准

UCC5320EC

2.4A 和 2.2A

UCC5350MC

UCC5350SB

UCC5390SC

5A 和 5A

10A 和 10A

米勒钳位

•

CMOS 输入

具有 8V UVLO 的分离输出

分离输出

工作温度范围：–40°C 至 +125°C

UVLO 以 IGBT 发射极为基

准

2 应用

UCC5390EC

10A 和 10A

•

电机驱动器

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

高压直流到直流转换器

UPS 和 PSU

(2) 有关器件的详细比较，请参见

器件比较表

混合动力汽车 (HEV) 和电动车 (EV) 电源模块

光伏逆变器

功能框图（S、E 和 M 版本）

V_CC2

V_CC1

V_CC2

V_CC1

UVLO2

V_CC2

UVLO,

Level

Shift

UVLO,

Level

Shift

UVLO,

Level

Shift

UVLO

and

Input

Logic

UVLO

and

Input

Logic

UVLO

and

Input

Logic

IN+

INœ

IN+

V_OUTH

V_OUTL

V_OUT

and

text

and

text

Ctrl

Logic

Ctrl

Logic

Ctrl

Logic

CLAMP

INœ

GND2

V_EE2

GND1

V_EE2

GND1

S Version

M Version

E Version

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLLSER8

UCC5310, UCC5320, UCC5350, UCC5390

ZHCSGC2F –JUNE 2017–REVISED JANUARY 2019

www.ti.com.cn

Configuration............................................................ 22

10 Detailed Description ........................................... 25

10.1 Overview ............................................................... 25

10.2 Functional Block Diagram ..................................... 25

10.3 Feature Description............................................... 27

10.4 Device Functional Modes...................................... 31

11 Application and Implementation........................ 33

11.1 Application Information.......................................... 33

11.2 Typical Application ............................................... 33

12 Power Supply Recommendations ..................... 39

13 Layout................................................................... 40

13.1 Layout Guidelines ................................................. 40

13.2 Layout Example .................................................... 41

13.3 PCB Material......................................................... 43

14 器件和文档支持 ..................................................... 44

14.1 文档支持................................................................ 44

14.2 认证....................................................................... 44

14.3 相关链接................................................................ 44

14.4 接收文档更新通知 ................................................. 44

14.5 社区资源................................................................ 44

14.6 商标....................................................................... 44

14.7 静电放电警告......................................................... 44

14.8 术语表 ................................................................... 44

15 机械、封装和可订购信息....................................... 45

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

功能框图（S、E 和 M 版本）.................................. 1

修订历史记录 ........................................................... 3

Device Comparison Table..................................... 4

Pin Configuration and Function........................... 5

Specifications......................................................... 6

8.1 Absolute Maximum Ratings ...................................... 6

8.2 ESD Ratings.............................................................. 6

8.3 Recommended Operating Conditions....................... 6

8.4 Thermal Information.................................................. 7

8.5 Power Ratings........................................................... 7

8.6 Insulation Specifications for D Package.................... 8

8.7 Insulation Specifications for DWV Package.............. 9

8.8 Safety-Related Certifications For D Package ......... 10

8.9 Safety-Related Certifications For DWV Package.... 10

8.10 Safety Limiting Values .......................................... 10

8.11 Electrical Characteristics....................................... 11

8.12 Switching Characteristics...................................... 13

8.13 Insulation Characteristics Curves ......................... 14

8.14 Typical Characteristics.......................................... 15

Parameter Measurement Information ................ 22

9.1 Propagation Delay, Inverting, and Noninverting

UCC5310, UCC5320, UCC5350, UCC5390

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ZHCSGC2F –JUNE 2017–REVISED JANUARY 2019

5 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision E (October 2018) to Revision F

Page

•

已删除从第 2 个项目中删除了“(UCC5390EC)”。现在有三个已发行的宽体器件 ................................................................... 1

已添加在“安全相关认证”中添加了“DIN EN 61010-1”............................................................................................................. 1

已添加在整个“安全相关认证”项目中添加了“（计划）”........................................................................................................... 1

已更改在“说明”中使用开关类型信息更改了“引脚配置和驱动强度型号”................................................................................. 1

Changed creepage and clearance from 9 mm to 8.5 mm in Insulation Specifications and throughout datasheet................ 9

Added VDE and CQC certification for D package and UL file number for DWV package .................................................. 10

Changed test condition for V_OH............................................................................................................................................. 11

已更改 a minor detail to the UCC53x0M figures................................................................................................................... 29

已更改 typical application circuit for E Version to include capacitors on negative bias ...................................................... 34

Changes from Revision D (May 2018) to Revision E

Page

•

Changed UCC5310 DWV package from Preview to Final. .................................................................................................... 4

Changed UCC5320 DWV package from Preview to Final. .................................................................................................... 4

Changes from Revision C (February 2018) to Revision D

Page

•

已更改将 UCC5390EC 的销售状态从“预览”更改成了“生产”。............................................................................................... 1

Changes from Revision B (August 2017) to Revision C

Page

•

已添加将 UCC5350SBD、UCC5320SCDWV、UCC5310MCDWV 和 UCC5390ECDWV 器件添加至数据表 .................... 1

已更改特性、应用、说明和功能框图，以包括 E 和 M 版本，以及 DWV 封装信息。......................................................... 1

Added UCC5350SB to the pin configuration and function .................................................................................................... 5

Added Minimum Storage Temperature .................................................................................................................................. 6

Changed from VDE V 0884-10 to VDE V 0884-11 in insulation specification and safety-related certification table ............. 8

Changed Safety Limiting Values ......................................................................................................................................... 10

Deleted test conditions for Supply Currents......................................................................................................................... 11

已添加 Typical Curves and Test Conditions to include UCC5390 and UCC5350 information............................................. 15

已删除 Device I/O Figure ..................................................................................................................................................... 32

已更改 ESD Figure .............................................................................................................................................................. 32

已添加在认证部分添加 UL 在线认证目录 ............................................................................................................................ 44

Changes from Revision A (June 2017) to Revision B

Page

•

已更改最低环境工作温度为 –55°C 至 –40°C ........................................................................................................................ 1

Changes from Original (June 2017) to Revision A

Page

•

已删除从标题中删除了可用于未来 10A 器件的 17A 规格...................................................................................................... 1

UCC5310, UCC5320, UCC5350, UCC5390

ZHCSGC2F –JUNE 2017–REVISED JANUARY 2019

www.ti.com.cn

6 Device Comparison Table

MINIMUM

DEVICE

MINIMUM

SINK

CURRENT

PACKAGE

SOURCE

UVLO

ISOLATION RATING

OPTION⁽¹⁾

UCC5310MC

UCC5320EC

UCC5320SC

CONFIGURATION

CURRENT

3-kV_RMS

5-kV_RMS

2.4 A

1.1 A

2.2 A

Miller clamp

12 V

DWV

UVLO with reference

to GND2

3-kV_RMS

DWV

3-kV_RMS

5-kV_RMS

3-kV_RMS

5-kV_RMS

3-kV_RMS

Split output

UCC5350MC

UCC5350SB

5 A

Miller clamp

Split Output

12 V

8 V

UVLO with reference

to GND2

UCC5390EC

UCC5390SC

10 A

12 V

DWV

Split output

(1) The S, E, and M suffixes are part of the orderable part number. See the 机械、封装和可订购信息 section for the full orderable part

number.

UCC5310, UCC5320, UCC5350, UCC5390

www.ti.com.cn

ZHCSGC2F –JUNE 2017–REVISED JANUARY 2019

7 Pin Configuration and Function

UCC5320S, UCC5350SB, and UCC5390S

UCC5310M and UCC5350M

8-Pin SOIC

Top View

V_CC1

IN+

V_EE2

V_CC1

IN+

V_EE2

CLAMP

OUT

OUTL

OUTH

V_CC2

INœ

GND1

V_CC2

GND1

Not to scale

UCC5320E and UCC5390E

8-Pin SOIC

Top View

V_CC1

V_EE2

IN+

INœ

GND2

OUT

V_CC2

GND1

Not to scale

Pin Functions

NO.

TYPE

DESCRIPTION

NAME

UCC53x0S UCC53x0M UCC53x0E

Active Miller-clamp input found on the UCC53x0M used to prevent false

turnon of the power switches.

CLAMP

GND1

GND2

—

Input ground. All signals on the input side are referenced to this ground.

Gate-drive common pin. Connect this pin to the IGBT emitter. UVLO

referenced to GND2 in the UCC53x0E.

—

Noninverting gate-drive voltage-control input. The IN+ pin has a CMOS

input threshold. This pin is pulled low internally if left open. Use 表 4 to

understand the input and output logic of these devices.

IN+

IN–

Inverting gate-drive voltage control input. The IN– pin has a CMOS input

threshold. This pin is pulled high internally if left open. Use 表 4 to

understand the input and output logic of these devices.

OUT

—

Gate-drive output for UCC53x0E and UCC53x0M versions.

Gate-drive pullup output found on the UCC53x0S.

Gate-drive pulldown output found on the UCC53x0S.

OUTH

OUTL

—

Input supply voltage. Connect a locally decoupled capacitor to GND. Use a

low-ESR or ESL capacitor located as close to the device as possible.

V_CC1

V_CC2

Positive output supply rail. Connect a locally decoupled capacitor to V_EE2

Use a low-ESR or ESL capacitor located as close to the device as possible.

Negative output supply rail for E version, and GND for S and M versions.

Connect a locally decoupled capacitor to GND2 for E version. Use a low-

ESR or ESL capacitor located as close to the device as possible.

V_EE2

UCC5310, UCC5320, UCC5350, UCC5390

ZHCSGC2F –JUNE 2017–REVISED JANUARY 2019

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8 Specifications

8.1 Absolute Maximum Ratings

Over operating free air temperature range (unless otherwise noted)⁽¹⁾

MIN

GND1 – 0.3

–0.3

MAX

UNIT

Input bias pin supply voltage

Driver bias supply

V_CC1– GND1

V_CC2– V_EE2

V_EE2bipolar supply voltage for

E version

V_EE2– GND2

–17.5

0.3

Output signal voltage

Input signal voltage

V_OUTH– V_EE2, V_OUTL– V_EE2, V_OUT– V_EE2, V_CLAMP– V_EE2

V_IN+– GND1, V_IN–– GND1

V_EE2– 0.3

GND1 – 5

–40

V_CC2+ 0.3

V_CC1+ 0.3

150

(2)

Junction temperature, T_J

°C

Storage temperature, T_stg

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) To maintain the recommended operating conditions for T_J, see the Thermal Information.

8.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS–001⁽¹⁾

±4000

Electrostatic

discharge

V_(ESD)

Charged device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±1500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

V_CC1

V_CC2

V_EE2

V_SUP2

T_A

Supply voltage, input side

Positive supply voltage output side (V_CC2– V_EE2), UCC53x0

Positive supply voltage output side (V_CC2– V_EE2), UCC5350SBD

Bipolar supply voltage for E version (V_EE2– GND2), UCC53x0

Total supply voltage output side (V_CC2– V_EE2), UCC53x0

Ambient temperature

13.2

9.5

–16

13.2

–40

125

°C

UCC5310, UCC5320, UCC5350, UCC5390

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ZHCSGC2F –JUNE 2017–REVISED JANUARY 2019

8.4 Thermal Information

UCC53x0

THERMAL METRIC⁽¹⁾

D (SOIC)

8 PINS

109.5

43.1

DWV (SOIC)

8 PINS

119.8

64.1

UNIT

R_θJA

R_θJC(top)

R_θJB

Ψ_JT

Junction–to-ambient thermal resistance

Junction–to-case (top) thermal resistance

Junction–to-board thermal resistance

°C/W

51.2

65.4

Junction–to-top characterization parameter

Junction–to-board characterization parameter

18.3

37.6

Ψ_JB

50.7

63.7

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

8.5 Power Ratings

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

D Package

Maximum power dissipation on input and

output

P_D

1.14

V_CC1= 15 V, V_CC2= 15 V, f = 2.1-MHz,

50% duty cycle, square wave, 2.2-nF

load

P_D1

P_D2

Maximum input power dissipation

Maximum output power dissipation

0.05

1.09

DWV Package

Maximum power dissipation on input and

output

P_D

1.04

V_CC1= 15 V, V_CC2= 15 V, f = 1.9-MHz,

50% duty cycle, square wave, 2.2-nF

load

P_D1

P_D2

Maximum input power dissipation

Maximum output power dissipation

0.05

0.99

UCC5310, UCC5320, UCC5350, UCC5390

ZHCSGC2F –JUNE 2017–REVISED JANUARY 2019

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UNIT

8.6 Insulation Specifications for D Package

VALUE

PARAMETER

TEST CONDITIONS

CLR

CPG

External Clearance⁽¹⁾

External Creepage⁽¹⁾

Shortest pin–to-pin distance through air

≥ 4

Shortest pin–to-pin distance across the package

surface

≥ 4

DTI

CTI

Distance through the insulation

Comparative tracking index

Material Group

Minimum internal gap (internal clearance)

DIN EN 60112 (VDE 0303–11); IEC 60112

According to IEC 60664–1

> 21

> 600

µm

Rated mains voltage ≤ 150 _VRMS

Rated mains voltage ≤ 300 _VRMS

I-IV

I-III

Overvoltage category per IEC 60664-1

DIN V VDE 0884–11: 2017–01⁽²⁾

Maximum repetitive peak

isolation voltage

V_IORM

AC voltage (bipolar)

990

700

V_PK

V_RMS

V_PK

Maximum isolation working

voltage

AC voltage (sine wave); time dependent dielectric

breakdown (TDDB) test;

V_IOWM

Maximum transient isolation

voltage

V_TEST= V_IOTM, t = 60 s (qualification) ;

V_TEST= 1.2 × V_IOTM, t = 1 s (100% production)

V_IOTM

4242

Maximum surge isolation

Test method per IEC 62368-1, 1.2/50-µs waveform,

V_TEST= 1.3 × V_IOSM(qualification)

V_IOSM

V_PK

voltage⁽³⁾

Method a: After I/O safety test subgroup 2/3,

V_ini= V_IOTM, t_ini= 60 s

V_pd(m)= 1.2 × V_IORM, t_m= 10 s

≤ 5

Method a: After environmental tests subgroup 1,

V_ini= V_IOTM, t_ini= 60 s;

q_pd

Apparent charge⁽⁴⁾

V_pd(m)= 1.2 × V_IORM, t_m= 10 s

Method b1: At routine test (100% production) and

preconditioning (type test),

V_ini= 1.2 x V_IOTM, t_ini= 1 s;

≤ 5

V_pd(m)= 1.5 × V_IORM, t_m= 1 s

Barrier capacitance, input to

output⁽⁵⁾

C_IO

R_IO

V_IO= 0.4 × sin (2πft), f = 1 MHz

1.2

V_IO= 500 V, T_A= 25°C

> 10¹²

> 10¹¹

> 10⁹

Isolation resistance, input to

output⁽⁵⁾

V_IO= 500 V, 100°C ≤ T_A≤ 125°C

V_IO= 500 V at T_S= 150°C

Pollution degree

Climatic category

40/125/21

UL 1577

V_TEST= V_ISO, t = 60 s (qualification); V_TEST= 1.2 ×

V_ISO, t = 1 s (100% production)

V_ISO

Withstand isolation voltage

3000

V_RMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care

should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on

the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.

Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.

(2) This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall

be ensured by means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-pin device.

UCC5310, UCC5320, UCC5350, UCC5390

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ZHCSGC2F –JUNE 2017–REVISED JANUARY 2019

8.7 Insulation Specifications for DWV Package

VALUE

UNIT

PARAMETER

TEST CONDITIONS

DWV

CLR

CPG

External Clearance⁽¹⁾

External Creepage⁽¹⁾

Shortest pin–to-pin distance through air

≥ 8.5

Shortest pin–to-pin distance across the package

surface

≥ 8.5

DTI

CTI

Distance through the insulation

Comparative tracking index

Material Group

Minimum internal gap (internal clearance)

DIN EN 60112 (VDE 0303–11); IEC 60112

According to IEC 60664–1

> 21

> 600

µm

Rated mains voltage ≤ 600 _VRMS

Rated mains voltage ≤ 1000 _VRMS

I-III

I-II

Overvoltage category per IEC 60664-1

DIN V VDE 0884–11: 2017–01⁽²⁾

Maximum repetitive peak

isolation voltage

V_IORM

AC voltage (bipolar)

2121

V_PK

AC voltage (sine wave); time dependent dielectric

breakdown (TDDB) test

1500

2121

7000

V_RMS

V_DC

V_PK

Maximum isolation working

voltage

V_IOWM

DC Voltage

Maximum transient isolation

voltage

V_TEST= V_IOTM, t = 60 s (qualification) ;

V_TEST= 1.2 × V_IOTM, t = 1 s (100% production)

V_IOTM

Maximum surge isolation

Test method per IEC 62368-1, 1.2/50-µs waveform,

V_TEST= 1.6 × V_IOSM(qualification)

V_IOSM

8000

V_PK

voltage⁽³⁾

Method a: After I/O safety test subgroup 2/3,

V_ini= V_IOTM, t_ini= 60 s

≤ 5

V_pd(m)= 1.2 × V_IORM, t_m= 10 s

Method a: After environmental tests subgroup 1,

V_ini= V_IOTM, t_ini= 60 s;

V_pd(m)= 1.6 × V_IORM, t_m= 10 s

≤ 5

(4)

q_pd

Apparent charge

Method b1: At routine test (100% production) and

preconditioning (type test),

V_ini= 1.2 x V_IOTM, t_ini= 1 s;

≤ 5

V_pd(m)= 1.875 × V_IORM, t_m= 1 s

Barrier capacitance, input to

output⁽⁵⁾

C_IO

R_IO

V_IO= 0.4 × sin (2πft), f = 1 MHz

1.2

V_IO= 500 V, T_A= 25°C

> 10¹²

> 10¹¹

> 10⁹

Isolation resistance, input to

output⁽⁵⁾

V_IO= 500 V, 100°C ≤ T_A≤ 125°C

V_IO= 500 V at T_S= 150°C

Pollution degree

Climatic category

40/125/21

UL 1577

V_TEST= V_ISO, t = 60 s (qualification); V_TEST= 1.2 ×

V_ISO, t = 1 s (100% production)

V_ISO

Withstand isolation voltage

5000

V_RMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care

should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on

the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.

Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by

means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-pin device.

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8.8 Safety-Related Certifications For D Package

VDE

CQC

Certified according to DIN V VDE V 0884–11:2017–01

and DIN EN 61010-1 (VDE 0411-1):2011-07

Recognized under UL 1577

Component Recognition Program

Certified according to GB 4943.1–2011

Basic Insulation

Maximum Transient Isolation Overvoltage, 4242 V_PK

Basic Insulation,

Altitude ≤ 5000m,

Tropical Climate,

;

Single protection, 3000 V_RMS

File Number: E181974

Maximum Repetitive Peak Voltage, 990 V_PK

Maximum Surge Isolation Voltage, 4242 V_PK

;

700 V_RMSMaximum Working Voltage

Certificate Number: 40047657

Certification number: CQC18001199354

8.9 Safety-Related Certifications For DWV Package

VDE

CQC

Plan to certify according to DIN V VDE V

0884–11:2017–01 and DIN EN 61010-1

Recognized under UL 1577

Component Recognition Program

Plan to certify according to GB

4943.1–2011

Reinforced Insulation

Maximum Transient isolation Overvoltage, 7000 V_PK

Maximum Repetitive Peak Isolation Voltage, 2121 V_PK

Reinforced Insulation,

Altitude ≤ 5000 m,

Tropical Climate

;

Single protection, 5000 V_RMS

File Number: E181974

;

Maximum Surge Isolation Voltage, 8000 V_PK

Certification planned

8.10 Safety Limiting Values

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.

PARAMETER

D PACKAGE

TEST CONDITIONS

MIN

TYP

MAX UNIT

_θJA= 109.5°C/W, V_CC2= 15 V, T_J= 150°C, T_A= 25°C,

Output side

see 图 1

_θJA= 109.5°C/W, V_CC2= 30 V, T_J= 150°C, T_A= 25°C,

see 图 1

Safety output supply

current

I_S

Input side

Output side

Total

0.05

Safety output supply

power

P_S

T_S

R_θJA= 109.5°C/W, T_J= 150°C, T_A= 25°C, see 图 3

1.09

1.14

Maximum safety

temperature⁽¹⁾

150

°C

DWV PACKAGE

图 2

_θJA= 119.8°C/W, V_I= 15 V, T_J= 150°C, T_A= 25°C, see

Output side

Safety input, output,

or supply current

I_S

R_θJA= 119.8°C/W, V_I= 30 V, T_J= 150°C, T_A= 25°C, see

图 2

Input side

Output side

Total

0.05

0.99

1.04

Safety input, output,

or total power

P_S

T_S

R_θJA= 119.8°C/W, T_J= 150°C, T_A= 25°C, see 图 4

Maximum safety

temperature⁽¹⁾

150

°C

(1) The maximum safety temperature, T_S, has the same value as the maximum junction temperature, T_J, specified for the device. The I_S

and P_Sparameters represent the safety current and safety power respectively. The maximum limits of I_Sand P_Sshould not be

exceeded. These limits vary with the ambient temperature, T_A.

The junction-to-air thermal resistance, R_θJA, in the Thermal Information table is that of a device installed on a high-K test board for

leaded surface-mount packages. Use these equations to calculate the value for each parameter:

T_J= T_A+ R_θJA× P, where P is the power dissipated in the device.

T_J(max)= T_S= T_A+ R_θJA× P_S, where T_J(max)is the maximum allowed junction temperature.

P_S= I_S× V_I, where V_Iis the maximum input voltage.

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8.11 Electrical Characteristics

V_CC1= 3.3 V or 5 V, 0.1-µF capacitor from V_CC1to GND1, V_CC2= 15 V, 1-µF capacitor from V_CC2to V_EE2, C_L= 100-pF, T_A=

–40°C to +125°C, (unless otherwise noted)

PARAMETER

SUPPLY CURRENTS

TEST CONDITIONS

MIN

TYP

MAX UNIT

I_VCC1

Input supply quiescent current

1.67

1.1

2.4

1.8

Output supply quiescent

current

I_VCC2

SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS

VCC1 Positive-going UVLO

V_IT+(UVLO1)

2.6

2.5

0.1

2.8

threshold voltage

VCC1 Negative-going UVLO

V_{IT– (UVLO1)}

2.4

threshold voltage

VCC1 UVLO threshold

V_hys(UVLO1)

hysteresis

UCC5310MC, UCC5320SC,UCC5320EC,UCC5390SC,UCC5390EC, and UCC5350MC UVLO THRESHOLDS (12-V UVLO Version)

VCC2 Positive-going UVLO

threshold voltage

V_IT+(UVLO2)

V_IT–(UVLO2)

V_hys(UVLO2)

VCC2 Negative-going UVLO

threshold voltage

10.3

VCC2 UVLO threshold voltage

hysteresis

UCC5350SB UVLO THRESHOLD (8-V UVLO Version)

VCC2 Positive-going UVLO

V_IT+(UVLO2)

8.7

8.0

0.7

9.4

threshold voltage

VCC2 Negative-going UVLO

V_IT–(UVLO2)

7.3

threshold voltage

VCC2 UVLO threshold voltage

V_hys(UVLO2)

hysteresis

LOGIC I/O

Positive-going input threshold

voltage (IN+, IN–)

V_IT+(IN)

0.55 × V_CC10.7 × V_CC1

Negative-going input threshold

voltage (IN+, IN–)

V_IT–(IN)

0.3 × V_CC10.45 × V_CC1

Input hysteresis voltage (IN+,

IN–)

V_hys(IN)

I_IH

I_IL

0.1 × V_CC1

High-level input leakage at IN+ IN+ = V_CC1

240

µA

IN– = GND1

–240

–310

–40

–80

Low-level input leakage at IN–

µA

IN– = GND1 – 5 V

GATE DRIVER STAGE

High-level output voltage

V_OH

(VCC2 - OUT) and

(VCC2 - OUTH)

I_OUT= –20 mA

100

240

UCC5320SC and UCC5320EC,

IN+ = low, IN– = high; I_O= 20 mA

9.4

UCC5310MC,

IN+ = low, IN– = high; I_O= 20 mA

Low level output voltage (OUT

and OUTL)

V_OL

UCC5390SC and UCC5390EC,

IN+ = low, IN– = high; I_O= 20 mA

UCC5350MC and UCC5350SB,

IN+ = low, IN– = high; I_O= 20 mA

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Electrical Characteristics (continued)

V_CC1= 3.3 V or 5 V, 0.1-µF capacitor from V_CC1to GND1, V_CC2= 15 V, 1-µF capacitor from V_CC2to V_EE2, C_L= 100-pF, T_A=

–40°C to +125°C, (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

2.4

TYP

4.3

MAX UNIT

UCC5320SC and UCC5320EC,

IN+ = high, IN– = low

UCC5310MC, IN+ = high, IN– = low

UCC5390SC and UCC5390EC,

IN+ = high, IN– = low

I_OH

Peak source current

UCC5350MC,

IN+ = high, IN– = low

UCC5350SB

IN+ = high, IN– = low

8.5

UCC5320SC and UCC5320EC,

IN+ = low, IN– = high

2.2

1.1

4.4

2.2

UCC5310MC, IN+ = low, IN– = high

UCC5390SC and UCC5390EC,

IN+ = low, IN– = high

I_OL

Peak sink current

UCC5350MC,

IN+ = low, IN– = high

UCC5350SB

IN+ = low, IN– = high

ACTIVE MILLER CLAMP (UCC53xxM only)

UCC5310MC, I_CLAMP= 20 mA

V_CLAMP

Low-level clamp voltage

Clamp low-level current

UCC5350MC, I_CLAMP= 20 mA

UCC5310MC, V_CLAMP= V_EE2+ 15 V

UCC5350MC, V_CLAMP= V_EE2+ 15 V

UCC5310MC, V_CLAMP= V_EE2+ 2 V

UCC5350MC, V_CLAMP= V_EE2+ 2 V

UCC5310MC and UCC5350MC

1.1

2.2

1.5

2.1

I_CLAMP

0.7

Clamp low-level current for

low output voltage

I_CLAMP(L)

V_CLAMP-TH

Clamp threshold voltage

2.3

1.3

SHORT CIRCUIT CLAMPING

IN+ = high, IN– = low, t_CLAMP= 10 µs,

I_OUTHor I_OUT= 500 mA

Clamping voltage

V_CLP-OUT

1.5

0.9

(V_OUTH– V_CC2or V_OUT–V_CC2

)

IN+ = low, IN– = high, t_CLAMP= 10 µs,

I_CLAMPor I_OUTL= –500 mA

Clamping voltage

V_CLP-OUT

(V_EE2– V_OUTLor V_EE2

–

IN+ = low, IN– = high,

I_CLAMPor I_OUTL= –20 mA

V_CLAMPor V_EE2– V_OUT

)

ACTIVE PULLDOWN

Active pulldown voltage on

OUTL, CLAMP, OUT

I_OUTLor I_OUT= 0.1 × I_OUTL(typ), V_CC2

open

V_OUTSD

1.8

2.5

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8.12 Switching Characteristics

V_CC1= 3.3 V or 5 V, 0.1-µF capacitor from V_CC1to GND1, V_CC2= 15 V, 1-µF capacitor from V_CC2to V_EE2, T_A= –40°C to

+125°C, (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

UCC5320SC, UCC5320EC, and UCC5310MC,

C_LOAD= 1 nF

t_r

Output-signal rise time

UCC5390SC, UCC5350SB, UCC5390EC, and

UCC5350MC, C_LOAD= 1 nF

UCC5320SC and UCC5320EC, C_LOAD= 1 nF

UCC5310MC, C_LOAD= 1 nF

t_f

Output-signal fall time

UCC5390SC, UCC5350SB, UCC5390EC, and

UCC5350MC, C_LOAD= 1 nF

UCC5320SC and UCC5320EC, C_LOAD= 100

Propagation delay

(default versions), high

t_PLH

UCC5310MC, C_LOAD= 100 pF

UCC5390SC, UCC5350SB, UCC5390EC, and

UCC5350MC, C_LOAD= 100 pF

100

UCC5320CS and UCC5320EC, C_LOAD= 100

Propagation delay

(default versions), low

t_PHL

UCC5310MC, C_LOAD= 100 pF

UCC5390SC, UCC5350SB, UCC5390EC, and

UCC5350MC, C_LOAD= 100 pF

100

t_{UVLO1_rec}

t_{UVLO2_rec}

UVLO recovery delay of V_CC1

UVLO recovery delay of V_CC2

See 图 55

µs

UCC5320SC and UCC5320EC, C_LOAD= 100

UCC5310MC, C_LOAD= 100 pF

Pulse width distortion

t_PWD

|t_PHL– t_PLH

UCC5390SC, UCC5350SB, and UCC5390EC,

C_LOAD= 100 pF

UCC5350MC, C_LOAD= 100 pF

UCC5320SC and UCC5320EC, C_LOAD= 100

UCC5310MC, C_LOAD= 100 pF

t_sk(pp)

Part-to-part skew⁽¹⁾

UCC5390SC, UCC5350SB, and UCC5390EC,

C_LOAD= 100 pF

UCC5350MC, C_LOAD= 100 pF

Common-mode transient

immunity

CMTI

PWM is tied to GND or V_CC1, V_CM= 1200 V

100

120

kV/µs

(1) t_sk(pp)is the magnitude of the difference in propagation delay times between the output of different devices switching in the same

direction while operating at identical supply voltages, temperature, input signals and loads guaranteed by characterization.

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8.13 Insulation Characteristics Curves

VCC2=15V

VCC2=30V

VCC2=15V

VCC2=30V

100

150

200

100

150

200

Ambient Temperature (èC)

DT0h0e1r

图 1. Thermal Derating Curve for Limiting Current per VDE

图 2. Thermal Derating Curve for Limiting Current per VDE

for D Package

for DWV Package

1500

1200

900

600

300

1500

1200

900

600

300

100

150

200

100

150

200

Ambient Temperature (èC)

DT0h0e1r

Ambient Temperature (èC)

DT0h0e1r

图 3. Thermal Derating Curve for Limiting Power per VDE for

图 4. Thermal Derating Curve for Limiting Power per VDE for

D Package

DWV Package

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8.14 Typical Characteristics

V_CC1= 3.3 V or 5 V, 0.1-µF capacitor from V_CC1to GND1, V_CC2= 15 V, 1-µF capacitor from V_CC2to V_EE2, C_LOAD= 1 nF, T_A=

–40°C to +125°C, (unless otherwise noted)

7.6

7.2

6.8

6.4

UCC5320SC

UCC5310MC

UCC5320EC

UCC5390SC

UCC5350MC

UCC5390EC

5.6

5.2

4.8

4.4

VCC2 (V)

D010

D019

C_LOAD= 150 nF

图 5. Output-High Drive Current vs Output Voltage

图 6. Output-High Drive Current vs Output Voltage

8.5

IOH

IOL

UCC5320SC

UCC5310MC

UCC5320EC

7.5

6.5

5.5

4.5

3.5

VCC2 (V)

D011

D010

C_LOAD= 150 nF

图 8. Output-Low Drive Current vs Output Voltage

图 7. UCC5350SBD Output-High Drive Current vs Output

Voltage

1.24

1.22

1.2

UCC5390SC

UCC5350MC

UCC5320SC

UCC5320EC

UCC5310MC

UCC5390EC

1.18

1.16

1.14

1.12

1.1

1.08

-60 -40 -20

80 100 120 140

VCC2 (V)

Temperature (èC)

D020

D004

C_LOAD= 150 nF

图 9. Output-Low Drive Current vs Output Voltage

IN+ = L

IN– = H

图 10. I_CC1Supply Current vs Temperature

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Typical Characteristics (接下页)

V_CC1= 3.3 V or 5 V, 0.1-µF capacitor from V_CC1to GND1, V_CC2= 15 V, 1-µF capacitor from V_CC2to V_EE2, C_LOAD= 1 nF, T_A=

–40°C to +125°C, (unless otherwise noted)

2.3

2.275

2.25

1.26

1.24

1.22

1.2

UCC5320SC

UCC5320EC

UCC5310MC

UCC5390SC

UCC5390EC

UCC5350MC

UCC5350SB

2.225

2.2

1.18

1.16

1.14

1.12

1.1

2.175

2.15

2.125

2.1

2.075

2.05

1.08

1.06

-60 -40 -20

80 100 120 140

-60 -40 -20

80 100 120 140

Temperature (èC)

D005

D046

IN+ = L

IN– = H

D005_Icc1_vs_temperature_SLLSER8.grf

IN+ = H

IN– = L

图 11. I_CC1Supply Current vs Temperature

图 12. I_CC1Supply Current vs Temperature

1.685

1.68

2.34

2.31

2.28

2.25

2.22

2.19

2.16

2.13

2.1

UCC5390SC

UCC5390EC

UCC5350MC

UCC5350SB

1.675

1.67

UCC5320SC

UCC5320EC

UCC5310MC

1.665

1.66

1.655

1.65

1.645

1.64

2.07

2.04

2.01

1.98

1.635

1.63

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

-60 -40 -20

80 100 120 140

Frequency (MHz)

Temperature (èC)

D006

D047

IN+ = H

IN– = L

D006_Icc1_vs_frequency_SLLSER8.grf

Duty Cycle = 50%

T = 25°C

图 13. I_CC1Supply Current vs Temperature

图 14. I_CC1Supply Current vs Input Frequency

1.68

1.675

1.67

1.25

1.2

UCC5320SC

UCC5320EC

UCC5310MC

1.665

1.66

1.15

1.1

UCC5390SC

UCC5390EC

UCC5350MC

UCC5350SB

1.655

1.65

1.645

1.64

1.05

1.635

1.63

0.95

0.9

1.625

1.62

1.615

1.61

0.85

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

-60 -40 -20

80 100 120 140

Frequency (MHz)

Temperature (èC)

D048

D007

Duty Cycle = 50%

T = 25°C

IN+ = L

IN– = H

图 15. I_CC1Supply Current vs Input Frequency

图 16. I_CC2Supply Current vs Temperature

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Typical Characteristics (接下页)

V_CC1= 3.3 V or 5 V, 0.1-µF capacitor from V_CC1to GND1, V_CC2= 15 V, 1-µF capacitor from V_CC2to V_EE2, C_LOAD= 1 nF, T_A=

–40°C to +125°C, (unless otherwise noted)

1.4

1.35

1.3

1.45

UCC5390SC

UCC5390EC

UCC5350MC

UCC5350SB

UCC5320SC

UCC5320EC

UCC5310MC

1.4

1.35

1.3

1.25

1.2

1.25

1.2

1.15

1.1

1.15

1.1

1.05

0.95

0.9

-60 -40 -20

80 100 120 140

-60 -40 -20

80 100 120 140

Temperature (èC)

D049

D008

IN+ = L

IN– = H

IN+ = H

IN– = L

图 17. I_CC2Supply Current vs Temperature

图 18. I_CC2Supply Current vs Temperature

1.7

1.65

1.6

1.14

1.12

1.1

UCC5390SC

UCC5390EC

UCC5350MC

UCC5350SB

UCC5320SC

UCC5320EC

UCC5310MC

1.55

1.5

1.45

1.4

1.35

1.3

1.08

1.06

1.04

1.25

1.2

1.15

1.1

1.05

-60 -40 -20

80 100 120 140

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Temperature (èC)

Frequency (MHz)

D050

D009

IN+ = H

IN– = L

Duty Cycle = 50%

T = 25°C

图 19. I_CC2Supply Current vs Temperature

图 20. I_CC2Supply Current vs Input Frequency

1.68

1.675

1.67

1.375

1.35

1.325

1.3

UCC5320SC

UCC5310MC

UCC5320EC

1.665

1.66

1.275

1.25

1.225

1.2

1.655

1.65

UCC5390SC

1.645

1.64

UCC5390EC

UCC5350MC

UCC5350SB

1.635

1.63

1.175

1.15

1.125

1.1

1.625

1.62

1.615

1.61

1.075

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Frequncy (MHz)

LOAD (nF)

D051

D014

Duty Cycle = 50%

T = 25°C

f_SW= 1 kHz

图 22. I_CC2Supply Current vs Load Capacitance

图 21. I_CC2Supply Current vs Input Frequency

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Typical Characteristics (接下页)

V_CC1= 3.3 V or 5 V, 0.1-µF capacitor from V_CC1to GND1, V_CC2= 15 V, 1-µF capacitor from V_CC2to V_EE2, C_LOAD= 1 nF, T_A=

–40°C to +125°C, (unless otherwise noted)

1.425

UCC5390SC

UCC5390EC

UCC5350MC

0mA

5mA

10mA

15mA

20mA

1.4

1.375

1.35

1.325

1.3

1.275

1.25

1.225

1.2

-5

-10

1.175

1.15

-60

-30

120

150

180

LOAD (nF)

Temperature (èC)

D045

D025

f_SW= 1 kHz

I_Clamp= 0mA~20mA

图 24. UCC5310M V_Clampvs Temperature

图 23. I_CC2Supply Current vs Load Capacitance

22.5

4.5

0mA

5mA

10mA

15mA

20mA

UCC5350MC

UCC5310MC

17.5

3.5

12.5

7.5

2.5

1.5

-2.5

-5

0.5

-7.5

-10

-75

-45

-15

105

135

165

-60 -40 -20

80 100 120 140

Temperature (èC)

D022

D040

I_Clamp= 0mA~20mA

图 25. UCC5350M V_Clampvs Temperature

图 26. V_Clamp-THvs Temperature

9.75

9.5

10.5

UCC5350MC

UCC5390EC

UCC5390SC

9.25

9.5

UCC5310MC

UCC5320EC

UCC5320SC

8.75

8.5

8.25

7.5

7.75

7.5

7.25

6.5

-60 -40 -20

80 100 120 140

-60 -40 -20

80 100 120 140

Temperature (èC)

D027

D028

图 27. Rise Time vs Temperature

图 28. Rise Time vs Temperature

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Typical Characteristics (接下页)

V_CC1= 3.3 V or 5 V, 0.1-µF capacitor from V_CC1to GND1, V_CC2= 15 V, 1-µF capacitor from V_CC2to V_EE2, C_LOAD= 1 nF, T_A=

–40°C to +125°C, (unless otherwise noted)

9.5

11.5

UCC5310MC

UCC5320EC

UCC5320SC

UCC5350MC

UCC5390EC

UCC5390SC

10.5

8.5

9.5

8.5

7.5

-60 -40 -20

80 100 120 140

-60

-30

120

150

Temperature (èC)

D029

D030

图 29. Fall Time Vs Temperature

图 30. Fall Time vs Temperature

53.25

53.5

UCC5310MC

UCC5320EC

UCC5320SC

UCC5350MC

UCC5390EC

UCC5390SC

52.75

52.5

52.25

52.5

51.5

51.75

51.5

51.25

50.5

49.5

50.75

48.5

50.5

-60 -40 -20

80 100 120 140

-60 -40 -20

80 100 120 140

Temperature (èC)

D031

D032

图 31. Propagation Delay t_PLHvs Temperature

图 32. Propagation Delay t_PLHvs Temperature

53.5

TPLH INP

TPHL INP

TPLH INN

TPHL INN

UCC5310MC

UCC5320EC

UCC5320SC

52.5

51.5

50.5

49.5

-60 -40 -20

80 100 120 140

-60 -40 -20

80 100 120 140

Temperature (èC)

D033

D016

图 34. Propagation Delay t_PHLvs Temperature

图 33. UCC5350SBD Propagation Delay vs Temperature

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Typical Characteristics (接下页)

V_CC1= 3.3 V or 5 V, 0.1-µF capacitor from V_CC1to GND1, V_CC2= 15 V, 1-µF capacitor from V_CC2to V_EE2, C_LOAD= 1 nF, T_A=

–40°C to +125°C, (unless otherwise noted)

56.5

55.5

UCC5350MC

UCC5390EC

UCC5390SC

54.5

53.5

52.5

UCC5320SC

UCC5310MC

UCC5320EC

51.5

-60 -40 -20

80 100 120 140

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

LOAD (nF)

Temperature (èC)

D034

D012

f_SW= 1 kHz

R_GH= 0 Ω

R_GL= 0 Ω

图 35. Propagation Delay t_PHLvs Temperature

图 36. Rise Time vs Load Capacitance

UCC5390SC

UCC5390EC

UCC5350MC

1-nF

2.2-nF

5.6-nF

10-nF

Load Capacitance (nF)

VCC2 (V)

D039

D011

f_SW= 1 kHz

R_GH= 0 Ω

R_GL= 0 Ω

图 37. Rise Time vs Load Capacitance

图 38. UCC5350SBD Rise Time vs C_Land V_CC2

UCC5390SC

UCC5390EC

UCC5350MC

UCC5320SC

UCC5310MC

UCC5320EC

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

LOAD (nF)

Load Capacitance (nF)

D013

D038

f_SW= 1 kHz

R_GH= 0 Ω

R_GL= 0 Ω

f_SW= 1 kHz

R_GH= 0 Ω

R_GL= 0 Ω

图 39. Fall Time vs Load Capacitance

图 40. Fall Time vs Load Capacitance

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Typical Characteristics (接下页)

V_CC1= 3.3 V or 5 V, 0.1-µF capacitor from V_CC1to GND1, V_CC2= 15 V, 1-µF capacitor from V_CC2to V_EE2, C_LOAD= 1 nF, T_A=

–40°C to +125°C, (unless otherwise noted)

1-nF

2.2-nF

5.6-nF

10-nF

VCC2 (V)

D013

图 41. UCC5350SBD Fall Time vs C_Land V_CC2

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9 Parameter Measurement Information

9.1 Propagation Delay, Inverting, and Noninverting Configuration

图 42 shows the propagation delay OUTH and OUTL for noninverting configurations. 图 43 shows the

propagation delay with the inverting configuration. These figures also demonstrate the method used to measure

the rise (t_r) and fall (t_f) times.

0 V

INœ

50%

t_f

t_r

IN+

90%

50%

OUTH

OUTL

10%

t_PLH

t_PHL

图 42. OUTH and OUTL Propagation Delay, Noninverting Configuration

INœ

50%

VCC2

IN+

t_f

t_r

90%

50%

OUTH

10%

OUTL

t_PLH

t_PHL

图 43. OUTH and OUTL Propagation Delay, Inverting Configuration

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Propagation Delay, Inverting, and Noninverting Configuration (接下页)

9.1.1 CMTI Testing

图 44, 图 45, and 图 46 are simplified diagrams of the CMTI testing configuration used for each device type.

15 V

5 V

V_CC2

V_CC1

GND1

OUTH

PWM

IN+

OUTL

V_EE2

INœ

V_CM

图 44. CMTI Test Circuit for Split Output (UCC53x0S)

15 V

5 V

V_CC2

V_CC1

GND1

OUT

PWM

IN+

CLAMP

V_EE2

INœ

V_CM

图 45. CMTI Test Circuit for Miller Clamp (UCC53x0M)

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Propagation Delay, Inverting, and Noninverting Configuration (接下页)

15 V

5 V

V_CC2

V_CC1

GND1

OUT

PWM

IN+

GND2

V_EE2

INœ

V_CM

图 46. CMTI Test Circuit for UVLO2 with Respect to GND2 (UCC53x0E)

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10 Detailed Description

10.1 Overview

The UCC53x0 family of isolated gate drivers has three variations: split output, Miller clamp, and UVLO2

referenced to GND2 (see Device Comparison Table). The isolation inside the UCC53x0 family of devices is

implemented with high-voltage SiO₂-based capacitors. The signal across the isolation has an on-off keying

(OOK) modulation scheme to transmit the digital data across a silicon dioxide based isolation barrier (see 图 48).

The transmitter sends a high-frequency carrier across the barrier to represent one digital state and sends no

signal to represent the other digital state. The receiver demodulates the signal after advanced signal conditioning

and produces the output through a buffer stage. The UCC53x0 devices also incorporate advanced circuit

techniques to maximize the CMTI performance and minimize the radiated emissions from the high frequency

carrier and IO buffer switching. The conceptual block diagram of a digital capacitive isolator, 图 47, shows a

functional block diagram of a typical channel. 图 48 shows a conceptual detail of how the OOK scheme works.

图 47 shows how the input signal passes through the capacitive isolation barrier through modulation (OOK) and

signal conditioning.

10.2 Functional Block Diagram

Transmitter

Receiver

OOK

Modulation

TX IN

SiO based

RX OUT

TX Signal

Conditioning

RX Signal

Conditioning

Envelope

Detection

Capacitive

Isolation

Barrier

Emissions

Reduction

Oscillator

Techniques

图 47. Conceptual Block Diagram of a Capacitive Data Channel

TX IN

Carrier signal through

isolation barrier

RX OUT

图 48. On-Off Keying (OOK) Based Modulation Scheme

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Functional Block Diagram (接下页)

V_CC2

UVLO2

V_CC1

UVLO1

V_CC2

IN+

Level

Shifting

and

Control

Logic

OUTH

OUTL

INœ

GND1

V_EE2

图 49. Functional Block Diagram — Split Output (UCC53x0S)

V_CC2

UVLO2

V_CC1

UVLO1

V_CC2

IN+

Level

Shifting

and

Control

Logic

OUT

INœ

CLAMP

2 V

GND1

V_EE2

图 50. Functional Block Diagram — Miller Clamp (UCC53x0M)

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Functional Block Diagram (接下页)

V_CC2

UVLO2

V_CC1

UVLO1

V_CC2

IN+

Level

Shifting

and

Control

Logic

OUT

INœ

GND2

V_EE2

GND1

图 51. Functional Block Diagram — UVLO With Respect to GND2 (UCC53x0E)

10.3 Feature Description

10.3.1 Power Supply

The V_CC1input power supply supports a wide voltage range from 3 V to 15 V and the V_CC2output supply

supports a voltage range from 9.5 V to 33 V. For operation with bipolar supplies, the power device is turned off

with a negative voltage on the gate with respect to the emitter or source. This configuration prevents the power

device from unintentionally turning on because of current induced from the Miller effect. The typical values of the

V_CC2and V_EE2output supplies for bipolar operation are 15 V and –8 V with respect to GND2 for IGBTs and 20 V

and –5 V for SiC MOSFETs.

For operation with unipolar supply, the V_CC2supply is connected to 15 V with respect to VEE2 for IGBTs, and 20

V for SiC MOSFETs. The V_EE2supply is connected to 0 V. In this use case, the UCC53x0 device with Miller

clamping function (UCC53x0M) can be used. The Miller clamping function is implemented by adding a low

impedance path between the gate of the power device and the V_EE2supply. Miller current sinks through the

clamp pin, which clamps the gate voltage to be lower than the turnon threshold value for the gate.

10.3.2 Input Stage

The input pins (IN+ and IN–) of the UCC53x0 family are based on CMOS-compatible input-threshold logic that is

completely isolated from the V_CC2supply voltage. The input pins are easy to drive with logic-level control signals

(such as those from 3.3-V microcontrollers), because the UCC53x0 family has a typical high threshold (V_IT+(IN)) of

0.55 × V_CC1and a typical low threshold of 0.45 × V_CC1. A wide hysteresis (V_hys(IN)) of 0.1 × V_CC1makes for good

noise immunity and stable operation. If any of the inputs are left open, 128 kΩ of internal pulldown resistance

forces the IN+ pin low and 128 kΩ of internal resistance pulls IN– high. However, TI still recommends grounding

an input or tying to VCC1 if it is not being used for improved noise immunity.

Because the input side of the UCC53x0 family is isolated from the output driver, the input signal amplitude can

be larger or smaller than V_CC2provided that it does not exceed the recommended limit. This feature allows

greater flexibility when integrating the gate-driver with control signal sources and allows the user to choose the

most efficient V_CC2for any gate. However, the amplitude of any signal applied to IN+ or IN– must never be at a

voltage higher than V_CC1

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Feature Description (接下页)

10.3.3 Output Stage

The output stages of the UCC53x0 family feature a pullup structure that delivers the highest peak-source current

when it is most needed which is during the Miller plateau region of the power-switch turnon transition (when the

power-switch drain or collector voltage experiences dV/dt). The output stage pullup structure features a P-

channel MOSFET and an additional pullup N-channel MOSFET in parallel. The function of the N-channel

MOSFET is to provide a brief boost in the peak-sourcing current, which enables fast turn-on. Fast turn-on is

accomplished by briefly turning on the N-channel MOSFET during a narrow instant when the output is changing

states from low to high. 表 1 lists the typical internal resistance values of the pullup and pulldown structure.

表 1. UCC53x0 On-Resistance

DEVICE OPTION

UCC5320SC and UCC5320EC

UCC5310MC

R_NMOS

4.5

R_OH

R_OL

0.65

1.3

R_CLAMP

Not applicable

1.3

UNIT

4.5

UCC5390SC and UCC5390EC

UCC5350MC

0.76

1.54

0.13

0.26

Not applicable

0.26

UCC5350SB

Not applicable

The R_OHparameter is a DC measurement and is representative of the on-resistance of the P-channel device

only. This parameter is only for the P-channel device, because the pullup N-channel device is held in the OFF

state in DC condition and is turned on only for a brief instant when the output is changing states from low to high.

Therefore, the effective resistance of the UCC53x0 pullup stage during this brief turnon phase is much lower than

what is represented by the R_OHparameter, which yields a faster turnon. The turnon-phase output resistance is

the parallel combination R_OH|| R_NMOS

The pulldown structure in the UCC53x0 S and E versions is simply composed of an N-channel MOSFET. For the

M version, an additional FET is connected in parallel with the pulldown structure when the CLAMP and OUT pins

are connected to the gate of the IGBT or MOSFET. The output voltage swing between V_CC2and V_EE2provides

rail-to-rail operation.

UVLO2

V_CC2

R_OH

Level

Shifting

and

Control

Logic

R_NMOS

OUTH

OUTL

R_OL

V_EE2

图 52. Output Stage—S Version

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UVLO2

V_CC2

R_OH

Level

Shifting

and

R_NMOS

OUT

Control

Logic

R_OL

GND2

V_EE2

图 53. Output Stage—E Version

UVLO2

V_CC2

R_OH

Level

Shifting

and

R_NMOS

OUT

Control

Logic

R_OL

CLAMP

V_EE2

2 V

图 54. Output Stage—M Version

10.3.4 Protection Features

10.3.4.1 Undervoltage Lockout (UVLO)

UVLO functions are implemented for both the V_CC1and V_CC2supplies between the V_CC1and GND1, and V_CC2

and V_EE2pins to prevent an underdriven condition on IGBTs and MOSFETs. When V_CCis lower than V_{IT+ (UVLO)}

at device start-up or lower than V_IT–(UVLO)after start-up, the voltage-supply UVLO feature holds the effected

output low, regardless of the input pins (IN+ and IN–) as shown in 表 4. The V_CCUVLO protection has a

hysteresis feature (V_hys(UVLO)). This hysteresis prevents chatter when the power supply produces ground noise;

this allows the device to permit small drops in bias voltage, which occurs when the device starts switching and

operating current consumption increases suddenly. 图 55 shows the UVLO functions.

表 2. UCC53x0 V_CC1UVLO Logic

INPUTS

OUTPUTS

OUT, OUTL

CONDITION

IN+

IN–

OUTH

Hi-Z

V_CC1– GND1 < V_IT+(UVLO1)during device start-up

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表 2. UCC53x0 V_CC1UVLO Logic (接下页)

INPUTS

OUTPUTS

CONDITION

IN+

IN–

OUTH

Hi-Z

OUT, OUTL

V_CC1– GND1 < V_IT–(UVLO1)after device start-up

表 3. UCC53x0 V_CC2UVLO Logic

INPUTS

OUTPUTS

CONDITION

IN+

IN–

OUTH

Hi-Z

OUT, OUTL

V_CC2– V_EE2< V_IT+(UVLO2)during device start-up

V_CC2– V_EE2< V_IT–(UVLO2)after device start-up

When V_CC1or V_CC2drops below the UVLO1 or UVLO2 threshold, a delay, t_{UVLO1_rec}or t_{UVLO2_rec}, occurs on the

output when the supply voltage rises above V_IT+(UVLO)or V_IT+(UVLO2)again. 图 55 shows this delay.

IN+

V_{IT+ (UVLO1)}

V_{IT (UVLO1)}

V_CC1

V_CC2

V_{IT+ (UVLO2)}

V_IT

(UVLO2)

t_{UVLO2_rec}

t_{UVLO1_rec}

V_OUT

图 55. UVLO Functions

10.3.4.2 Active Pulldown

The active pulldown function is used to pull the IGBT or MOSFET gate to the low state when no power is

connected to the V_CC2supply. This feature prevents false IGBT and MOSFET turnon on the OUT, OUTL, and

CLAMP pins by clamping the output to approximately 2 V.

When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low by an

active clamp circuit that limits the voltage rise on the driver outputs. In this condition, the upper PMOS is

resistively held off by a pullup resistor while the lower NMOS gate is tied to the driver output through a 500-kΩ

resistor. In this configuration, the output is effectively clamped to the threshold voltage of the lower NMOS

device, which is approximately 1.5 V when no bias power is available.

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10.3.4.3 Short-Circuit Clamping

The short-circuit clamping function is used to clamp voltages at the driver output and pull the active Miller clamp

pins slightly higher than the V_CC2voltage during short-circuit conditions. The short-circuit clamping function helps

protect the IGBT or MOSFET gate from overvoltage breakdown or degradation. The short-circuit clamping

function is implemented by adding a diode connection between the dedicated pins and the V_CC2pin inside the

driver. The internal diodes can conduct up to 500-mA current for a duration of 10 µs and a continuous current of

20 mA. Use external Schottky diodes to improve current conduction capability as needed.

10.3.4.4 Active Miller Clamp (UCC53x0M)

The active Miller-clamp function is used to prevent false turn-on of the power switches caused by Miller current in

applications where a unipolar power supply is used. The active Miller-clamp function is implemented by adding a

low impedance path between the power-switch gate terminal and ground (V_EE2) to sink the Miller current. With

the Miller-clamp function, the power-switch gate voltage is clamped to less than 2 V during the off state. 图 58

shows a typical application circuit of UCC5310M and UCC5350M.

10.4 Device Functional Modes

表 4 lists the functional modes for the UCC53x0 devices assuming V_CC1and V_CC2are in the recommended

range.

表 4. Function Table for UCC53x0S

IN+

Low

IN–

OUTH

Hi-Z

OUTL

Low

High

Low

Hi-Z

Low

High

High-Z

表 5. Function Table for UCC53x0M and UCC53x0E

IN+

Low

IN–

OUT

Low

High

Low

High

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10.4.1 ESD Structure

图 56 shows the multiple diodes involved in the ESD protection components of the UCC53x0 devices . This

provides pictorial representation of the absolute maximum rating for the device.

V_CC1

V_CC2

IN+

OUTH

OUTL

18 V

35 V

INœ

5.5 V

GND1

V_EE2

图 56. ESD Structure

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11 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

11.1 Application Information

The UCC53x0 is a family of simple, isolated gate drivers for power semiconductor devices, such as MOSFETs,

IGBTs, or SiC MOSFETs. The family of devices is intended for use in applications such as motor control, solar

inverters, switched-mode power supplies, and industrial inverters.

The UCC53x0 family of devices has three pinout configurations, featuring split outputs, Miller clamp, and UVLO

with reference to GND2. The UCC5320SC, UCC5350SB, and UCC5390SC have a split output, OUTH and

OUTL. The two pins can be used to separately decouple the power transistor turnon and turnoff commutations.

The UCC5310MC and UCC5350MC feature active Miller clamping, which can be used to prevent false turn-on of

the power transistors induced by the Miller current. The UCC5320EC and UCC5390EC offer true UVLO

protection by monitoring the voltage between the V_CC2and GND2 pins to prevent the power transistors from

operating in a saturation region. The UCC53x0 family of devices comes in an 8-pin D and 8-pin DWV package

options and have a creepage, or clearance, of 4 mm and 8.5 mm respectively, which are suitable for applications

where basic or reinforced isolation is required. Different drive strengths enable a simple driver platform to be

used for applications demanding power transistors with different power ratings. Specifically, the UCC5390 device

offers a 10-A minimum drive current which can help remove the external current buffer used to drive high power

transistors.

11.2 Typical Application

The circuits in 图 57, 图 58, and 图 59 show a typical application for driving IGBTs.

15 V

V_CC2

5 V

V_CC1

GND1

R_GON

OUTH

OUTL

R_GOFF

Signal Emitter

Power Emitter

Rin

PWM

IN+

Cin

INœ

V_EE2

图 57. Typical Application Circuit for UCC53x0S to Drive IGBT

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Typical Application (接下页)

15 V

V_CC2

5 V

V_CC1

GND1

R_G

OUT

Rin

Signal Emitter

Power Emitter

PWM

CLAMP

IN+

Cin

INœ

V_EE2

图 58. Typical Application Circuit for UCC5310M and UCC5350M to Drive IGBT

15 V

V_CC2

5 V

V_CC1

GND1

R_G

OUT

Rin

Signal Emitter

Power Emitter

PWM

IN+

Cin

GND2

V_EE2

INœ

œ 8 V

图 59. Typical Application Circuit for UCC5320E and UCC5390E to Drive IGBT

11.2.1 Design Requirements

表 6 lists the recommended conditions to observe the input and output of the UCC5320S split-output gate driver

with the IN– pin tied to the GND1 pin.

表 6. UCC5320S Design Requirements

PARAMETER

VALUE

UNIT

V_CC1

3.3

V_CC2

3.3

IN+

IN–

GND1

Switching frequency

IGBT

kHz

IKW50N65H5

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11.2.2 Detailed Design Procedure

11.2.2.1 Designing IN+ and IN– Input Filter

TI recommends that users avoid shaping the signals to the gate driver in an attempt to slow down (or delay) the

signal at the output. However, a small input filter, R_IN-C_IN, can be used to filter out the ringing introduced by

nonideal layout or long PCB traces.

Such a filter should use an R_INresistor with a value from 0 Ω to 100 Ω and a C_INcapacitor with a value from 10

pF to 1000 pF. In the example, the selected value for R_INis 51 Ω and C_INis 33 pF, with a corner frequency of

approximately 100 MHz.

When selecting these components, pay attention to the trade-off between good noise immunity and propagation

delay.

11.2.2.2 Gate-Driver Output Resistor

The external gate-driver resistors, R_G(ON)and R_G(OFF)are used to:

1. Limit ringing caused by parasitic inductances and capacitances

2. Limit ringing caused by high voltage or high current switching dv/dt, di/dt, and body-diode reverse recovery

3. Fine-tune gate drive strength, specifically peak sink and source current to optimize the switching loss

4. Reduce electromagnetic interference (EMI)

The output stage has a pullup structure consisting of a P-channel MOSFET and an N-channel MOSFET in

parallel. The combined peak source current is 4.3 A for the UCC5320 family and 17 A for the UCC5390 family.

Use 公式 1 to estimate the peak source current using the UCC5320S as an example.

≈

’

V_CC2

I_OH= min∆4.3 A,

◊

∆

R_NMOS|| R_OH+ R_ON+ R_{GFET _Int}

where

•

R_ONis the external turnon resistance.

R_{GFET_Int}is the power transistor internal gate resistance, found in the power transistor data sheet. We will

assume 0Ω for our example

•

I_OHis the peak source current which is the minimum value between 4.3 A, the gate-driver peak source current,

and the calculated value based on the gate-drive loop resistance.

(1)

In this example, the peak source current is approximately 1.8 A as calculated in 公式 2.

V_CC2

R_NMOS||R_OH+ R_ON+ R_{GFET _Int}4.5 W ||12 W + 5.1W + 0 W

15 V

I_OH

ö 1.8 A

(2)

Similarly, use 公式 3 to calculate the peak sink current.

≈

’

V_CC2

I_OL= min∆4.4 A,

◊

∆

R_OL+ R_OFF+R_{GFET _Int}

where

•

R_OFFis the external turnoff resistance.

I_OLis the peak sink current which is the minimum value between 4.4 A, the gate-driver peak sink current, and

the calculated value based on the gate-drive loop resistance. (3)

In this example, the peak sink current is the minimum of 公式 4 and 4.4 A.

V_CC2

R_OL+ R_OFF+ R_{GFET _Int}0.65 W +10 W + 0 W

15 V

I_OL

ö 1.4 A

(4)

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注

The estimated peak current is also influenced by PCB layout and load capacitance.

Parasitic inductance in the gate-driver loop can slow down the peak gate-drive current and

introduce overshoot and undershoot. Therefore, TI strongly recommends that the gate-

driver loop should be minimized. Conversely, the peak source and sink current is

dominated by loop parasitics when the load capacitance (C_ISS) of the power transistor is

very small (typically less than 1 nF) because the rising and falling time is too small and

close to the parasitic ringing period.

11.2.2.3 Estimate Gate-Driver Power Loss

The total loss, P_G, in the gate-driver subsystem includes the power losses (P_GD) of the UCC53x0 device and the

power losses in the peripheral circuitry, such as the external gate-drive resistor.

The P_GDvalue is the key power loss which determines the thermal safety-related limits of the UCC53x0 device,

and it can be estimated by calculating losses from several components.

The first component is the static power loss, P_GDQ, which includes quiescent power loss on the driver as well as

driver self-power consumption when operating with a certain switching frequency. The P_GDQparameter is

measured on the bench with no load connected to the OUT or OUTH and OUTL pins at a given V_CC1, V_CC2

switching frequency, and ambient temperature. In this example, V_CC1is 3.3V and V_CC2is 15 V. The current on

each power supply, with PWM switching from 0 V to 3.3 V at 10 kHz, is measured to be I_CC1= 1.67 mA and I_CC2

= 1.11 mA. Therefore, use 公式 5 to calculate P_GDQ

P_GDQ= V_CC1ì I_VCC1+ V_CC2ì I_CC2ö22mW

(5)

The second component is the switching operation loss, P_GDO, with a given load capacitance which the driver

charges and discharges the load during each switching cycle. Use 公式 6 to calculate the total dynamic loss from

load switching, P_GSW

P_GSW= V_CC2ìQ_Gì f_SW

where

•

Q_Gis the gate charge of the power transistor at V_CC2

(6)

So, for this example application the total dynamic loss from load switching is approximately 18 mW as calculated

in 公式 7.

P_GSW= 15 V ì120 nC ì10 kHz = 18 mW

(7)

Q_Grepresents the total gate charge of the power transistor switching 520 V at 50 A, and is subject to change

with different testing conditions. The UCC5320S gate-driver loss on the output stage, P_GDO, is part of P_GSW. P_GDO

is equal to P_GSWif the external gate-driver resistance and power-transistor internal resistance are 0 Ω, and all the

gate driver-loss will be dissipated inside the UCC5320S. If an external turn-on and turn-off resistance exists, the

total loss is distributed between the gate driver pull-up/down resistance, external gate resistance, and power-

transistor internal resistance. Importantly, the pull-up/down resistance is a linear and fixed resistance if the

source/sink current is not saturated to 4.3 A/4.4 A, however, it will be non-linear if the source/sink current is

saturated. Therefore, P_GDOis different in these two scenarios.

Case 1 - Linear Pull-Up/Down Resistor:

≈

’

P_GSW

R_OH||R_NMOS

R_OL

P_GDO

∆

◊

R_OH||R_NMOS+R_ON+R_{GFET _Int}R_OL+R_OFF+R_{GFET _Int}

(8)

In this design example, all the predicted source and sink currents are less than 4.3 A and 4.4 A, therefore, use 公

式 9 to estimate the UCC53x0 gate-driver loss.

≈

∆

’

◊

18 mW

12 W || 4.5 W

12 W || 4.5 W + 5.1W + 0 W 0.65 W +10 W + 0 W

0.65 W

P_GDO

ö4.1mW

(9)

Case 2 - Nonlinear Pull-Up/Down Resistor:

UCC5310, UCC5320, UCC5350, UCC5390

www.ti.com.cn

ZHCSGC2F –JUNE 2017–REVISED JANUARY 2019

T_{R _ Sys}

T_{F_ Sys}

…

P_GDO=f_SWì 4.3 A ì

_CC2- V_OUTH(t) dt + 4.4 A ì

V_OUTL(t)dt

(

)

—

…

⁄

where

•

V_OUTH/L(t)is the gate-driver OUTH and OUTL pin voltage during the turnon and turnoff period. In cases where

the output is saturated for some time, this value can be simplified as a constant-current source (4.3 A at turnon

and 4.4 A at turnoff) charging or discharging a load capacitor. Then, the V_OUTH/L(t)waveform will be linear and

the T_{R_Sys}and T_{F_Sys}can be easily predicted.

(10)

For some scenarios, if only one of the pullup or pulldown circuits is saturated and another one is not, the P_GDOis

a combination of case 1 and case 2, and the equations can be easily identified for the pullup and pulldown based

on this discussion.

Use 公式 11 to calculate the total gate-driver loss dissipated in the UCC53x0 gate driver, P_GD

P_GD= P_GDQ+P_GDO= 22mW + 4.1mW = 26.1mW

(11)

11.2.2.4 Estimating Junction Temperature

Use 公式 12 to estimate the junction temperature (T_J) of the UCC53x0 family.

T_J= T_C+ Y_JTìP_GD

where

•

T_Cis the UCC53x0 case-top temperature measured with a thermocouple or some other instrument.

Ψ_JTis the junction-to-top characterization parameter from the Thermal Information table.

(12)

Using the junction-to-top characterization parameter (Ψ_JT) instead of the junction-to-case thermal resistance

(R_θJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal

energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the

total energy is released through the top of the case (where thermocouple measurements are usually conducted).

The R_θJCresistance can only be used effectively when most of the thermal energy is released through the case,

such as with metal packages or when a heat sink is applied to an IC package. In all other cases, use of R_θJCwill

inaccurately estimate the true junction temperature. The Ψ_JTparameter is experimentally derived by assuming

that the dominant energy leaving through the top of the IC will be similar in both the testing environment and the

application environment. As long as the recommended layout guidelines are observed, junction temperature

estimations can be made accurately to within a few degrees Celsius.

11.2.3 Selecting V_CC1and V_CC2Capacitors

Bypass capacitors for the V_CC1and V_CC2supplies are essential for achieving reliable performance. TI

recommends choosing low-ESR and low-ESL, surface-mount, multi-layer ceramic capacitors (MLCC) with

sufficient voltage ratings, temperature coefficients, and capacitance tolerances.

注

DC bias on some MLCCs will impact the actual capacitance value. For example, a 25-V,

1-μF X7R capacitor is measured to be only 500 nF when a DC bias of 15-V_DCis applied.

11.2.3.1 Selecting a V_CC1Capacitor

A bypass capacitor connected to the V_CC1pin supports the transient current required for the primary logic and the

total current consumption, which is only a few milliamperes. Therefore, a 50-V MLCC with over 100 nF is

recommended for this application. If the bias power-supply output is located a relatively long distance from the

V_CC1pin, a tantalum or electrolytic capacitor with a value greater than 1 μF should be placed in parallel with the

MLCC.

11.2.3.2 Selecting a V_CC2Capacitor

A 50-V, 10-μF MLCC and a 50-V, 0.22-μF MLCC are selected for the C_VCC2capacitor. If the bias power supply

output is located a relatively long distance from the V_CC2pin, a tantalum or electrolytic capacitor with a value

greater than 10 μF should be used in parallel with C_VCC2

UCC5310, UCC5320, UCC5350, UCC5390

ZHCSGC2F –JUNE 2017–REVISED JANUARY 2019

www.ti.com.cn

11.2.3.3 Application Circuits With Output Stage Negative Bias

When parasitic inductances are introduced by nonideal PCB layout and long package leads (such as TO-220

and TO-247 type packages), ringing in the gate-source drive voltage of the power transistor could occur during

high di/dt and dv/dt switching. If the ringing is over the threshold voltage, unintended turnon and shoot-through

could occur. Applying a negative bias on the gate drive is a popular way to keep such ringing below the

threshold. A few examples of implementing negative gate-drive bias follow.

图 60 shows the first example with negative bias turnoff on the output using a Zener diode on the isolated power-

supply output stage. The negative bias is set by the Zener diode voltage. If the isolated power supply is equal to

20 V, the turnoff voltage is –5.1 V and the turnon voltage is 20 V – 5.1 V ≈ 15 V.

20 V

V_CC2

V_CC1

C_A1

GND1

R_GON

OUTH

R_GOFF

Signal Emitter

OUTL

V_EE2

IN+

INœ

C_A2

图 60. Negative Bias With Zener Diode on Iso-Bias Power-Supply Output

图 61 shows another example which uses two supplies (or single-input, double-output power supply). The power

supply across V_CC2and GND2 determines the positive drive output voltage and the power supply across V_EE2

and GND2 determines the negative turnoff voltage. This solution requires more power supplies than the first

example, however, it provides more flexibility when setting the positive and negative rail voltages.

V_CC2

V_CC1

C_A1

GND1

R_G

OUT

Signal Emitter

GND2

IN+

C_A2

INœ

V_EE2

图 61. Negative Bias With Two Iso-Bias Power Supplies (UCC5320E and UCC5390E)

UCC5310, UCC5320, UCC5350, UCC5390

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ZHCSGC2F –JUNE 2017–REVISED JANUARY 2019

11.2.4 Application Curve

V_CC2= 20 V

V_EE2= GND f_SW= 10 kHz

图 62. PWM Input And Gate Voltage Waveform

12 Power Supply Recommendations

The recommended input supply voltage (V_CC1) for the UCC53x0 device is from 3 V to 15 V. The lower limit of the

range of output bias-supply voltage (V_CC2) is determined by the internal UVLO protection feature of the device.

The V_CC1and V_CC2voltages should not fall below their respective UVLO thresholds for normal operation, or else

the gate-driver outputs can become clamped low for more than 50 μs by the UVLO protection feature. For more

information on UVLO, see the Undervoltage Lockout (UVLO) section. The higher limit of the V_CC2range depends

on the maximum gate voltage of the power device that is driven by the UCC53x0 device, and should not exceed

the recommended maximum V_CC2of 33 V. A local bypass capacitor should be placed between the V_CC2and V_EE2

pins, with a value of 220-nF to 10-μF for device biasing. TI recommends placing an additional 100-nF capacitor in

parallel with the device biasing capacitor for high frequency filtering. Both capacitors should be positioned as

close to the device as possible. Low-ESR, ceramic surface-mount capacitors are recommended. Similarly, a

bypass capacitor should also be placed between the V_CC1and GND1 pins. Given the small amount of current

drawn by the logic circuitry within the input side of the UCC53x0 device, this bypass capacitor has a minimum

recommended value of 100 nF.

If only a single, primary-side power supply is available in an application, isolated power can be generated for the

secondary side with the help of a transformer driver such as Texas Instruments' SN6501 or SN6505A. For such

applications, detailed power supply design and transformer selection recommendations are available in SN6501

Transformer Driver for Isolated Power Supplies data sheet and SN6505A Low-Noise 1-A Transformer Drivers for

Isolated Power Supplies data sheet.

UCC5310, UCC5320, UCC5350, UCC5390

ZHCSGC2F –JUNE 2017–REVISED JANUARY 2019

www.ti.com.cn

13 Layout

13.1 Layout Guidelines

Designers must pay close attention to PCB layout to achieve optimum performance for the UCC53x0. Some key

guidelines are:

•

Component placement:

–

Low-ESR and low-ESL capacitors must be connected close to the device between the V_CC1and GND1

pins and between the V_CC2and V_EE2pins to bypass noise and to support high peak currents when turning

on the external power transistor.

–

To avoid large negative transients on the V_EE2pins connected to the switch node, the parasitic

inductances between the source of the top transistor and the source of the bottom transistor must be

minimized.

•

Grounding considerations:

–

Limiting the high peak currents that charge and discharge the transistor gates to a minimal physical area

is essential. This limitation decreases the loop inductance and minimizes noise on the gate terminals of

the transistors. The gate driver must be placed as close as possible to the transistors.

High-voltage considerations:

–

To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces

or copper below the driver device. A PCB cutout or groove is recommended in order to prevent

contamination that may compromise the isolation performance.

Thermal considerations:

–

A large amount of power may be dissipated by the UCC53x0 if the driving voltage is high, the load is

heavy, or the switching frequency is high (for more information, see the Estimate Gate-Driver Power Loss

section). Proper PCB layout can help dissipate heat from the device to the PCB and minimize junction-to-

board thermal impedance (θ_JB).

–

Increasing the PCB copper connecting to the V_CC2and V_EE2pins is recommended, with priority on

maximizing the connection to V_EE2. However, the previously mentioned high-voltage PCB considerations

must be maintained.

If the system has multiple layers, TI also recommends connecting the V_CC2and V_EE2pins to internal

ground or power planes through multiple vias of adequate size. These vias should be located close to the

IC pins to maximize thermal conductivity. However, keep in mind that no traces or coppers from different

high voltage planes are overlapping.

UCC5310, UCC5320, UCC5350, UCC5390

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ZHCSGC2F –JUNE 2017–REVISED JANUARY 2019

13.2 Layout Example

图 63 shows a PCB layout example with the signals and key components labeled.

(1) No PCB traces or copper are located between the primary and secondary side, which ensures isolation performance.

图 63. Layout Example

UCC5310, UCC5320, UCC5350, UCC5390

ZHCSGC2F –JUNE 2017–REVISED JANUARY 2019

www.ti.com.cn

Layout Example (接下页)

图 64 and 图 65 show the top and bottom layer traces and copper.

图 64. Top-Layer Traces and Copper

图 65. Bottom-Layer Traces and Copper (Flipped)

UCC5310, UCC5320, UCC5350, UCC5390

www.ti.com.cn

ZHCSGC2F –JUNE 2017–REVISED JANUARY 2019

Layout Example (接下页)

图 66 shows the 3D layout of the top view of the PCB.

(1) The location of the PCB cutout between primary side and secondary sides ensures isolation performance.

图 66. 3-D PCB View

13.3 PCB Material

Use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper alternatives because of

lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and the self-

extinguishing flammability-characteristics.

图 67 shows the recommended layer stack.

High-speed traces

10 mils

Ground plane

Keep this space

FR-4

free from planes,

40 mils

10 mils

0_r~ 4.5

traces, pads, and

vias

Power plane

Low-speed traces

图 67. Recommended Layer Stack

UCC5310, UCC5320, UCC5350, UCC5390

ZHCSGC2F –JUNE 2017–REVISED JANUARY 2019

www.ti.com.cn

14 器件和文档支持

14.1 文档支持

14.1.1 相关文档

请参阅如下相关文档：

•

德州仪器 (TI)，《数字隔离器设计指南》

德州仪器 (TI)，隔离相关术语

德州仪器 (TI)，《SN6501 用于隔离式电源的变压器驱动器》数据表

德州仪器 (TI)，《SN6505A 用于隔离式电源的低噪声 1A 变压器驱动器》数据表

德州仪器 (TI)，UCC53x0xD 评估模块用户指南

14.2 认证

UL 在线认证目录，“FPPT2.E181974 非光学隔离器件 - 组件”证书编号：20170718-E181974，

14.3 相关链接

下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。

表 7. 相关链接

器件

产品文件夹

请单击此处

立即订购

请单击此处

技术文档

请单击此处

工具与软件

请单击此处

支持和社区

请单击此处

UCC5310

UCC5320

UCC5350

UCC5390

14.4 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

14.5 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

14.6 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

14.7 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

14.8 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

UCC5310, UCC5320, UCC5350, UCC5390

www.ti.com.cn

ZHCSGC2F –JUNE 2017–REVISED JANUARY 2019

15 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

UCC5310, UCC5320, UCC5350, UCC5390

ZHCSGC2F –JUNE 2017–REVISED JANUARY 2019

www.ti.com.cn

PACKAGE OUTLINE

D0008B

SOIC - 1.75 mm max height

SCALE 2.800

SOIC

SEATING PLANE

.228-.244 TYP

[5.80-6.19]

.004 [0.1] C

PIN 1 ID AREA

6X .050

[1.27]

.189-.197

[4.81-5.00]

NOTE 3

.150

[3.81]

8X .012-.020

[0.31-0.51]

.150-.157

[3.81-3.98]

NOTE 4

.069 MAX

[1.75]

.010 [0.25]

C A

.005-.010 TYP

[0.13-0.25]

SEE DETAIL A

.010

[0.25]

.004-.010

[0.11-0.25]

0 - 8

.016-.050

[0.41-1.27]

DETAIL A

TYPICAL

.041

[1.04]

4221445/B 04/2014

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15], per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

www.ti.com

UCC5310, UCC5320, UCC5350, UCC5390

www.ti.com.cn

ZHCSGC2F –JUNE 2017–REVISED JANUARY 2019

EXAMPLE BOARD LAYOUT

D0008B

SOIC - 1.75 mm max height

SOIC

8X (.055)

[1.4]

8X (.061 )

[1.55]

SEE

DETAILS

SEE

DETAILS

SYMM

8X (.024)

[0.6]

8X (.024)

[0.6]

SYMM

6X (.050 )

[1.27]

6X (.050 )

[1.27]

(.213)

[5.4]

(.217)

[5.5]

HV / ISOLATION OPTION

.162 [4.1] CLEARANCE / CREEPAGE

IPC-7351 NOMINAL

.150 [3.85] CLEARANCE / CREEPAGE

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

.0028 MAX

[0.07]

ALL AROUND

.0028 MIN

[0.07]

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4221445/B 04/2014

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

UCC5310, UCC5320, UCC5350, UCC5390

ZHCSGC2F –JUNE 2017–REVISED JANUARY 2019

www.ti.com.cn

EXAMPLE STENCIL DESIGN

D0008B

SOIC - 1.75 mm max height

SOIC

8X (.061 )

[1.55]

8X (.055)

[1.4]

SYMM

8X (.024)

[0.6]

8X (.024)

[0.6]

SYMM

6X (.050 )

[1.27]

6X (.050 )

[1.27]

(.217)

[5.5]

(.213)

[5.4]

HV / ISOLATION OPTION

.162 [4.1] CLEARANCE / CREEPAGE

IPC-7351 NOMINAL

.150 [3.85] CLEARANCE / CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.127 MM] THICK STENCIL

SCALE:6X

4221445/B 04/2014

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

UCC5310MCD

UCC5310MCDR

UCC5310MCDWV

UCC5310MCDWVR

UCC5320ECD

ACTIVE

SOIC

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

5310M

2500 RoHS & Green

64 RoHS & Green

1000 RoHS & Green

75 RoHS & Green

2500 RoHS & Green

75 RoHS & Green

2500 RoHS & Green

64 RoHS & Green

1000 RoHS & Green

75 RoHS & Green

2500 RoHS & Green

64 RoHS & Green

1000 RoHS & Green

75 RoHS & Green

2500 RoHS & Green

75 RoHS & Green

2500 RoHS & Green

64 RoHS & Green

1000 RoHS & Green

NIPDAU

5310M

5310MC

5320E

DWV

UCC5320ECDR

UCC5320SCD

5320E

5320S

UCC5320SCDR

UCC5320SCDWV

UCC5320SCDWVR

UCC5350MCD

5320S

DWV

5320SC

5350M

5350MC

5350SB

53X0E

UCC5350MCDR

UCC5350MCDWV

UCC5350MCDWVR

UCC5350SBD

DWV

UCC5350SBDR

UCC5390ECD

UCC5390ECDR

UCC5390ECDWV

UCC5390ECDWVR

53X0E

DWV

5390EC

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

UCC5390SCD

ACTIVE

SOIC

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

53X0S

UCC5390SCDR

2500 RoHS & Green

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

UCC5310MCDR

UCC5310MCDWVR

UCC5320ECDR

UCC5320SCDR

UCC5320SCDWVR

UCC5350MCDR

UCC5350MCDWVR

UCC5350SBDR

UCC5390ECDR

UCC5390ECDWVR

UCC5390SCDR

SOIC

2500

1000

2500

1000

2500

1000

2500

1000

2500

330.0

12.4

16.4

12.4

16.4

12.4

16.4

12.4

16.4

12.4

6.4

5.2

2.1

3.3

2.1

3.3

2.1

3.3

2.1

3.3

2.1

8.0

12.0

16.0

12.0

16.0

12.0

16.0

12.0

16.0

12.0

DWV

12.05 6.15

16.0

8.0

6.4

5.2

8.0

DWV

12.05 6.15

16.0

8.0

6.4

5.2

8.0

DWV

12.05 6.15

16.0

8.0

6.4

5.2

8.0

DWV

12.05 6.15

6.4 5.2

16.0

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

UCC5310MCDR

UCC5310MCDWVR

UCC5320ECDR

UCC5320SCDR

UCC5320SCDWVR

UCC5350MCDR

UCC5350MCDWVR

UCC5350SBDR

UCC5390ECDR

UCC5390ECDWVR

UCC5390SCDR

SOIC

2500

1000

2500

1000

2500

1000

2500

1000

2500

356.0

350.0

356.0

350.0

356.0

350.0

356.0

350.0

35.0

43.0

35.0

43.0

DWV

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2023

TUBE

T - Tube

height

L - Tube length

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device

Package Name Package Type

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

UCC5310MCD

UCC5310MCDWV

UCC5320ECD

UCC5320SCD

UCC5320SCDWV

UCC5350MCD

UCC5350MCDWV

UCC5350SBD

UCC5390ECD

UCC5390ECDWV

UCC5390SCD

SOIC

506.6

505.46

506.6

3940

3810

4826

3810

4826

3810

3940

4826

3810

3940

3810

4826

3810

4.32

6.76

13.94

6.76

13.94

6.76

DWV

6.6

DWV

6.6

4.32

6.6

DWV

505.46

506.6

13.94

6.76

4.32

505.46

6.76

13.94

6.76

DWV

6.6

Pack Materials-Page 3

PACKAGE OUTLINE

DWV0008A

SOIC - 2.8 mm max height

SOIC

SEATING PLANE

11.5 0.25

TYP

PIN 1 ID

AREA

0.1 C

6X 1.27

5.95

5.75

NOTE 3

3.81

0.51

0.31

7.6

7.4

0.25

C A

2.8 MAX

NOTE 4

0.33

0.13

TYP

SEE DETAIL A

(2.286)

0.25

GAGE PLANE

0.46

0.36

0 -8

1.0

0.5

DETAIL A

TYPICAL

(2)

4218796/A 09/2013

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

www.ti.com

EXAMPLE BOARD LAYOUT

DWV0008A

SOIC - 2.8 mm max height

SOIC

8X (1.8)

SEE DETAILS

SYMM

8X (0.6)

6X (1.27)

(10.9)

LAND PATTERN EXAMPLE

9.1 mm NOMINAL CLEARANCE/CREEPAGE

SCALE:6X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4218796/A 09/2013

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DWV0008A

SOIC - 2.8 mm max height

SOIC

SYMM

8X (1.8)

8X (0.6)

SYMM

6X (1.27)

(10.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:6X

4218796/A 09/2013

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

D0008A

SOIC - 1.75 mm max height

SCALE 2.800

SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE

.228-.244 TYP

[5.80-6.19]

.004 [0.1] C

PIN 1 ID AREA

6X .050

[1.27]

.189-.197

[4.81-5.00]

NOTE 3

.150

[3.81]

4X (0 -15 )

8X .012-.020

[0.31-0.51]

.150-.157

[3.81-3.98]

NOTE 4

.069 MAX

[1.75]

.010 [0.25]

C A B

.005-.010 TYP

[0.13-0.25]

4X (0 -15 )

SEE DETAIL A

.010

[0.25]

.004-.010

[0.11-0.25]

0 - 8

.016-.050

[0.41-1.27]

DETAIL A

TYPICAL

(.041)

[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

SEE

DETAILS

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

6X (.050 )

[1.27]

(.213)

[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED

METAL

EXPOSED

METAL

.0028 MAX

[0.07]

.0028 MIN

[0.07]

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

6X (.050 )

[1.27]

(.213)

[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

UCC5350MCDWV [TI]

相关型号：

UCC5350MCDWVR

UCC5350MCQDQ1

UCC5350MCQDRQ1

UCC5350MCQDWVQ1

UCC5350MCQDWVRQ1

UCC5350SBD

UCC5350SBDR

UCC5350SBQDRQ1

UCC5390

UCC5390-Q1

UCC5390ECD

UCC5390ECDR