UCC5390ECQDWVRQ1 [TI]
适用于 IGBT/SiC MOSFET 且具有 UVLO(以 GND 为基准)的汽车类 5kVrms、17A 单通道隔离式栅极驱动器 | DWV | 8 | -40 to 125;型号: | UCC5390ECQDWVRQ1 |
厂家: | TEXAS INSTRUMENTS |
描述: | 适用于 IGBT/SiC MOSFET 且具有 UVLO(以 GND 为基准)的汽车类 5kVrms、17A 单通道隔离式栅极驱动器 | DWV | 8 | -40 to 125 栅极驱动 双极性晶体管 驱动器 |
文件: | 总37页 (文件大小:1346K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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UCC5390-Q1
ZHCSKG7A –OCTOBER 2019–REVISED NOVEMBER 2019
适用于 SiC/IGBT 和汽车应用的 UCC5390-Q1 单通道隔离式栅极驱动器
1 特性
•
工作结温范围:–40°C 至 +150°C
1
•
•
5kVRMS 单通道隔离式栅极驱动器
符合面向汽车应用的 AEC-Q100 标准
2 应用
•
•
•
车载充电器
–
–
–
温度等级 1
适用于电动汽车的牵引逆变器
直流充电站
HBM ESD 分类等级 H2
CDM ESD 分类等级 C6
•
•
•
•
•
•
•
•
•
•
以 GND2 为基准的 12V UVLO
8 引脚 DWV(8.5mm 爬电)封装
60ns(典型)传播延迟
较小的部件间传播延迟偏移
100V/ns 最小 CMTI
3 说明
UCC5390-Q1 是一款单通道隔离式栅极驱动器,具有
10A 峰值拉电流和 10A 峰值灌电流旨在驱动
MOSFET、IGBT 和 SiC MOSFET。UCC5390-Q1 的
UVLO2 以 GND2 为基准,从而有利于使用双极电源并
优化 SiC 和 IGBT 开关行为和稳健性。
10A 最小峰值电流
3V 至 15V 输入电源电压
驱动器电源电压高达 33V
输入引脚具有负 5V 电压处理能力
安全相关认证:
UCC5390-Q1 采用 8.5mm SOIC-8 (DWV) 封装,可支
持高达 5kVRMS 的隔离电压。输入侧通过 SiO2 电容隔
离技术与输出侧相隔离,隔离层寿命超过 40 年。凭借
高驱动强度和真正的 UVLO 检测,该器件非常适用于
在车载充电器和牵引逆变器等 应用 中驱动 IGBT 和
SiC MOSFET。
–
–
–
符合 DIN V VDE V 0884-11:2017-01 标准的
7000VPK 隔离 (DWV)(计划)
5000VRMS (DWV) 隔离等级长达 1 分钟(符合
UL 1577 标准)
与光耦合器相比,UCC5390-Q1 的部件间偏移更低,
传播延迟更小,工作温度更高,并且 CMTI 更高。
符合 GB4943.1-2011 的 CQC 认证
•
CMOS 输入
4 功能方框图
5 V
15V
VCC2
VCC1
UVLO2
VCC2
Rest of
Circuit
UVLO,
Level
Shift
UVLO
and
IN+
OUT
and
t
Control
Logic
Input
Logic
INœ
GND2
GND1
VEE2
-8V
1
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLUSDR3
UCC5390-Q1
ZHCSKG7A –OCTOBER 2019–REVISED NOVEMBER 2019
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
功能方框图............................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Function........................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 5
7.5 Power Ratings........................................................... 5
7.6 Insulation Specifications for DWV Package.............. 6
7.7 Safety-Related Certifications For DWV Package...... 6
7.8 Safety Limiting Values .............................................. 7
7.9 Electrical Characteristics........................................... 8
7.10 Switching Characteristics........................................ 9
7.11 Insulation Characteristics Curves ........................... 9
7.12 Typical Characteristics.......................................... 10
Parameter Measurement Information ................ 12
9
Detailed Description ............................................ 14
9.1 Overview ................................................................. 14
9.2 Functional Block Diagram ....................................... 14
9.3 Feature Description................................................. 15
9.4 Device Functional Modes........................................ 18
10 Application and Implementation........................ 20
10.1 Application Information.......................................... 20
10.2 Typical Application ............................................... 20
11 Power Supply Recommendations ..................... 24
12 Layout................................................................... 26
12.1 Layout Guidelines ................................................. 26
12.2 Layout Example .................................................... 27
12.3 PCB Material......................................................... 29
13 器件和文档支持 ..................................................... 30
13.1 文档支持................................................................ 30
13.2 认证....................................................................... 30
13.3 相关链接................................................................ 30
13.4 接收文档更新通知 ................................................. 30
13.5 社区资源................................................................ 30
13.6 商标....................................................................... 30
13.7 静电放电警告......................................................... 30
13.8 Glossary................................................................ 30
8
8.1 Propagation Delay, Inverting, and Noninverting
Configuration............................................................ 12
5 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
Changes from Original (June 2019) to Revision A
Page
•
已更改 将销售状态从“预告信息”更改为“生产数据”.................................................................................................................. 1
2
Copyright © 2019, Texas Instruments Incorporated
UCC5390-Q1
www.ti.com.cn
ZHCSKG7A –OCTOBER 2019–REVISED NOVEMBER 2019
6 Pin Configuration and Function
UCC5390-Q1
8-Pin SOIC
Top View
VCC1
IN+
1
2
3
4
8
7
6
5
VEE2
GND2
OUT
VCC2
INœ
GND1
Not to scale
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
GND1
4
G
G
Input ground. All signals on the input side are referenced to this ground.
Gate-drive common pin. Connect this pin to the IGBT emitter or MOSFET source. UVLO
referenced to GND2.
GND2
7
Noninverting gate-drive voltage-control input. The IN+ pin has a CMOS input threshold. This pin
is pulled low internally if left open. Use 表 4 to understand the input and output logic of these
devices.
IN+
2
I
I
Inverting gate-drive voltage control input. The IN– pin has a CMOS input threshold. This pin is
pulled high internally if left open. Use 表 4 to understand the input and output logic of these
devices.
IN–
3
OUT
VCC1
6
1
O
P
Gate-drive output.
Input supply voltage. Connect a locally decoupled capacitor to GND1. Use a low-ESR or ESL
capacitor located as close to the device as possible.
Positive output supply rail. Connect a locally decoupled capacitor to VEE2. Use a low-ESR or
ESL capacitor located as close to the device as possible.
VCC2
VEE2
5
8
P
P
Negative output supply rail. Connect a locally decoupled capacitor to GND2. Use a low-ESR or
ESL capacitor located as close to the device as possible.
(1) P = Power, G = Ground, I = Input, O = Output
Copyright © 2019, Texas Instruments Incorporated
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free air temperature range (unless otherwise noted)(1)
MIN
GND1 – 0.3
–0.3
MAX
18
UNIT
V
Input bias pin supply voltage
Driver bias supply
VCC1 – GND1
VCC2 – VEE2
35
V
VEE2 bipolar supply voltage
Output signal voltage
Input signal voltage
VEE2 – GND2
–17.5
0.3
V
VOUT – VEE2
VEE2 – 0.3
GND1 – 5
–40
VCC2 + 0.3
VCC1 + 0.3
150
V
VIN+ – GND1, VIN– – GND1
V
(2)
Junction temperature, TJ
°C
°C
Storage temperature, Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) To maintain the recommended operating conditions for TJ, see the Thermal Information.
7.2 ESD Ratings
VALUE
±4000
±1500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
Electrostatic
discharge
V(ESD)
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
3
NOM
MAX
15
UNIT
VCC1
VCC2
VEE2
VSUP2
TJ
Supply voltage, input side
V
V
Positive supply voltage output side (VCC2 – GND2)
Negative supply voltage output side (VEE2 – GND2)
13.2
–16
13.2
-40
33
0
V
Total supply voltage output side (VCC2 – VEE2
Junction Temperature
)
33
V
150
°C
4
Copyright © 2019, Texas Instruments Incorporated
UCC5390-Q1
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ZHCSKG7A –OCTOBER 2019–REVISED NOVEMBER 2019
7.4 Thermal Information
UCC5390-Q1
THERMAL METRIC(1)
DWV (SOIC)
8 PINS
119.8
64.1
UNIT
RθJA
RθJC(top)
RθJB
ΨJT
Junction–to-ambient thermal resistance
Junction–to-case (top) thermal resistance
Junction–to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
65.4
Junction–to-top characterization parameter
Junction–to-board characterization parameter
37.6
ΨJB
63.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DWV Package
Maximum power dissipation on input and
output
PD
1.04
W
VCC1 = 15 V, VCC2 = 15 V, f = 1.9-MHz,
50% duty cycle, square wave, 2.2-nF
load
PD1
PD2
Maximum input power dissipation
Maximum output power dissipation
0.05
0.99
W
W
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UNIT
7.6 Insulation Specifications for DWV Package
VALUE
DWV
PARAMETER
TEST CONDITIONS
CLR
CPG
External Clearance(1)
External Creepage(1)
Shortest pin–to-pin distance through air
≥ 8.5
mm
mm
Shortest pin–to-pin distance across the package
surface
≥ 8.5
DTI
CTI
Distance through the insulation
Comparative tracking index
Material Group
Minimum internal gap (internal clearance)
DIN EN 60112 (VDE 0303–11); IEC 60112
According to IEC 60664–1
> 21
> 600
I
µm
V
Rated mains voltage ≤ 600 VRMS
Rated mains voltage ≤ 1000 VRMS
I-III
I-II
Overvoltage category per IEC 60664-1
DIN V VDE 0884–11: 2017–01(2)
Maximum repetitive peak
isolation voltage
VIORM
AC voltage (bipolar)
2121
VPK
AC voltage (sine wave); time dependent dielectric
breakdown (TDDB) test
1500
2121
7000
VRMS
VDC
VPK
Maximum isolation working
voltage
VIOWM
DC Voltage
Maximum transient isolation
voltage
VTEST = VIOTM, t = 60 s (qualification) ;
VTEST = 1.2 × VIOTM, t = 1 s (100% production)
VIOTM
Maximum surge isolation
Test method per IEC 62368-1, 1.2/50-µs waveform,
VTEST = 1.6 × VIOSM (qualification)
VIOSM
8000
VPK
voltage(3)
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s
≤ 5
Vpd(m) = 1.2 × VIORM, tm = 10 s
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM, tm = 10 s
≤ 5
(4)
qpd
Apparent charge
pC
Method b1: At routine test (100% production) and
preconditioning (type test),
Vini = 1.2 x VIOTM, tini = 1 s;
≤ 5
Vpd(m) = 1.875 × VIORM, tm = 1 s
Barrier capacitance, input to
output(5)
CIO
RIO
VIO = 0.4 × sin (2πft), f = 1 MHz
1.2
pF
VIO = 500 V, TA = 25°C
> 1012
> 1011
> 109
Isolation resistance, input to
output(5)
VIO = 500 V, 100°C ≤ TA ≤ 125°C
VIO = 500 V at TS = 150°C
Ω
Pollution degree
Climatic category
2
40/125/21
UL 1577
VTEST = VISO, t = 60 s (qualification); VTEST = 1.2 ×
VISO, t = 1 s (100% production)
VISO
Withstand isolation voltage
5000
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.
7.7 Safety-Related Certifications For DWV Package
VDE
UL
CQC
Plan to certify according to DIN V VDE V
0884–11:2017–01 and DIN EN 61010-1
Recognized under UL 1577
Component Recognition Program
Certified according to GB 4943.1–2011
6
Copyright © 2019, Texas Instruments Incorporated
UCC5390-Q1
www.ti.com.cn
ZHCSKG7A –OCTOBER 2019–REVISED NOVEMBER 2019
Safety-Related Certifications For DWV Package (continued)
VDE
UL
CQC
Reinforced Insulation
Maximum Transient Isolation Overvoltage, 7000 VPK
Maximum Repetitive Peak Isolation Voltage, 2121 VPK
Reinforced Insulation,
Altitude ≤ 5000 m,
Tropical Climate
;
Single protection, 5000 VRMS
File Number: E181974
;
Maximum Surge Isolation Voltage, 8000 VPK
Certification planned
Certification Number: CQC19001226950
7.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
DWV PACKAGE
TEST CONDITIONS
MIN
TYP
MAX UNIT
R
图 1
θJA = 119.8°C/W, VI = 15 V, TJ = 150°C, TA = 25°C, see
Output side
Output side
66
Safety input, output,
or supply current
IS
mA
33
RθJA = 119.8°C/W, VI = 30 V, TJ = 150°C, TA = 25°C, see
图 1
Input side
Output side
Total
0.05
Safety input, output,
or total power
PS
TS
RθJA = 119.8°C/W, TJ = 150°C, TA = 25°C, see 图 2
0.99
1.04
W
Maximum safety
temperature(1)
150
°C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the table is that of a device installed on a high-K test board for leaded surface-mount
packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
Copyright © 2019, Texas Instruments Incorporated
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7.9 Electrical Characteristics
VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, CL = 100-pF, TJ =
–40°C to +125°C, (unless otherwise noted)
PARAMETER
SUPPLY CURRENTS
TEST CONDITIONS
MIN
TYP
MAX UNIT
IVCC1
Input supply quiescent current
1.67
1.1
2.4
1.8
mA
mA
Output supply quiescent
current
IVCC2
SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VCC1 Positive-going UVLO
VIT+(UVLO1)
2.6
2.5
0.1
2.8
V
V
V
threshold voltage
VCC1 Negative-going UVLO
VIT– (UVLO1)
2.4
threshold voltage
VCC1 UVLO threshold
Vhys(UVLO1)
hysteresis
OUTPUT SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VCC2 Positive-going UVLO
VIT+(UVLO2)
12
11
1
13
V
V
V
threshold voltage
VCC2 Negative-going UVLO
VIT–(UVLO2)
10.3
threshold voltage
VCC2 UVLO threshold voltage
Vhys(UVLO2)
hysteresis
LOGIC I/O
Positive-going input threshold
voltage (IN+, IN–)
VIT+(IN)
0.55 × VCC1 0.7 × VCC1
V
V
Negative-going input threshold
voltage (IN+, IN–)
VIT–(IN)
0.3 × VCC1 0.45 × VCC1
Input hysteresis voltage (IN+,
IN–)
Vhys(IN)
IIH
IIL
0.1 × VCC1
40
V
High-level input leakage at IN+ IN+ = VCC1
240
µA
IN– = GND1
–240
–310
–40
–80
Low-level input leakage at IN–
µA
IN– = GND1 – 5 V
GATE DRIVER STAGE
High-level output voltage
(OUT)
VOH
VOL
IOUT = –20 mA
VCC2 – 0.1 VCC2 – 0.24
V
Low level output voltage
(OUT)
IN+ = low, IN– = high; IO = 20 mA
2
3
mV
IOH
IOL
Peak source current
Peak sink current
IN+ = high, IN– = low
IN+ = low, IN– = high
10
10
17
17
A
A
SHORT CIRCUIT CLAMPING
IN+ = high, IN– = low, tCLAMP = 10 µs,
IOUT= 500 mA
Clamping voltage
VCLP-OUT
1
1.5
0.9
1.3
V
V
(VOUT –VCC2
)
IN+ = low, IN– = high, tCLAMP = 10 µs,
IOUT = –500 mA
Clamping voltage
( VEE2 – VOUT
VCLP-OUT
)
IN+ = low, IN– = high,
IOUT = –20 mA
1
ACTIVE PULLDOWN
Active pulldown voltage on
OUT
VOUTSD
IOUT = 0.1 × IOUT(typ), VCC2 = open
1.8
2.5
V
8
Copyright © 2019, Texas Instruments Incorporated
UCC5390-Q1
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ZHCSKG7A –OCTOBER 2019–REVISED NOVEMBER 2019
7.10 Switching Characteristics
VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, TJ = –40°C to
+125°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
10
MAX UNIT
tr
Output-signal rise time
Output-signal fall time
Propagation delay, high
Propagation delay, low
UVLO recovery delay of VCC1
UVLO recovery delay of VCC2
Pulse width distortion
CLOAD = 1 nF
CLOAD = 1 nF
26
22
ns
ns
ns
ns
µs
µs
tf
10
tPLH
CLOAD = 100 pF
CLOAD = 100 pF
65
100
100
tPHL
65
tUVLO1_rec
tUVLO2_rec
30
50
tPWD
CLOAD = 100 pF
1
1
20
25
ns
ns
|tPHL – tPLH
|
tsk(pp)
CMTI
Part-to-part skew(1)
CLOAD = 100 pF
Common-mode transient
immunity
PWM is tied to GND or VCC1, VCM = 1200 V
100
120
kV/µs
(1) tsk(pp) is the magnitude of the difference in propagation delay times between the output of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads guaranteed by characterization.
7.11 Insulation Characteristics Curves
80
60
40
20
0
1500
1200
900
600
300
0
VCC2=15V
VCC2=30V
0
50
100
Ambient Temperature (èC)
150
200
0
50
100
Ambient Temperature (èC)
150
200
图 1. Thermal Derating Curve for Limiting Current per VDE
图 2. Thermal Derating Curve for Limiting Power per VDE for
for DWV Package
DWV Package
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7.12 Typical Characteristics
VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, CLOAD = 1 nF, TJ =
–40°C to +125°C, (unless otherwise noted)
25
22
19
16
13
10
24
21
18
15
12
14
17
20
23
VCC2 (V)
26
29
32
34
14
17
20
23
VCC2 (V)
26
29
32
34
CLOAD = 150 nF
CLOAD = 150 nF
图 3. Output-High Drive Current vs Output Voltage
2.7
图 4. Output-Low Drive Current vs Output Voltage
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
2.4
2.1
1.8
1.5
1.2
0.9
0.6
-60 -40 -20
0
20
40
60
80 100 120 140
-60 -40 -20
0
20
40
60
80 100 120 140
Temperature (èC)
Temperature (èC)
IN+ = L
IN– = H
IN+ = H
IN– = L
图 5. ICC1 Supply Current vs Temperature
1.82
图 6. ICC1 Supply Current vs Temperature
3
1.79
1.76
1.73
1.7
2.6
2.2
1.8
1.4
1
1.67
1.64
1.61
0.6
0.1
0.2
0.3
0.4
0.5
Frequency (MHz)
0.6
0.7
0.8
0.9
1
-60 -40 -20
0
20
40
60
80 100 120 140
Temperature (èC)
Duty Cycle = 50%
T = 25°C
IN+ = L
IN– = H
图 7. ICC1 Supply Current vs Input Frequency
图 8. ICC2 Supply Current vs Temperature
3
2.6
2.2
1.8
1.4
1
1.68
1.56
1.44
1.32
1.2
0.6
-60 -40 -20
0
20
40
60
80 100 120 140
0.1
0.2
0.3
0.4
0.5
Frequency (MHz)
0.6
0.7
0.8
0.9
1
Temperature (èC)
IN+ = H
图 9. ICC2 Supply Current vs Temperature
IN– = L
Duty Cycle = 50%
T = 25°C
图 10. ICC2 Supply Current vs Input Frequency
10
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Typical Characteristics (接下页)
VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, CLOAD = 1 nF, TJ =
–40°C to +125°C, (unless otherwise noted)
2.26
2.08
1.9
12.5
11.5
10.5
9.5
1.72
1.54
1.36
1.18
1
8.5
7.5
6.5
0
2
4
Load Capacitance (nF)
6
8
10
-60 -40 -20
0
20
40
60
80 100 120 140
Temperature (èC)
fSW = 1 kHz
图 11. ICC2 Supply Current vs Load Capacitance
11.5
图 12. Rise Time vs Temperature
65
61
57
53
49
45
10.5
9.5
8.5
7.5
6.5
-60 -40 -20
0
20
40
60
80 100 120 140
-60 -40 -20
0
20
40
60
80 100 120 140
Temperature (èC)
Temperature (èC)
图 14. Propagation Delay tPLH vs Temperature
图 13. Fall Time vs Temperature
56
54.5
53
28
24
20
16
12
8
51.5
50
4
-60 -40 -20
0
20
40
60
80 100 120 140
0
2
4
Load Capacitance (nF)
6
8
10
Temperature (èC)
fSW = 1 kHz
RGH = 0 Ω
RGL = 0 Ω
图 15. Propagation Delay tPHL vs Temperature
图 16. Rise Time vs Load Capacitance
40
36
32
28
24
20
16
12
8
4
0
2
4 6
Load Capacitance (nF)
8
10
fSW = 1 kHz
RGH = 0 Ω
RGL = 0 Ω
图 17. Fall Time vs Load Capacitance
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8 Parameter Measurement Information
8.1 Propagation Delay, Inverting, and Noninverting Configuration
图 18 shows the propagation delay for noninverting configurations. 图 19 shows the propagation delay with the
inverting configuration. These figures also demonstrate the method used to measure the rise (tr) and fall (tf)
times.
0 V
INœ
50%
tf
tr
IN+
90%
50%
10%
OUT
tPLH
tPHL
图 18. Propagation Delay, Noninverting Configuration
INœ
50%
IN+
tf
tr
90%
50%
OUT
10%
tPLH
tPHL
图 19. Propagation Delay, Inverting Configuration
12
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Propagation Delay, Inverting, and Noninverting Configuration (接下页)
8.1.1 CMTI Testing
图 20 is a simplified diagram of the CMTI testing configuration.
15 V
5 V
VCC2
VCC1
C3
C4
C1
C2
GND1
OUT
PWM
IN+
GND2
VEE2
INœ
+
œ
VCM
图 20. CMTI Test Circuit for UCC5390-Q1
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9 Detailed Description
9.1 Overview
The isolation inside the UCC5390-Q1 is implemented with high-voltage SiO2-based capacitors. The signal across
the isolation has an on-off keying (OOK) modulation scheme to transmit the digital data across a silicon dioxide
based isolation barrier (see 图 22). The transmitter sends a high-frequency carrier across the barrier to represent
one digital state and sends no signal to represent the other digital state. The receiver demodulates the signal
after advanced signal conditioning and produces the output through a buffer stage. The UCC5390-Q1 also
incorporates advanced circuit techniques to maximize the CMTI performance and minimize the radiated
emissions from the high frequency carrier and IO buffer switching. The conceptual block diagram of a digital
capacitive isolator, 图 21, shows a functional block diagram of a typical channel. 图 22 shows a conceptual detail
of how the OOK scheme works.
图 21 shows how the input signal passes through the capacitive isolation barrier through modulation (OOK) and
signal conditioning.
9.2 Functional Block Diagram
Transmitter
Receiver
OOK
Modulation
TX IN
SiO based
2
RX OUT
TX Signal
Conditioning
RX Signal
Conditioning
Envelope
Detection
Capacitive
Isolation
Barrier
Emissions
Reduction
Techniques
Oscillator
图 21. Conceptual Block Diagram of a Capacitive Data Channel
TX IN
Carrier signal through
isolation barrier
RX OUT
图 22. On-Off Keying (OOK) Based Modulation Scheme
14
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Functional Block Diagram (接下页)
VCC2
UVLO2
VCC1
UVLO1
VCC2
IN+
Level
Shifting
and
Control
Logic
OUT
INœ
GND2
VEE2
GND1
图 23. Functional Block Diagram — UVLO With Respect to GND2 (UCC5390-Q1)
9.3 Feature Description
9.3.1 Power Supply
The VCC1 input power supply supports a wide voltage range from 3 V to 15 V and the VCC2 output supply
supports a voltage range from 9.5 V to 33 V. For operation with bipolar supplies, the power device is turned off
with a negative voltage on the gate with respect to the emitter or source. This configuration prevents the power
device from unintentionally turning on because of current induced from the Miller effect. The typical values of the
VCC2 and VEE2 output supplies for bipolar operation are 15 V and –8 V with respect to GND2 for IGBTs and 20 V
and –5 V for SiC MOSFETs.
For operation with unipolar supply, the VCC2 supply is connected to 15 V with respect to VEE2 for IGBTs, and 20
V for SiC MOSFETs. The VEE2 supply is connected to 0 V.
9.3.2 Input Stage
The input pins (IN+ and IN–) of the UCC5390-Q1 are based on CMOS-compatible input-threshold logic that is
completely isolated from the VCC2 supply voltage. The input pins are easy to drive with logic-level control signals
(such as those from 3.3-V microcontrollers), because the UCC5390-Q1 has a typical high threshold (VIT+(IN)) of
0.55 × VCC1 and a typical low threshold of 0.45 × VCC1. A wide hysteresis (Vhys(IN)) of 0.1 × VCC1 makes for good
noise immunity and stable operation. If any of the inputs are left open, 128 kΩ of internal pulldown resistance
forces the IN+ pin low and 128 kΩ of internal resistance pulls IN– high. However, TI still recommends grounding
an input or tying to VCC1 if it is not being used for improved noise immunity.
Because the input side of the UCC5390-Q1 is isolated from the output driver, the input signal amplitude can be
larger or smaller than VCC2 provided that it does not exceed the recommended limit. This feature allows greater
flexibility when integrating the gate-driver with control signal sources and allows the user to choose the most
efficient VCC2 for any gate. However, the amplitude of any signal applied to IN+ or IN– must never be at a voltage
higher than VCC1
.
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Feature Description (接下页)
9.3.3 Output Stage
The output stage of the UCC5390-Q1 features a pullup structure that delivers the highest peak-source current
when it is most needed which is during the Miller plateau region of the power-switch turnon transition (when the
power-switch drain or collector voltage experiences dV/dt). The output stage pullup structure features a P-
channel MOSFET and an additional pullup N-channel MOSFET in parallel. The function of the N-channel
MOSFET is to provide a brief boost in the peak-sourcing current, which enables fast turn-on. Fast turn-on is
accomplished by briefly turning on the N-channel MOSFET during a narrow instant when the output is changing
states from low to high. 表 1 lists the typical internal resistance values of the pullup and pulldown structure.
表 1. UCC5390-Q1 On-Resistance
DEVICE OPTION
UCC5390-Q1
RNMOS
0.76
ROH
12
ROL
UNIT
0.13
Ω
The ROH parameter is a DC measurement and is representative of the on-resistance of the P-channel device
only. This parameter is only for the P-channel device, because the pullup N-channel device is held in the OFF
state in DC condition and is turned on only for a brief instant when the output is changing states from low to high.
Therefore, the effective resistance of the UCC5390-Q1 pullup stage during this brief turnon phase is much lower
than what is represented by the ROH parameter, which yields a faster turnon. The turnon-phase output resistance
is the parallel combination ROH || RNMOS
.
The pulldown structure in the UCC5390-Q1 is simply composed of an N-channel MOSFET. The output of the
UCC5390-Q1 is capable of delivering, or sinking, 10-A peak current pulses. The output voltage swing between
VCC2 and VEE2 provides rail-to-rail operation because of the MOS-out stage which delivers very low dropout.
UVLO2
VCC2
ROH
Level
Shifting
and
RNMOS
OUT
Control
Logic
ROL
GND2
VEE2
图 24. Output Stage
9.3.4 Protection Features
9.3.4.1 Undervoltage Lockout (UVLO)
UVLO functions are implemented for both the VCC1 and VCC2 supplies between the VCC1 and GND1, and VCC2
and VEE2 pins to prevent an underdriven condition on IGBTs and MOSFETs. When VCC is lower than VIT+ (UVLO)
at device start-up or lower than VIT–(UVLO) after start-up, the voltage-supply UVLO feature holds the effected
output low, regardless of the input pins (IN+ and IN–) as shown in 表 2. The VCC UVLO protection has a
hysteresis feature (Vhys(UVLO)). This hysteresis prevents chatter when the power supply produces ground noise;
this allows the device to permit small drops in bias voltage, which occurs when the device starts switching and
operating current consumption increases suddenly. 图 25 shows the UVLO functions.
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表 2. UCC5390-Q1 VCC1 UVLO Logic
INPUTS
OUTPUT
CONDITION
IN+
IN–
L
OUT
H
L
L
L
L
L
L
L
L
L
H
H
L
VCC1 – GND1 < VIT+(UVLO1) during device start-up
H
L
H
L
L
H
H
L
VCC1 – GND1 < VIT–(UVLO1) after device start-up
H
L
表 3. UCC5390-Q1 VCC2 UVLO Logic
INPUTS
OUTPUT
CONDITION
IN+
IN–
L
OUT
H
L
L
L
L
L
L
L
L
L
H
H
L
VCC2 – VEE2 < VIT+(UVLO2) during device start-up
H
L
H
L
L
H
H
L
VCC2 – VEE2 < VIT–(UVLO2) after device start-up
H
L
When VCC1 or VCC2 drops below the UVLO1 or UVLO2 threshold, a delay, tUVLO1_rec or tUVLO2_rec, occurs on the
output when the supply voltage rises above VIT+(UVLO) or VIT+(UVLO2) again. 图 25 shows this delay.
IN+
IN+
VIT+ (UVLO1)
VCC1
VCC1
VIT (UVLO1)
œ
VCC2
VCC2
VIT+ (UVLO2)
VIT
œ
(UVLO2)
tUVLO2_rec
tUVLO1_rec
VOUT
VOUT
图 25. UVLO Functions
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9.3.4.2 Active Pulldown
The active pulldown function is used to pull the IGBT or MOSFET gate to the low state when no power is
connected to the VCC2 supply. This feature prevents false IGBT and MOSFET turnon on the OUT pin by
clamping the output to approximately 2 V.
When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low by an
active clamp circuit that limits the voltage rise on the driver outputs. In this condition, the upper PMOS is
resistively held off by a pullup resistor while the lower NMOS gate is tied to the driver output through a 500-kΩ
resistor. In this configuration, the output is effectively clamped to the threshold voltage of the lower NMOS
device, which is approximately 1.5 V when no bias power is available.
9.3.4.3 Short-Circuit Clamping
The short-circuit clamping function is used to clamp voltages at the driver output slightly higher than the VCC2
voltage during short-circuit conditions. The short-circuit clamping function helps protect the IGBT or MOSFET
gate from overvoltage breakdown or degradation. The short-circuit clamping function is implemented by adding a
diode connection between the dedicated pins and the VCC2 pin inside the driver. The internal diodes can conduct
up to 500-mA current for a duration of 10 µs and a continuous current of 20 mA. Use external Schottky diodes to
improve current conduction capability as needed.
9.4 Device Functional Modes
lists the functional modes for the UCC5390-Q1 assuming VCC1 and VCC2 are in the recommended range.
表 4. Function Table
IN+
Low
X
IN–
X
OUT
Low
Low
High
High
Low
High
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9.4.1 ESD Structure
图 26 shows the multiple diodes involved in the ESD protection components of the UCC5390-Q1. This provides
pictorial representation of the absolute maximum rating for the device.
VCC1
VCC2
1
5
2
3
6
IN+
OUT
20 V
40 V
INœ
5.5 V
4
8
GND1
VEE2
图 26. ESD Structure
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10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The UCC5390-Q1 is a simple, isolated gate driver for power semiconductor devices, such as MOSFETs, IGBTs,
or SiC MOSFETs. The family of devices is intended for use in applications such as motor control, solar inverters,
switched-mode power supplies, and industrial inverters.
10.2 Typical Application
The circuit in 图 27 show a typical application for driving IGBTs.
15 V
VCC2
5 V
VCC1
C3
C4
C1
C2
GND1
RG
OUT
Rin
PWM
IN+
Cin
GND2
VEE2
INœ
C5
C3
œ 8 V
图 27. Typical Application Circuit for UCC5390-Q1 to Drive IGBT
10.2.1 Design Requirements
表 5 lists the recommended conditions to observe the input and output of the UCC5390-Q1 gate driver with the
IN– pin tied to the GND1 pin.
表 5. UCC5390-Q1 Design Requirements
PARAMETER
VALUE
3.3
UNIT
V
VCC1
VCC2
18
V
VEE2
-3
V
IN+
3.3
V
IN–
GND1
300
126
-
Switching frequency
Gate Charge of Power Device
kHz
nC
10.2.2 Detailed Design Procedure
10.2.2.1 Designing IN+ and IN– Input Filter
TI recommends that users avoid shaping the signals to the gate driver in an attempt to slow down (or delay) the
signal at the output. However, a small input filter, RIN-CIN, can be used to filter out the ringing introduced by
nonideal layout or long PCB traces.
20
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Such a filter should use an RIN resistor with a value from 0 Ω to 100 Ω and a CIN capacitor with a value from 10
pF to 1000 pF. In the example, the selected value for RIN is 51 Ω and CIN is 33 pF, with a corner frequency of
approximately 100 MHz.
When selecting these components, pay attention to the trade-off between good noise immunity and propagation
delay.
10.2.2.2 Gate-Driver Output Resistor
The external gate-driver resistors, RG(ON) and RG(OFF) are used to:
1. Limit ringing caused by parasitic inductances and capacitances
2. Limit ringing caused by high voltage or high current switching dv/dt, di/dt, and body-diode reverse recovery
3. Fine-tune gate drive strength, specifically peak sink and source current to optimize the switching loss
4. Reduce electromagnetic interference (EMI)
The output stage has a pullup structure consisting of a P-channel MOSFET and an N-channel MOSFET in
parallel. The combined peak source current is 17 A for UCC5390-Q1 . Use 公式 1 to estimate the peak source
current.
≈
’
VCC2 - VEE2
RNMOS || ROH + RON + RGFET _Int
IOH = min∆17A,
÷
÷
◊
∆
«
where
•
•
RON is the external turnon resistance, which is 2.2 Ω in this example.
RGFET_Int is the power transistor internal gate resistance, found in the power transistor data sheet. We will
assume 1.8Ω for our example.
•
IOH is the peak source current which is the minimum value between 17 A, the gate-driver peak source current,
and the calculated value based on the gate-drive loop resistance.
(1)
In this example, the peak source current is approximately 4.45 A as calculated in 公式 2.
VCC2 - VEE2
RNMOS || ROH + RON + RGFET _Int 0.76 W ||12 W + 2.2 W +1.8 W
21 V
IOH
=
=
ö 4.45 A
(2)
Similarly, use 公式 3 to calculate the peak sink current.
≈
’
VCC2 - VEE2
ROL + ROFF+RGFET _Int
IOL = min∆17 A,
÷
÷
◊
∆
«
where
•
•
ROFF is the external turnoff resistance, which is 2.2 Ω in this example.
IOL is the peak sink current which is the minimum value between 17 A, the gate-driver peak sink current, and
the calculated value based on the gate-drive loop resistance.
(3)
In this example, the peak sink current is the minimum of 公式 4 and 17 A.
VCC2 - VEE2
21 V
IOL
=
=
ö 5.08 A
ROL + ROFF + RGFET _Int 0.13 W + 2.2 W +1.8 W
(4)
注
The estimated peak current is also influenced by PCB layout and load capacitance.
Parasitic inductance in the gate-driver loop can slow down the peak gate-drive current and
introduce overshoot and undershoot. Therefore, TI strongly recommends that the gate-
driver loop should be minimized. Conversely, the peak source and sink current is
dominated by loop parasitics when the load capacitance (CISS) of the power transistor is
very small (typically less than 1 nF) because the rising and falling time is too small and
close to the parasitic ringing period.
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10.2.2.3 Estimate Gate-Driver Power Loss
The total loss, PG, in the gate-driver subsystem includes the power losses (PGD) of the UCC5390-Q1 device and
the power losses in the peripheral circuitry, such as the external gate-drive resistor.
The PGD value is the key power loss which determines the thermal safety-related limits of the UCC5390-Q1
device, and it can be estimated by calculating losses from several components.
The first component is the static power loss, PGDQ, which includes quiescent power loss on the driver as well as
driver self-power consumption when operating with a certain switching frequency. The PGDQ parameter is
measured on the bench with no load connected to the OUT pins at a given VCC1, VCC2, switching frequency, and
ambient temperature. In this example, VCC1 is 3.3V, VCC2 is 18 V and VEE2 is -3 V. The current on each power
supply, with PWM switching from 0 V to 3.3 V at 300 kHz, is measured to be ICC1 = 1.67 mA and ICC2 = 1.28 mA.
Therefore, use 公式 5 to calculate PGDQ
.
PGDQ =VCC1 ì IVCC1 + (VCC2 - VEE2 )ì ICC2 ö32.4mW
(5)
The second component is the switching operation loss, PGDO, with a given load capacitance which the driver
charges and discharges the load during each switching cycle. Use 公式 6 to calculate the total dynamic loss from
load switching, PGSW
.
PGSW = (VCC2 - VEE2)ìQG ì fSW
where
•
QG is the gate charge of the power transistor at VCC2
.
(6)
So, for this example application the total dynamic loss from load switching is approximately 793.8 mW as
calculated in 公式 7.
PGSW = 21 V ì126 nCì300 kHz = 793.8 mW
(7)
QG represents the total gate charge of the power transistor, and is subject to change with different testing
conditions. The UCC5390-Q1 gate-driver loss on the output stage, PGDO, is part of PGSW. PGDO is equal to PGSW if
the external gate-driver resistance and power-transistor internal resistance are 0 Ω, and all the gate driver-loss
will be dissipated inside the UCC5390-Q1. If an external turn-on and turn-off resistance exists, the total loss is
distributed between the gate driver pull-up/down resistance, external gate resistance, and power-transistor
internal resistance. Importantly, the pull-up/down resistance is a linear and fixed resistance if the source/sink
current is not saturated to 17 A, however, it will be non-linear if the source/sink current is saturated. Therefore,
PGDO is different in these two scenarios.
Case 1 - Linear Pull-Up/Down Resistor:
≈
’
PGSW
2
ROH ||RNMOS
ROL
PGDO
=
∆
∆
«
+
÷
÷
◊
ROH ||RNMOS +RON +RGFET _Int ROL +ROFF +RGFET _Int
(8)
In this design example, all the predicted source and sink currents are less than 17 A, therefore, use 公式 9 to
estimate the UCC5390-Q1 gate-driver loss.
≈
∆
«
’
÷
◊
793.8 mW
2
12 W || 0.76 W
12 W || 0.76 W + 2.2 W +1.8 W 0.13 W + 2.2 W +1.8 W
0.13 W
PGDO
=
+
ö72.66 mW
(9)
Case 2 - Nonlinear Pull-Up/Down Resistor:
TR_Sys
TF_Sys
»
ÿ
Ÿ
…
PGDO =fSW ì 17 A ì
V
- VOUTH(t) dt +17 A ì
(VOUTL(t) - VEE2)dt
(
)
CC2
—
—
…
Ÿ
0
0
…
Ÿ
⁄
where
•
VOUTH/L(t) is the gate-driver OUT pin voltage during the turnon and turnoff period. In cases where the output is
saturated for some time, this value can be simplified as a constant-current source (17 A at turnon and turnoff)
charging or discharging a load capacitor. Then, the VOUTH/L(t) waveform will be linear and the TR_Sys and TF_Sys
can be easily predicted.
(10)
22
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For some scenarios, if only one of the pullup or pulldown circuits is saturated and another one is not, the PGDO is
a combination of case 1 and case 2, and the equations can be easily identified for the pullup and pulldown based
on this discussion.
Use 公式 11 to calculate the total gate-driver loss dissipated in the UCC5390-Q1 gate driver, PGD
.
PGD = PGDQ + PGDO = 32.4mW + 72.66mW = 105.06mW
(11)
10.2.2.4 Estimating Junction Temperature
Use 公式 12 to estimate the junction temperature (TJ) of the UCC5390-Q1 family.
TJ = TC + YJT ìPGD
where
•
•
TC is the UCC5390-Q1 case-top temperature measured with a thermocouple or some other instrument.
ΨJT is the junction-to-top characterization parameter from the table.
(12)
Using the junction-to-top characterization parameter (ΨJT) instead of the junction-to-case thermal resistance
(RθJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal
energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the
total energy is released through the top of the case (where thermocouple measurements are usually conducted).
The RθJC resistance can only be used effectively when most of the thermal energy is released through the case,
such as with metal packages or when a heat sink is applied to an IC package. In all other cases, use of RθJC will
inaccurately estimate the true junction temperature. The ΨJT parameter is experimentally derived by assuming
that the dominant energy leaving through the top of the IC will be similar in both the testing environment and the
application environment. As long as the recommended layout guidelines are observed, junction temperature
estimations can be made accurately to within a few degrees Celsius.
10.2.3 Selecting VCC1 and VCC2 Capacitors
Bypass capacitors for the VCC1 and VCC2 supplies are essential for achieving reliable performance. TI
recommends choosing low-ESR and low-ESL, surface-mount, multi-layer ceramic capacitors (MLCC) with
sufficient voltage ratings, temperature coefficients, and capacitance tolerances.
注
DC bias on some MLCCs will impact the actual capacitance value. For example, a 25-V,
1-μF X7R capacitor is measured to be only 500 nF when a DC bias of 15-VDC is applied.
10.2.3.1 Selecting a VCC1 Capacitor
A bypass capacitor connected to the VCC1 pin supports the transient current required for the primary logic and the
total current consumption, which is only a few milliamperes. Therefore, a 50-V MLCC with over 100 nF is
recommended for this application. If the bias power-supply output is located a relatively long distance from the
VCC1 pin, a tantalum or electrolytic capacitor with a value greater than 1 μF should be placed in parallel with the
MLCC.
10.2.3.2 Selecting a VCC2 Capacitor
A 50-V, 10-μF MLCC and a 50-V, 0.22-μF MLCC are selected for the CVCC2 capacitor. If the bias power supply
output is located a relatively long distance from the VCC2 pin, a tantalum or electrolytic capacitor with a value
greater than 10 μF should be used in parallel with CVCC2
.
10.2.3.3 Application Circuits With Output Stage Negative Bias
When parasitic inductances are introduced by nonideal PCB layout and long package leads (such as TO-220
and TO-247 type packages), ringing in the gate-source drive voltage of the power transistor could occur during
high di/dt and dv/dt switching. If the ringing is over the threshold voltage, unintended turnon and shoot-through
could occur. Applying a negative bias on the gate drive is a popular way to keep such ringing below the
threshold. A few examples of implementing negative gate-drive bias follow.
版权 © 2019, Texas Instruments Incorporated
23
UCC5390-Q1
ZHCSKG7A –OCTOBER 2019–REVISED NOVEMBER 2019
www.ti.com.cn
图 28 shows another example which uses two supplies (or single-input, double-output power supply). The power
supply across VCC2 and GND2 determines the positive drive output voltage and the power supply across VEE2
and GND2 determines the negative turnoff voltage. This solution requires more power supplies than the first
example, however, it provides more flexibility when setting the positive and negative rail voltages.
VCC2
VCC1
CA1
+
œ
GND1
RG
OUT
GND2
IN+
CA2
+
œ
INœ
VEE2
图 28. Negative Bias With Two Iso-Bias Power Supplies
10.2.4 Application Curve
VCC2 = 20 V
VEE2 = GND fSW = 10 kHz
图 29. PWM Input And Gate Voltage Waveform
11 Power Supply Recommendations
The recommended input supply voltage (VCC1) for the UCC5390-Q1 device is from 3 V to 15 V. The lower limit of
the range of output bias-supply voltage (VCC2) is determined by the internal UVLO protection feature of the
device. The VCC1 and VCC2 voltages should not fall below their respective UVLO thresholds for normal operation,
or else the gate-driver outputs can become clamped low for more than 50 μs by the UVLO protection feature. For
more information on UVLO, see the Undervoltage Lockout (UVLO) section. The higher limit of the VCC2 range
depends on the maximum gate voltage of the power device that is driven by the UCC5390-Q1 device, and
should not exceed the recommended maximum VCC2 of 33 V. A local bypass capacitor should be placed
between the VCC2 and VEE2 pins, with a value of 220-nF to 10-μF for device biasing. TI recommends placing an
additional 100-nF capacitor in parallel with the device biasing capacitor for high frequency filtering. Both
capacitors should be positioned as close to the device as possible. Low-ESR, ceramic surface-mount capacitors
are recommended. Similarly, a bypass capacitor should also be placed between the VCC1 and GND1 pins. Given
the small amount of current drawn by the logic circuitry within the input side of the UCC5390-Q1 device, this
bypass capacitor has a minimum recommended value of 100 nF.
24
版权 © 2019, Texas Instruments Incorporated
UCC5390-Q1
www.ti.com.cn
ZHCSKG7A –OCTOBER 2019–REVISED NOVEMBER 2019
If only a single, primary-side power supply is available in an application, isolated power can be generated for the
secondary side with the help of a transformer driver such as Texas Instruments' SN6501 or SN6505A. For such
applications, detailed power supply design and transformer selection recommendations are available in SN6501
Transformer Driver for Isolated Power Supplies data sheet and SN6505A Low-Noise 1-A Transformer Drivers for
Isolated Power Supplies data sheet.
版权 © 2019, Texas Instruments Incorporated
25
UCC5390-Q1
ZHCSKG7A –OCTOBER 2019–REVISED NOVEMBER 2019
www.ti.com.cn
12 Layout
12.1 Layout Guidelines
Designers must pay close attention to PCB layout to achieve optimum performance for the UCC5390-Q1. Some
key guidelines are:
•
Component placement:
–
Low-ESR and low-ESL capacitors must be connected close to the device between the VCC1 and GND1
pins and between the VCC2 and VEE2 pins to bypass noise and to support high peak currents when turning
on the external power transistor.
–
To avoid large negative transients on the VEE2 pins connected to the switch node, the parasitic
inductances between the source of the top transistor and the source of the bottom transistor must be
minimized.
•
•
•
Grounding considerations:
–
Limiting the high peak currents that charge and discharge the transistor gates to a minimal physical area
is essential. This limitation decreases the loop inductance and minimizes noise on the gate terminals of
the transistors. The gate driver must be placed as close as possible to the transistors.
High-voltage considerations:
–
To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces
or copper below the driver device. A PCB cutout or groove is recommended in order to prevent
contamination that may compromise the isolation performance.
Thermal considerations:
–
A large amount of power may be dissipated by the UCC5390-Q1 if the driving voltage is high, the load is
heavy, or the switching frequency is high (for more information, see the Estimate Gate-Driver Power Loss
section). Proper PCB layout can help dissipate heat from the device to the PCB and minimize junction-to-
board thermal impedance (θJB).
–
–
Increasing the PCB copper connecting to the VCC2 and VEE2 pins is recommended, with priority on
maximizing the connection to VEE2. However, the previously mentioned high-voltage PCB considerations
must be maintained.
If the system has multiple layers, TI also recommends connecting the VCC2 and VEE2 pins to internal
ground or power planes through multiple vias of adequate size. These vias should be located close to the
IC pins to maximize thermal conductivity. However, keep in mind that no traces or coppers from different
high voltage planes are overlapping.
26
版权 © 2019, Texas Instruments Incorporated
UCC5390-Q1
www.ti.com.cn
ZHCSKG7A –OCTOBER 2019–REVISED NOVEMBER 2019
12.2 Layout Example
图 30 shows a PCB layout example with the signals and key components labeled.
(1) No PCB traces or copper are located between the primary and secondary side, which ensures isolation performance.
图 30. Layout Example
版权 © 2019, Texas Instruments Incorporated
27
UCC5390-Q1
ZHCSKG7A –OCTOBER 2019–REVISED NOVEMBER 2019
www.ti.com.cn
Layout Example (接下页)
图 31 and 图 32 show the top and bottom layer traces and copper.
图 31. Top-Layer Traces and Copper
图 32. Bottom-Layer Traces and Copper (Flipped)
28
版权 © 2019, Texas Instruments Incorporated
UCC5390-Q1
www.ti.com.cn
ZHCSKG7A –OCTOBER 2019–REVISED NOVEMBER 2019
Layout Example (接下页)
图 33 shows the 3D layout of the top view of the PCB.
图 33. 3-D PCB View
12.3 PCB Material
Use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper alternatives because of
lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and the self-
extinguishing flammability-characteristics.
图 34 shows the recommended layer stack.
High-speed traces
10 mils
Ground plane
Keep this space
FR-4
free from planes,
traces, pads, and
vias
40 mils
0r ~ 4.5
Power plane
10 mils
Low-speed traces
图 34. Recommended Layer Stack
版权 © 2019, Texas Instruments Incorporated
29
UCC5390-Q1
ZHCSKG7A –OCTOBER 2019–REVISED NOVEMBER 2019
www.ti.com.cn
13 器件和文档支持
13.1 文档支持
13.1.1 相关文档
请参阅如下相关文档:
•
•
•
•
•
德州仪器 (TI),《数字隔离器设计指南》
德州仪器 (TI),隔离相关术语
德州仪器 (TI),《SN6501 用于隔离式电源的变压器驱动器》数据表
德州仪器 (TI),《SN6505A 用于隔离式电源的低噪声 1A 变压器驱动器》数据表
德州仪器 (TI),UCC53x0xD 评估模块用户指南
13.2 认证
UL 在线认证目录,“FPPT2.E181974 非光学隔离器件 - 组件”证书编号:20170718-E181974,
13.3 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件,以及立即订购快速访问。
13.4 接收文档更新通知
要接收文档更新通知,请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册,即可每周接收产品
信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
13.5 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.6 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.7 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
30
版权 © 2019, Texas Instruments Incorporated
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资
源,不保证其中不含任何瑕疵,且不做任何明示或暗示的担保,包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任:(1) 针对您的应用选择合适的TI 产品;(2) 设计、
验证并测试您的应用;(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更,恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源,也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等,TI对此概不负责,并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址:上海市浦东新区世纪大道 1568 号中建大厦 32 楼,邮政编码:200122
Copyright © 2020 德州仪器半导体技术(上海)有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
UCC5390ECQDWVQ1
UCC5390ECQDWVRQ1
ACTIVE
ACTIVE
SOIC
SOIC
DWV
DWV
8
8
64
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
5390ECQ
5390ECQ
1000 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE OUTLINE
DWV0008A
SOIC - 2.8 mm max height
S
C
A
L
E
2
.
0
0
0
SOIC
C
SEATING PLANE
11.5 0.25
TYP
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
5.95
5.75
NOTE 3
3.81
4
5
0.51
0.31
8X
7.6
7.4
0.25
C A
B
A
B
2.8 MAX
NOTE 4
0.33
0.13
TYP
SEE DETAIL A
(2.286)
0.25
GAGE PLANE
0.46
0.36
0 -8
1.0
0.5
DETAIL A
TYPICAL
(2)
4218796/A 09/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DWV0008A
SOIC - 2.8 mm max height
SOIC
8X (1.8)
SEE DETAILS
SYMM
SYMM
8X (0.6)
6X (1.27)
(10.9)
LAND PATTERN EXAMPLE
9.1 mm NOMINAL CLEARANCE/CREEPAGE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218796/A 09/2013
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DWV0008A
SOIC - 2.8 mm max height
SOIC
SYMM
8X (1.8)
8X (0.6)
SYMM
6X (1.27)
(10.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4218796/A 09/2013
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资
源,不保证其中不含任何瑕疵,且不做任何明示或暗示的担保,包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任:(1) 针对您的应用选择合适的TI 产品;(2) 设计、
验证并测试您的应用;(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更,恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源,也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等,TI对此概不负责,并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址:上海市浦东新区世纪大道 1568 号中建大厦 32 楼,邮政编码:200122
Copyright © 2020 德州仪器半导体技术(上海)有限公司
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