UCC5631A_09 [TI]
Multimode SCSI 9 Line Terminator;
| 型号： | UCC5631A_09 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Multimode SCSI 9 Line Terminator |
| 文件： | 总6页 (文件大小：65K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCC5631A
Multimode SCSI 9 Line Terminator
FEATURES
DESCRIPTION
• Auto Selection Single Ended (SE) or
Low Voltage Differential (LVD)
Termination
The UCC5631A Multimode SCSI Terminator provides a smooth transition
into the next generation of the SCSI Parallel Interface (SPI-2). It automati-
cally senses the bus, via DIFFB, and switches the termination to either sin-
gle ended (SE) or low voltage differential (LVD) SCSI, dependent on which
type of devices are connected to the bus. The UCC5631A can not be used
on a HVD, EIA485, differential SCSI bus. If the UCC5631A detects a HVD
SCSI device, it switches to a high impedance state.
• Meets SCSI-1, SCSI-2, SCSI-3, SPI,
Ultra (Fast-20), Ultra2 (SPI-2 LVD)
and Ultra3 Standards
• 2.7V to 5.25V Operation
• Differential Failsafe Bias
The Multimode terminator contains all functions required to terminate and
auto detect and switch modes for SPI-2 bus architectures. Single Ended
and Differential impedances and currents are trimmed for maximum effec-
tiveness. Fail Safe biasing is provided to insure signal integrity. Device/Bus
type detection circuitry is integrated into the terminator to provide automatic
switching of termination between single ended and LVD SCSI and a high
impedance for HVD SCSI. The multimode function provides all the perfor-
mance analog functions necessary to implement SPI-2 termination in a sin-
gle monolithic device.
• Thermal packaging for low junction
temperature and better MTBF
• Master/Slave Input
• Supports Active Negation
• 3pF Channel Capacitance
• Reversed Disconnect Polarity
The UCC5631A is offered in a 36 pin SSOP package, as well as a 48 pin
LQFP package for a temperature range of 0°C to 70°C.
BLOCK DIAGRAM
HIPD LVD
35 34
SE
33
(NOISE LOAD)
REF 1.3V
HIPD
2.15V
1.3V
20 DIFSENS
DIFFB 21
LVD
SE
–15mA ≤ I
≤ –5mA
SOURCE
0.6V
50µA ≤ I
≤ 200µA
SINK
19
MSTR/SLV
110
124
SOURCE/SINK REGULATOR
SE REF 2.7V
56mV
52.5
52.5
–
+
5
4
L1–
L1+
LVD REF 1.25V
56mV
+
–
ALL
SWITCHES
MODE
SE GND SWITCH
SE
LVD
UP
110
124
10µA
DOWN
OPEN
OPEN
HIPD
56mV
52.5
52.5
ENABLE
SWITCHES
–
+
DISCNCT
17
DISCNCT
32 L9–
31 L9+
56mV
+
–
TRMPWR 36
SE GND SWITCH
18
8
9
10
26
27
28
1
PATENTED CIRCUIT DESIGN
GND
REG
HS/GND
UDG-99165
Note: Indicated pinout is for 36 pin SSOP package.
SLUS443 - OCTOBER 1999
UCC5631A
CONNECTION DIAGRAM
ABSOLUTE MAXIMUM RATINGS
TRMPWR Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V
Signal Line Voltage . . . . . . . . . . . . . . . . . . . . . 0V to TRMPWR
Package Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 2W
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature. . . . . . . . . . . . . . . . . . . –55°C to +150°C
Lead Temperature (Soldering, 10sec.) . . . . . . . . . . . . . +300°C
QSOP-36 (Top View)
MWP Package
REG
N/C
1
2
3
4
5
6
7
8
9
36 TRMPWR
35
34
33
HIPD
LVD
SE
All voltages are with respect to pin 18. Currents are positive
into, negative out of the specified terminal. Consult Packaging
Section of the Databook for thermal limitations and consider-
ations of packages.
N/C
L1+
L1–
32 L9–
L2+
31 L9+
RECOMMENDED OPERATING CONDITIONS
TRMPWR Voltage . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.25V
L2–
30 L8–
HS/GND
HS/GND
29 L8+
28 HS/GND
27 HS/GND
26 HS/GND
25 L7–
HS/GND 10
L3+ 11
LQFP-48 (Top View)
FQP Package
L3– 12
HS/GND
HS/GND
L5+
HS/GND
L4–
L4+ 13
24 L7+
L4+
L5–
L3–
L4– 14
23 L6–
DISCNCT
GND
L3+
NC
L5+ 15
22 L6+
48
46
38
47
45 44 43 42
40 39
37
36
41
L5– 16
21 DIFF B
20 DIFSENS
19 MSTR/SLV
MSTR/SLV
DIFSENS
DIFFB
N/C
L2–
1
2
3
35
L2+
DISCNCT 17
GND 18
L1–
34
33
32
31
30
29
28
27
26
25
4
5
L1+
HS/GND
HS/GND
HS/GND
HS/GND
L6+
HS/GND
HS/GND
HS/GND
HS/GND
NC
6
7
8
9
L6–
NC
10
11
12
L7+
REG
L7–
NC
13
15
14
17
21
16
18 19 20
22 23 24
L8+
L8–
NC
TERMPWR
HIPD
L9+
L9–
LVD
HS/GND
HS/GND
SE
HS/GND
2
UCC5631A
ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = TJ = 0°C to 70°C,
TRMPWR = 2.7V to 5.25V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
TRMPWR Supply Current Section
TRMPWR Supply Current
LVD Mode (No Load)
13
1.6
250
20
10
mA
mA
A
SE Mode (No Load)
Disabled
400
Regulator Section
REG Output Voltage (LVD Mode)
REG Output Voltage (SE Mode)
0.5V ≤ VCM ≤ 2.0V (Note1)
0V ≤ VL– ≤ 4.2V (Note2)
VREG= 0V
1.15
2.5
1.25
2.7
1.35
3.0
V
V
REG Short-Circuit Source Current
(LVD and SE Modes)
–800 –420 –225
mA
REG Short-Circuit Sink Current
(LVD and SE Modes)
VREG= 3.0V
100
180
800
mA
DIFSENS Output Section
Output Voltage
–5mA ≤ IDIFSENS ≤ 50µA
VDIFSENS = 0V
1.2
–15
50
1.3
–8
80
1.4
–5
V
Short-Circuit Source Current
Short-Circuit Sink Current
mA
µA
VDIFSENS = 2.75V
200
Differential Termination Section (Applies to each line pair, 1-9, in LVD mode)
Differential Impedance
100
110
100
1.15
105
140
110
165
125
1.35
3
Common Mode Impedance
Differential Bias Voltage
Common Mode Bias Voltage
Output Capacitance
L+ and L– shorted together. (Note 3)
mV
V
L+ and L– shorted together.
1.25
110
Single ended measurement to ground. (Note 4)
pF
Single Ended Termination Section (Applies to each line pair, 1-9, in SE mode)
Impedance
(Note 5)
102.3
–25.4
–22.4
117.7
–21
–18
3
Termination Current
Signal Level 0.2V
mA
mA
pF
Signal Level 0.5V
Output Capacitance
Single ended measurement to ground. (Note 4)
I= 10mA
Single Ended GND Switch Impedance
20
60
Disconnected Termination Section (Applies to each line pair, 1-9, in DISCNCT or HIPD mode)
Output Leakage
400
3
nA
pF
Output Capacitance
Single ended measurement to ground. (Note 4)
VDISCNCT = 0V
DISCNCT and DIFFB Input Section
DISCNCT Threshold
0.8
–30
0.5
1.9
–1
2.0
– 3
0.7
2.4
1
V
A
V
V
A
DISCNCT Input Current
–10
DIFFB Single Ended to LVD Threshold
DIFFB LVD to HIPD Threshold
DIFFB Input Current
0V ≤ VDIFFB ≤ 2.75V
3
UCC5631A
ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = TJ = 0°C to 70°C,
TRMPWR = 2.7V to 5.25V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
Master/Slave (MSTR/SLV) Input Section
MSTR/SLV Threshold
V
TRMPWR = 2.7V
0.8
1
1.9
2.4
3.7
1
V
V
V
VTRMPWR = 3.3V
VTRMPWR = 5.25V
1.5
–1
MSTR/SLV Input Current
A
Status Bits (SE, LVD, HIPD) Output Section
ISOURCE
ISINK
VLOAD = 2.4V
VLOAD = 0.5V
VLOAD = 0.4V
–8.7
6
–4
mA
mA
mA
3
2
5
Note 1: VCM is applied to all L+ and L– lines simultaneously.
Note 2: VL– is applied to all L– lines simultaneously.
(
)
2.0V −0.5V
Note 3: ZCM
=
;
I
−I
at V = 2V
at V = 0.5V
)
(
)
(
CM
CM
Note 4: Guaranteed by design. Not 100% tested in production.
VL X) −0.2V
(
Note 5: Z =
; where
I L X
(
)
VL(X)= Output voltage for each terminator minus output pin (L1– through L9–) with each pin unloaded.
IL(X )= Output current for each terminator minus output pin (L1– through L9–) with the minus output pin forced to 0.2V.
PIN DESCRIPTIONS
DIFFB: Input pin for the comparators that select SE, L1– thru L9–: Termination lines. These are the active
LVD, or HIPD modes of operation. This pin should be de- lines in SE mode and are the negative lines for LVD
mode. In HIPD mode, these lines are high impedance.
coupled with a 0.1 F capacitor to ground and then cou-
pled to the DIFSENS pin through a 20k resistor.
L1+ thru L9+: Termination lines. These lines switch to
ground in SE mode and are the positive lines for LVD
mode. In HIPD mode, these lines are high impedance.
DIFSENS: Connects to the Diff Sense line of the SCSI
bus. The bus mode is controlled by the voltage level on
this pin.
MSTR/SLV: If the terminator is enabled, this input pin en-
ables / disables the DIFSENS driver, when connected to
TRMPWR or ground respectively. When the terminator is
disabled, the DIFSENS driver is off, independent of this
input.
DISCNCT: Input pin used to shut down the terminator if
the terminator is not connected at the end of the bus.
Connect this pin to ground to disable the terminator or
open pin to activate the terminator.
LVD: TTL compatible status bit. This output pin is high
when the SCSI bus is in LVD mode.
HIPD: TTL compatible status bit. This output pin is high
when a high voltage differential device is detected on the
bus.
REG: Regulator output bypass pin. This pin must be
connected to a 4.7 F capacitor to ground.
HS/GND: Heat sink ground pins. These should be con-
nected to large area PC board traces to increase the
power dissipation capability.
SE: TTL compatible status bit. This output pin is high
when the SCSI bus is in SE mode.
GND: Power Supply return.
TRMPWR: 2.7V to 5.25V power input pin.
4
UCC5631A
APPLICATION INFORMATION
TERMPWR
36 TERMPWR
CONTROL LINES
TERMPWR 36
CONTROL LINES
TERMPWR
19 MSTR/SLV
MSTR/SLV 19
DIFSENS 20
20 DIFSENS
17 DISCNCT
DISCNCT 17
REG
1
DIFFB
21
DIFF B
21
REG
1
20k
20k
4.7µF .
0.1µF .
0.1µF .
4.7µF
36 TERMPWR
DATA LINES (9)
TERMPWR 36
DATA LINES (9)
19 MSTR/SLV
MSTR/SLV 19
4.7µF .
4.7µF .
17 DISCNCT
DISCNCT 17
REG
1
DIFF B
21
DIFFB
21
REG
1
4.7µF .
4.7µF
36 TERMPWR
DATA LINES (9)
19 MSTR/SLV
TERMPWR 36
DATA LINES (9)
MSTR/SLV 19
17 DISCNCT
DISCNCT 17
REG
1
DIFFB
21
DIFFB
21
REG
1
4.7µF .
4.7µF
UDG-99166
Figure 2. Application diagram.
All SCSI buses require a termination network at each The SCSI bus DIFSENS signal line is used to identify
end to function properly. Specific termination require- which types of SCSI devices are present on the bus. On
ments differ, depending on which types of SCSI devices power-up, the UCC5631A DIFSENS drivers will try to de-
are present on the bus.
liver 1.3V to the DIFSENS line. If only LVD devices are
present, the DIFSENS line will be successfully driven to
1.3V and the terminators will configure for LVD operation.
If any single ended devices are present, they will present
a short to ground on the DIFSENS line, signaling the
UCC5631A(s) to configure into the SE mode, accommo-
dating the SE devices. Or, if any high voltage differential
(HVD) devices are present, the DIFSENS line is pulled
high and the terminator will enter a high impedance
state, effectively disconnecting from the bus.
The UCC5631A is used in multi-mode active termination
applications, where single ended (SE) and low voltage
differential (LVD) devices might coexist. The UCC5631A
has both SE and LVD termination networks integrated
into a single monolithic component. The correct termina-
tion network is automatically determined by the SCSI bus
"DIFSENS" signal.
5
UCC5631A
APPLICATION INFORMATION (cont.)
The DIFSENS line is monitored by each terminator requirement is a maximum difference of 2pF when com-
through a 50Hz noise filter at the DIFFB input pin. A set paring pair to pair. These requirements apply to differen-
of comparators detect and select the appropriate termi- tial bus termination circuitry that is not part of a SCSI
nation for the bus as follows. If the DIFSENS signal is be- device. If the termination circuitry is included as part of a
low 0.5V, the termination network is SE. Between 0.7V device, then the corresponding balance requirements are
and 1.9V, the termination network switches to LVD, and 2.25pF maximum difference within a pair, and 3pF from
above 2.4V is HVD, causing the terminators to discon- pair to pair.
nect from the bus. The thresholds accommodate differ-
ences in ground potential that can occur with long lines.
lengths need to be carefully balanced. Standard
Feed-throughs, through-hole connections, and etch
Three UCC5631A multi-mode parts are required at each multi-layer power and ground plane spacing add about
end of the bus to terminate 27 (18 data, plus 9 control) 1pF to each plane. Each feed-through will add about
lines. Each part includes a DIFSENS driver, but only one 2.5pF to 3.5pF. Enlarging the clearance holes on both
is necessary to drive the line. A MSTR/SLV input pin is power and ground planes will reduce the capacitance.
provided to disable the other two. The "master" part must Similarly, opening up the power and ground planes under
have its' MSTR/SLV pin connected to TRMPWR and the the connector will reduce the capacitance for
two "slave" parts must have the MSTR/SLV inputs through-hole connector applications. Capacitance will
grounded. Only the "master" is connected directly to the also be affected by components, in close proximity,
SCSI bus DIFSENS line. The DIFFB inputs on all three above and below the circuit board.
parts are connected together, allowing them to share the
Unitrode multi-mode terminators are designed with very
same 50Hz noise filter. This multi-mode terminator oper-
tight balance, typically 0.1pF between pins in a pair and
ates in full specification down to 2.7V TRMPWR voltage.
0.3pF between pairs. At each L+ pin, a ground driver
This accommodates 3.3V systems, with allowance for the
drives the pin to ground, while in single ended mode. The
3.3V supply tolerance (+/- 10%), a unidirectional fusing
ground driver is specially designed to not effect the ca-
device and cable drop. In 3.3V TRMPWR systems, the
pacitive balance of the bus when the device is in LVD or
UCC3912 is recommended in place of the fuse and di-
disconnect mode.
ode. The UCC3912's lower voltage drop allows additional
Multi-layer boards need to adhere to the 120 imped-
ance standard, including the connectors and feed-
throughs. This is normally done on the outer layers with
4 mil etch and 4 mil spacing between runs within a pair,
and a minimum of 8 mil spacing to the adjacent pairs to
reduce crosstalk. Microstrip technology is normally too
low of impedance and should not be used. It is designed
for 50 rather than 120 differential systems. Careful
consideration must be given to the issue of heat man-
agement. A multi-mode terminator, operating in SE
mode, will dissipate as much as 130mW of instanta-
neous power per active line with TRMPWR = 5.25V. The
UCC5631A is offered in a 36 pin SSOP and a 48 lead
LFQP. Both packages include heat sink ground pins.
These heat sink/ground pins are directly connected to
the die mount paddle under the die and conduct heat
from the die to reduce the junction temperature. All of the
HS/GND pins need to be connected to etch area or a
feed-through per pin connecting to the ground plane
layer on a multi-layer board.
margin over the fuse and diode, for the far end termina-
tor.
Layout is critical for Ultra2 and Ultra3 systems. The SPI-2
standard for capacitance loading is 10pF maximum from
each positive and negative signal line to ground, and a
maximum of 5pF between the positive and negative sig-
nal lines of each pair is allowed. These maximum capaci-
tances apply to differential bus termination circuitry that
is not part of a SCSI device, (e.g. a cable terminator). If
the termination circuitry is included as part of a SCSI de-
vice, (e.g., a host adaptor, disk or tape drive), then the
corresponding requirements are 30pF maximum from
each positive and negative signal line to ground and
15pF maximum between the positive and negative signal
lines of each pair.
The SPI-2 standard for capacitance balance of each pair
and balance between pairs is more stringent. The stan-
dard is 0.75pF maximum difference from the positive and
negative signal lines of each pair to ground. An additional
UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460
6
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