UCD3138064ARGCR [TI]
适用于隔离电源的高集成度数字控制器 | RGC | 64 | -40 to 125;
| 型号： | UCD3138064ARGCR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于隔离电源的高集成度数字控制器 | RGC | 64 | -40 to 125 控制器 |
| 文件： | 总89页 (文件大小：3324K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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UCD3138064A
ZHCSER5 –DECEMBER 2015
UCD3138064A 用于隔离电源的高度集成数字控制器
1 器件概述
1.1 特性
1
– 突发模式
– 理想的二极管仿真
• UCD3138 系列的 64kB 程序闪存衍生器件
– 2-32kB 程序闪存存储器组
– 同步镇流器软启动/关闭
– 低集成电路 (IC) 待机功率
• 初级侧电压感应
– 支持从组 1 执行，同时对其它组进行编程
– 在不关闭电源的情况下，能够更新固件
– 与 UCD3138 (+1 SPI，+1 I2C) 相对的额外通信
端口
• 磁通和相位电流均衡
– 与 UCD3138 (SLUSAP2B) 引脚到引脚兼容。
• 可对多达 3 个独立式反馈环路的数字控制
– 专用的基于 PID 的硬件
• 电流共享（平均 & 主/从）
• 特有丰富的故障保护选项
– 7 个模拟比较器/4 个数字比较器
– 逐周期电流限制
– 支持双极点/双零点配置
– 非线性控制
• 带和不带预偏置电压的软启动/停止
• 快速输入电压前馈硬件
– 可编程消隐时间和故障计数
– 外部故障输入
• 多个 UCD3138064A 器件间的 DPWM 波形同步
• 同步整流死区优化外设，可与 UCD7138 同步整流
驱动器搭配使用
• 14 通道，12 位，267ksps 通用 ADC，此 ADC 具
有集成的
• 高达 16MHz 误差数模 (A/D) 转换器 (EADC)
– 可配置低至 1mV/LSB 的分辨率
– 高达 8 倍过采样
– 可编程平均滤波器
– 双采样保持
• 内部温度传感器
– 基于硬件的取平均值操作（高达 8 倍）
– 带有 4 位抖动值的 14 位有效数模转换器 (DAC)
– 自适应触发定位
• 完全可编程高性能 31.25MHz，32 位 ARM7TDMI-S
处理器
– 64kB 程序闪存（2-32kB 组）
– 具有纠错码 (ECC) 的 2kB 数据闪存
– 4kB 数据 RAM
• 高达 8 个高分辨率数字脉宽已调制 (DPWM) 输出
– 脉宽分辨率为 250ps
– 8kB 引导 ROM
– 4ns 频率和相位分辨率
– 输出间的可调相移
– 配对间的可调死区
– 逐周期占空比匹配
– 可通过 I2C 或通用异步收发器 (UART) 实现现场
固件引导加载
• 通信外设
– 1 - I2C/PMBus，1 - I2C （只适用于主控模式）
– 2 - UART
– 高达 2MHz 开关频率
• 可配置后缘/前缘/三角调制
• 可配置的反馈控制
– 1 - SPI
• UART 自动波特率调整
• 具有可选输入引脚的定时器捕捉
• 内置安全装置：欠压检测 (BOD) 和加电复位 (POR)
• 64 引脚四方扁平无引线 (QFN) 和 48 引脚 QFN 封
装
– 电压、平均电流和峰值电流模式控制
– 恒定电流、恒定功率
• 可配置 FM，相移调制和脉宽调制 (PWM)
• 快速，自动和平滑模式开关
– 频率调制和 PWM
– 相移调制和 PWM
– 频率调制和相移调制
• 高效和轻负载管理
• 运行温度：-40°C 至 125°C
• 调试接口
– Code Composer StudioTM（JTAG 接口）
– Fusion Digital PowerTM Designer GUI 支持
1.2 应用范围
•
•
电源和电信整流器
功率因数校正
•
独立的 DC-DC 模块
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLUSCA5
UCD3138064A
ZHCSER5 –DECEMBER 2015
www.ti.com.cn
1.3 说明
UCD3138064A 是一款德州仪器 (TI) 数字电源控制器，此控制器在一个单芯片解决方案内提供高集成度和优
异的性能。相对于德州仪器 (TI) 的 UCD3138 数字电源控制器 (Section 3)，UCD3138064A 可提供 64kB 闪
存程序存储器（UCD3138 可提供 32kB 闪存程序存储器），以及 SPI 和 I2C 端口等附加通信选件。2-32kB
组内的 64kB 程序闪存存储器的可用性使得设计人员能够在器件中执行固件的双镜像（例如，一个主镜像 +
一个备份镜像），以及从任一使用适当算法的组中执行的灵活性。它还为处理器创造了独一无二的机会来载
入一个新程序并随后执行那个程序，而不会中断电源传送。该特性使得最终用户能够现场为电源添加新 特
性， 同时消除了载入新程序所需的任何停机时间。
UCD3138064A 灵活的特性使得此器件适用于广泛的电源转换 应用。此外，器件内的多种外设已经过专门优
化，用于提升 AC/DC 和隔离式 DC/DC 应用 性能并减少信息技术 (IT) 和网络基础设施空间内的解决方案组
件数量。UCD3138064A 是完全可编程的解决方案，可以使用户对相关应用实现完全控制，并且能够在同类
解决方案中脱颖而出。与此同时，德州仪器 (TI) 致力于通过提供一流的开发工具来简化用户的开发工作，其
中包括应用固件、Code Composer StudioTM 软件开发环境和德州仪器 (TI) 的整合电源开发 GUI，这使得用
户能够配置和监控关键系统参数。
UCD3138064A 控制器的核心是数字电源外设 (DPP)。每个 DPP 实现一个高速数字控制环路，此环路由专
用误差模数转换器 (EADC)、基于 PID 的双极点/双零点数字补偿器以及脉宽分辨率为 250ps 的 DPWM 输出
组成。此器件还包含一个 12 位、267ksps 通用 ADC，此 ADC 具有多达 14 个通道、定时器、中断控制、
PMBus、I2C 以及 UART 通信端口。此器件基于一个32 位 ARM7TDMI-S 精简指令集计算机 (RISC) 微控制
器，该微控制器可执行实时监控、配置外设以及管理通信。ARM 微控制器从可编程闪存存储器以及片载
RAM 和 ROM 里执行它的程序。
除了 DPP，特定电源管理外设已被添加以便在全部运行范围内启用高效、针对增加的功率密度的高集成度、
可靠性、和最低总体系统成本以及支持最广泛控制体系和拓扑数量的高灵活性。此类外设包括：轻负载突发
模式、同步整流、自动模式切换、输入电压前馈、铜走线电流感测、理想二极管仿真、恒定电流/恒定功率控
制、同步整流软开启和关闭、峰值电流模式控制、磁通均衡、二次侧输入电压感测、高分辨率电流均流、带
预偏置电压的硬件可配置软启动 等。已经针对电压模式和峰值电流模式受控相移全桥、单双相位功率因数校
正 (PFC)、无桥 PFC、硬开关全桥和半桥、以及 LLC 半桥和全桥进行了拓扑支持优化。
UCD3138064A 是 UCD3138064 数字电源控制器的功能变型，相比 UCD3138064 具有显著改进。有关
UCD3138064A 中的功能改进的完整说明，请参见《UCD3138064A 迁移指南》。主要改进如下：
提高了通用 ADC 在极低温度 (-40℃) 环境下的精度和性能。
UART 外设新增了基于硬件的自动波特率调整功能。
新增了同步整流死区优化硬件外设。优势包括：
–
–
–
提高了效率
减小了同步整流电压应力
缩短了开发周期
添加了占空比读取功能，以便改善器件在峰值电流模式下的使用。
(1)
器件信息
产品型号
封装
封装尺寸（标称值）
9.00mm x 9.00mm
6.00mm x 6.00mm
VQFN (64)
WQFN (40)
UCD3138064A
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
2
器件概述
版权 © 2015, Texas Instruments Incorporated
UCD3138064A
www.ti.com.cn
ZHCSER5 –DECEMBER 2015
1.4 功能方框图
Loop MUX
DPWM0A
EAP0
EAN0
EAP1
EAN1
PID Based
Filter 0
Front End 0
Front End 1
DPWM0
DPWM0B
DPWM1A
PID Based
Filter 1
DPWM1
DPWM2
DPWM3
DPWM1B
DPWM2A
DPWM2B
DPWM3A
PID Based
Filter 2
Front End 2
AFE
Constant Power Constant
Current
23-AFE
DPWM3B
SYNC
EAP2
EAN2
Front End Averaging
Digital Comparators
EADC
2AFE
X
Avg()
SAR/Prebias
Ramp
DAC0
Input Voltage Feed Forward
A0
Filter x
CPCC
ꢀ
Value
Dither
Abs()
Peak Current Mode
Control Comparator
Advanced Power Control
Mode Switching, Burst Mode, IDE,
Synchronous Rectification soft on & off
PMBUS_ALERT
PMBUS_CTRL
PMBUS_DATA
PMBUS_CLK
PWM0
ADC_EXT_TRIG
AD[13:0]
ADC12 Control
Sequencing, Averaging,
Digital Compare, Dual
Sample and hold
PMBus
Timers
ADC12
AD00
AD01
Internal Temperature
Sensor
4 œ 16 bit (PWM)
1 œ 24 bit
PWM1
AD02
AD13
Current Share
Analog, Average, Master/Slave
AGND
Oscillator
TCAP
SCI_TX0
SCI_RX0
SCI_TX1
SCI_RX1
EXT_INT
FAULT0
UART0
UART1
ARM7TDMI-S
32 bit, 31.25 MHz
Analog
Comparators
AD02
AD03
Memory
DFLASH 2 kB
RAM 4 kB
A
B
ROM 4 kB
PFLASH 64 kB
C
GPIO
Control
Bank 1
32kB
Bank 2
32kB
FAULT1
AD04
AD13
AD06
AD07
Fault MUX &
Control
FAULT2
D
Power On Reset
V33D
V33DIO
VREG
DGND
V33A
FAULT3
Cycle by Cycle
Current Limit
E
/RESET
Brown Out Detection
Power and
1.8 V Voltage
Regulator
Digital
Comparators
TCK
JTAG
F
TMS
G
TDI(DTC0)
TDO(DTC1)
SPI_MISO
SPI_MOSI
SPI_CLK
SPI_CS
DTC
AGND
SPI
I2C
I2C_DATA
I2C_CLK
图 1-1. 功能框图
版权 © 2015, Texas Instruments Incorporated
器件概述
3
UCD3138064A
ZHCSER5 –DECEMBER 2015
www.ti.com.cn
UCD3138064A
Rising edge
optimization
control
UCD7138
CTRL
IN
SR1 DPWM
SR2 DPWM
6
4
5
1
2
3
DPWM
module
Thermal Pad
(GND)
DTC
VCC
OUT
VD
SR1
Dead Time
Control
Computation
Engine
Rising edge
optimization
control
UCD7138
IN
CTRL
OUT
6
4
5
1
2
3
DTC0
DTC1
Thermal Pad
(GND)
SR2
DTC
VCC
Decoder
VD
图 1-2. 同步整流外设与同步整流驱动器搭配使用
4
器件概述
版权 © 2015, Texas Instruments Incorporated
UCD3138064A
www.ti.com.cn
ZHCSER5 –DECEMBER 2015
内容
1
器件概述.................................................... 1
5.8 Parametric Measurement Information .............. 18
5.9 Typical Characteristics ............................. 20
Detailed Description ................................... 22
6.1 Overview ............................................ 22
6.2 ARM Processor ..................................... 22
6.3 Memory.............................................. 22
6.4 Feature Description ................................. 23
6.5 Device Functional Modes ........................... 50
6.6 Memory.............................................. 61
Applications, Implementation, and Layout........ 65
7.1 Application Information.............................. 65
7.2 Typical Application .................................. 66
器件和文档支持 .......................................... 79
8.1 器件支持............................................. 79
8.2 文档支持 ............................................ 80
8.3 社区资源............................................. 81
8.4 商标.................................................. 81
8.5 静电放电警告 ........................................ 81
8.6 Glossary ............................................. 81
机械、封装和可订购信息................................ 81
1.1 特性 ................................................... 1
1.2 应用范围 .............................................. 1
1.3 说明 ................................................... 2
1.4 功能方框图............................................ 3
修订历史记录............................................... 5
Device Options ........................................... 6
3.1 Device Comparison Table............................ 6
3.2 Product Selection Matrix ............................. 7
Pin Configuration and Functions..................... 8
4.1 Pin Diagrams ......................................... 8
4.2 Pin Functions ......................................... 9
Specifications ........................................... 12
5.1 Absolute Maximum Ratings......................... 12
5.2 ESD Ratings ........................................ 12
5.3 Recommended Operating Conditions............... 12
5.4 Thermal Information................................. 12
5.5 Electrical Characteristics............................ 13
5.6 Timing Characteristics .............................. 16
5.7 PMBus/SMBus/I2C Timing .......................... 17
6
2
3
4
5
7
8
9
2 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
注释
2015 年 12 月
*
最初发布版本
Copyright © 2015, Texas Instruments Incorporated
修订历史记录
5
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Product Folder Links: UCD3138064A
UCD3138064A
ZHCSER5 –DECEMBER 2015
www.ti.com.cn
3 Device Options
3.1 Device Comparison Table
UCD
3138
3138A
RHA/RMH
3138064
3138064A
RMH
3138
3138A
RGC
3138064
3138064A
RGC
3138128
3138128A
PFC
3138A64
3138A64A
PFC
FEATURE
3138064
RGZ
80 Pin QFP
(14 mm x 14
mm)
(Includes
leads)
80 Pin QFP
(14 mm x 14
mm)
(Includes
leads)
40 Pin QFN
(6 mm x 6
mm)
40 Pin QFN
(6 mm x 6
mm)
64 Pin QFN
(9 mm x 9
mm)
64 Pin QFN
(9 mm x 9
mm)
48 Pin QFN
(7 mm x 7
mm)
Package Offering
ARM7TDMI-S Core
Processor
31.25 MHz
8
31.25 MHz
8
31.25 MHz
8
31.25 MHz
8
31.25 MHz
8
31.25 MHz
31.25 MHz
High Resolution DPWM
Outputs (250ps
Resolution)
8
8
Number of High Speed
Independent Feedback
Loops (# Regulated
Output Voltages
3
7
3
7
3
3
3
9
3
3
12-bit, 256kps, General
Purpose ADC Channels
14
14
15
15
Digital Comparators at
ADC Outputs
4
4
4
4
4
4
4
Flash Memory (Program)
32 kB
64 kB
32 kB
64 kB
64 kB
128 kB
64 kB
Only 1 bank of
64 kB Flash
available
Number of Memory 32kB
Flash Memory Banks
1
2
1
2
2
4
Flash Memory (Data)
RAM
2 kB
4 kB
2 kB
4 kB
2 kB
4 kB
2 kB
4 kB
2 kB
4 kB
2 kB
8 kB
2 kB
8 kB
Programmable Fault
Inputs
1 + 2(1)
1 + 2(1)
4
2 + 2(1)
1 + 2(1)
4
4
High Speed Analog
Comparators with Cycle-
by-Cycle Current Limiting
6
6
7
7
6
7
7
UART (SCI)
PMBus/I2C
Additional I2C
SPI
1(1)
1
1(1)
1
2
1
0
0
2
2
2
1
1
1
2
1
1
1
1
1
0
0
1(1)
1(1)
1(1)
1(1)
0
0
4 (16 bit) and 4 (16 bit) and 4 (16 bit) and 4 (16 bit) and 4 (16 bit) and 4 (16 bit) and 4 (16 bit) and
Timers
1 (24 bit)
1 (24 bit)
1 (24 bit)
1 (24 bit)
1 (24 bit)
2 (24 bit)
2 (24 bit)
Timer PWM Outputs
Timer Capture Inputs
Total Digital GPIOs
External Interrupts
1(1)
2(1)
18
0
1(1)
2(1)
18
0
2
1 + 3(1)
30
2
1 + 3(1)
30
1(1)
2(1)
24
0
4
2 + 2(1)
43
4
2 + 2(1)
43
1
1
1
1
External Crystal Clock
Support
Yes (pins #61, Yes (pins #61,
no
no
no
no
no
62)
62)
Peak Current Mode
Control
All EADC
channels
All EADC
channels
All EADC
channels
All EADC
Channels
All EADC
Channels
EADC2 Only
EADC Only
(1) Represents an alternate pin out that is programmable via firmware.
6
Device Options
Copyright © 2015, Texas Instruments Incorporated
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UCD3138064A
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ZHCSER5 –DECEMBER 2015
3.2 Product Selection Matrix
FEATURE
UCD3138064A 64 PIN
UCD3138064A 40 PIN
ARM7TDMI-S Core Processor
31.25 MHz
8
31.25 MHz
8
High Resolution DPWM Outputs (250ps Resolution)
Number of High Speed Independent Feedback Loops (# Regulated
Output Voltages)
3
3
12-bit, 267 ksps, General Purpose ADC Channels
14
7
Digital Comparators at ADC Outputs
4
4
Flash Memory (Program)
64 kB
64 KB
Flash Memory (Data)
2 kB
2 KB
Flash Security
√
√
RAM
4 kB
4 KB
DPWM Switching Frequency
up to 2 MHz
up to 2 MHz
Programmable Fault Inputs
2 + 2(1)
1 + 2(1)
High Speed Analog Comparators with Cycle-by-Cycle Current Limiting
7(2)
6
UART (SCI)
2
1(1)
PMBus
1
√
I2C
1(1)
0
SPI
1(1)
0
Timers
4 (16 bit) and 1 (24 bit)
4 (16 bit) and 1 (24 bit)
Timer PWM Outputs
Timer Capture Inputs
Watchdog
2
1
√
√
√
√
1
1(1)
√
On Chip Oscillator
Power-On Reset and Brown-Out Reset
Sync IN and Sync OUT Functions
√
√
√
Total GPIO (includes all pins with multiplexed functions such as, DPWM,
Fault Inputs, SCI, etc.)
30
1
18
0
External Interrupts
64 Pin QFN
(9.00 mm x 9.00 mm)
40 Pin QFN
(6.00 mm x 6.00mm)
Package Offering
(1) This number represents an alternate pin out that is programmable via firmware. See the UCD3138064A Digital Power Peripherals
Programmer’s Manual for details.
(2) To facilitate simple OVP and UVP connections both comparators B and C are connected to the AD03 pin.
Copyright © 2015, Texas Instruments Incorporated
Device Options
7
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4 Pin Configuration and Functions
4.1 Pin Diagrams
64-Pin QFN
RGC Package
Top View
63
62
61
60
59
58
57
56
64
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
AGND
AGND
V33D
AD13
3
AD12
BP18
4
AD10
V33DIO
DGND
FAULT3
FAULT2
TCAP
5
AD07
AD06
6
7
AD04
8
AD03
9
V33DIO
TMS
10
11
12
13
14
15
16
DGND
TDI/SCI_RX0/PMBUS_CTRL/FAULT1/SPI_MISO/DTC0
TDO/SCI_TX0/PMBUS_ALERT/FAULT0/SPI_MOSI/DTC1
TCK/TCAP/SYNC/PWM0/DTC0
FAULT1/SPI_CLK/I2C_CLK
/RESET
ADC_EXT/TCAP/SYNC/PWM0
SCI_RX0/DTC0
SCI_TX0/DTC1
PMBUS_CLK/SCI_TX0
PMBUS_DATA/SCI_RX0
FAULT0/SPI_CS/I2C_DATA
INT_EXT
DGND
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
8
Pin Configuration and Functions
Copyright © 2015, Texas Instruments Incorporated
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ZHCSER5 –DECEMBER 2015
40-Pin QFN
RMH Package
Top View
40 39 38 37 36 35 34 33 32 31
1
2
30
29
28
27
26
25
24
23
22
21
AGND
AD13
AD06
AGND
AGND
BP18
3
4
AD04
AD03
V33D
5
DGND
6
DGND
FAULT2
TMS
7
/RESET
8
ADC_EXT_TRIG/TCAP/SYNC/PWM0
PMBUS_CLK/SCI_TX0
TDI/SCI_RX0/PMBUS_CTRL/FAULT1/DTC0
TDO/SCI_TX0/PMBUS_ALERT/FAULT0/DTC1
TCK/TCAP/SYNC/PWM0/DTC0
9
10
PMBUS_DATA/SCI_RX0
11 12 13 14 15 16
17 18 19 20
NOTE: The RMH package has thinner package height compared to the RHA package. There are also four corner
pins on the RMH package. These features help to improve solder-joint reliability. The corner anchor pins and thermal
pad should be soldered for robust mechanical performance and should be tied to the appropriate ground signal.
4.2 Pin Functions
Pin Functions - 64 VQFN
PIN
ALTERNATE ASSIGNMENT
CONFIGURABLE
AS A GPIO?
PRIMARY ASSIGNMENT
Analog ground
NUMBER
NAME
NO. 1
NO. 2
NO. 3
NO. 4
NO. 5
1
2
3
4
AGND
AD13
AD12
AD10
12-bit ADC, Ch 13, comparator E, I-share
12-bit ADC, Ch 12
DAC output
12-bit ADC, Ch 10
12-bit ADC, Ch 7, Connected to comparator F
and reference to comparator G
5
AD07
DAC output
6
7
AD06
AD04
12-bit ADC, Ch 6, Connected to comparator F
12-bit ADC, Ch 4, Connected to comparator D
DAC output
DAC output
12-bit ADC, Ch 3, Connected to comparator B
and C
8
9
AD03
Digital I/O 3.3V core supply, connected to V33D
internally
V33DIO
10
11
12
13
14
15
16
17
18
19
DGND
Digital ground
RESET
Device Reset Input, active low
ADC conversion external trigger input
SCI RX 0
ADC_EXT
SCI_RX0
SCI_TX0
TCAP
DTC0
SYNC
PWM0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SCI TX 0
DTC1
PMBUS_CLK
PMBUS_DATA
DPWM0A
DPWM0B
DPWM1A
PMBUS Clock (Open Drain)
PMBus data (Open Drain)
DPWM 0A output
SCI TX 0
SCI RX 0
DPWM 0B output
DPWM 1A output
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Pin Functions - 64 VQFN (continued)
PIN
ALTERNATE ASSIGNMENT
CONFIGURABLE
AS A GPIO?
PRIMARY ASSIGNMENT
NUMBER
NAME
DPWM1B
NO. 1
NO. 2
NO. 3
NO. 4
NO. 5
20
21
22
23
24
25
DPWM 1B output
Yes
Yes
Yes
Yes
Yes
DPWM2A
DPWM2B
DPWM3A
DPWM3B
DGND
DPWM 2A output
DPWM 2B output
DPWM 3A output
DPWM 3B output
Digital ground
ADC_EXT_TRI
G
26
SYNC
DPWM Synchronize pin
TCAP
PWM0
DTC1
Yes
27
28
PMBUS_ALERT PMBus Alert (Open Drain)
Yes
Yes
PMBUS_CTRL
SCI_TX1
PMBus Control (Open Drain)
SCI TX 1
PMBUS_ALER
T
29
Yes
30
31
32
33
34
35
36
37
SCI_RX1
PWM0
SCI RX 1
PMBUS_CTRL
Yes
Yes
Yes
General purpose PWM 0
General purpose PWM 1
Digital ground
PWM1
DGND
INT_EXT
FAULT0
FAULT1
TCK(1)
External Interrupt
Yes
Yes
Yes
Yes
External fault input 0
External fault input 1
JTAG TCK (for manufacturer test only)
SPI_CS
SPI_CLK
TCAP
I2C_DATA
I2C_CLK
SYNC
PWM0
DTC0
PMBUS_ALER
T
38
TDO(1)
JTAG TDO (for manufacturer test only)
SCI_TX0
SCI_RX0
FAULT0
SPI_MOSI
SPI_MISO
DTC1
DTC0
Yes
39
40
41
42
43
44
TDI(1)
JTAG TDI (for manufacturer test only)
JTAG TMS (for manufacturer test only)
Timer capture input
PMBUS_CTRL FAULT1
Yes
Yes
Yes
Yes
Yes
TMS(1)
TCAP
FAULT2
FAULT3
DGND
External fault input 2
External fault input 3
Digital ground
Digital I/O 3.3 V core supply, connected to
V33D internally
45
46
47
V33DIO
BP18
1.8V Bypass
Digital 3.3V core supply; V33DIO is connected
to V33D internally
V33D
48
49
AGND
AGND
Substrate analog ground
Analog ground
Channel #0, differential analog voltage, positive
input
50
51
52
53
54
55
EAP0
EAN0
EAP1
EAN1
EAP2
EAN2
Channel #0, differential analog voltage,
negative input
Channel #1, differential analog voltage, positive
input
Channel #1, differential analog voltage,
negative input
Channel #2, differential analog voltage, positive
input
Channel #2, differential analog voltage,
negative input
56
57
58
59
AGND
V33A
AD00
AD01
Analog ground
Analog 3.3 V supply
12-bit ADC, Ch 0, Connected to current source
12-bit ADC, Ch 1, Connected to current source
12-bit ADC, Ch 2, Connected to comparator A,
I-share
60
AD02
61
62
63
64
AD05
AD08
AD09
AD11
12-bit ADC, Ch 5
12-bit ADC, Ch 8
12-bit ADC, Ch 9
12-bit ADC, Ch 11
(1) Fusion Digital Power based debug tools are recommended instead of JTAG.
10
Pin Configuration and Functions
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Pin Functions - 40 WQFN
PIN
ALTERNATE ASSIGNMENT
CONFIGURABLE
AS A GPIO?
PRIMARY ASSIGNMENT
NUMBER
NAME
NO. 1
NO. 2
NO. 3
NO. 4
1
2
AGND
AD13
AD06
AD04
AD03
DGND
RESET
Analog ground
12-bit ADC, Ch 13, Connected to comparator E, I-share
12-bit ADC, Ch 6, Connected to comparator F
12-bit ADC, Ch 4, Connected to comparator D
12-bit ADC, Ch 3, Connected to comparator B & C
Digital ground
3
4
5
6
7
Device Reset Input, active low
ADC conversion external trigger input
PMBUS Clock (Open Drain)
PMBUS Data (Open Drain)
DPWM 0A output
8
ADC_EXT_TRIG
PMBUS_CLK
PMBUS_DATA
DPWM0A
TCAP
SYNC
PWM0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
9
SCI_TX0
SCI_RX0
10
11
12
13
14
15
16
17
18
19
20
21
22
DPWM0B
DPWM 0B output
DPWM1A
DPWM 1A output
DPWM1B
DPWM 1B output
DPWM2A
DPWM 2A output
DPWM2B
DPWM 2B output
DPWM3A
DPWM 3A output
DPWM3B
DPWM 3B output
PMBUS_ALERT
PMBUS_CTRL
TCK(1)
PMBus Alert (Open Drain)
PMBus Control (Open Drain)
JTAG TCK (for manufacturer test only)
JTAG TDO (for manufacturer test only)
TCAP
SYNC
PWM0
DTC0
DTC1
Yes
Yes
TDO(1)
SCI TX0 PMBUS_AL FAULT0
ERT
23
TDI(1)
JTAG TDI (for manufacturer test only)
SCI_RX0 PMBUS_C
TRL
FAULT1
DTC0
Yes
24
25
26
27
28
29
30
31
32
33
34
35
TMS(1)
FAULT2
DGND
V33D
JTAG TMS (for manufacturer test only)
External fault input 2
Yes
Yes
Digital ground
Digital 3.3 V core supply; V33DIO is connected to V33D internally
1.8V Bypass
BP18
AGND
AGND
EAP0
EAN0
EAP1
EAN1
EAP2
Substrate analog ground
Analog ground
Channel #0, differential analog voltage, positive input
Channel #0, differential analog voltage, negative input
Channel #1, differential analog voltage, positive input
Channel #1, differential analog voltage, negative input
Channel #2, differential analog voltage, positive input
(Recommended for peak current mode control)
36
37
38
39
40
AGND
V33A
AD00
AD01
AD02
Analog ground
Analog 3.3 V supply
12-bit ADC, Ch 0, Connected to current source
12-bit ADC, Ch 1, Connected to current source
12-bit ADC, Ch 2, Connected to comparator A, I-share
All four anchors should be soldered and tied to GND
Corner
NA
Corner anchor pin
(RMH only)
(1) Fusion Digital Power based debug tools are recommended instead of JTAG.
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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
UNIT
V
V33D
V33D to DGND
3.8
3.8
3.8
2.5
0.3
3.8
125
150
V33DIO
V33DIO to DGND
V33A to AGND
V
V33A
V
BP18
BP18 to DGND
V
Ground difference
All Pins, excluding AGND
Junction Temperature, TJ
Storage temperature, Tstg
|DGND – AGND|
Voltage applied to any pin
V
(2)
–0.3
–40
–55
V
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommend Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Referenced to DGND
5.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-
001
±2000
(1)
V(ESD) Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification
JESD22-C101
±500
(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible if necessary precautions are taken.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible if necessary precautions are taken.
5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM
MAX UNIT
V33D
V33DIO
V33A
BP18
TJ
Digital power
3
3
3.3
3.3
3.3
1.8
-
3.6
3.6
3.6
2
V
V
Digital I/O power
Analog power
3
V
1.8-V digital power
Junction temperature
1.6
–40
V
125
°C
5.4 Thermal Information
UCD3138064A
(1)
THERMAL METRIC
VQFN (RGC)
VQFN (RGZ) WQFN (RMH)
UNIT
64 PINS
19.9
5.7
48 PINS
26.9
12.5
3.9
40 PINS
30.8
15.7
5.7
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
RθJB
ψJT
Junction-to-board thermal resistance
3.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
0.1
0.2
0.2
ψJB
3
4
5.7
RθJC(bot) Junction-to-case (bottom) thermal resistance
0.3
0.5
0.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
12
Specifications
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5.5 Electrical Characteristics
V33A = V33D = V33DIO = 3V to 3.6 V; 1μF from BP18 to DGND, TJ = –40 °C to 125 °C (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX UNIT
Measured on V33A. The device is powered up
but all ADC12 and EADC sampling is disabled
I33A
6.3
mA
I33DIO
I33D
All GPIO and communication pins are open
ROM program execution
0.35
60
mA
mA
(1)
I33D
Flash programming in ROM mode
70
mA
The device is in ROM mode with all DPWMs
enabled and switching at 2 MHz. The DPWMs
are all unloaded.
I33
105
mA
ERROR ADC INPUTS EAP, EAN
EAP – AGND
–0.15
–0.256
–256
0.8
1.998
1.848
248
V
EAP – EAN
V
Typical error range
AFE = 0
mV
mV
mV
mV
mV
MΩ
μA
AFE = 3
1
2
4
8
1.20
2.30
4.45
9.10
AFE = 2
1.7
EAP – EAN Error voltage digital
resolution
AFE = 1
3.55
6.90
0.5
AFE = 0
(1)
REA
Input impedance (See 图 6-2)
AGND reference
IOFFSET Input offset current (See 图 6-2)
–5
5
2
Input voltage = 0 V at AFE = 0
Input voltage = 0 V at AFE = 1
Input voltage = 0 V at AFE = 2
Input voltage = 0 V at AFE = 3
–2
LSB
LSB
LSB
LSB
–2.5
–3
2.5
3
EADC Offset
–4
4
15.62
5
Sample Rate
MHz
(1)
Analog Front End Amplifier Bandwidth
100
1
MHz
V/V
mV
Gain
A0
See 图 6-3
Minimum output voltage
21
EADC DAC
DAC range
0
1.6
V
VREF DAC reference resolution
10-bit, No dithering enabled
With 4-bit dithering enabled
1.56
97.6
mV
μV
VREF DAC reference resolution
INL
DNL
–2.0
–2.0
1.58
2.0
2.0
LSB
LSB
V
DAC reference voltage
ADC12
1.61
IBIAS
Bias current for PMBus address pins
9.5
0
10.5
2.5
μA
V
Measurement range for voltage
monitoring
Internal ADC reference voltage
–40 to 125 °C
–40 to 25 °C
25 to 125 °C
2.475
2.500
–0.3
–3.4
2.53
V
Change in Internal ADC reference from
mV
(1)
25°C reference voltage
(1) Characterized by design and not production tested.
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Specifications
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Electrical Characteristics (continued)
V33A = V33D = V33DIO = 3V to 3.6 V; 1μF from BP18 to DGND, TJ = –40 °C to 125 °C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
-3.9
-2.4
TYP MAX UNIT
ADC12 INL integral nonlinearity, end
–2/+2
4.5 LSB
2.9 LSB
(1)
point
ADC12 INL integral nonlinearity, best fit
-
1.5/+1.
5
ADC_SAMPLING_SEL = 6 for all ADC12 data,
25 to 125 °C
–0.8/+2
.9
(1)
ADC12 DNL differential nonlinearity
LSB
ADC Zero Scale Error
ADC Full Scale Error
Input bias
–7
7
35
mV
mV
nA
–35
2.5 V applied to pin
200
(1)
Input leakage resistance
ADC_SAMPLING_SEL= 6 or 0
1
10
MΩ
pF
(1)
Input Capacitance
ADC single sample conversion time
3.744
μs
(2)
DIGITAL INPUTS/OUTPUTS
DGND
+ 0.25
(3)
(3)
VOL
VOH
Low-level output voltage
High-level output voltage
IOH = 4 mA, V33DIO = 3 V
IOH = –4 mA, V33DIO = 3 V
V
V
V33DIO
– 0.6
VIH
VIL
IOH
IOL
High-level input voltage
Low-level input voltage
Output sinking current
Output sourcing current
V33DIO = 3 V
V33DIO = 3 V
2.1
V
V
1.1
4
mA
mA
–4
Low-level output voltage for PMBus pins
(PMBUS_CLK, PMBUS_DATA,
PMBUS_ALERT, PMBUS_CTRL)
VOL(PMB
us)
IOL = 20mA
400
mV
SYSTEM PERFORMANCE
tWD
Watchdog timeout resolution
13.1
17
22.7
6
ms
Processor master clock (MCLK)
31.25
MHz
(4)
tDelay
Digital filter delay
(1 clock = 32 ns)
TJ = 25 °C
MCLKs
Retention period of flash content (data
retention and program)
100
240
years
f(PCLK)
f(LFO)
Internal oscillator frequency
250
10
260 MHz
MHz
Internal low frequency oscillator
frequency
Flash Read
1
MCLKs
Current share current source (See 图 6-
25)
ISHARE
238
259
μA
kΩ
RSHARE Current share resistor (See 图 6-25)
POWER ON RESET AND BROWN OUT (V33A PIN, SEE 图 5-4)
9.75
10.3
VGH
VGL
Vres
Voltage Good High
2.6
2.55
0.8
V
V
V
V
Voltage Good Low
(1)
Voltage at which IReset signal is valid(1)
Brownout
Internal signal warning of brownout conditions
Voltage range of sensor
2.9
(1)
TEMPERATURE SENSOR
VTEMP
1.46
2.44
V
(2) DPWM outputs are low after reset. Other GPIO pins are configured as inputs after reset. During power up or power down, all GPIO pins
output low.
(3) The maximum total current, IOHmax and IOLmax for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop
specified. Maximum sink current per pin = –6 mA at VOL; maximum source current per pin = 6 mA at VOH
.
(4) Time from close of error ADC sample window to time when digitally calculated control effort (duty cycle) is available. This delay, which
has no variation associated with it, must be accounted for when calculating the system dynamic response.
14
Specifications
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Electrical Characteristics (continued)
V33A = V33D = V33DIO = 3V to 3.6 V; 1μF from BP18 to DGND, TJ = –40 °C to 125 °C (unless otherwise noted)
PARAMETER
Voltage resolution
TEST CONDITIONS
MIN
TYP
5.9
MAX UNIT
mV/ºC
Volts/°C
Temperature resolution
Degree C per bit
0.1034
±5
ºC/LSB
(1) (5)
Accuracy
–40 to 125 °C
–10
–40
10
ºC
ºC
μA
V
Temperature range
–40 to 125 °C
125
ITEMP
VAMB
Current draw of sensor when active
Trimmed 25 °C reading
30
Ambient temperature
1.85
ANALOG COMPARATOR
DAC Reference DAC Range
0.01953
2.478
2.5
V
Reference Voltage
Bits
2.5 2.513
V
7
bits
LSB
LSB
mV
mA
mV
mV
(1)
INL
–0.5
0.06
–19.5
–0.5
-10
0.21
0.12
19.5
1
(1)
DNL
(1)
Offset
(6)
Reference DAC buffered output load
Buffer Offset (–0.5 mA)
0.156V < DAC < 2.363V
0.059V < DAC < 2.305V
10
Buffer Offset (1.0 mA)
-10
10
(5) Ambient temperature offset value should be used from the TEMPSENCTRL register to meet accuracy.
(6) Available from reference DACs for comparators D, E, F and G.
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5.6 Timing Characteristics
V33A = V33D = V33DIO = 3.3 V; 1 μF from BP18 to DGND, TJ = –40 to 125 °C (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
250
3.9
MAX UNIT
EADC DAC
τ
Settling Time
From 10 to 90%
ns
ADC12
(1)
ADC single sample conversion time
ADC_SAMPLING_SEL= 6 or 0
μs
SYSTEM PERFORMANCE
Time to disable DPWM output based on
active FAULT pin signal
High level on FAULT pin
TJ = 25 °C
70
ns
years
ms
Retention period of flash content (data
retention and program)
100
Program time to erase one page or block
in data flash or program flash
20
30
Program time to write one word in data
flash or program flash
µs
Sync-in/sync-out pulse width
Flash Write
Sync pin
256
20
ns
μs
POWER ON RESET AND BROWN OUT (V33D PIN, SEE 图 5-4
Time delay after Power is good or RESET*
relinquished
tPOR
1
ms
ms
The time it takes from the device to exit a IRESET goes from a low state to a high state.
reset state and begin executing program This is approximately equivalent to toggling the
tEXC1
9.5
(1)
flash bank 1 (32 kB).
external reset pin from low to high state.
The time it takes from the device to exit a IRESET goes from a low state to a high state.
tEXC2
reset state and begin executing program This is approximately equivalent to toggling the
19
19
ms
ms
(1)
flash bank 2 (32 kB).
external reset pin from low to high state.
The time it takes from the device to exit a IRESET goes from a low state to a high state.
tEXCT
reset state and begin executing the total This is approximately equivalent to toggling the
(1)
program flash (64 kB).
external reset pin from low to high state.
(1)
TEMPERATURE SENSOR
tON
Turn on time / settling time of sensor
100
μs
ANALOG COMPARATOR
Time to disable DPWM output based on
0 V to 2.5 V step input on the analog
comparator.
150
ns
(1)
(1) Characterized by design and not production tested.
16
Specifications
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5.7 PMBus/SMBus/I2C Timing
The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus,
and PMBus in Slave or Master mode are shown in 表 5-1, 图 5-1, and 图 5-2. The numbers in 表 5-1
shows that the device supports standard (100 kHz), fast (400 kHz), and fast-mode plus (1 MHz) speeds.
表 5-1. I2C/SMBus/PMBus Timing Characteristics
100 kHz Class
MIN MAX
400 kHz Class
1 MHz Class
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
Typical values at TA = 25 °C and VCC = 3.3 V (unless otherwise noted)
SMBus/PMBus
operating
frequency
Slave mode, SMBC 50%
duty cycle
fSMB
10
10
100
100
10
10
400
400
10
10
1000
1000
kHz
kHz
µs
I2C operating
frequency
Slave mode, SCL 50% duty
cycle
fI2C
Bus free time
between start and
stop(1)
t(BUF)
4.7
1.3
0.5
Hold time after
t(HD:STA)
t(SU:STA)
4
0.6
0.6
0.26
0.26
µs
µs
(repeated) start(1)
Repeated start
setup time(1)
4.7
t(SU:STO)
t(HD:DAT)
t(SU:DAT)
Stop setup time(1)
4
0
0.6
0
0.26
0
µs
ns
ns
Data hold time
Receive mode
Data setup time
250
100
50
Error
t(TIMEOUT)
t(LOW)
25
4.7
4
35
25
1.3
0.6
35
25
0.5
35
ms
µs
µs
signal/detect(2)
Clock low period
Clock high
period(3)
t(HIGH)
50
25
50
25
0.26
50
25
Cumulative clock
t(LOW:SEXT) low slave extend
ms
ns
time(4)
20
+ 0.1
Cb(5)
20
+ 0.1
Cb(5)
20
+ 0.1
Cb(5)
Rise time tr = (VILmax
0.15) to (VIHmin + 0.15)
–
tr
Clock/data fall time
300
300
120
120
20
+ 0.1
Cb(5)
20
+ 0.1
Cb(5)
20
+ 0.1
Cb(5)
Clock/data rise
time
Fall time tf = 0.9 VDD to
(VILmax – 0.15)
tf
1000
300
400
ns
Total capacitance
of one bus line
Cb
pF
(1) Fast mode, 400 kHz
(2) The device times out when any clock low exceeds t(TIMEOUT)
.
(3) t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction that is in progress. This
specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0] = 0).
(4) t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(5) Cb (pF)
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图 5-1. I2C/SMBus/PMBus Timing Diagram
图 5-2. Bus Timing in Extended Mode
5.8 Parametric Measurement Information
ADC output code
INL, Best fit
Actual ADC Transfer Function
INL, End Point
Best Fit Line
Line Connecting Actual Zero
Scale Point and Actual Full
Scale Point
ADC input voltage
图 5-3. Best Fit INL and End Point INL
18
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V33D
3.3 V
Brown Out
VGH
VGL
Vres
t
TPOR
TPOR
IReset
t
undefined
图 5-4. Power On Reset (POR) / Brown Out Reset (BOR)
VGH
– This is the V33A threshold where the internal power is declared good. The UCD3138064A
comes out of reset when above this threshold.
VGL
Vres
– This is the V33A threshold where the internal power is declared bad. The device goes into
reset when below this threshold.
– This is the V33A threshold where the internal reset signal is no longer valid. Below this
threshold the device is in an indeterminate state.
IReset
TPOR
– This is the internal reset signal. When low, the device is held in reset. This is equivalent to
holding the reset pin on the IC low.
– The time delay from when VGH is exceeded to when the device comes out of reset.
Brown
Out
– This is the V33A voltage threshold at which the device sets the brown out status bit. In
addition an interrupt can be triggered if enabled.
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5.9 Typical Characteristics
(Data is taken from the UCD3138)
ADC12 Measurement Temperature Sensor Voltage
2.1
2
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.9
1.8
1.7
1.6
−40
−20
0
20
40
Temperature (°C)
60
80
100
120
−60 −40 −20
0
20 40 60 80 100 120 140 160
Temperature (°C)
图 5-6. ADC12 Measurement Temperature Sensor VoltagGe00v6bs
G005a
图 5-5. EADC LSB Size with 4X Gain (mV) vs Temperature
Temperature
ADC12 2.5-V Reference
ADC12 Temperature Sensor Measurement Error
8
2.515
2.510
2.505
2.500
6
4
2
2.495
2.490
2.485
0
−2
−4
2.480
2.475
−40
−20
0
20
40
60
Temperature (°C)
80
100
120
−40
−20
0
20
40
60
80
100
120
G002b
Temperature (°C)
G003b
图 5-8. ADC12 Temperature Sensor Measurement Error vs
图 5-7. ADC12 2.5-V Reference vs Temperature
Temperature
2.08
2.06
3 σ
1 σ
AVG
-1 σ
-3 σ
2.04
2.02
2
1.98
1.96
1.94
1.92
-100
-50
0
50
100
150
200
Temperature (°C)
图 5-9. Oscillator Frequency (2MHz Reference, Divided Down from 250MHz) vs Temperature
20
Specifications
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6.00
5.00
4.00
3.00
2.00
1.00
0.00
DPWM
ADC12
Front-end Control Peak Current
Mode
Timer
Filter
Constant
Power/Constant
Current
SCI
GIO
C001
Module
图 5-10. Clock Gating Power Savings
The power disable control register provides control bits that can enable or disable the clock to several
peripherals such as, PCM, CPCC, digital filters, front ends, DPWMs, UARTs, ADC-12 and more.
By default, all these controls are enabled. If a specific peripheral is not used the clock gate can be
disabled in order to block the propagation of the clock signal to that peripheral and therefore reduce the
overall current consumption of the device. The power savings chart displays the power savings per
module. For example there are 4 DPWM modules, therefore, if all 4 are disabled a total of ~20 mA can be
saved.
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6 Detailed Description
6.1 Overview
The UCD3138064A family is a digital power supply controller from Texas Instruments offering superior
levels of integration and performance in a single chip solution. The flexible nature of the UCD3138064A
family makes it suitable for a wide variety of power conversion applications. Multiple peripherals inside the
device have been specifically optimized to enhance the performance of AC/DC and isolated DC/DC
applications and reduce the solution component count in the IT and network infrastructure space. The
UCD3138064A family is a fully programmable solution offering customers complete control of their
application, along with ample ability to differentiate their solution.
6.2 ARM Processor
The ARM7TDMI-S processor is a synthesizable member of the ARM family of general purpose 32-bit
microprocessors. The ARM architecture is based on RISC (Reduced Instruction Set Computer) principles
where two instruction sets are available: the 32-bit ARM instruction set and the 16-bit Thumb instruction
set. The Thumb instructions allow for higher code density equivalent to a 16-bit microprocessor, with the
performance of the 32-bit microprocessor.
The three-staged pipelined ARM processor has fetch, decode and execute stage architecture. Major
blocks in the ARM processor include a 32-bit ALU, 32 x 8 multiplier, and a barrel shifter.
6.3 Memory
The UCD3138064A (ARM7TDMI-S) is a Von-Neumann architecture, where a single bus provides access
to all of the memory modules. All of the memory module addresses are sequentially aligned along the
same address range.
Within the UCD3138064A family architecture, there is a 1024x32-bit Boot ROM that contains the initial
firmware startup routines for PMBUS communication and non-volatile (FLASH) memory download. This
boot ROM is executed after power-up-reset checks if there is a valid FLASH program written. If a valid
program is present, the ROM code branches to the main FLASH-program execution. If there is no valid
program, the device waits for a program download through the PMBus.
The UCD3138064A family also supports customization of the boot program by allowing an alternative boot
routine to be executed from program FLASH. This feature enables assignment of a unique address to
each device; therefore, enabling firmware reprogramming even when several devices are connected on
the same communication bus.
There are three separate flash memory areas present inside the device. There are 2-32 kB program flash
blocks and 1-2 kB data flash area. The 32 kB program areas are organized as 8 k x 32 bit memory blocks
and are intended to be for the firmware programs. The blocks are configured with page erase capability for
erasing blocks as small as 1 kB per page, or with a mass erase for erasing the entire 32 kB array. The
flash endurance is specified at 1000 erase/write cycles and the data retention is good for 100 years. The 2
kB data flash array is organized as a 512 x 32 bit memory (32 byte page size). The data flash is intended
for firmware data value storage and data logging. Thus, the Data flash is specified as a high endurance
memory of 20 k cycles with embedded error correction code (ECC).
For run time data storage and scratchpad memory, a 8 kB RAM is available. The RAM is organized as a 2
k x 32 bit array. The availability of 64 kB of program Flash memory in 2-32 kB banks, enables designers to
implement multiple images of firmware (e.g. one main image + one back-up image) in the device and the
flexibility to execute from either of the banks using appropriate algorithms. It also creates the unique
opportunity for the processor to load a new program and subsequently execute that program without
interrupting power delivery. This feature allows the end user to add new features to the power supply while
eliminating any down-time required to load the new program.
22
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6.4 Feature Description
6.4.1 System Module
The System Module contains the interface logic and configuration registers to control and configure all the
memory, peripherals and interrupt mechanisms. The blocks inside the system module are the address
decoder, memory management controller, system management unit, central interrupt unit, and clock
control unit.
6.4.1.1 Address Decoder (DEC)
The Address Decoder generates the memory selects for the FLASH, ROM and RAM arrays. The memory
map addresses are selectable through configurable register settings. These memory selects can be
configured from 1 kB to 16 MB. Power on reset uses the default addresses in the memory map for ROM
execution, which is then configured by the ROM code to the application setup. During access to the DEC
registers, a wait state is asserted to the CPU. DEC registers are only writable in the ARM privilege mode
for user mode protection.
6.4.1.2 Memory Management Controller (MMC)
The MMC manages the interface to the peripherals by controlling the interface bus for extending the read
and write accesses to each peripheral. The unit generates eight peripheral select lines with 1 kB of
address space decoding.
6.4.1.3 System Management (SYS)
The SYS unit contains the software access protection by configuring user privilege levels to memory or
peripherals modules. It contains the ability to generate fault or reset conditions on decoding of illegal
address or access conditions. A clock control setup for the processor clock (MCLK) speed, is also
available.
6.4.1.4 Central Interrupt Module (CIM)
The CIM accepts 32 interrupt requests for meeting firmware timing requirements. The ARM processor
supports two interrupt levels: FIQ and IRQ. FIQ is the highest priority interrupt. The CIM provides
hardware expansion of interrupts by use of FIQ/IRQ vector registers for providing the offset index in a
vector table. This numerical index value indicates the highest precedence channel with a pending interrupt
and is used to locate the interrupt vector address from the interrupt vector table. Interrupt channel 0 has
the lowest precedence and interrupt channel 31 has the highest precedence. To remove the interrupt
request, the firmware should clear the request as the first action in the interrupt service routine. The
request channels are maskable, allowing individual channels to be selectively disabled or enabled.
表 6-1. Interrupt Priority Table
MODULE COMPONENT OR
REGISTER
NAME
DESCRIPTION
PRIORITY
BRN_OUT_INT
EXT_INT
Brownout
Brownout interrupt
0 (Lowest)
External Interrupts
Watchdog Control
Interrupt on external input pin
Interrupt from watchdog exceeded (reset)
1
2
WDRST_INT
Wake-up interrupt when watchdog equals half of set watch
time
WDWAKE_INT
Watchdog Control
3
SCI_ERR_INT
SCI_RX_0_INT
SCI_TX_0_INT
SCI_RX_1_INT
SCI_TX_1_INT
PMBUS_INT
UART or SCI Control
UART or SCI Control
UART or SCI Control
UART or SCI Control
UART or SCI Control
UART or SCI error Interrupt. Frame, parity or overrun
UART0 RX buffer has a byte
4
5
UART0 TX buffer empty
6
UART1 RX buffer has a byte
7
UART1 TX buffer empty
8
PMBus related interrupt
9
DIG_COMP_SPI_I2C_INT 12-bit ADC Control, SPI, I2C
Digital comparator, SPI and I2C interrupt
10
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表 6-1. Interrupt Priority Table (continued)
MODULE COMPONENT OR
REGISTER
NAME
DESCRIPTION
PRIORITY
“Prebias complete”, “Ramp Delay Complete”, “Ramp
Complete”, “Load Step Detected”,
FE0_INT
Front End 0
11
“Over-Voltage Detected”, “EADC saturated”
“Prebias complete”, “Ramp Delay Complete”, “Ramp
Complete”, “Load Step Detected”,
“Over-Voltage Detected”, “EADC saturated”
FE1_INT
FE2_INT
Front End 1
Front End 2
12
13
“Prebias complete”, “Ramp Delay Complete”, “Ramp
Complete”, “Load Step Detected”,
“Over-Voltage Detected”, “EADC saturated”
PWM3_INT
16-bit Timer PWM 3
16-bit Timer PWM 2
16-bit Timer PWM 1
16-bit timer PWM 0
24-bit Timer Control
DTC Fault Interrupt
16-bit Timer PWM3 counter overflow or compare interrupt
16-bit Timer PWM2 counter Overflow or compare interrupt
16-bit Timer PWM1 counter overflow or compare interrupt
16-bit Timer PWM0 counter overflow or compare interrupt
24-bit Timer counter overflow interrupt
14
15
16
17
18
19
20
21
22
PWM2_INT
PWM1_INT
PWM0_INT
OVF24_INT
DTC_FLT_INT
Reserved for future use
CAPTURE_0_INT
COMP_0_INT
DTC module fault interrupt
24-bit Timer Control
24-bit Timer Control
24-bit Timer capture 0 interrupt
24-bit Timer compare 0 interrupt
Constant Power Constant Current Mode switched in CPCC module Flag needs to be read for
CPCC_RTC_INT
ADC_CONV_INT
23
24
or Real Time Clock Output
details. RTC timer output generates an interrupt.
12-bit ADC Control
ADC end of conversion interrupt
Analog comparator interrupts, Over-Voltage detection,
Under-Voltage detection,
FAULT_INT
Fault Mux Interrupt
25
LLM load step detection
DPWM3
DPWM2
DPWM3
DPWM2
Same as DPWM1
Same as DPWM1
26
27
1) Every (1-256) switching cycles
2) Fault Detection
DPWM1
DPWM1
28
3) Mode switching
DPWM0
DPWM0
Same as DPWM1
29
30
EXT_FAULT_INT
SYS_SSI_INT
External Faults
System Software
Fault pin interrupt
System software interrupt
31 (highest)
6.4.2 Peripherals
6.4.2.1 Digital Power Peripherals
At the core of the UCD3138x controller are 3 Digital Power Peripherals (DPP). Each DPP can be
configured to drive from one to eight DPWM outputs. Each DPP consists of:
•
•
•
Differential input error ADC (EADC) with sophisticated controls
Hardware accelerated digital 2-pole/2-zero PID based filter
Digital PWM module with support for a variety of topologies
These can be connected in many different combinations, with multiple filters and DPWMs. They are
capable of supporting functions like input voltage feed forward, current mode control, and constant
current/constant power, etc.. The simplest configuration is shown in 图 6-1:
EAP
DPWMA
Digital
PWM
Error ADC
(Front End)
Filter
DPWMB
EAN
图 6-1. Simple Digital Power Configuration
24
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6.4.2.1.1 Front End
图 6-2 shows the block diagram of the front end module. It consists of a differential amplifier, an adjustable
gain error amplifier, a high speed flash analog to digital converter (EADC), digital averaging filters and a
precision high resolution set point DAC reference. The programmable gain amplifier in concert with the
EADC and the adjustable digital gain on the EADC output work together to provide 9 bits of range with 6
bits of resolution on the EADC output. The output of the Front End module is a 9 bit sign extended result
with a gain of 1 LSB / mV. Depending on the value of AFE selected, the resolution of this output could be
either 1, 2, 4 or 8 LSBs. In addition Front End 0 has the ability to automatically select the AFE value such
that the minimum resolution is maintained that still allows the voltage to fit within the range of the
measurement. The EADC control logic receives the sample request from the DPWM module for initiating
an EADC conversion. EADC control circuitry captures the EADC-9-bit-code and strobes the filter for
processing of the representative error. The set point DAC has 10 bits with an additional 4 bits of dithering
resulting in an effective resolution of 14 bits. This DAC can be driven from a variety of sources to facilitate
things like soft start, nested loops, etc. Some additional features include the ability to change the polarity
of the error measurement and an absolute value mode which automatically adds the DAC value to the
error.
It is possible to operate the controller in a peak current mode control configuration. In this mode topologies
like the phase shifted full bridge converter can be controlled to maintain transformer flux balance. The
internal DAC can be ramped at a synchronously controlled slew rate to achieve a programmable slope
compensation. This eliminates the sub-harmonic oscillation as well as improves input voltage feed-forward
performance. A0 is a unity gain buffer used to isolate the peak current mode comparator. The offset of this
buffer is specified in the Electrical Characteristics table.
EAP
Front End Differential
Amplifier
REA
IOFFSET
AGND
EAN
REA
IOFFSET
AGND
图 6-2. Input Stage Of EADC Module
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AFE_GAIN
23-AFE_GAIN
EAP0
EAN0
6 bit ADC
8mV/LSB
Signed 9 bit result
(error) 1 mV /LSB
2AFE_GAIN
EADC
X
Averaging
SAR/Prebias
Ramp
Filter x
CPCC
DAC0
A0
10 bit DAC
1.5625mV/LSB
ꢁ
Value
Dither
4 bit dithering gives 14 bits of effective resolution
97.65625ꢀV/LSB effective resolution
Absolute Value
Calculation
10 bit result
1.5625mV/LSB
Peak Current
Detected
Peak Current Mode
Comparator
图 6-3. Front End Module
6.4.2.1.2 DPWM Module
The DPWM module represents one complete DPWM channel with 2 independent outputs, A and B.
Multiple DPWM modules within the UCD3138x system can be configured to support all key power
topologies. DPWM modules can be used as independent DPWM outputs, each controlling one power
supply output voltage rail. It can also be used as a synchronized DPWM—with user selectable phase shift
between the DPWM channels to control power supply outputs with multiphase or interleaved DPWM
configurations.
The output of the filter feeds the high resolution DPWM module. The DPWM module produces the pulse
width modulated outputs for the power stage switches. The filter calculates the necessary duty ratio as a
24-bit number in Q23 fixed point format (23 bit integer with 1 sign bit). This represents a value within the
range 0.0 to 1.0. This duty ratio value is used to generate the corresponding DPWM output ON time. The
resolution of the DPWM ON time is 250 psec.
Each DPWM module can be synchronized to another module or to an external synchronization signal. An
input SYNC signal causes a DPWM ramp timer to reset. The SYNC signal outputs—from each of the four
DPWM modules—occur when the ramp timer crosses a programmed threshold. This allows the phase of
the DPWM outputs for multiple power stages to be tightly controlled.
The DPWM logic takes the output of the filter and converts it into the correct DPWM output for several
power supply topologies. It provides for programmable dead times and cycle adjustments for current
balancing between phases. It controls the triggering of the EADC. It can synchronize to other DPWMs or
to external sources. It can provide synchronization information to other DPWMs or to external recipients.
In addition, it interfaces to several fault handling circuits. Some of the control for these fault handling
circuits is in the DPWM registers. Fault handling is covered in the Fault Mux section.
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Each DPWM module supports the following features:
•
•
•
Dedicated 14 bit time-base with period and frequency control
Shadow period register for end of period updates.
Quad-event control registers (A and B, rising and falling) (Events 1-4)
–
Used for on/off DPWM duty ratio updates.
•
•
•
•
•
•
•
•
Phase control relative to other DPWM modules
Sample trigger placement for output voltage sensing at any point during the DPWM cycle.
Support for 2 independent edge placement DPWM outputs (same frequency or period setting)
Dead-time between DPWM A and B outputs
High Resolution PWM capability – 250 ps
Pulse cycle adjustment of up to ±8.192 µs ( 32768 × 250 ps)
Active high/ active low output polarity selection
Provides events to trigger both CPU interrupts and start of ADC12 conversions.
6.4.2.1.3 DPWM Events
Each DPWM can control the following timing events:
1. Sample Trigger Count–This register defines where the error voltage is sampled by the EADC in
relationship to the DPWM period. The programmed value set in the register should be one fourth of the
value calculated based on the DPWM clock. As the DCLK (DCLK = 62.5 MHz max) controlling the
circuitry runs at one fourth of the DPWM clock (PCLK = 250MHz max). When this sample trigger count
is equal to the DPWM Counter, it initiates a front end calculation by triggering the EADC, resulting in a
CLA calculation, and a DPWM update. Over-sampling can be set for 2, 4 or 8 times the sampling rate.
2. Phase Trigger Count–count offset for slaving another DPWM (Multi-Phase/Interleaved operation).
3. Period–low resolution switching period count. (count of PCLK cycles)
4. Event 1–count offset for rising DPWM A event. (PCLK cycles)
5. Event 2–DPWM count for falling DPWM A event that sets the duty ratio. Last 4 bits of the register are
for high resolution control. Upper 14 bits are the number of PCLK cycle counts.
6. Event 3–DPWM count for rising DPWM B event. Last 4 bits of the register are for high resolution
control. Upper 14 bits are the number of PCLK cycle counts.
7. Event 4–DPWM count for falling DPWM B event. Last 4 bits of the register are for high resolution
control. Upper 14 bits are the number of PCLK cycle counts.
8. Cycle Adjust–Constant offset for Event 2 and Event 4 adjustments.
Basic comparisons between the programmed registers and the DPWM counter can create the desired
edge placements in the DPWM. High resolution edge capability is available on Events 2, 3 and 4.
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Multi Mode Open Loop
Start of Period
Period
Start of Period
Period Counter
DPWM Output A
Event 1
Event 2 (High Resolution)
Cycle Adjust A (High Resolution)
Sample Trigger 1
To Other
Modules
Blanking A Begin
Blanking A End
DPWM Output B
Event 3 (High Resolution)
Event 4 (High Resolution)
Cycle Adjust B (High Resolution)
Sample Trigger 2
Blanking B Begin
To Other
Modules
Blanking B End
Phase Trigger
Events which change with DPWM mode:
DPWM A Rising Edge = Event 1
DPWM A Falling Edge = Event 2 + Cycle Adjust A
DPWM B Rising Edge = Event 3
DPWM B Falling Edge = Event 4 + Cycle Adjust B
Phase Trigger = Phase Trigger Register value
Events always set by their registers, regardless of mode:
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B Begin,
Blanking B End
图 6-4. Multi Mode Open Loop
图 6-4 is for multi-mode, open loop. Open loop means that the DPWM is controlled entirely by its own
registers, not by the filter output. In other words, the power supply control loop is not closed.
The Sample Trigger signals are used to trigger the Front End to sample input signals. The Blanking
signals are used to blank fault measurements during noisy events, such as FET turn on and turn off.
Additional DPWM modes are described below.
28
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6.4.2.1.4 High Resolution DPWM
Unlike conventional PWM controllers where the frequency of the clock dictates the maximum resolution of
PWM edges, the UCD3138x DPWM can generate waveforms with resolutions as small as 250 ps. This is
16 times the resolution of the clock driving the DPWM module.
This is achieved by providing the DPWM mechanism with 16 phase shifted clock signals of 250 MHz
each.
6.4.2.1.5 Over Sampling
The DPWM module has the capability to trigger an over sampling event by initiating the EADC to sample
the error voltage. The default “00” configuration has the DPWM trigger the EADC once based on the
sample trigger register value. The over sampling register has the ability to trigger the sampling 2, 4 or 8
times per PWM period. Thus the time the over sample happens is at the divide by 2, 4, or 8 time set in the
sampling register. The “01” setting triggers 2X over sampling, the “10” setting triggers 4X over sampling,
and the “11” triggers over sampling at 8X.
6.4.2.1.6 DPWM Interrupt Generation
The DPWM has the capability to generate a CPU interrupt based on the PWM frequency programmed in
the period register. The interrupt can be scaled by a divider ratio of up to 255 for developing a slower
interrupt service execution loop. This interrupt can be fed to the ADC circuitry for providing an ADC12
trigger for sequence synchronization. 表 6-2 outlines the divide ratios that can be programmed.
6.4.2.1.7 DPWM Interrupt Scaling/Range
表 6-2. DPWM Interrupt Divide Ratio
NUMBER OF 32
INTERRUPT
DIVIDE
SETTING
INTERRUPT
DIVIDE
COUNT
INTERRUPT
DIVIDE
COUNT (HEX)
SWITCHING PERIOD
FRAMES (assume
1MHz loop)
MHZ
PROCESSOR
CYCLES
1
2
0
1
00
01
03
07
0F
1F
2F
3F
4F
5F
7F
9F
BF
DF
FF
1
2
32
64
3
3
4
128
4
7
8
256
5
15
31
47
63
79
95
127
159
191
223
255
16
32
48
64
80
96
128
160
192
224
256
512
6
1024
1536
2048
2560
3072
4096
5120
6144
7168
8192
7
8
9
10
11
12
13
14
15
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6.4.3 Synchronous Rectifier Dead Time Optimization Peripheral
The UCD3138064A has an advanced dead time control interface where it can accept UCD7138 output
signals and optimize SR gate driver signals accordingly. The UCD7138 low-side MOSFET driver is a high-
performance driver for secondary-side synchronous rectification (SR) with body diode conduction sensing.
The device is suitable for high power high efficiency isolated converter applications where dead-time
optimization is desired. The UCD7138 gate driver is a companion device to UCD3138064A highly
integrated digital controller for isolated power.
UCD3138064A
Rising edge
optimization
control
UCD7138
CTRL
IN
SR1 DPWM
SR2 DPWM
6
4
5
1
2
3
DPWM
module
Thermal Pad
(GND)
DTC
VCC
OUT
VD
SR1
Dead Time
Control
Computation
Engine
Rising edge
optimization
control
UCD7138
IN
CTRL
OUT
6
4
5
1
2
3
DTC0
DTC1
Thermal Pad
(GND)
SR2
DTC
VCC
Decoder
VD
图 6-5. Synchronous Rectifier Peripheral use with Synchronous Rectifier Driver
DTC0 and DTC1 are received body diode conduction inputs from UCD7138. SR0_DPWM and
SR1_DPWM are the DPWM waveforms for the SRs. The red and green edges are moving edges
controlled by both the filter output and the DTC interface. In each cycle, right after the falling edge of the
SR DPWM waveform, a body diode conduction time detection window is generated. The detection window
is defined by both DETECT_BLANK and DETECT_LEN registers. During this detection window, a 4-ns
timer capture counts how long the body diode conducts. Then the DPWM turn off edge of the next cycle is
adjusted accordingly.
{w0_ 5tía
!5WÜ{Ç
{w1_ 5tía
5Ç/0
!5WÜ{Ç
59Ç9/Ç
59Ç9/Ç
59Ç9/Ç
59Ç9/Ç
5Ç/1
59Ç9/Ç_ .[!bY
59Ç9/Ç_[9b
图 6-6. Timing Diagram of the DTC Interface
图 6-7 shows how the turn-off edge is adjusted based on the DTC measurement of the previous cycle.
The A_ADJ and B_ADJ registers in DTCMONITOR are signed accumulators; default value is 0.
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!_/bÇ or ._/bÇ vꢀlue
127
Lf in aꢀnuꢀl /onꢁrol aode
P = aꢀnuꢀl /onꢁrol regisꢁer vꢀlue
P = 1
P = 0
9lse if !_/bÇ or ._/bÇ < C[Ç_ÇIw9{I
P = C[Ç_{Ç9t
Ç!wD9Ç_hCC{9Ç
Ç!wD9Ç_[hí
9lse if !_/bÇ or ._/bÇ < Ç!wD9Ç_[hí
P = - 1
9lse if !_/bÇ or ._/bÇ > Ç!wD9Ç_[hí + Ç!wD9Ç_hCC{9Ç
P = 1
P = - 1
9lse
P = 0
C[Ç_ÇIw9{I
P = C[Ç_{Ç9t
图 6-7. DTC Interface Principle
Based on the DTC measured, in the next cycle:
•
•
A_ADJ = A_ADJ + A_∆
A_ADJ = A_ADJ + B_∆
In each cycle, the A_ADJ and B_ADJ accumulator values are dynamically adjust the dead time. The ∆
value changes after the measured body diode conduction time. A_ADJ and B_ADJ have been measured
and compared to the threshold values in automatic control mode. A_ADJ and B_ADJ can be controlled by
firmware while in manual control mode.
Other figures of this peripheral include negative current fault protection, consecutive fault counter, DTC
input multiplexor, etc. For details, refer to the programmer's manual.
6.4.4 Automatic Mode Switching
Automatic Mode switching enables the DPWM module to switch between modes automatically, with no
firmware intervention. This is useful to increase efficiency and power range. The following paragraphs
describe phase-shifted full bridge and LLC examples.
6.4.4.1 Phase Shifted Full Bridge Example
In phase shifted full bridge topologies, efficiency can be increased by using pulse width modulation, rather
than phase shift, at light load. This is shown in 图 6-8 below:
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DPWM3A
(QB1)
DPWM3B
(QT1)
DPWM2A
(QT2)
DPWM2B
(QB2)
VTrans
DPWM1B
(QSYN1,3)
DPWM0B
(QSYN2,4)
IPRI
图 6-8. Phase-Shifted Full Bridge Waveforms
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L1
T1
Q7
+12V
Q6
Q5
C1
RL
VBUS
I_pri
PRIM
CURRENT
ORING
CTL
T2
VOUT
C2
R2
D1
T1
QT2
QB2
QT1
Lr
VA
Current
Sensing
QB1
D2
DPWM0B
DPWM1B
Vref
DPWM0
Duty for mode
switching
Vout
Iout
CPCC
<
EADC0
EADC1
CLA0
DPWM1
DPWM2
CLA1
DPWM2A
DPWM2B
Load Current
DPWM3A
DPWM3B
I_pri
EADC2
DPWM3
PCM
AD00
AD01
ISOLATED
GATE Transformer
ACFAIL_IN
FAULT 0
FAULT 1
FAULT 2
SYNCHRONOUS
GATE DRIVE
ACFAIL_OUT
FAILURE
AD02/CMP0
AD03/CMP1/CMP2
AD04/CMP3
AD05/CMP4
AD06/CMP5
AD07/CMP6
AD08
I_SHARE
Vout
FAULT
GPIO1
GPIO2
GPIO3
ORING_CRTL
ON/OFF
Iout
I_pri
CBC
temp
P_GOOD
Vin
VA
WD
ARM7
AD09
PMBus
UART0
RST
OSC
Primary
UART1
Memory
图 6-9. Secondary-Referenced Phase-Shifted Full Bridge Control With Synchronous Rectification
6.4.4.2 LLC Example
In LLC, three modes are used. At the highest frequency, a pulse width modulated mode (Multi Mode) is
used. As the frequency decreases, resonant mode is used. As the frequency gets still lower, the
synchronous MOSFET drive changes so that the on-time is fixed and does not increase. In addition, the
LLC control supports cycle-by-cycle current limiting. This protection function operates by a comparator
monitoring the maximum current during the DPWMA conduction time. Any time this current exceeds the
programmable comparator reference the pulse is immediately terminated. Due to classic instability issues
associated with half-bridge topologies it is also possible to force DPWMB to match the truncated pulse
width of DPWMA. The waveforms for the LLC are shown in 图 6-10:
PWM
Mode
LLC Mode
fr
fs= fr_max
fs< fr
fs> fr
Q1T
Q1B
QSR1
QSR2
Tr= 1/fr
Tr= 1/fr
ISEC(t)
图 6-10. LLC Waveforms
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VBUS
Q1T
ILR(t)
Transformer
QSR2
LRES
LK
NS
NS
Driver
DPWM1B
ISEC(t)
Oring Circuitry
RLRES
Q1B
ILM(t)
LM
VOUT
NP
RF1
RF2
AD03
COUT1
COUT2
EAP0
VOUT(t)
VBUS
ESR1
ESR2
CF
QSR1
EAN0
AD04
CRES
RS
Driver
DPWM1A
CS
CRES
VCR(t)
RS1
RS2
ADC13
EAP1
Driver
Driver
DPWM0B
DPWM0A
图 6-11. Secondary-Referenced Half-Bridge Resonant LLC Control With Synchronous Rectification
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6.4.4.3 Mechanism For Automatic Mode Switching
The UCD3138064A allows the customer to enable up to two distinct levels of automatic mode switching.
These different modes are used to enhance light load operation, short circuit operation and soft start.
Many of the configuration parameters for the DPWM are in DPWM Control Register 1. For automatic
mode switching, some of these parameters are duplicated in the Auto Config Mid and Auto Config High
registers.
If automatic mode switching is enabled, the filter duty signal is used to select which of these three
registers is used. There are 4 registers which are used to select the points at which the mode switching
takes place. They are used as shown in 图 6-12 below.
Automatic Mode Switching
With Hysteresis
Filter Duty
Full Range
Auto Config High
High – Upper Threshold
High – Lower Threshold
Auto Config Mid
Low – Upper Threshold
Low – Lower Threshold
Control
Register 1
0
图 6-12. Automatic Mode Switching
As shown, the registers are used in pairs for hysteresis. The transition from Control Register 1 to Auto
Config Mid only takes place when the Filter Duty goes above the Low Upper threshold. It does not go
back to Auto Config Mid until the Low Lower Threshold is passed. This prevents oscillation between
modes if the filter duty is close to a mode switching point.
6.4.5 DPWMC, Edge Generation, IntraMux
The UCD3138064A has hardware for generating complex waveforms beyond the simple DPWMA and
DPWMB waveforms already discussed – DPWMC, the Edge Generation Module, and the IntraMux.
DPWMC is a signal inside the DPWM logic. It goes high at the Blanking A begin time, and low at the
Blanking A end time.
The Edge Gen module takes DPWMA and DPWMB from its own DPWM module, and the next one, and
uses them to generate edges for two outputs. For DPWM3, the DPWM0 is considered to be the next
DPWM. Each edge (rising and falling for DPWMA and DPWMB) has 8 options which can cause it.
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The options are:
0 = DPWM(n) A Rising edge
1 = DPWM(n) A Falling edge
2 = DPWM(n) B Rising edge
3 = DPWM(n) B Falling edge
4 = DPWM(n+1) A Rising edge
5 = DPWM(n+1) A Falling edge
6 = DPWM(n+1) B Rising edge
7 = DPWM(n+1) B Falling edge
Where “n" is the numerical index of the DPWM module of interest. For example n=1 refers to DPWM1.
The Edge Gen is controlled by the DPWMEDGEGEN register. It also has an enable/disable bit.
The IntraMux is controlled by the Auto Config registers. Intra Mux is short for intra multiplexer. The
IntraMux takes signals from multiple DPWMs and from the Edge Gen and combines them logically to
generate DPWMA and DPWMB signals This is useful for topologies like phase-shifted full bridge,
especially when they are controlled with automatic mode switching. Of course, it can all be disabled, and
DPWMA and DPWMB will be driven as described in the sections above. If the Intra Mux is enabled, high
resolution must be disabled, and DPWM edge resolution goes down to 4 ns.
图 6-13 shows the Edge Gen/Intra Mux:
A/B/C (N)
A/B/C (N+1)
INTRAMUX
C (N+2)
C (N+3)
PWM A
PWM B
EDGE GEN
A(N)
B(N)
EGEN A
EGEN B
A(N+1)
B(N+1)
B SELECT
A SELECT
A ON SELECT
A OFF SELECT
B ON SELECT
B OFF SELECT
图 6-13. Edge Generation / IntraMux
Here is a list of the IntraMux modes for DPWMA:
0 = DPWMA(n) pass through (default)
1 = Edge-gen output, DPWMA(n)
2 = DPWNC(n)
3 = DPWMB(n) (Crossover)
4 = DPWMA(n+1)
5 = DPWMB(n+1)
6 = DPWMC(n+1)
7 = DPWMC(n+2)
8 = DPWMC(n+3)
and for DPWMB:
0 = DPWMB(n) pass through (default)
1 = Edge-gen output, DPWMB(n)
2 = DPWNC(n)
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3 = DPWMA(n) (Crossover)
4 = DPWMA(n+1)
5 = DPWMB(n+1)
6 = DPWMC(n+1)
7 = DPWMC(n+2)
8 = DPWMC(n+3)
The DPWM number wraps around just like the Edge Gen unit. For DPWM3 the following definitions apply:
DPWM(n)
DPWM3
DPWM0
DPWM1
DPWM2
DPWM(n+1)
DPWM(n+2)
DPWM(n+3)
6.4.6 Filter
The UCD3138064A filter is a PID filter with many enhancements for power supply control. Some of its
features include:
•
•
Traditional PID Architecture
Programmable non-linear limits for automated modification of filter coefficients based on received
EADC error
•
•
•
•
•
•
•
•
•
Multiple coefficient sets fully configurable by firmware
Full 24-bit precision throughout filter calculations
Programmable clamps on integrator branch and filter output
Ability to load values into internal filter registers while system is running
Ability to stall calculations on any of the individual filter branches
Ability to turn off calculations on any of the individual filter branches
Duty cycle, resonant period, or phase shift generation based on filter output.
Flux balancing
Voltage feed forward
The first section of the filter is shown in 图 6-14 :
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Limit Comparator
Limit 6
Limit 5
…..
PID Filter Branch Stages
Limit 0
Coefficient
select
EADC_DATA
Xn
16
24
9
24
X
P
9
9
24
16
24
24
9
9
24
24
9
+
+
X
I
24
24
Ki Low
9
24
24
X
32
9
Round
24
16
24
X –X
9
n
n-1
9
24
24
-
X
Clamp
+
D
图 6-14. First Section of the Filter
The filter input, Xn, generally comes from a front end. Then there are three branches, P, I. and D. Note
that the D branch also has a pole, Kd Alpha. Clamps are provided both on the I branch and on the D
alpha pole.
The filter also supports a nonlinear mode, where up to 7 different sets of coefficients can be selected
depending on the magnitude of the error input Xn. This can be used to increase the filter gain for higher
errors to improve transient response.
Tthe output section of the filter (S0.23 means that there is 1 sign bit, 0 integer bits and 23 fractional bits) is
shown in 图 6-15.:
Filter Yn
Clamp High
Yn Scale
Shifter
24
24
24
P
I
24
24
24
S0.23
26
Filter Yn
Saturate
Yn
Clamp
+
D
S2.23
S0.23
S0.23
Filter Yn
Clamp Low
All are S0.23
图 6-15. Output Section of the Filter
This section combines the P, I, and D sections, and provides for saturation, scaling, and clamping.
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There is a final section for the filter, shown in 图 6-16 that permits its output to be matched to the DPWM:
Filter Output
Clamp High
Round to
18 bits,
Truncate
low 4 bits
Filter Period
Bits [17:4]
Filter YN
38
18
14
X
Clamp to
Positive
Round to
18 bits,
S14.23
24
S0.23
14.4
14.0
Filter YN (Duty %)
18
Filter Duty
14.4
38
18
Clamp
X
Clamp to
Positive
24
S0.23
S14.23
14.4
KCompx 14.0
14
14.0
14.0
KCompx
DPWMx Period
Loop_VFF
14
DPWMx Period 14.0
Filter Output
Clamp Low
14.0
14.0
14.0
14.0
PERIOD_MULT_SEL
Resonant Duty
OUTPUT_MULT_SEL
图 6-16. Final Section for the Filter
This permits the filter output to be multiplied by a variety of correction factors to match the DPWM Period,
to provide for Voltage Feed Forward, or for other purposes. After this, there is another clamp. For resonant
mode, the filter can be used to generate both period and duty cycle.
6.4.6.1 Loop Multiplexer
The Loop Mux controls interconnections between the filters, front ends, and DPWMs. Any filter, front end,
and DPWM can be combined in a variety of configurations.
It also controls the following connections:
•
•
•
•
•
DPWM to Front End
Front End DAC control from Filters or Constant Current/Constant Power Module
Filter Special Coefficients and Feed Forward
DPWM synchronization
Filter to DPWM
The following control modules are configured in the Loop Mux:
•
•
•
•
•
Constant Power/Constant Current
Cycle Adjustment (Current and flux balancing)
Global Period
Light Load (Burst Mode)
Analog Peak Current Mode
6.4.6.2 Fault Multiplexer
In order to allow a flexible way of mapping several fault triggering sources to all the DPWMs channels, the
UCD3138x provides an extensive array of multiplexers that are united under the name Fault Mux module.
The Fault Mux Module supports the following types of mapping between all the sources of fault and all the
different fault response mechanisms inside each DPWM module.
•
Many fault sources may be mapped to a single fault response mechanism. For instance an analog
comparator in charge of over voltage protection, a digital comparator in charge of over current
protection and an external digital fault pin can be all mapped to a Fault-A signal connected to a single
FAULT MODULE and shut down DPWM1-A.
•
•
A single fault source can be mapped to many fault response mechanisms inside many DPWM
modules. For instance an analog comparator in charge of over current protection can be mapped to
DPWM-0 through DPWM-3 by way of several fault modules.
Many fault sources can be mapped to many fault modules inside many DPWM modules.
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CBC_PWM_AB_EN
FAULT MUX
DPWM
Bit20 in DPWMCTRL0
CYCLE BY CYCLE
ANALOG PCM
FAULT- CBC
AB FLAG
FAULT MODULE
DISABLE PWM A AND B
CBC_FAULT_EN
Bit30 in DPWMFLTCTRL
FAULT- AB
FAULT-A
FAULT-B
AB FLAG
FAULT MODULE
DISABLE PWM A AND B
DCOMP– 4X
EXT GPIO– 4X
ACOMP – 7X
A FLAG
FAULT MODULE
DISABLE PWM A ONLY
B FLAG
FAULT MODULE
DISABLE PWM B ONLY
ALL_FAULT_EN
DPWM_EN
Bit0 in DPWMCTRL0
Bit 31 in DPWMFLTCTRL
图 6-17. Fault Mux Module
The Fault Mux Module provides a multitude of fault protection functions within the UCD3138x high-speed
loop (Front End Control, Filter, DPWM and Loop Mux modules). The Fault Mux Module allows highly
configurable fault generation based on digital comparators, high-speed analog comparators and external
fault pins. Each of the fault inputs to the DPWM modules can be configured to one or any combination of
the fault events provided in the Fault Mux Module.
Each one of the DPWM engines has four fault modules. The modules are called CBC fault module, AB
fault module, A fault module and B fault module.
The internal circuitry in all the four fault modules is identical, and the difference between the modules is
limited to the way the modules are attached to the DPWMs.
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FAULT FLAG
FAULT IN
FAULT MODULE
图 6-18. Fault Module
All fault modules provide immediate fault detection but only once per DPWM switching cycle. Each one of
the fault modules own a separate max_count and the fault flag will be set only if sequential cycle-by-cycle
fault count exceeds max_count.
Once the fault flag is set, DPWMs need to be disabled by DPWM_EN going low in order to clear the fault
flags. Please note, all four Fault Modules share the same DPWM_EN control, all fault flags (output of Fault
Modules) will be cleared simultaneously.
All four Fault Modules share the same global FAULT_EN as well. Therefore a specific Fault Module
cannot be enabled/ disabled separately.
FAULT - CBC
CLIM
CYCLE BY CYCLE
图 6-19. Cycle-By-Cycle Block
Unlike Fault Modules, only one Cycle by Cycle block is available in each DPWM module.
The Cycle by Cycle block works in conjunction with CBC Fault Module and enables DPWM reaction to
signals arriving from the Analog Peak current mode (PCM) module.
The Fault Mux Module supports the following basic functions:
•
•
•
•
4 digital comparators with programmable thresholds and fault generation
Configuration for 7 high speed analog comparators with programmable thresholds and fault generation
External GPIO detection control with programmable fault generation
Configurable DPWM fault generation for DPWM Current Limit Fault, DPWM Over-Voltage Detection
Fault, DPWM A External Fault, DPWM B External Fault and DPWM IDE Flag
•
•
Clock Failure Detection for High and Low Frequency Oscillator blocks
Discontinuous Conduction Mode Detection
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HFO/LFO
Fail Detect
DCM Detection
Analog Comparator 0
Control
Analog
Comparator 0
Digital Comparator 0
Control
Front End
Control 0
Analog Comparator 1
Control
Analog
Comparator 1
Digital Comparator 1
Control
Front End
Control 1
Analog Comparator 2
Control
Analog
Comparator 2
Digital Comparator 2
Control
Analog Comparator 3
Control
Analog
Comparator 3
Front End
Control 2
Digital Comparator 3
Control
Analog Comparator 4
Control
Analog
Comparator 4
fault[2:0]
External GPIO
Detection
Analog Comparator 5
Control
Analog
Comparator 5
DPWM 0
Fault Control
DPWM 1
Fault Control
DPWM 2
Fault Control
DPWM 3
Fault Control
Analog Comparator 6
Control
Analog
Comparator 6
DPWM 0
DPWM 1
DPWM 2
DPWM 3
Analog Comparator
Automated Ramp
图 6-20. Fault Mux Block Diagram
6.4.7 Communication Ports
6.4.7.1 SCI (UART) Serial Communication Interface
A maximum of two independent Serial Communication Interface (SCI) or Universal Asynchronous
Receiver/Transmitter (UART) interfaces are included within the device for asynchronous start-stop serial
data communication (see the pin out sections for details). Each interface has a 24 bit pre-scaler for
supporting programmable baud rates, a programmable data word and stop bit options. Half or full duplex
operation is configurable through register bits. A loop back feature can also be setup for firmware
verification. Both SCI-TX and SCI-RX pin sets can be used as GPIO pins when the peripheral is not being
used.
The UART peripheral includes a hardware based auto baud rate adjustment feature. Power supply
controllers typically use temperature compensated RC based oscillators. Despite the temperature
compensation, the clock speed will change with temperature. This can lead to a difference in baud rate
between two controllers, leading to lost of communication. The UCD3138064A adds logic which can
match the receive baud rate by measuring the bit timing of the incoming signal.
In Addition, the UCD3138064A increases the resolution of the baud rate adjustment. The UCD3138064
has 512 ns resolution, while the UCD3138064A adds 3 bits and provides 64 ns resolution on the baud
rate. This makes the use ot auto baud possible at higher baud rates.
6.4.7.2 PMBUS/I2C
The PMBus interface in UCD3138064A supports both master and slave modes. The I2C interface only
supports master mode. Only one of the interfaces has control of the address pin current sources as well
as support for the optional Control and Alert lines described in the PMBus specification. Other than these
differences, the interfaces are identical.
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The PMBus/I2C interface is designed to minimize the processor overhead required for interface. It can
automatically detect and acknowledge addresses. It handles start and stop conditions automatically, and
can clock stretch until the processor has time to poll the PMBus status. It will automatically receive and
send up to 4 bytes at a time. It can automatically verify and generate a PEC. This means that a write byte
command can be received by the processor with only one function call. There is no need for any interrupts
at all with this PMBus/I2C interface. If it is polled every few milliseconds, it will work perfectly.
The interface also supports automatic ACK of two independent addresses. If both PMBus/I2C interfaces
are used at the same time a total of 4 independent addresses can be automatically detected.
Example: PMBus Address Decode via ADC12 Reading
The user can allocate 2 pins of the 12-bit ADC input channels, AD_00 and AD_01, for PMBus address
decoding. At power-up the device applies IBIAS to each address detect pin and the voltage on that pin is
captured by the internal 12-bit ADC.
Vdd
AD00,
AD01
pin
On/Off Control
I
BIAS
Resistor to
set PMBus
Address
To ADC Mux
图 6-21. PMBUS Address Detection Method
PMBus/I2C address 0x7E is a reserved address and should not be used in a system using the UCD3138x.
This address is used for manufacturing test.
6.4.7.3 SPI
The SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed
length (1 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is
normally used for communication between the UCD3138x and external peripherals. Typical applications
include an interface to external I/O or peripheral expansion via devices such as shift registers, display
drivers, SPI EPROMs and analog-to-digital converters. The SPI allows serial communication with other
SPI devices through a 3-pin or 4-pin mode interface.
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SCS
tCSS
tWH
tWL
tCSH
SCK
tSU
tH
MISO
MOSI
VALID IN
tV
tHO
VALID OUT
PSCK
tWH
tWL
tSU
tH
tV
tHO
tCSS
Period SCK
2 ICLK
1/2 PSCK
1/2 PSCK
2 ns (typical)
4 ns (typical)
4 ns (typical)
2 ns (typical)
1 PSCK
SCK High Time
SCK Low Time
Data in setup
Data in hold
Ouput Valid
Ouput Data Hold
Chip Select Setup
tCSH
Chip Select Hold
1 PSCK
图 6-22. SPI Timing Diagram
6.4.8 Timers
External to the Digital Power Peripherals there are 3 different types of timers in UCD3138x. They are the
24-bit timer, 16-bit timer and the watchdog timer
6.4.8.1 24-Bit Timer
There is one 24 bit timer which runs off the Interface Clock. It can be used to measure the time between
two events, and to generate interrupts after a specific interval. Its clock can be divided down by an 8-bit
pre-scalar to provide longer intervals. The timer has two compare registers (Data Registers). Both can be
used to generate an interrupt after a time interval. . Additionally, the timer has a shadow register (Data
Buffer register) which can be used to store CPU updates of the compare events while still using the timer.
The selected shadow register update mode happens after the compare event matches.
The two capture pins TCAP0 and TCAP1 are inputs for recording a capture event. A capture event can be
set either to rising, falling, or both edges of the capture pin signal. Upon this event, the counter value is
stored in the corresponding capture data register. Five Interrupts from the 24 bit timer can be set, which
are the counter rollover event (overflow), capture events 0 and 1, and the two comparison match events.
Each interrupt can be disabled or enabled.
6.4.8.2 16-Bit PWM Timers
There are four 16 bit counter PWM timers which run off the Interface Clock and can further be divided
down by a 8-bit pre-scaler to generate slower PWM time periods. Each timer has two compare registers
(Data Registers) for generating the PWM set/unset events. Additionally, each timer has a shadow register
(Data Buffer register) which can be used to store CPU updates of compare events while still using the
timer. The selected shadow register update mode happens after the compare event matches.
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The counter reset can be configured to happen on a counter roll over, a compare equal event, or by a
software controlled register. Interrupts from the PWM timer can be set due to the counter rollover event
(overflow) or by the two comparison match events. Each comparison match and the overflow interrupts
can be disabled or enabled.
Upon an event comparison, the PWM pin can be configured to set, clear, toggle or have no action at the
output. The value of PWM pin output can be read for status or simply configured as General Purpose I/O
for reading the value of the input at the pin.
6.4.8.3 Watchdog Timer
A watchdog timer is provided on the device for ensuring proper firmware loop execution. The timer is
clocked off of a separate low speed oscillator source. If the timer is allowed to expire, a reset condition is
issued to the ARM processor. The watchdog is reset by a simple CPU write bit to the watchdog key
register by the firmware routine. On device power-up the watchdog is disabled. Yet after it is enabled, the
watchdog cannot be disabled by firmware. Only a device reset can put this bit back to the default disabled
state. A half timer flag is also provided for status monitoring of the watchdog.
6.4.9 General Purpose ADC12
The ADC12 is a 12 bit, high speed analog to digital converter, equipped with the following options:
•
•
•
•
Typical conversion speed of 267 ksps
Conversions can consist from 1 to 16 ADC channel conversions in any desired sequence
Post conversion averaging capability, ranging from 4X, 8X, 16X or 32X samples
Configurable triggering for ADC conversions from the following sources: firmware, DPWM rising edge,
ADC_EXT_TRIG pin or Analog Comparator results
•
•
Interrupt capability to embedded processor at completion of ADC conversion
Six digital comparators on the first 6 channels of the conversion sequence using either raw ADC data
or averaged ADC data
•
•
•
Two 10 µA current sources for excitation of PMBus addressing resistors
Dual sample and hold for accurate power measurement
Internal temperature sensor for temperature protection and monitoring
The control module (图 6-23) contains the control and conversion logic for auto-sequencing a series of
conversions. The sequencing is fully configurable for any combination of 16 possible ADC channels
through an analog multiplexer embedded in the ADC12 block. Once converted, the selected channel value
is stored in the result register associated with the sequence number. Input channels can be sampled in
any desired order or programmed to repeat conversions on the same channel multiple times during a
conversion sequence. Selected channel conversions are also stored in the result registers in order of
conversion, where the result 0 register is the first conversion of a 16-channel sequence and result 15
register is the last conversion of a 16-channel sequence. The number of channels converted in a
sequence can vary from 1 to 16.
Unlike EADC0 through EADC2, which are primarily designed for closing high speed compensation loops,
the ADC12 is not usually used for loop compensation purposes. The EADC converters have a
substantially faster conversion rate, thus making them more attractive for closed loop control. The ADC12
features make it best suited for monitoring and detection of currents, voltages, temperatures and faults.
Please see 节 5.9 for the temperature variation associated with this function.
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ADC12 Block
ADC12 Registers
ADC
Averaging
12-bit SAR
ADC
S/H
ADC
Channels
ADC12
Control
Digital
Comparators
ADC Channel
ADC External Trigger (from pin)
Analog
Comparators
DPWM
Modules
图 6-23. ADC12 Control Block Diagram
6.4.10 Miscellaneous Analog
The Miscellaneous Analog Control (MAC) Registers are a catch-all of registers that control and monitor a
wide variety of functions. These functions include device supervisory features such as Brown-Out and
power saving configuration, general purpose input/output configuration and interfacing, internal
temperature sensor control and current sharing control.
The MAC module also provides trim signals to the oscillator and AFE blocks. These controls are usually
used at the time of trimming at manufacturing; therefore this document will not cover these trim controls.
6.4.11 Brownout
Brownout function is used to determine if the device supply voltage is lower than a threshold voltage, a
condition that may be considered unsafe for proper operation of the device.
The brownout threshold is higher than the reset threshold voltage; therefore, when the supply voltage is
lower than brownout threshold, it still does not necessarily trigger a device reset.
The brownout interrupt flag can be polled or alternatively can trigger an interrupt to service such case by
an interrupt service routine. Please see 图 5-4.
6.4.12 Global I/O
Up to 32 pins in UCD3138x can be configured in the Global I/O register to serve as a general purpose
input or output pins (GPIO). This includes all digital input or output pins except for the RESET pin.
The pins that cannot be configured as GPIO pins are the supply pins, ground pins, ADC-12 analog input
pins, EADC analog input pins and the RESET pin. Additional digital pins not listed in this register can be
configured through their local configuration registers.
There are two ways to configure and use the digital pins as GPIO pins:
1. Through the centralized Global I/O control registers.
2. Through the distributed control registers in the specific peripheral that shares it pins with the standard
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GPIO functionality.
The Global I/O registers offer full control of:
1. Configuring each pin as a GPIO.
2. Setting each pin as input or output.
3. Reading the pin’s logic state, if it is configured as an input pin.
4. Setting the logic state of the pin, if it is configured as an output pin.
5. Connecting pin/pins to high rail through internal push/pull drivers or external pull up resistors.
The Global I/O registers include Global I/O EN register, Global I/O OE Register, Global I/O Open Drain
Control Register, Global I/O Value Register and Global I/O Read Register.
The following is showing the format of Global I/O EN Register (GLBIOEN) as an example:
BIT NUMBER
Bit Name
Access
31:0
GLOBAL_IO_EN
R/W
Default
0000_0000_0000_0000_0000_0000_0000_0000
Bits 29-0: GLOBAL_IO_EN – This register enables the global control of digital I/O pins
0 = Control of IO is done by the functional block assigned to the IO (Default)
1 = Control of IO is done by Global IO registers.
PIN NUMBER
BIT
PIN_NAME
UCD3138x
11
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
PWM2
PWM3
12
FAULT3
ADC_EXT_TRIG
TCK
55
14
45
TDO
46
TMS
48
TDI
47
SCI_TX1
SCI_TX0
SCI_RX1
SCI_RX0
TCAP0
37
35
38
36
49
PWM1
40
PWM0
39
TCAP1
13
I2C_DATA
PMBUS_CTRL
PMBUS_ALERT
EXT_INT
FAULT2
FAULT1
FAULT0
SYNC
20
18
17
42
54
44
43
8
34
7
DPWM3B
DPWM3A
DPWM2B
DPWM2A
DPWM1B
29
6
28
5
27
4
26
3
25
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PIN NUMBER
BIT
PIN_NAME
UCD3138x
2
1
0
DPWM1A
DPWM0B
DPWM0A
24
23
22
6.4.13 Temperature Sensor Control
Temperature sensor control register provides internal temperature sensor enabling and trimming
capabilities. The internal temperature sensor is disabled by default.
Temperature
Calibration
ADC 12
Temperature
Sensor
CH15
图 6-24. Internal Temp Sensor
Temperature sensor is calibrated at room temperature (25 °C) via a calibration register value.
The temperature sensor is measured using ADC12 (via Ch15). The temperature is then calculated using a
mathematical formula involving the calibration register (this effectively adds a delta to the ADC
measurement).
The temperature sensor can be enabled or disabled.
6.4.14 I/O Mux Control
I/O Mux Control register may be used in order to choose a single specific functionality that is desired to be
assigned to a physical device pin for your application. See the UCD3138x programmer's manual for
details on the available configurations.
6.4.15 Current Sharing Control
UCD3138x provides three separate modes of current sharing operation.
•
•
•
•
Analog bus current sharing
PWM bus current sharing
Master/Slave current sharing
AD02 has a special ESD protection mechanism that prevents the pin from pulling down the current-
share bus if power is missing from the UCD3138x
The simplified current sharing circuitry is shown in the drawing below. The digital pulse connected to SW3
transforms SW3 into a pulse-width-modulated current source. Details on the frequency and resolution of
this feature are in the digital power fusion peripherals manual.
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3.3 V
ISHARE
SW3
Digital
3.3 V
3.3V
ESD
AD13
ESD
3.2 kΩ
400 Ω
250 Ω
AD02
ESD
SW2
SW1
250 Ω
EXT CAP
RSHARE
ADC12 and
CMP
ADC12 and
CMP
图 6-25. Simplified Current Sharing Circuitry
FOR TEST ONLY,
ALWAYS KEEP 00
CURRENT SHARING MODE
CS_MODE
EN_SW1
EN_SW2
DPWM
Off or Slave Mode (3-state)
PWM Bus
00
00
00
00
00 (default)
0
1
0
0
0
0
0
1
0
01
10
11
ACTIVE
Off or Slave Mode (3-state)
Analog Bus or Master
0
0
The period and the duty of 8-bit PWM current source and the state of the SW1 and SW2 switches can be
controlled through the current sharing control register (CSCTRL).
6.4.16 Temperature Reference
The temperature reference register (TEMPREF) provides the ADC12 count when ADC12 measures the
internal temperature sensor (channel 15) during the factory trim and calibration.
This information can be used by different periodic temperature compensation routines implemented in the
firmware. But it should not be overwritten by firmware, otherwise this factory written value will be lost until
the device is reset.
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6.5 Device Functional Modes
6.5.1 DPWM Modes Of Operation
The DPWM is a complex logic system which is highly configurable to support several different power
supply topologies. The discussion below will focus primarily on waveforms, timing and register settings,
rather than on logic design.
The DPWM is centered on a period counter, which counts up from 0 to PRD, and then is reset and starts
over again.
The DPWM logic causes transitions in many digital signals when the period counter hits the target value
for that signal.
6.5.1.1 Normal Mode
In Normal mode, the Filter output determines the pulse width on DPWM A. DPWM B fits into the rest of
the switching period, with a dead time separating it from the DPWM A on-time. It is useful for buck
topologies, among others. 图 6-26 is a drawing of the Normal Mode waveforms:
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Start of Period
Period
Start of Period
Period Counter
Filter controlled edge
DPWM Output A
Event 1
Filter Duty (High Resolution)
Cycle Adjust A (High Resolution)
Adaptive Sample Trigger A
Adaptive Sample Trigger B
Sample Trigger 1
Blanking A Begin
To Other
Modules
Blanking A End
DPWM Output B
Event 3 – Event 2 (High Res)
Event 4 (High Res)
DTC Adjustment
Sample Trigger 2
Blanking B Begin
Blanking B End
Phase Trigger
To Other
Modules
Events which change with DPWM mode:
DPWM A Rising Edge = Event 1
DPWM A Falling Edge = Event 1 + Filter Duty + Cycle Adjust A
Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive Sample Register or
Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive Sample Register
DPWM B Rising Edge = Event 1 + Filter Duty + Cycle Adjust A + (Event 3 – Event 2)
DPWM B Falling Edge = Event 4 + DTC Adjustment
Phase Trigger = Phase Trigger Register value or Filter Duty
Events always set by their registers, regardless of mode:
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End,
Blanking B Begin, Blanking B End
图 6-26. Normal Mode - Closed Loop
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Cycle adjust A can be used to adjust pulse widths on individual phases of a multi-phase system. This can
be used for functions like current balancing. The Adaptive Sample Triggers can be used to sample in the
middle of the on-time (for an average output), or at the end of the on-time (to minimize phase delay) The
Adaptive Sample Register provides an offset from the center of the on-time. This can compensate for
external delays, such as MOSFET and gate driver turn on times.
Blanking A-Begin and Blanking A-End can be used to blank out noise from the MOSFET turn on at the
beginning of the period (DPWMA rising edge). Blanking B could be used at the turn off time of DPWMB.
The other edges are dynamic, so blanking is more difficult.
Cycle Adjust B has no effect in Normal Mode.
6.5.1.2 Phase Shifting
In most modes, it is possible to synchronize multiple DPWM modules using the phase shift signal. The
phase shift signal has two possible sources. It can come from the Phase Trigger Register. This provides a
fixed value, which is useful for an application like interleaved PFC.
The phase shift value can also come from the filter output. In this case, the changes in the filter output
causes changes in the phase relationship of two DPWM modules. This is useful for phase shifted full
bridge topologies.
图 6-27 shows the mechanism of phase shift:
Phase Shift
DPWM0 Start of Period
DPWM0 Start of Period
Period Counter
DPWM1 Start of Period
DPWM1 Start of Period
Period Counter
Phase Trigger = Phase Trigger Register value or Filter Duty
图 6-27. Phase Shifting
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6.5.1.3 DPWM Multiple Output Mode
Multi mode is used for systems where each phase has only one driver signal. It enables each DPWM
peripheral to drive two phases with the same pulse width, but with a time offset between the phases, and
with different cycle adjusts for each phase.
The Multi-Mode diagram is shown in 图 6-28.
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Start of Period
Period
Period Counter
Start of Period
Filter controlled edge
DPWM Output A
Event 1
Filter Duty (High Resolution)
Cycle Adjust A (High Resolution)
DTC Adjustment
Adaptive Sample Trigger A
Adaptive Sample Trigger B
Sample Trigger 1
To Other
Modules
Blanking A Begin
Blanking A End
DPWM Output B
Event 3 (High Resolution)
Filter Duty (High Resolution)
Cycle Adjust B (High Resolution)
DTC Adjustment
Sample Trigger 2
Blanking B Begin
Blanking B End
Phase Trigger
To Other
Modules
Events which change with DPWM mode:
DPWM A Rising Edge = Event 1
DPWM A Falling Edge = Event 1 + Filter Duty + Cycle Adjust A + DTC Adjustment
Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive Sample Register or
Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive Sample Register
DPWM B Rising Edge = Event 3
DPWM B Falling Edge = Event 3 + Filter Duty + Cycle Adjust B + DTC Adjustment
Phase Trigger = Phase Trigger Register value or Filter Duty
Events always set by their registers, regardless of mode:
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End,
Blanking B Begin, Blanking B End
图 6-28. DPWM Multi-Mode Closed Loop
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Event 2 and Event 4 are not relevant in Multi mode.
DPWMB can cross over the period boundary safely, and still have the proper pulse width, so full 100%
pulse width operation is possible. DPWMA cannot cross over the period boundary.
Since the rising edge on DPWM B is also fixed, Blanking B-Begin and Blanking B-End can be used for
blanking this rising edge.
And, of course, Cycle Adjust B is usable on DPWM B.
6.5.1.4 DPWM Resonant Mode
This mode provides a symmetrical waveform where DPWMA and DPWMB have the same pulse width. As
the switching frequency changes, the dead times between the pulses remain the same.
The equations for this mode are designed for a smooth transition from PWM mode to resonant mode, as
described in 节 6.4.4.2. A diagram of this mode is shown in 图 6-29:
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Start of Period
Filter Period
Start of Period
Period Counter
Filter controlled edge
DPWM Output A
Event 1
Filter Duty – 2 x Event 1
DTC Adjustment
Adaptive Sample Trigger A
Adaptive Sample Trigger B
Sample Trigger 1
Blanking A Begin
To Other
Modules
Blanking A End
DPWM Output B
2 x Event 1
Event 1
DTC Adjustment
Sample Trigger 2
Blanking B Begin
Blanking B End
Phase Trigger
To Other
Modules
Events which change with DPWM mode:
DPWM A Rising Edge = Event 1
DPWM A Falling Edge = Filter Duty – Event 1 + DTC Adjustment
Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive Sample Register or
Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive Sample Register
DPWM B Rising Edge = Filter Duty + Event 1
DPWM B Falling Edge = Filter Period – Event 1 + DTC Adjustment
Phase Trigger = Phase Trigger Register value or Filter Duty
Events always set by their registers, regardless of mode:
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End,
Blanking B Begin, Blanking B End
图 6-29. DPWM Resonant Symmetrical Mode
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The Filter has two outputs, Filter Duty and Filter Period. In this case, the Filter is configured so that the
Filter Period is twice the Filter Duty. So if there were no dead times, each DPWM pin would be on for half
of the period. For dead time handling, the average of the two dead times is subtracted from the Filter Duty
for both DPWM pins. Therefore, both pins will have the same on-time, and the dead times will be fixed
regardless of the period. The only edge which is fixed relative to the start of the period is the rising edge of
DPWM A. This is the only edge for which the blanking signals can be used easily.
6.5.2 Triangular Mode
Triangular mode provides a stable phase shift in interleaved PFC and similar topologies. In this case, the
PWM pulse is centered in the middle of the period, rather than starting at one end or the other. In
Triangular Mode, only DPWM-B is available. A diagram for Triangular Mode is shown in 图 6-30:
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Triangular Mode Closed Loop
Start of Period
Period
Start of Period
Period Counter
DPWM Output A
Sample Trigger 1
Blanking A Begin
Blanking A End
To Other
Modules
Filter controlled edge
DPWM Output B
Cycle Adjust A (High Resolution)
Cycle Adjust B (High Resolution)
Filter Duty/2 (High Resolution)
Period/2
Sample Trigger 2
Blanking B Begin
Blanking B End
To Other
Phase Trigger
Modules
Events which change with DPWM mode:
DPWM A Rising Edge = None
DPWM A Falling Edge = None
Adaptive Sample Trigger None
DPWM B Rising Edge = Period/2 – Filter Duty/2 + Cycle Adjust A
DPWM B Falling Edge = Period/2 + Filter Duty/2 + Cycle Adjust B
Phase Trigger = Phase Trigger Register value or Filter Duty
Events always set by their registers, regardless of mode:
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End,
Blanking B Begin, Blanking B End
图 6-30. Triangular Mode
All edges are dynamic in triangular mode, so fixed blanking is not that useful. The adaptive sample trigger
is not needed. It is very easy to put a fixed sample trigger exactly in the center of the FET on-time,
because the center of the on-time does not move in this mode.
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6.5.3 Leading Edge Mode
Leading edge mode is similar to Normal mode, reversed in time. The DPWM A falling edge is fixed, and
the rising edge moves to the left, or backwards in time, as the filter output increases. The DPWM B falling
edge stays ahead of the DPWMA rising edge by a fixed dead time. A diagram of the Leading Edge Mode
is shown in 图 6-31:
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Leading Edge Closed Loop
Start of Period
Period
Start of Period
Period Counter
DPWM Output A
Event 1
Filter Duty (High Resolution)
Cycle Adjust A (High Resolution)
Adaptive Sample Trigger A
Adaptive Sample Trigger B
Sample Trigger 1
Blanking A Begin
To Other
Modules
Blanking A End
DPWM Output B
Event 2 - Event 3 (High Resolution)
Event 4 (High Resolution)
Sample Trigger 2
Blanking B Begin
Blanking B End
Phase Trigger
To Other
Modules
Events which change with DPWM mode:
DPWM A Falling Edge = Event 1
DPWM A Rising Edge = Event 1 – Filter Duty + Cycle Adjust A
Adaptive Sample Trigger A = Event 1 – Filter Duty + Adaptive Sample Register or
Adaptive Sample Trigger B = Event 1 – Filter Duty/2 + Adaptive Sample Register
DPWM B Rising Edge = Event 4
DPWM B Falling Edge = Event 1 – Filter Duty + Cycle Adjust A – (Event 2 – Event 3)
Phase Trigger = Phase Trigger Register value or Filter Duty
Events always set by their registers, regardless of mode:
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End,
Blanking B Begin, Blanking B End
图 6-31. Leading Edge Mode
As in the Normal mode, the two edges in the middle of the period are dynamic, so the fixed blanking
intervals are mainly useful for the edges at the beginning and end of the period.
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6.6 Memory
6.6.1 Register Maps
6.6.1.1 CPU Memory Map and Interrupts
When the device comes out of power-on-reset, the data memories are mapped to the processor as
follows:
6.6.1.1.1 Memory Map (After Reset Operation)
Address
Size (Bytes)
Module
0x0000_0000 – 0x0003_FFFF
In 32 repeated blocks of 8 k each
32 X 8 k
Boot ROM
0x0004_0000 – 0x0004_7FFF
0x0004_8000 – 0x0004_FFFF
0x0006_8800 – 0x0006_8FFF
0x0006_9000 – 0x0006_9FFF
32 k
32 k
2 k
Program Flash 1
Program Flash 2
Data Flash
4 k
Data RAM
6.6.1.1.2 Memory Map (Normal Operation)
Just before the boot ROM program gives control to flash program, the ROM configures the memory as
follows:
Address
Size (Bytes)
Module
Program Flash 1 (or 2)
Program Flash 2 (or 1)
Boot ROM
0x0000_0000 – 0x0000_7FFF
0x0000_8000 – 0x0000_FFFF
0x0002_0000 – 0x0002_1FFF
0x0006_8800 – 0x0006_8FFF
0x0006_9000 – 0x0006_9FFF
32 k
32 k
8 k
2 k
Data Flash
4 k
Data RAM
6.6.1.1.3 Memory Map (System and Peripherals Blocks)
Address
Size
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
Module
0x0012_0000 - 0x0012_00FF
0x0013_0000 - 0x0013_00FF
0x0014_0000 - 0x0014_00FF
0x0015_0000 - 0x0015_00FF
0x0016_0000 - 0x0016_00FF
0x0017_0000 - 0x0017_00FF
0x0018_0000 - 0x0018_00FF
0x0019_0000 - 0x0019_00FF
0x001A_0000 - 0x001A_00FF
0x001B_0000 – 0x001B_00FF
0x001C_0000 - 0x001C_00FF
0x001D_0000 - 0x001D_00FF
0x001E_0000 - 0x001E_00FF
0xFFF7_EC00 - 0xFFF7_ECFF
0xFFF7_ED00 - 0xFFF7_EDFF
0xFFF7_F000 - 0xFFF7_F0FF
0xFFF7_F600 - 0xFFF7_F6FF
0xFFF7_FA00 - 0xFFF7_FAFF
0xFFF7_FD00 - 0xFFF7_FDFF
0xFFFF_FD00 - 0xFFFF_FDFF
0xFFFF_FE00 - 0xFFFF_FEFF
Loop Mux
Fault Mux
ADC
DPWM 3
Filter 2
DPWM 2
Front End/Ramp Interface 2
Filter 1
DPWM 1
Front End/Ramp Interface 1
Filter 0
DPWM 0
Front End/Ramp Interface 0
UART 0
UART 1
Miscellaneous Analog Control
PMBus Interface
GIO
Timer
MMC
DEC
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Address
Size
23
Module
CIM
0xFFFF_FF20 - 0xFFFF_FF37
0xFFFF_FF40 - 0xFFFF_FF50
0xFFFF_FFD0 - 0xFFFF_FFEC
16
PSA
28
SYS
The registers and bit definitions inside the System and Peripheral blocks are detailed in the programmer’s
guide for each peripheral.
6.6.1.2 Boot ROM
The UCD3138064A incorporates a 8 kB boot ROM. This boot ROM includes support for:
•
•
•
•
•
•
Program download through the PMBus
Device initialization
Examining and modifying registers and memory
Verifying and executing program flash automatically
Jumping to a customer defined boot program
Checksum evaluation to facilitate program execution from either Program Flash 1 or Program Flash 2
The Boot ROM is entered automatically on device reset. It initializes the device and then performs
checksums on the program flash. If the first 2 kB of either program FLASH has a valid checksum, the
program branches to location 0 in the appropriate Program FLASH module. This permits the use of a
custom boot program. If the first checksum fails, it performs some additional checksum calculations to
determine where the valid program is located. This permits full automated program memory checking,
when there is no need for a custom boot program. The complete decision tree is located in 图 6-32.
"Branch to Program Flash 1" means Flash 1 is at address 0x0000, and Flash 2 is at address 0x8000.
"Branch to Program Flash 2" means Flash 2 is at address 0x0000, and Flash 1 is at address 0x8000.
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Device Reset
Does Program Flash 1 have a
BRANCH instruction at the
beginning?
Yes
No
Is there a valid checksum on the
first 2 kB of Program Flash 1 or all
32 kB of Program Flash 1?
Does Program Flash 2 have a
BRANCH instruction at the
beginning?
Yes
No
Yes
No
Is there a valid checksum on the
first 2 kB of Program Flash 2 or all
32 kB of Program Flash 2?
Yes
No
BRANCH to
Program Flash 2
Is there a valid
checksum on all 64 kB?
Yes
No
BRANCH to
Program Flash 1
Stay in ROM
图 6-32. Check Sum Evaluation Flowchart
If neither checksum is valid, the Boot ROM stays in control, and accepts commands via the PMBus
interface. These functions can be used to read and write to all memory locations in the UCD3138064A.
Typically they are used to download a program to Program Flash, and to command its execution.
6.6.1.3 Customer Boot Program
As described above, it is possible to generate a user boot program using 2 kB or more of the Program
Flash. This can support things which the Boot ROM does not support, including:
•
Program download via UART – useful especially for applications where the UCD3138064A is isolated
from the host (e.g., PFC)
•
•
Encrypted download – useful for code security in field updates.
PMBus download at different addresses
6.6.1.4 Flash Management
The UCD3138064A offers a variety of features providing for easy prototyping and easy flash
programming. At the same time, high levels of security are possible for production code, even with field
updates. Standard firmware will be provided for storing multiple copies of system parameters in data flash.
This minimizes the risk of losing information if data-flash programming is interrupted.
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6.6.1.5 Synchronous Rectifier MOSFET Ramp and IDE Calculation
The UCD3138064A has built in logic for optimizing the performance of the synchronous rectifier
MOSFETs. This comes in two forms:
•
•
Synchronous Rectifier MOSFET ramp
Ideal Diode Emulation (IDE) calculation
When starting up a power supply, It is not uncommon for there to already be a voltage present on the
output – this is called pre-bias. It can be very difficult to calculate the ideal synchronous rectifier MOSFET
on-time for this case. If it is not calculated correctly, it may pull down the pre-bias voltage, causing the
power supply to sink current. To avoid this, the synchronous rectifier MOSFETs are not turned on until
after the power supply has ramped up to the nominal output voltage. The synchronous rectifier MOSFETs
are then turned on slowly in order to avoid an output voltage glitch. The synchronous rectifier MOSFET
ramp logic can be used to turn them on at a rate well below the bandwidth of the filter.
In discontinuous mode, the ideal on-time for the synchronous rectifier MOSFETs is a function of Vin, Vout
,
and the primary side duty cycle (D). The IDE logic in the UCD3138064A takes Vin and Vout data from the
firmware and combines it with D data from the filter hardware. It uses this information to calculate the ideal
on-time for the synchronous rectifier MOSFETs.
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7 Applications, Implementation, and Layout
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
7.1 Application Information
The UCD3138x has an extensive set of fully-programmable, high-performance peripherals that make it
suitable for a wide range of power supply applications. In order to make the part easier to use, TI has
prepared an extensive set of materials to demonstrate the features of the device for several key
applications. In each case the following items are available:
1. Full featured EVM hardware that demonstrates classic power supply functionality.
2. An EVM user guide that contains schematics, bill-of-materials, layout guidance and test data
showcasing the performance and features of the device and the hardware.
3. A firmware programmers manual that provides a step-by-step walk through of the code.
表 7-1. Application Information
APPLICATION
EVM DESCRIPTION
This EVM demonstrates a PSFB DC-DC power converter with digital control using the UCD3138x device. Control is
implemented by using PCMC with slope compensation. This simplifies the hardware design by eliminating the need
for a series blocking capacitors and providing the inherent input voltage feed-forward that comes from PCMC. The
controller is located on a daughter card and requires firmware in order to operate. This firmware, along with the entire
source code, is made available through TI. A free, custom function GUI is available to help the user experiment with
the different hardware and software enabled features. The EVM accepts a DC input from 350 VDC to 400 VDC, and
outputs a nominal 12 VDC with full load output power of 360 W, or full output current of 30 A.
Phase shifted full
bridge
This EVM demonstrates an LLC resonant half-bridge DC-DC power converter with digital control using the
UCD3138x device. The controller is located on a daughter card and requires firmware in order to operate. This
firmware, along with the entire source code, is made available through TI. A free, custom function GUI is available to
help the user experiment with the different hardware and software enabled features. The EVM accepts a DC input
from 350 VDC to 400 VDC, and outputs a nominal 12 VDC with full load output power of 340 W, or full output current
of 29 A.
LLC resonant
converter
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7.2 Typical Application
This section summarizes the PSFB EVM DC-DC power converter.
L1
T1
Q7
+12V
Q6
C1
RL
VBUS
I_pri
PRIM
ORING
CTL
CURRENT
Q5
T2
VOUT
C2
R2
D1
T1
QT2
QB2
QT1
VA
Lr
Current
Sensing
QB1
D2
Vref
DPWM0
DPWM0B
DPWM1B
Duty for mode
switching
Vout
CPCC
<
EADC0
EADC1
CLA0
DPWM1
DPWM2
Iout
CLA1
DPWM2A
DPWM2B
Load Current
DPWM3A
DPWM3B
I_pri
EADC2
PCM
DPWM3
AD00
AD01
ISOLATED
GATE Transformer
ACFAIL_IN
FAULT0
FAULT1
FAULT2
SYNCHRONOUS
GATE DRIVE
ACFAIL_OUT
FAILURE
AD02/CMP0
AD03/CMP1/CMP2
AD04/CMP3
AD05/CMP4
AD06/CMP5
AD07/CMP6
AD08
I_SHARE
Vout
FAULT
UCD3138
GPIO1
GPIO2
GPIO3
ORING_CRTL
ON/OFF
Iout
I_pri
CBC
temp
P_GOOD
Vin
VA
WD
ARM7
AD09
PMBus
UART0
RST
OSC
Primary
UART1
Memory
图 7-1. Phase-Shifted Full-Bridge
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7.2.1 Design Requirements
表 7-2. Input Characteristics
PARAMETER
CONDITIONS
MIN
TYP
MAX UNIT
ALL SPECIFICATIONS at Vin=400V and 25°C AMBIENT UNLESS OTHERWISE NOTED.
Vin
Input voltage range
Max input voltage
Input current
Normal Operating
Continuous
350
385
420
420
V
V
Vinmax
Iin
Vin=350V, Full Load
1.15
30
A
Istby
Von
Vhys
Input no load current Output current is 0A
mA
V
Vin Decreasing (input voltage is detected on secondary side)
340
360
Under voltage lockout
Vin Increasing
V
表 7-3. Output Characteristics
PARAMETER
CONDITIONS
MIN
TYP
MAX UNIT
ALL SPECIFICATIONS at Vin=400V and 25°C AMBIENT UNLESS OTHERWISE NOTED.
VO
Output voltage setpoint
Line regulation
No load on outputs
12
V
0.5%
Regline
All outputs; 360 ≤ Vin ≤ 420; IO = IOmax
All outputs; 0 ≤ IO ≤ IOmax; Vin = 400 V
5Hz to 20 MHz
Regload
Load regulation
Ripple and noise(1)
1%
Vn
IO
η
100
mVpp
Output current
0
30
A
Efficiency at phase-shift mode
Efficiency at PWM ZVS mode
Efficiency at hard switching mode
Output adjust range
Vo = 12 V, Io = 15 A
Vo = 12 V, Io = 15 A
Vo = 12 V, Io = 15 A
93%
93%
90%
η
η
Vadj
11.4
12.6
V
V
Transient response
overshoot/undershoot
Vtr
50% Load Step at 1AµS, min load at 2A
±0.36
tsettling
tstart
Transient response settling time
Output rise time
100
50
µS
10% to 90% of Vout
At Startup
mS
Overshoot
2%
fs
Switching frequency
Current sharing accuracy
Loop phase margin
Loop gain margin
Over Vin and IO ranges
50% - full load
150
±5%
45
kHz
Ishare
φ
10% - Full load
10% - Full load
degree
dB
G
10
(1) Ripple and noise are measured with 10µF Tantalum capacitor and 0.1µF ceramic capacitor across output.
7.2.2 Detailed Design Procedure
7.2.2.1 PCMC (Peak Current Mode Control) PSFB (Phase Shifted Full Bridge) Hardware Configuration
Overview
The hardware configuration of the UCD3138x PCMC PSFB converter contains two critical elements that
are highlighted in the subsequent sections.
•
DPWM initialization - This section will highlight the key register settings and considerations necessary
for the UCD3138x to generate the correct MOSFET waveforms for this topology. This maintains the
proper phase relationship between the MOSFETs and synchronous rectifiers as well as the proper set
up required to function correctly with PCMC.
•
PCMC initialization - This section will discuss the register settings and hardware considerations
necessary to modulate the DPWM pins with PCMC and internal slope compensation.
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7.2.2.2 DPWM Initialization for PSFB
The UCD3138x DPWM peripheral provides flexibility for a wide range of topologies. The PSFB
configuration utilizes the Intra-Mux and Edge Generation Modules of the DPWM. For a diagram showing
these modules, see the UCD3138x Digital Power Peripherals Manual.
A schematic of the power stage of the PSFB is shown in 图 7-2:
L1
T1
VOUT
Q6
VBUS
I_pri
PRIM
CURRENT
Q5
T2
R2
D1
T1
QT2
QB2
QT1
Lr
QB1
D2
ISOLATED
GATE Transformer
SYNCHRONOUS
GATE DRIVE
图 7-2. Schematic – PSFB Power Stage
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Here is an overview of the key PSFB signals:
3 A – QB1
( DPWM1C)
3 B – QT1
( DPWM2C)
2 A – QT2
( EDGEGEN)
X1
Y3
2 B – QB2
( EDGEGEN)
X3
Y2
Transformer
Voltage
X2
1 B –
QSYN 1,3
Y1
0 B –
QSYN 2,4
DPWM3AF
DPWM3BF
DPWM 2AF
DPWM 2BF
Current
Peak Level
X1, X2 ,X3 and Y1 , Y2 , Y3 are sets of moving edges
All other edges are fixed .
图 7-3. Key PSFB Signals
7.2.2.2.1 DPWM Synchronization
DPWM1 is synchronized to DPWM0, DPWM2 is synchronized to DPWM1, and DPWM3 is synchronized to
DPWM2, ½ period out of phase using these commands:
Dpwm1Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; //configured to slave
Dpwm2Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; // configured to slave
Dpwm3Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; // configured to slave
Dpwm0Regs.DPWMPHASETRIG.all = PWM_SLAVESYNC;
Dpwm1Regs.DPWMPHASETRIG.all = PWM_SLAVESYNC;
Dpwm2Regs.DPWMPHASETRIG.all = PWM_SLAVESYNC;
LoopMuxRegs.DPWMMUX.bit.DPWM1_SYNC_SEL // Slave to dpwm-0
= 0;
// Slave to dpwm-1
LoopMuxRegs.DPWMMUX.bit.DPWM2_SYNC_SEL // Slave to dpwm-2
= 1;
LoopMuxRegs.DPWMMUX.bit.DPWM3_SYNC_SEL
= 2;
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If the event registers on the DPWMs are the same, the two pairs of signals will be symmetrical. All code
examples are taken from the PSFB EVM code, unless otherwise stated.
7.2.2.3 Fixed Signals to Bridge
The two top signals in the above drawing have fixed timing. The DPWM1CF and DPWM2CF signals are
used for these pins. DPWMCxF refers to the signal coming out of the fault module of DPWMx, as shown
in 图 7-4.
图 7-4. Fixed Signals to Bridge
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These signals are actually routed to pins DPWM3A and 3B using the Intra Mux with these statements:
Dpwm3Regs.DPWMCTRL0.bit.PWM_A_INTRA_MUX = 7; // Send DPWM1C
Dpwm3Regs.DPWMCTRL0.bit.PWM_B_INTRA_MUX = 8; // Send DPWM2C
Since these signals are really being used as events in the timer, the #defines are called EV5 and EV6.
Here are the statements which initialize them:
// Setup waveform for DPWM-C (re-using blanking B regs)
Dpwm2Regs.DPWMBLKBBEG.all = PWM2_EV5 + (4 *16);
Dpwm2Regs.DPWMBLKBEND.all = PWM2_EV6;
Period End
Controlled by DPWM1 Blanking register
Period Start
Blank B Begin
Blank B End
3 A – QB1
Even 6
Even 5
( DPWM1C)
3 B – QT1
Even 6
Even 6
Even 5
( DPWM 2C)
Blank B Begin
Blank B End
Controlled by DPWM2 Blanking register
图 7-5. Blank B Timing Information
The statements for DPWM1 are the same. Remember that DPWMC reuses the Blank B registers for
timing information.
7.2.2.4 Dynamic Signals to Bridge
DPWM0 and 1 are set at normal mode. PCMC triggering signal (fault) chops DPWM0A and 1A cycle by
cycle. The corresponding DPWM0B and 1B are used for synchronous rectifier MOSFET control. The
same PCMC triggering signal is applied to DPWM2 and DPWM3. Both of these are set to normal mode as
well. DPWM2 and 3 are chopped and their edges are used to generate the next two dynamic signals to
the bridge. They are generated using the Edge Generator Module in DPWM2. The Edge Generator
sources are DPWM2 and DPWM3. The edges used are:
DPWM2A turned on by a rising edge on DPWM2BF
DPWM2A turned off by a falling edge on DPWM3AF
DPWM2B turned on by a rising edge on DPWM3BF
DPWM2B turned off by a falling edge on DPWM2AF
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Period Start
Period End
3 A – QB1
( DPWM 1C)
3 B – QT1
( DPWM 2C)
2 A – QT2
( EDGEGEN )
2 B – QB2
( EDGEGEN )
Y3
X3
1A
1 B –
QSYN 1,3
Y2
Y1
X2
0A
0 B –
QSYN 2,4
X1
DPWM 3AF
DPWM 3BF
DPWM 2AF
DPWM 2BF
Current
Peak Level
Chopping point
Chopping point
X1 , X2 , X3 and Y1 , Y2 , Y3 are sets of moving edges
All other edges are fixed .
图 7-6. Dynamic Signals to Bridge
The Edge Generator is configured with these statements:
Dpwm2Regs.DPWMEDGEGEN.bit.A_ON_EDGE = 2;
Dpwm2Regs.DPWMEDGEGEN.bit.A_OFF_EDGE = 5;
Dpwm2Regs.DPWMEDGEGEN.bit.B_ON_EDGE = 6;
Dpwm2Regs.DPWMEDGEGEN.bit.B_OFF_EDGE = 1;
Dpwm2Regs.DPWMCTRL0.bit.PWM_A_INTRA_MUX = 1; // EDGEGEN-A out the A output
Dpwm2Regs.DPWMCTRL0.bit.PWM_B_INTRA_MUX = 1; // EDGEGEN-B out the B output
Dpwm2Regs.DPWMEDGEGEN.bit.EDGE_EN = 1;
The EDGE_EN bits are set for all 4 DPWMs. This is done to ensure that all signals have the same timing
delay through the DPWM.
The final 6 gate signals are shown in 图 7-7.
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Period Start
Period End
3 A – QB1
( DPWM 1C)
3 B – QT1
( DPWM 2C)
2 A – QT2
( EDGEGEN )
2 B – QB2
( EDGEGEN )
Y3
X3
1 B –
QSYN 1,3
Y2
Y1
X2
X1
0 B –
QSYN 2,4
Peak Level
Current
Chopping point
Chopping point
图 7-7. Final 6 Gate Signals
Note how the falling edge of DPWM2AF aligns with the X1 edge, and how the rising edge of DPWM2BF
aligns with the X3 edge. The falling edges on DPWM2AF and DPWM3AF are caused by the peak
detection logic. This is fed through the Cycle By Cycle logic. The Cycle By Cycle logic also has a special
feature to control the rising edges of DPWM2BF (X1 and X3) and DPWM3BF (Y1 and Y3). It uses the
value of Event3 – Event2 to control the time between the edges. The same feature is used with DPWM0
and DPWM1 to control the X2 and Y2 signals. Using the other 2 DPWMs permits these signals to have a
different dead time.
The same setup can be used for voltage mode control. In this case, the Filter output sets the timing of the
falling edge on DPWMxAF.
All DPWMs are configured in Normal mode, with CBC enabled. If external slope compensation is used,
DPWM1A and DPWM1B are used to reset the external compensator at the beginning of each half cycle. If
no PCMC event occurs, the values of Events 2 and 3 determine the locations of the edges, just as in open
loop mode.
7.2.2.5 System Initialization for PCM
PCM (Peak Current Mode) is a specialized configuration for the UCD3138x which involves several
peripherals. This section describes how it works across the peripherals.
7.2.2.5.1 Use of Front Ends and Filters in PSFB
All three front ends are used in PSFB. The same signals are used in the same places for both PCMC and
voltage mode. The same hardware can be used for both control modes, with the mode determined by
which firmware is loaded into the device. FE0 and FE1 are used with their associated filters, but Filter 2 is
not used at all.
FE0 – Vout – voltage loop
FE1 – Iout – current loop
FE2 – Ipri – PCM
In PCMC mode, FE2 is used for PCMC, and the voltage loop is normally used to provide the start point for
the compensation ramp. If the CPCC firmware detects a need for constant current mode, it switches to the
current loop for the start point.
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7.2.2.5.2 Peak Current Detection
Peak current detection involves all the major modules of the DPPs, the Front End, Filter, Loop Mux, Fault
Mux and the DPWMs. A drawing of the major elements is shown in 图 7-8.
Ipri
PCM
Comparator
Loop
Mux
Fault
Mux
DPWM
Voltage Loop
Filter
Loop
Mux
Ramp
Module
Loop
Mux
Vout
Front
End
图 7-8. Peak Current Detection Function
All signals without arrows flow from left to right. The voltage loop is used to select a peak current level.
This level is fed to the Ramp module to generate a compensation ramp. The compensation ramp is
compared to the primary current by the PCMC comparator in the Front End. When the ramp value is
greater than the primary current, the APCMC signal is sent to the DPWM, causing the events described in
the previous sections.
The DPWM frame start and output pin signals can be used to trigger the Ramp Module. In this case,
unlike in the case of other ramp module functions, each DPWM frame triggers the start of the ramp. The
ramp steps every 32 ns.
The Filter is configured normally, there is no real difference for PCMC. The PCM_FILTER_SEL bits in the
LoopMux.PCMCTRL register are used to select which filter is connected to the ramp module:
LoopMuxRegs.PCMCTRL.bit.PCM_FILTER_SEL =0; //select filter0
With Firmware Constant Power/Constant current, Filter 1 and Front End 1 are used as a current control
loop, with the EADCDAC set to high current. If the voltage loop value becomes higher than the current
loop value, then Filter 1 is used to control the PCM ramp start value:
LoopMuxRegs.PCMCTRL.bit.PCM_FILTER_SEL =1;
S P A C E //select filter1 for slope compensation source
In the ramp module, there are 2 bitfields in the RAMPCTRL register which must be configured. The
PCM_START_SEL must be set to a 1 to enable the Filter to be used as a ramp start source. The
RAMP_EN bit must be set, of course.
The DAC_STEP register sets the slope of the compensation ramp. The DAC value is in volts, of course,
so it is necessary to calculate the slope after the current to voltage conversion. Here is the formula for
converting from millivolts per microsecond to DACSTEP.
m = compensation slope in millivolts per microsecond
ACSTEP = 335.5 × M
In C, this can be written:
#define COMPENSATION_SLOPE 150 //compensation slope in millivolts per microsecond
#define DACSTEP_COMP_VALUE ((int) (COMPENSATION_SLOPE*335.5) )
S P A C E //value in DACSTEP for desired compensation slope
S P A C E FeCtrl0Regs.DACSTEP.all = DACSTEP_COMP_VALUE;
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It may also be necessary to set a ramp ending value in the RAMPDACEND register.
In addition, it is necessary to set the D2S_COMP_EN bit in the EADCCTRL register. This is for enabling
the differential to single ended comparator function. The front end diagram leaves it out for simplicity, but
the connection between the DAC and the EADC amplifier is actually differential. The PCMC comparator,
however, is single ended. So a conversion is necessary as shown in 图 7-9.
AFE_GAIN
23-AFE_GAIN
6 bit ADC
8mV/LSB
EAP0
2AFE_GAIN
EAN0
Signed 9 bit result
(error) 1 mV /LSB
EADC
X
Averaging
SAR/Prebias
Ramp
Filter x
CPCC
DAC0
10 bit DAC
1.5625mV/LSB
Σ
Value
Differential to
Single Ended
Dither
4 bit dithering gives 14 bits of effective resolution
97.65625μV/LSB effective resolution
Absolute Value
Calculation
10 bit result
1.5625mV/LSB
Peak Current
Detected
Peak Current Mode
Comparator
图 7-9. Differential to Single-Ended Comparator Function
The EADC_MODE bit in EADCCTRL should be set to a 5 for peak current mode.
The peak current detection signal next goes to the Loop Mux. The Fault Mux has only 1 APCM input, but
there are 3 front ends. So the PCM_FE_SEL bits in APCMCTRL must be used to select which front end is
used:
LoopMuxRegs.APCMCTRL.bit.PCM_FE_SEL = 2; // use FE2 for PCM */
The PCM_EN bit must also be set.
LoopMuxRegs.APCMCTRL.bit.PCM_EN = 1; // Enable PCM
Next the Fault Mux is used to enable the APCM bit to the CLIM/CBC signal to the DPWM. There are 4
DPWMxCLIM registers, one for each DPWM. The ANALOG_PCM_EN bit must be set in each one to
connect the PCM detection signal to the CLIM/CBC signal on each DPWM. For the latest configuration
information on all of these bits, consult the appropriate EVM firmware. To avoid errors, it is best to
configure your hardware design using the same DPWMs, filters, and front ends for the same functions as
the EVM.
DPWM timing is used to trigger the start of the ramp. This is selected by the FECTRLxMUX registers in
the Loop Mux. DPWMx_FRAME_SYNC_EN bits, when set, cause the ramp to be triggered at the start of
the DPWM period.
7.2.2.5.3 Peak Current Mode (PCM)
There is one peak current mode control module in the device however any front end can be configured to
use this module.
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7.2.3 Application Curves
30A Load
syncFETs off
1A-16A-1A
Vin =385V
图 7-11. VOUT Soft Start
图 7-10. Load Transient
Kp =14000
Ki =300
Kd =2000
Alpha = –2
图 7-12. Bode Plot
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7.2.4 Power Supply Recommendations
•
Both 3.3 VD and 3.3 VA should have a local capacitor of at least 4.7-µF in parallel with a 10-nF
capacitor placed as close as possible to the device pins.
•
BP18 should have a 1-µF capacitor to ground.
7.2.5 Layout
7.2.5.1 IC Grounding and Layout Guidelines
•
•
•
•
Single ground is recommended: SGND. A multilayer such as 4 layers board is recommended so that
one solid SGND is dedicated for return current path, referred to the layout example.
Apply multiple different capacitors for different frequency range on decoupling circuits. Each capacitor
has different ESL, Capacitance and ESR, and they have different frequency response.
Avoid long traces close to radiation components, and place them into an internal layer, and it is
preferred to have grounding shield, and in the end, add a termination circuit.
Analog circuit such as ADC sensing lines needs a return current path into the analog circuitry; digital
circuit such as GPIO, PMBus and PWM has a return current path into the digital circuitry; although with
a single plane, still try to avoid to mix analog current and digital current.
•
•
Don’t use a ferrite bead or larger than 3 Ω resistor to connect between V33A and V33D.
Both 3.3VD and 3.3VA should have local decoupling capacitors close to the device power pins, add
vias to connect decoupling caps directly to SGND.
•
Avoid negative current/negative voltage on all pins, so Schottky diodes may need to clamp the voltage;
avoid the voltage spike on all pins more than 3.8 V or less than –0.3 V, add Schottky diodes on the
pins which could have voltage spikes during surge test; be aware that a Schottky has relatively higher
leakage current, which can affect the voltage sensing at high temperature.
•
RESET pin should have one at least 2.2 µF low ESL capacitor locally decoupled with SGND plane.
This capacitor must be located close to the device RESET pin. It is highly recommended to use a small
resistance (such as 220 Ω) to connect the RESET pin with 3.3 VD.
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7.2.5.2 Layout Example
图 7-13. PCB Layout Example
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8 器件和文档支持
8.1 器件支持
UCD3138064A 应用固件在德州仪器 (TI) Code Composer Studio (CCS) 集成开发环境（建议采用版本
v3.3）中开发。
特定电源拓扑的器件编程、实时调试以及主要器件参数的监视/配置工作都可通过德州仪器
(TI)
的
FUSION_DIGITAL_POWER_DESIGNER 图形用户界面进行 (http://www.ti.com.cn/tool/cn/fusion_digital_
power_designer)。FUSION_DIGITAL_POWER_DESIGNER 软件应用采用 PMBus 协议通过串行总线与器
件通信，所使用的接口适配器为德州仪器
(TI)
评估模块
(EVM)
USB-TO-GPIO
(http://www.ti.com.cn/tool/cn/usb-to-gpio)。FUSION_DIGITAL_POWER_DESIGNER GUI 的器件 GUI 模块
中的“内存调试器”工具可提供基于 PMBUS 的实时调试功能，这是替代基于 JTAG 的传统方法的有效选择。
该软件应用还可用于器件编程，所使用的工具是针对生产环境进行优化的
FUSION_MFR_GUI
(http:/
/www.ti.com.cn/tool/cn/fusion_mfr_gui)。FUSION_MFR_GUI 工具支持多个板载器件，且具有内置记录和报
告功能。
在参考文档方面，以下编程手册可提供关于 UCD3138064A 数字控制器应用和使用方法的详细信息：
1. 《UCD3138064A 编程手册》
2. 本手册中涵盖的 UCD3138064A 数字电源外设编程手册关键主题包括：
–
数字脉宽调制器 (DPWM)
–
–
–
工作模式（正常/多相/相移/谐振等）
自动模式切换
数字脉宽调制控制器 (DPWMC)，边沿生成和内部多路复用
–
前端
–
–
–
–
–
模拟前端
ADC 或 EADC 误差
前端 DAC
斜坡模块
逐次逼近寄存器模块
–
–
滤波器
– 滤波器数学函数
环路复用
–
–
–
模拟峰值电流模式
恒定电流/恒定功率 (CCCP)
自动周期调整
–
故障复用
–
–
–
–
–
–
模拟比较器
数字比较器
故障引脚功能
DPWM 故障动作
理想二极管仿真 (IDE)，断续传导模式 (DCM) 检测
振荡器故障检测
–
UCD3138064A 中上述全部外设的寄存器映射
3. 《UCD3138064A 监视和通信编程手册》本手册中介绍的关键主题包括：
–
ADC12
–
–
–
–
–
控制、转换、定序和取平均值
数字比较器
温度传感器
PMBUS 寻址
双路采样与保持
–
–
–
其它模拟控制（电流分流、欠压、时钟门控）
PMBUS 接口
通用输入输出 (GPIO)
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–
–
–
定时器模块
PMBus
UCD3138064A 中上述全部外设的寄存器映射
4. 《UCD3138064A ARM 和数字系统编程手册》本手册中介绍的关键主题包括：
–
引导 ROM 和引导闪存
–
–
–
–
–
BootROM 函数
存储器读/写功能
校验和函数
闪存函数
避免程序闪存锁定
–
ARM7 构架
–
–
–
–
工作模式
硬件/软件中断
指令集
两种内部工作状态（Thumb 16 位模式/ARM 32 位模式）
–
–
存储器与系统模块
–
–
–
地址解码器、DEC（存储器映射）
存储器控制器 (MMC)
中央中断模块
UCD3138064A 中上述全部外设的寄存器映射
5. 《UCD31xx 隔离电源应用 FUSION_DIGITAL_POWER_DESIGNER 》 – 用户指南
除上述工具和文档外，如需获取有关评估模块、参考应用固件和应用手册/设计提示的最新信息，请访问
http://www.ti.com.cn/product/cn/ucd3138064。
8.2 文档支持
8.2.1 相关文档
1. 《UCD3138064A 编程手册》（文献编号：SLUUAD8）
2. 《UCD3138 数字电源外设编程手册》（文献编号：SLUU995）
3. 《UCD3138 监视和通信编程手册》（文献编号：SLUU996）
4. 《UCD3138 ARM 和数字系统编程手册》（文献编号：SLUU994）
5. 《隔离电源应用 FUSION_DIGITAL_POWER_DESIGNER 》 （文献编号：SLUA676）
6. 《Code Composer Studio 开发工具 v3.3》– 入门指南（文献编号：SPRU509H）
7. ARM7TDMI-S 技术参考手册
8. 系统管理总线 (SMBus) 技术规范
9. PMBus™电源系统管理协议规范
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8.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools
and contact information for technical support.
8.4 商标
E2E is a trademark of Texas Instruments.
PMBus is a trademark of SMIF, Inc..
All other trademarks are the property of their respective owners.
8.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
8.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
9 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知
且不对本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
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重要声明
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JESD48 最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息, 并验证这些信息是否完整且是最新的。所有产品的销售
都遵循在订单确认时所提供的TI 销售条款与条件。
TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内，且 TI 认为 有必要时才会使
用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。
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对于 TI 的产品手册或数据表中 TI 信息的重要部分，仅在没有对内容进行任何篡改且带有相关授权、条件、限制和声明的情况 下才允许进行
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在转售 TI 组件或服务时，如果对该组件或服务参数的陈述与 TI 标明的参数相比存在差异或虚假成分，则会失去相关 TI 组件 或服务的所有明
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客户认可并同意，尽管任何应用相关信息或支持仍可能由 TI 提供，但他们将独力负责满足与其产品及在其应用中使用 TI 产品 相关的所有法
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及其后果、降低有可能造成人身伤害的故障的发生机率并采取适当的补救措施。客户将全额赔偿因 在此类安全关键应用中使用任何 TI 组件而
对 TI 及其代理造成的任何损失。
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只有那些 TI 特别注明属于军用等级或“增强型塑料”的 TI 组件才是设计或专门用于军事/航空应用或环境的。购买者认可并同 意，对并非指定面
向军事或航空航天用途的 TI 组件进行军事或航空航天方面的应用，其风险由客户单独承担，并且由客户独 力负责满足与此类使用相关的所有
法律和法规要求。
TI 已明确指定符合 ISO/TS16949 要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到 ISO/TS16949 要
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IMPORTANT NOTICE
邮寄地址： 上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122
Copyright © 2016, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
UCD3138064ARGCR
UCD3138064ARGCT
ACTIVE
ACTIVE
VQFN
VQFN
RGC
RGC
64
64
2000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
UCD3138064A
UCD3138064A
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
RGC 64
9 x 9, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224597/A
www.ti.com
PACKAGE OUTLINE
RGC0064B
VQFN - 1 mm max height
S
C
A
L
E
1
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
9.15
8.85
A
B
PIN 1 INDEX AREA
9.15
8.85
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
2X 7.5
SYMM
EXPOSED
THERMAL PAD
(0.2) TYP
17
32
16
33
65
SYMM
2X 7.5
4.25 0.1
60X
0.5
1
48
0.30
0.18
64X
49
64
PIN 1 ID
0.1
C A B
0.5
0.3
64X
0.05
4219010/A 10/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGC0064B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
4.25)
SEE SOLDER MASK
DETAIL
SYMM
64X (0.6)
49
64
64X (0.24)
1
48
60X (0.5)
(R0.05) TYP
(1.18) TYP
(8.8)
65
SYMM
(0.695) TYP
(
0.2) TYP
VIA
33
16
32
17
(0.695) TYP
(1.18) TYP
(8.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219010/A 10/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RGC0064B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
64X (0.6)
64
49
64X (0.24)
1
48
60X (0.5)
(R0.05) TYP
9X ( 1.19)
65
SYMM
(8.8)
(1.39)
33
16
17
32
(1.39)
(8.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 10X
EXPOSED PAD 65
71% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219010/A 10/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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