UCD3138064RGCR [TI]
具有 64kB 存储器、适用于隔离电源的高集成度数字控制器 | RGC | 64 | -40 to 125;
| 型号： | UCD3138064RGCR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 64kB 存储器、适用于隔离电源的高集成度数字控制器 | RGC | 64 | -40 to 125 控制器 存储 |
| 文件： | 总104页 (文件大小：5384K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
UCD3138064 Highly Integrated Digital Controller for Isolated Power With 64-kB
Program Flash Memory
– Cycle-by-cycle current limiting
– Programmable blanking time and fault counting
– External fault inputs
Synchronization of DPWM waveforms between
multiple UCD3138 family devices
14-channel, 12-bit, 267-ksps general purpose ADC
with integrated
– Programmable averaging filters
– Dual sample and hold
1 Features
•
64 kB program flash derivative of UCD3138 family
– 2-32 kB program flash memory banks
– Supports execution from 1 bank, while
programming another
•
•
– Capability to update firmware without shutting
down the power supply
– Additional communication ports compared to
the UCD3138 (+1 SPI, +1 I2C)
•
•
Internal temperature sensor
– RGC and RJA packages pin-to-pin compatible
with UCD3138 (SLUSAP2B). Section 6.1
Digital control of up to 3 independent feedback
Loops
– Dedicated PID based hardware
– 2-pole/2-zero configurable, non-linear control
Up to 16-MHz error A/D converter (EADC)
– Configurable resolution (min: 1 mV/LSB)
– Up to 8x oversampling and adaptive trigger
positioning
Fully programmable high-performance 31.25-MHz,
32-bit ARM7TDMI-S processor
– 64-kB program flash (2-32-kB banks)
– 2-kB data flash with ECC
– 4-kB data RAM
– 8-kB boot ROM enables firmware bootload
Communication Peripherals
– 1 - I2C/PMBus, 1 - I2C (master mode only)
– 2 - UARTs
– 1 - SPI
•
•
•
– Hardware based averaging (up to 8x)
– 14-bit effective DAC
Up to 8 high resolution digital pulse width
modulated (DPWM) outputs
– 250-ps pulse width resolution
– 4-ns frequency and phase resolution
– Adjustable phase shift and dead-bands
– Cycle-by-cycle duty cycle matching
– Up to 2-MHz switching frequency
Configurable trailing, leading and triangular
modulation
•
•
•
•
•
Timer capture with selectable input pins
Built in watchdog: BOD and POR
64-pin QFN, and 40-pin QFN packages
Operating temperature: –40°C to 125°C
Fusion digital power studio GUI support
•
2 Applications
•
•
•
Power supplies and telecom rectifiers
Power factor correction
Isolated DC-to-DC modules
•
•
Configurable feedback control
– Voltage, average current and peak current
mode control
– Constant current, constant power
Configurable FM, phase shift modulation and
PWM
Fast, Automatic and smooth mode switching
– Frequency modulation and PWM
– Phase shift modulation and PWM
High efficiency and light load management
– Burst mode and ideal diode emulation
– Synchronous rectifier soft on and off
– Low device standby power
•
•
•
•
•
Primary side voltage sensing
Flux and phase current balancing for non-peak
current mode control applications
Current share
•
•
Feature rich fault protection options
– 7 analog and 4 digital domparators,
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
3 Description
The UCD3138064 is a digital power supply controller from Texas Instruments offering superior levels of
integration and performance in a single chip solution. The UCD3138064, in comparison to Texas Instruments
UCD3138 digital power controller (Section 6), offers 64 kB of program Flash memory (vs 32 kB in UCD3138)
and additional options for communication such as SPI and a second I2C port. The availability of 64 kB of
program Flash memory in 2-32 kB banks, enables the designers to implement dual images of firmware (e.g.
one main image + one back-up image) in the device and the flexibility to execute from either of the banks
using appropriate algorithms. It also creates the unique opportunity for the processor to load a new program and
subsequently execute that program without interrupting power delivery. This feature allows the end user to add
new features to the power supply in the field while eliminating any down-time required to load the new program.
The flexible nature of the UCD3138064 makes it suitable for a wide variety of power conversion applications.
In addition, multiple peripherals inside the device have been specifically optimized to enhance the performance
of AC/DC and isolated DC/DC applications and reduce the solution component count in the IT and network
infrastructure space. The UCD3138064 is a fully programmable solution offering customers complete control
of their application, along with ample ability to differentiate their solution. At the same time, TI is committed
to simplifying our customer’s development effort through offering best in class development tools, including
application firmware, Code Composer StudioTM software development environment, and TI’s Fusion Power
Development GUI which enables customers to configure and monitor key system parameters.
At the core of the UCD3138064 controller are the Digital Power Peripherals (DPP). Each DPP implements a high
speed digital control loop consisting of a dedicated Error Analog to Digital Converter (EADC), a PID based 2 pole
- 2 zero digital compensator and DPWM outputs with 250ps pulse width resolution. The device also contains a
12-bit, 267 ksps general purpose ADC with up to 15 channels, timers, interrupt control, PMBus, I2C, SPI and
UART communications ports. The device is based on a 32-bit ARM7TDMI-S RISC microcontroller that performs
real-time monitoring, configures peripherals and manages communications. The ARM microcontroller executes
its program out of programmable flash memory as well as on chip RAM and ROM.
In addition to the DPP, specific power management peripherals have been added to enable high efficiency
across the entire operating range, high integration for increased power density, reliability, and lowest overall
system cost and high flexibility with support for the widest number of control schemes and topologies. Such
peripherals include: light load burst mode, synchronous rectification, LLC and phase shifted full bridge mode
switching, input voltage feed forward, copper trace current sense, ideal diode emulation, constant current
constant power control, synchronous rectification soft on and off, peak current mode control, flux balancing,
secondary side input voltage sensing, high resolution current sharing, hardware configurable soft start with pre
bias, as well as several other features. Topology support has been optimized for voltage mode and peak current
mode controlled phase shifted full bridge, single and dual phase PFC, bridgeless PFC, hard switched full bridge
and half bridge, and LLC half bridge and full bridge.
Device Information
PART NUMBER(1)
PACKAGE DRAWING
PACKAGE TYPE
BODY SIZE
RGC
RMH
RJA
VQFN (64)
9.00 mm × 9.00 mm
6.00 mm × 6.00 mm
6.00 mm × 6.00 mm
UCD3138064
WQFN (40)
VQFN (40) (2)
(1) For more information, see , Section 14 Mechanical Packaging and Orderable Information.
(2) Recommended for new 40-pin designs, optimized for improved performance under temperature cycling test for board level reliability
(BLR).
Copyright © 2021 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
4 Functional Block Diagram
Loop MUX
DPWM0A
DPWM0
DPWM0B
EAP0
Front End 0
EAN0
PID Based
Filter 0
DPWM1A
DPWM1
DPWM1B
EAP1
Front End 1
EAN1
PID Based
Filter 1
DPWM2A
DPWM2
DPWM2B
PID Based
Filter 2
Front End 2
AFE
DPWM3A
DPWM3
DPWM3B
Constant Power Constant
Current
23-AFE
EAP2
EAN2
Front End Averaging
Digital Comparators
EADC
2AFE
SYNC
X
Avg()
SAR/Prebias
Ramp
DAC0
Input Voltage Feed Forward
A0
Filter x
CPCC
ꢀ
Value
Dither
Abs()
Peak Current Mode
Control Comparator
Advanced Power Control
Mode Switching, Burst Mode, IDE,
Synchronous Rectification soft on & off
PMBUS_ALERT
ADC_EXT
AD[13:0]
ADC12 Control
Sequencing, Averaging,
Digital Compare, Dual
Sample and hold
PMBUS_CTRL
PMBus
ADC12
PMBUS_DATA
AD00
AD01
PMBUS_CLK
Internal Temperature
Sensor
PWM0
Timers
4 œ 16 bit (PWM)
1 œ 24 bit
PWM1
AD02
AD13
Current Share
Analog, Average, Master/Slave
AGND
Oscillator
TCAP
SCI_TX0
SCI_RX0
SCI_TX1
SCI_RX1
EXT_INT
FAULT0
FAULT1
FAULT2
FAULT3
/RESET
TCK
UART0
UART1
ARM7TDMI-S
32 bit, 31.25 MHz
Analog
Comparators
AD02
AD03
A
B
Memory
DFLASH 2 kB
RAM 4 kB
ROM 8 kB
C
GPIO
Control
PFLASH 64 kB
AD04
AD13
AD06
AD07
Fault MUX &
Control
D
Bank 1
32 kB
Bank 2
32 kB
V33D
V33DIO
VREG
DGND
V33A
Cycle by Cycle
Current Limit
E
Power and
1.8 V Voltage
Regulator
Digital
Comparators
F
Power On Reset
JTAG
TDI
G
TMS
Brown Out Detection
AGND
TDO
SPI_MISO
SPI_MOSI
SPI_CLK
SPI_CS
I2C_DATA
I2C_CLK
SPI
I2C
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................2
4 Functional Block Diagram.............................................. 3
5 Revision History.............................................................. 4
6 Device Options................................................................ 6
6.1 Device Comparison Table...........................................6
6.2 Product Selection Matrix.............................................6
7 Pin Configuration and Functions...................................8
7.1 Pin Diagrams.............................................................. 8
7.2 Pin Functions.............................................................. 9
8 Specifications................................................................ 12
8.1 Absolute Maximum Ratings (1) .................................12
8.2 Handling Ratings.......................................................12
8.3 Recommended Operating Conditions.......................12
8.4 Thermal Information..................................................13
8.5 Electrical Characteristics...........................................14
8.6 Timing Characteristics...............................................16
8.7 PMBus/SMBus/I2C Timing........................................18
8.8 Power On Reset (POR) / Brown Out Reset (BOR)...19
8.9 Typical Clock Gating Power Savings........................ 20
8.10 Typical Characteristics............................................21
9 Detailed Description......................................................22
9.1 Overview...................................................................22
9.2 Functional Block Diagram.........................................23
9.3 Feature Description...................................................24
9.4 Device Functional Modes..........................................49
9.5 Memory.....................................................................57
10 Applications and Implementation..............................61
10.1 Application Information........................................... 61
10.2 Typical Application.................................................. 62
11 Power Supply Recommendations..............................73
11.1 Introduction To Power Supply and Layout
Recommendations...................................................... 73
11.2 3.3-V Supply Pins....................................................73
11.3 Recommendation for V33 Ramp up Slew Rate
for UCD3138 and UCD3138064..................................73
11.4 Recommendation for RC Time Constant of
RESET Pin for UCD3138 and UCD3138064.............. 74
12 Layout...........................................................................77
12.1 Layout Guidelines................................................... 77
12.2 Layout Example...................................................... 82
13 Device and Documentation Support..........................87
13.1 Device Support....................................................... 87
13.2 Documentation Support.......................................... 88
13.3 Trademarks.............................................................88
13.4 Electrostatic Discharge Caution..............................88
13.5 Glossary..................................................................88
14 Mechanical, Packaging, and Orderable
Information.................................................................... 88
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (March 2017) to Revision D (April 2021)
Page
•
Add 40 pin RJA Package option (global). Change sync feature description to say it works with all UCD3138
family members instead of just UCD3138064. Split Device Overview section into 4 sections to conform to TI
data sheet standards. ........................................................................................................................................ 1
Add RJA Package to Device Information table. Change number of ADC channels from 14 to 15, because
channels 0 to 13 are for external pins, and channel 14 is for the internal temperature sensor.......................... 2
Add RJA package for new designs note ............................................................................................................2
Added RJA to top line, deleted empty column, deleted row with External Crystal Clock Support, since only
UCD3138128A supports it .................................................................................................................................6
Add RJA Package top view, as well as notes about corner pad soldering and reliability for both RMH and RJA
packages............................................................................................................................................................ 8
Add DAC Output as an alternate pin assignment for pins 2, 3, and 4 on the 40 pin QFN package table.
Change package descriptions in tables for clarity and consistency....................................................................9
Add reference to IC Package Thermal Metrics application report in thermal table ..........................................13
Add RJA package to thermal table .................................................................................................................. 13
Fixed cross reference for current share resistor and current source ...............................................................14
Rise and fall time descriptions were switched to make them match the data. Before the rise time spec was in
the row for fall times and vice versa. They were labeled correctly, so the error was obvious.......................... 18
Add "Using Front End EADCs" to the bullet describing the digital comparators...............................................38
Remove pin numbers from table, as they were unnecessary and only applied to 64 pin package. Add note
that Global I/O settings travel with the pin and don't move when the IOMUX register moves the pin function to
another pin. ......................................................................................................................................................45
Changed temperature sensor ADC channel from 15 to 14 ..............................................................................47
•
•
•
•
•
•
•
•
•
•
•
•
Copyright © 2021 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
•
Replaced the Device Grounding and Layout Guidelines sub -section with the Power Supply
Recommendations Section and Layout Section. The new content is copied directly from the UCD3138 Family
Practical Design Guideline Application Note. .................................................................................................. 73
Update links and references to latest tool and document set ..........................................................................87
•
Changes from Revision B (September 2014) to Revision C (March 2017)
Page
•
Changed Device Grounding and Layout Guidelines section ........................................................................... 73
Changes from Revision A (February 2014) to Revision B (July 2014)
Page
•
Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ............................................................................................................................................................... 1
Added 40-pin RMH QFN package option (global).............................................................................................. 1
•
Changes from Revision * (March 2013) to Revision A (February 2014)
Page
Finalize for release. Changed rev to A............................................................................................................... 1
Deleted table: Summary Of Key Differences Between UCD3138x & UCD3138................................................ 6
•
•
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
6 Device Options
6.1 Device Comparison Table
UCD3138
RHA/RMH/RJA
UCD3138064
RMH/RJA
UCD3138
RGC
UCD3138064
RGC
UCD3138128
PFC
UCD3138A64
PFC
FEATURE
80 Pin QFP
(14 mm x 14
mm)
80 Pin QFP
(14 mm x 14
mm)
40 Pin QFN
40 Pin QFN
64 Pin QFN
64 Pin QFN
Package Offering
(6 mm x 6 mm) (6 mm x 6 mm) (9 mm x 9 mm) (9 mm x 9 mm)
(Includes leads) (Includes leads)
ARM7TDMI-S Core Processor
31.25 MHz
8
31.25 MHz
8
31.25 MHz
8
31.25 MHz
8
31.25 MHz
8
31.25 MHz
8
High Resolution DPWM Outputs
(250ps Resolution)
Number of High Speed
Independent Feedback Loops (#
Regulated Output Voltages
3
7
3
7
3
3
3
3
12-bit, 256kps, General Purpose
ADC Channels
14
14
15
15
Digital Comparators at ADC
Outputs
4
4
4
4
4
4
Flash Memory (Program)
32 kB
64 kB
32 kB
64 kB
128 kB
64 kB
Only 1 bank of
64 kB Flash
available
Number of Memory 32kB Flash
Memory Banks
1
2
1
2
4
Flash Memory (Data)
RAM
2 kB
4 kB
2 kB
4 kB
2 kB
4 kB
4
2 kB
4 kB
2 kB
8 kB
4
2 kB
8 kB
4
Programmable Fault Inputs
1 + 2(1)
1 + 2(1)
2 + 2(1)
High Speed Analog Comparators
with Cycle-by-Cycle Current
Limiting
6
6
7
7
7
7
UART (SCI)
PMBus/I2C
Additional I2C
SPI
1(1)
1
1(1)
1
2
1
0
0
2
2
1
1
1
2
1
1
1
1
0
0
1(1)
1(1)
0
0
4 (16 bit) and
1 (24 bit)
4 (16 bit) and
1 (24 bit)
4 (16 bit) and
1 (24 bit)
4 (16 bit) and
1 (24 bit)
4 (16 bit) and
2 (24 bit)
4 (16 bit) and
2 (24 bit)
Timers
Timer PWM Outputs
Timer Capture Inputs
Total Digital GPIOs
External Interrupts
1(1)
2(1)
18
0
1(1)
2(1)
18
0
2
1 + 3(1)
30
2
1 + 3(1)
30
4
2 + 2(1)
43
4
2 + 2(1)
43
1
1
1
1
All EADC
channels
All EADC
channels
All EADC
Channels
All EADC
Channels
Peak Current Mode Control
EADC2 Only
EADC2 Only
(1) Represents an alternate pin out that is programmable via firmware.
6.2 Product Selection Matrix
FEATURE
ARM7TDMI-S Core Processor
UCD3138064 64 PIN
UCD3138064 40 PIN
31.25 MHz
8
31.25 MHz
8
High Resolution DPWM Outputs (250ps Resolution)
Number of High Speed Independent Feedback Loops (#
Regulated Output Voltages)
3
3
12-bit, 267 ksps, General Purpose ADC Channels
Digital Comparators at ADC Outputs
Flash Memory (Program)
14
4
7
4
64 kB
32 KB
Copyright © 2021 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
FEATURE
UCD3138064 64 PIN
UCD3138064 40 PIN
Flash Memory (Data)
Flash Security
RAM
2 kB
√
2 KB
√
4 kB
4 KB
DPWM Switching Frequency
Programmable Fault Inputs
up to 2 MHz
2 + 2(1)
up to 2 MHz
1 + 2(1)
High Speed Analog Comparators with Cycle-by-Cycle
Current Limiting
7(2)
6
UART (SCI)
2
1(1)
PMBus
1
√
I2C
1(1)
0
SPI
1(1)
0
Timers
4 (16 bit) and 1 (24 bit)
4 (16 bit) and 1 (24 bit)
Timer PWM Outputs
Timer Capture Inputs
Watchdog
2
1
√
√
√
√
1
1(1)
√
On Chip Oscillator
Power-On Reset and Brown-Out Reset
Sync IN and Sync OUT Functions
√
√
√
Total GPIO (includes all pins with multiplexed functions
such as, DPWM, Fault Inputs, SCI, etc.)
30
1
18
0
External Interrupts
Package Offering
64 Pin QFN (9.00 mm x 40 Pin QFN (6.00 mm x
9.00 mm) 6.00mm)
(1) This number represents an alternate pin out that is programmable via firmware. See the UCD3138064 Enhancements Programmer’s
Manual for details.
(2) To facilitate simple OVP and UVP connections both comparators B and C are connected to the AD03 pin.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
7 Pin Configuration and Functions
7.1 Pin Diagrams
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
AGND
AGND
AD13
V33D
3
AD12
BP18
4
AD10
V33DIO
5
AD07
DGND
6
AD06
FAULT3
7
AD04
AD03
FAULT2
8
TCAP
9
V33DIO
QFN (64)
TMS
10
11
12
13
14
15
16
DGND
TDI/SCI_RX0/PMBUS_CTRL/FAULT1/SPI_MISO
TDO/SCI_TX0/PMBUS_ALERT/FAULT0/SPI_MOSI
TCK/TCAP/SYNC/PWM0
/RESET
ADC_EXT/TCAP/SYNC/PWM0
SCI_RX0
FAULT1/SPI_CLK/I2C_CLK
FAULT0/SPI_CS/I2C_DATA
INT_EXT
SCI_TX0
PMBUS_CLK/SCI_TX0
PMBUS_DATA/SCI_RX0
DGND
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64-Pin QFN RGC Package Top View
40 39 38 37 36 35 34 33 32 31
1
2
30
29
28
27
26
25
24
23
22
21
AGND
AD13
AD06
AGND
AGND
BP18
3
4
AD04
AD03
V33D
QFN (40)
5
DGND
6
DGND
FAULT2
7
/RESET
ADC_EXT_TRIG/TCAP/SYNC/PWM0
PMBUS_CLK/SCI_TX0
TMS
8
TDI/SCI_RX0/PMBUS_CTRL/FAULT1
TDO/SCI_TX0/PMBUS_ALERT/FAULT0
TCK/TCAP/SYNC/PWM0
9
10
PMBUS_DATA/SCI_RX0
11 12 13 14 15 16
17 18 19 20
NOTE: There are four corner pins on the RMH package. The corner anchor pins and thermal pad should be soldered for robust
mechanical performance and should be tied to the appropriate ground signal.
40-Pin QFN RMH Package Top View
Copyright © 2021 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
40 39 38 37 36 35 34 33 32 31
1
2
30
29
28
27
26
25
24
23
22
21
AGND
AD13
AD06
AGND
AGND
BP18
3
4
AD04
AD03
V33D
QFN (40)
5
DGND
6
DGND
/RESET
FAULT2
7
TMS
8
ADC_EXT_TRIG/TCAP/SYNC/PWM0
PMBUS_CLK/SCI_TX0
TDI/SCI_RX0/PMBUS_CTRL/FAULT1
TDO/SCI_TX0/PMBUS_ALERT/FAULT0
TCK/TCAP/SYNC/PWM0
9
10
PMBUS_DATA/SCI_RX0
11 12 13 14 15 16
17 18 19 20
NOTE: The RJA package has thicker package height compared to the RMH package. There are also four corner pins on the RJA
package. These features help to improve solder-joint reliability. The corner anchor pins and thermal pad should be soldered for robust
mechanical performance and should be tied to the appropriate ground signal. The RJA package is recommended for new product
designs.
40-Pin QFN RJA Package Top View
7.2 Pin Functions
UCD3138064RGC QFN 64 Pin Attributes
PIN
ALTERNATE ASSIGNMENT
CONFIGURABLE
AS A GPIO?
PRIMARY ASSIGNMENT
NUMBER
NAME
NO. 1
NO. 2
NO. 3
NO. 4
1
2
3
4
AGND
AD13
AD12
AD10
Analog ground
12-bit ADC, Ch 13, comparator E, I-share
12-bit ADC, Ch 12
DAC output
12-bit ADC, Ch 10
12-bit ADC, Ch 7, Connected to comparator F and
reference to comparator G
5
AD07
DAC output
6
AD06
AD04
AD03
12-bit ADC, Ch 6, Connected to comparator F
12-bit ADC, Ch 4, Connected to comparator D
12-bit ADC, Ch 3, Connected to comparator B and C
Digital I/O 3.3V core supply
Digital ground
DAC output
DAC output
7
8
9
V33DIO
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
DGND
RESET
Device Reset Input, active low
ADC conversion external trigger input
SCI RX 0
ADC_EXT
SCI_RX0
SCI_TX0
PMBUS_CLK
PMBUS_DATA
DPWM0A
DPWM0B
DPWM1A
DPWM1B
DPWM2A
DPWM2B
DPWM3A
DPWM3B
DGND
TCAP
SYNC
PWM0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SCI TX 0
PMBUS Clock (Open Drain)
PMBus data (Open Drain)
DPWM 0A output
SCI TX 0
SCI RX 0
DPWM 0B output
DPWM 1A output
DPWM 1B output
DPWM 2A output
DPWM 2B output
DPWM 3A output
DPWM 3B output
Digital ground
SYNC
DPWM Synchronize pin
TCAP
ADC_EXT_TRIG
PWM0
Yes
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
UCD3138064RGC QFN 64 Pin Attributes (continued)
PIN
ALTERNATE ASSIGNMENT
CONFIGURABLE
AS A GPIO?
PRIMARY ASSIGNMENT
NUMBER
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
NAME
NO. 1
NO. 2
NO. 3
NO. 4
PMBUS_ALERT
PMBUS_CTRL
SCI_TX1
SCI_RX1
PWM0
PWM1
DGND
PMBus Alert (Open Drain)
Yes
Yes
Yes
Yes
Yes
Yes
PMBus Control (Open Drain)
SCI TX 1
PMBUS_ALERT
PMBUS_CTRL
SCI RX 1
General purpose PWM 0
General purpose PWM 1
Digital ground
INT_EXT
FAULT0
FAULT1
TCK(1)
External Interrupt
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
External fault input 0
SPI_CS
SPI_CLK
TCAP
I2C_DATA
I2C_CLK
External fault input 1
JTAG TCK (for manufacturer test only)
JTAG TDO (for manufacturer test only)
JTAG TDI (for manufacturer test only)
JTAG TMS (for manufacturer test only)
Timer capture input
SYNC
PWM0
FAULT0
FAULT1
TDO(1)
TDI(1)
SCI_TX0
SCI_RX0
PMBUS_ALERT
PMBUS_CTRL
SPI_MOSI
SPI_MISO
TMS(1)
TCAP
FAULT2
FAULT3
DGND
External fault input 2
External fault input 3
Digital ground
V33DIO
BP18
Digital I/O 3.3 V core supply
1.8V Bypass
V33D
Digital 3.3V core supply
AGND
Substrate analog ground
AGND
Analog ground
EAP0
Channel #0, differential analog voltage, positive input
Channel #0, differential analog voltage, negative input
Channel #1, differential analog voltage, positive input
Channel #1, differential analog voltage, negative input
Channel #2, differential analog voltage, positive input
Channel #2, differential analog voltage, negative input
Analog ground
EAN0
EAP1
EAN1
EAP2
EAN2
AGND
V33A
Analog 3.3 V supply
AD00
12-bit ADC, Ch 0, Connected to current source
12-bit ADC, Ch 1, Connected to current source
AD01
12-bit ADC, Ch 2, Connected to comparator A, I-
share
60
AD02
61
62
63
64
AD05
AD08
AD09
AD11
12-bit ADC, Ch 5
12-bit ADC, Ch 8
12-bit ADC, Ch 9
12-bit ADC, Ch 11
(1) Fusion Digital Power based debug tools are recommended instead of JTAG.
UCD3138064RMH and UCD3138064RJA QFN 40 Pin Attributes
PIN
ALTERNATE ASSIGNMENT
CONFIGURABL
E
AS A GPIO?
PRIMARY ASSIGNMENT
NUMBER
NAME
NO. 1
NO. 2
NO. 3
1
2
AGND
AD13
Analog ground
12-bit ADC, Ch 13, Connected to comparator E, I-share
12-bit ADC, Ch 6, Connected to comparator F
12-bit ADC, Ch 4, Connected to comparator D
DAC Output
DAC Output
DAC Output
3
4
AD06
AD04
5
6
7
8
9
AD03
12-bit ADC, Ch 3, Connected to comparator B & C
Digital ground
DGND
RESET
Device Reset Input, active low
ADC conversion external trigger input
PMBUS Clock (Open Drain)
ADC_EXT_TRIG
PMBUS_CLK
TCAP
SYNC
PWM0
Yes
Yes
SCI_TX0
Copyright © 2021 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
UCD3138064RMH and UCD3138064RJA QFN 40 Pin Attributes (continued)
PIN
ALTERNATE ASSIGNMENT
CONFIGURABL
E
AS A GPIO?
PRIMARY ASSIGNMENT
NUMBER
NAME
NO. 1
NO. 2
NO. 3
10
11
12
13
14
15
16
17
18
19
20
21
22
PMBUS_DATA
DPWM0A
DPWM0B
DPWM1A
DPWM1B
DPWM2A
DPWM2B
DPWM3A
DPWM3B
PMBUS_ALERT
PMBUS_CTRL
TCK(1)
PMBUS Data (Open Drain)
DPWM 0A output
SCI_RX0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
DPWM 0B output
DPWM 1A output
DPWM 1B output
DPWM 2A output
DPWM 2B output
DPWM 3A output
DPWM 3B output
PMBus Alert (Open Drain)
PMBus Control (Open Drain)
JTAG TCK (for manufacturer test only)
JTAG TDO (for manufacturer test only)
TCAP
SYNC
PWM0
TDO(1)
SCI TX0
PMBUS_AL
ERT
FAULT0
23
TDI(1)
JTAG TDI (for manufacturer test only)
SCI_RX0
PMBUS_C
TRL
FAULT1
Yes
24
25
26
27
28
29
30
31
32
33
34
35
TMS(1)
FAULT2
DGND
V33D
JTAG TMS (for manufacturer test only)
External fault input 2
Yes
Yes
Digital ground
Digital 3.3 V core supply
BP18
1.8V Bypass
AGND
AGND
EAP0
EAN0
EAP1
EAN1
EAP2
Substrate analog ground
Analog ground
Channel #0, differential analog voltage, positive input
Channel #0, differential analog voltage, negative input
Channel #1, differential analog voltage, positive input
Channel #1, differential analog voltage, negative input
Channel #2, differential analog voltage, positive input
(Recommended for peak current mode control)
36
37
38
39
40
AGND
V33A
AD00
AD01
AD02
Analog ground
Analog 3.3 V supply
12-bit ADC, Ch 0, Connected to current source
12-bit ADC, Ch 1, Connected to current source
12-bit ADC, Ch 2, Connected to comparator A, I-share
All four anchors should be soldered and tied to GND
Corner
NA
Corner anchor pin
(RMH only)
(1) Fusion Digital Power based debug tools are recommended instead of JTAG.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
8 Specifications
8.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
3.8
3.8
3.8
2.5
0.3
UNIT
V33D
V33D to DGND
V33DIO to DGND
V33A to AGND
BP18 to DGND
Ground difference
V
V
V
V
V
V33DIO
V33A
BP18
|DGND – AGND|
All Pins, excluding
AGND(2)
Voltage applied to any pin
Junction Temperature
–0.3
–40
3.8
V
TOPT
125
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 8.3 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Referenced to DGND
8.2 Handling Ratings
MIN
–55
MAX
150
UNIT
TSTG
VESD
Storage temperature
°C
(1)
Human Body Model (HBM) ESD stress voltage(2)
Charge Device Model (CDM) ESD Stress voltage(3)
–2000
–500
2000
500
V
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges
in to the device.
(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows
safe manufacturing with a standard ESD control process.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.0
3.0
3.0
1.6
–40
TYP
3.3
3.3
3.3
1.8
-
MAX UNIT
V33D
V33DIO
V33A
BP18
TJ
Digital power
3.6
3.6
3.6
2.0
125
V
V
Digital I/O power
Analog power
V
1.8 V digital power
Junction temperature
V
°C
Copyright © 2021 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
8.4 Thermal Information
UCD3138064
THERMAL METRIC(1)
UNIT
64 Pin
QFN (RGC)
40 Pin QFN
(RJA)
40 Pin
QFN (RMH)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
19.9
5.7
3.1
0.1
3.0
0.3
25.4
14.0
7.7
30.8
15.7
5.7
RθJC(top)
RθJB
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.1
0.2
ψJB
7.6
5.7
RθJC(bot)
0.9
0.9
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
8.5 Electrical Characteristics
V33A = V33D = V33DIO = 3.3 V; 1μF from BP18 to DGND, TJ = –40 °C to 125 °C (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP MAX UNIT
SUPPLY CURRENT
Measured on V33A. The device is powered up
but all ADC12 and EADC sampling is disabled
I33A
6.3
mA
I33DIO
I33D
All GPIO and communication pins are open
ROM program execution
0.35
60
mA
mA
mA
I33D (5)
Flash programming in ROM mode
70
The device is in ROM mode with all DPWMs
enabled and switching at 2 MHz. The DPWMs
are all unloaded.
I33
100
mA
ERROR ADC INPUTS EAP, EAN
EAP – AGND
–0.15
–0.256
–256
0.8
1.998
1.848
248
V
EAP – EAN
V
Typical error range
AFE = 0
mV
mV
mV
mV
mV
MΩ
μA
AFE = 3
1
2
4
8
1.20
2.30
4.45
9.10
AFE = 2
1.7
EAP – EAN Error voltage digital resolution
AFE = 1
3.55
6.90
0.5
AFE = 0
REA
Input impedance (See Figure 9-1)
AGND reference
IOFFSET Input offset current (See Figure 9-1)
–5
5
2
Input voltage = 0 V at AFE = 0
Input voltage = 0 V at AFE = 1
Input voltage = 0 V at AFE = 2
Input voltage = 0 V at AFE = 3
–2
LSB
LSB
LSB
LSB
–2.5
–3
2.5
-3
4
EADC Offset
–4
15.62
5
Sample Rate
MHz
Analog Front End Amplifier Bandwidth
100
1
MHz
V/V
mV
Gain
See Figure 9-2
A0
Minimum output voltage
21
EADC DAC
DAC range
0
1.6
V
VREF DAC reference resolution
VREF DAC reference resolution
INL
10-bit, No dithering enabled
With 4-bit dithering enabled
1.56
97.6
mV
μV
–2.0
–1.0
2.0
2.1
LSB
LSB
LSB
V
DNL
Does not include MSB transition
DNL at MSB transition
DAC reference voltage
ADC12
–1.4
1.58
1.61
IBIAS
Bias current for PMBus address pins
Measurement range for voltage monitoring
Internal ADC reference voltage
9.5
0
10.5
2.5
μA
V
–40 to 125 °C
–40 to 25 °C
25 to 125 °C
2.475
2.500 2.53
–0.7
V
Change in Internal ADC reference from
25°C reference voltage (5)
mV
–2.1
Copyright © 2021 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
V33A = V33D = V33DIO = 3.3 V; 1μF from BP18 to DGND, TJ = –40 °C to 125 °C (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP MAX UNIT
–
ADC12 INL integral nonlinearity (5)
LSB
7.5/+2.9
–
ADC12 DNL differential nonlinearity (5)
LSB
ADC_SAMPLING_SEL = 6 for all ADC12 data,
25 to 125 °C
0.7/+3.2
ADC Zero Scale Error
ADC Full Scale Error
Input bias
–7
7
35
mV
mV
nA
–35
2.5 V applied to pin
200
Input leakage resistance (5)
Input Capacitance (5)
ADC_SAMPLING_SEL= 6 or 0
1
MΩ
pF
10
DIGITAL INPUTS/OUTPUTS(1) (2)
DGND
+ 0.25
VOL
VOH
Low-level output voltage(3)
High-level output voltage (3)
IOH = 4 mA, V33DIO = 3 V
IOH = –4 mA, V33DIO = 3 V
V
V
V33DIO
– 0.6
VIH
VIL
IOH
IOL
High-level input voltage
Low-level input voltage
Output sinking current
Output sourcing current
V33DIO = 3 V
V33DIO = 3 V
2.1
V
V
1.1
4
mA
mA
–4
SYSTEM PERFORMANCE
TWD
tDelay
Watchdog time out resolution
Total time is: TWD x (WDCTRL.PERIOD+1)
13.1
17 22.7
31.25
ms
Processor master clock (MCLK)
Digital filter delay(4)
MHz
(1 clock = 32 ns)
TJ = 25 °C
6
MCLKs
Retention period of flash content (data
retention and program)
100
240
years
f(PCLK) Internal oscillator frequency
Flash Read
250
1
260 MHz
MCLKs
Current share current source (See Section
9.3.15)
ISHARE
238
259
μA
kΩ
Current share resistor (See Section
9.3.15)
RSHARE
9.75
10.3
POWER ON RESET AND BROWN OUT (V33A pin, See Figure 8-3)
VGH
VGL
Vres
Voltage Good High
Voltage Good Low
2.7
2.5
0.8
2.9
V
V
V
V
Voltage at which IReset signal is valid(5)
Brownout
Internal signal warning of brownout conditions
TEMPERATURE SENSOR(5)
VTEMP
Voltage range of sensor
Volts/°C
1.46
2.44
V
mV/°C
°C/LSB
°C
Voltage resolution
Temperature resolution
Accuracy(5) (6)
5.9
0.1034
±5
Degree C per bit
–40 to 125 °C
–10
–40
10
Temperature range
ITEMP
–40 to 125 °C
125
°C
Current draw of sensor when active
Trimmed 25 °C reading
30
μA
VAMB
ANALOG COMPARATOR
DAC Reference DAC Range
Ambient temperature
1.85
V
0
2.5
V
V
Reference Voltage
2.478
2.5 2.513
Bits
7
bits
LSB
INL(5)
–0.42
0.21
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
V33A = V33D = V33DIO = 3.3 V; 1μF from BP18 to DGND, TJ = –40 °C to 125 °C (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
0.06
–5.5
–0.5
4.6
TYP MAX UNIT
DNL(5)
Offset
0.12
19.5
1
LSB
mV
mA
mV
mV
V
Reference DAC buffered output load(7)
Buffer offset (–0.5 mA)
8.3
17
Buffer offset (1.0 mA)
–0.05
0.2
Output Range (–0.5 mA)
Output Range (1.0 mA)
2.5
2.5
0
V
(1) DPWM outputs are low after reset. Other GPIO pins are configured as inputs after reset.
(2) On the 40 pin package V33DIO is connected to V33D internally.
(3) The maximum total current, IOHmax and IOLmax for all outputs combined, should not exceed 12 mA to hold the maximum voltage
drop specified. Maximum sink current per pin = –6 mA at VOL; maximum source current per pin = 6 mA at VOH
.
(4) Time from close of error ADC sample window to time when digitally calculated control effort (duty cycle) is available. This delay, which
has no variation associated with it, must be accounted for when calculating the system dynamic response.
(5) Characterized by design and not production tested.
(6) Ambient temperature offset value should be used from the TEMPSENCTRL register to meet accuracy.
(7) Available from reference DACs for comparators D, E, F and G.
8.6 Timing Characteristics
V33A = V33D = V33DIO = 3.3 V; 1 μF from BP18 to DGND, TJ = –40 to 125 °C (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP MAX UNIT
EADC DAC
τ
Settling Time
From 10 to 90%
250
3.9
ns
μs
ADC12
ADC single sample conversion time(1)
ADC_SAMPLING_SEL= 6 or 0
SYSTEM PERFORMANCE
tWD Watchdog time out resolution
Total time is: tWD x (WDCTRL.PERIOD+1)
High level on FAULT pin
14.6
100
17 20.5
ms
ns
Time to disable DPWM output based on
active FAULT pin signal
70
Retention period of flash content (data
retention and program)
TJ = 25 °C
years
ms
Program time to erase one page or block
in data flash or program flash
20
30
Program time to write one word in data
flash or program flash
µs
Sync-in/sync-out pulse width
Flash Write
Sync pin
256
20
ns
μs
POWER ON RESET AND BROWN OUT (V33D PIN, SEE Figure 8-3)
Time delay after Power is good or RESET*
relinquished
tPOR
1
ms
ms
The time it takes from the device to exit
IRESET goes from a low state to a high state.
a reset state and begin executing program This is approximately equivalent to toggling the
tEXC1
9.5
flash bank 1 (32 kB).(1)
external reset pin from low to high state.
The time it takes from the device to exit
IRESET goes from a low state to a high state.
tEXC2
a reset state and begin executing program This is approximately equivalent to toggling the
19
19
ms
ms
flash bank 2 (32 kB).(1)
external reset pin from low to high state.
The time it takes from the device to exit
IRESET goes from a low state to a high state.
tEXCT
a reset state and begin executing the total This is approximately equivalent to toggling the
program flash (64 kB).(1)
external reset pin from low to high state.
TEMPERATURE SENSOR(1)
tON
Turn on time / settling time of sensor
100
μs
Copyright © 2021 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
V33A = V33D = V33DIO = 3.3 V; 1 μF from BP18 to DGND, TJ = –40 to 125 °C (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP MAX UNIT
ANALOG COMPARATOR
Time to disable DPWM output based on
0 V to 2.5 V step input on the analog
comparator.(1)
150
ns
(1) Characterized by design and not production tested.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
8.7 PMBus/SMBus/I2C Timing
The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus, and
PMBus in Slave or Master mode are shown in Table 8-1, Figure 8-1, and Figure 8-2. The numbers in Table 8-1
are for 400 kHz operating frequency. However, the device supports all three speeds, standard (100 kHz), fast
(400 kHz), and fast mode plus (1 MHz).
Table 8-1. I2C/SMBus/PMBus Timing Characteristics
PARAMETER
Typical values at TA = 25 °C and VCC = 3.3 V (unless otherwise noted)
fSMB SMBus/PMBus operating frequency Slave mode, SMBC 50% duty cycle
fI2C
TEST CONDITIONS
MIN TYP MAX UNIT
100 400 kHz
100 400 kHz
I2C operating frequency
Slave mode, SCL 50% duty cycle
Bus free time between start and
stop(5)
t(BUF)
1.3
µs
t(HD:STA)
t(SU:STA)
t(SU:STO)
t(HD:DAT)
t(SU:DAT)
Hold time after (repeated) start(5)
Repeated start setup time(5)
Stop setup time(5)
0.6
0.6
0.6
0
µs
µs
µs
ns
ns
ms
µs
µs
Data hold time
Receive mode
Data setup time
100
t(TIMEOUT) Error signal/detect(1)
35
t(LOW)
t(HIGH)
Clock low period
1.3
Clock high period(2)
0.6
50
25
Cumulative clock low slave extend
time(3)
t(LOW:SEXT)
tf
ms
ns
20 + 0.1
Cb(4)
Clock/data fall time
Fall time tf = 0.9 VDD to (VILmax – 0.15)
300
20 + 0.1
Cb(4)
tr
Clock/data rise time
Rise time tr = (VILmax – 0.15) to (VIHmin + 0.15)
300
400
ns
Cb
Total capacitance of one bus line
pF
(1) The device times out when any clock low exceeds t(TIMEOUT)
.
(2) t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction that is in progress. This
specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0] = 0).
(3) t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(4) Cb (pF)
(5) Fast mode, 400 kHz
Figure 8-1. I2C/SMBus/PMBus Timing Diagram
Copyright © 2021 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
Figure 8-2. Bus Timing in Extended Mode
8.8 Power On Reset (POR) / Brown Out Reset (BOR)
V33D
3.3 V
Brown Out
VGH
VGL
Vres
t
TPOR
TPOR
IReset
t
undefined
Figure 8-3. Power On Reset (POR) / Brown Out Reset (BOR)
VGH
VGL
Vres
– This is the V33A threshold where the internal power is declared good. The UCD3138064 comes out of reset when above
this threshold.
– This is the V33A threshold where the internal power is declared bad. The device goes into reset when below this
threshold.
– This is the V33A threshold where the internal reset signal is no longer valid. Below this threshold the device is in an
indeterminate state.
IReset
– This is the internal reset signal. When low, the device is held in reset. This is equivalent to holding the reset pin on the IC
low.
TPOR
– The time delay from when VGH is exceeded to when the device comes out of reset.
Brown Out
– This is the V33A voltage threshold at which the device sets the brown out status bit. In addition an interrupt can be
triggered if enabled.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
8.9 Typical Clock Gating Power Savings
6.00
5.00
4.00
3.00
2.00
1.00
0.00
DPWM
ADC12
Front-end Control Peak Current
Mode
Timer
Filter
Constant
Power/Constant
Current
SCI
GIO
C001
Module
Figure 8-4. Clock Gating Power Savings
The power disable control register provides control bits that can enable or disable the clock to several
peripherals such as, PCM, CPCC, digital filters, front ends, DPWMs, UARTs, ADC-12 and more.
By default, all these controls are enabled. If a specific peripheral is not used the clock gate can be disabled
in order to block the propagation of the clock signal to that peripheral and therefore reduce the overall current
consumption of the device. The power savings chart displays the power savings per module. For example there
are 4 DPWM modules, therefore, if all 4 are disabled a total of ~20 mA can be saved.
Copyright © 2021 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
8.10 Typical Characteristics
(Data is taken from the UCD3138)
ADC12 Measurement Temperature Sensor Voltage
2.1
2.6
2.4
2.2
2.0
1.8
1.6
1.4
2
1.9
1.8
1.7
1.6
−40
−20
0
20
40
60
Temperature (°C)
80
100
120
−60 −40 −20
0
20 40 60 80 100 120 140 160
Temperature (°C)
G005a
G006b
Figure 8-5. EADC LSB Size with 4X Gain (mV) vs
Temperature
Figure 8-6. ADC12 Measurement Temperature
Sensor Voltage vs Temperature
ADC12 2.5-V Reference
ADC12 Temperature Sensor Measurement Error
8
2.515
2.510
2.505
2.500
6
4
2
2.495
2.490
2.485
0
−2
−4
2.480
2.475
−40
−20
0
20
40
60
Temperature (°C)
80
100
120
−40
−20
0
20
40
60
Temperature (°C)
80
100
120
G002b
G003b
Figure 8-8. ADC12 Temperature Sensor
Measurement Error vs Temperature
Figure 8-7. ADC12 2.5-V Reference vs Temperature
2.08
2.06
3 σ
1 σ
AVG
-1 σ
-3 σ
2.04
2.02
2
1.98
1.96
1.94
1.92
-100
-50
0
50
100
150
200
Temperature (°C)
Figure 8-9. Oscillator Frequency (2MHz Reference, Divided Down from 250MHz) vs Temperature
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
9 Detailed Description
9.1 Overview
9.1.1 ARM Processor
The ARM7TDMI-S processor is a synthesizable member of the ARM family of general purpose 32-bit
microprocessors. The ARM architecture is based on RISC (Reduced Instruction Set Computer) principles where
two instruction sets are available. The 32-bit ARM instruction set and the 16-bit Thumb instruction set. The
Thumb instructions allow for higher code density equivalent to a 16-bit microprocessor, with the performance of
the 32-bit microprocessor.
The three-staged pipelined ARM processor has fetch, decode and execute stage architecture. Major blocks in
the ARM processor include a 32-bit ALU, 32 x 8 multiplier, and a barrel shifter.
9.1.2 Memory
The UCD3138x (ARM7TDMI-S) is a Von-Neumann architecture, where a single bus provides access to all of the
memory modules. All of the memory module addresses are sequentially aligned along the same address range.
This applies to program flash, data flash, ROM and all other peripherals. Within the UCD3138 family
architecture, there is a 1024x32-bit Boot ROM that contains the initial firmware startup routines for PMBUS
communication and non-volatile (FLASH) memory download. This boot ROM is executed after power-up-reset
checks if there is a valid FLASH program written. If a valid program is present, the ROM code branches to the
main FLASH-program execution. If there is no valid program, the device waits for a program download through
the PMBus.
The UCD3138 family also supports customization of the boot program by allowing an alternative boot
routine to be executed from program FLASH. This feature enables assignment of a unique address to each
device; therefore, enabling firmware reprogramming even when several devices are connected on the same
communication bus.
There are three separate flash memory areas present inside the device. There are 2-32 kB program flash blocks
and 1-2 kB data flash area. The 32 kB program areas are organized as 8 k x 32 bit memory blocks and are
intended to be for the firmware programs. The blocks are configured with page erase capability for erasing
blocks as small as 1 kB per page, or with a mass erase for erasing the entire 32 kB array. The flash endurance
is specified at 1000 erase/write cycles and the data retention is good for 100 years. The 2 kB data flash array
is organized as a 512 x 32 bit memory (32 byte page size). The data flash is intended for firmware data value
storage and data logging. Thus, the Data flash is specified as a high endurance memory of 20 k cycles with
embedded error correction code (ECC).
For run time data storage and scratchpad memory, a 8 kB RAM is available. The RAM is organized as a 2 k x 32
bit array. The availability of 64 kB of program Flash memory in 2-32 kB banks, enables designers to implement
multiple images of firmware (e.g. one main image + one back-up image) in the device and the flexibility to
execute from either of the banks using appropriate algorithms. It also creates the unique opportunity for the
processor to load a new program and subsequently execute that program without interrupting power delivery.
This feature allows the end user to add new features to the power supply while eliminating any down-time
required to load the new program.
Copyright © 2021 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
9.2 Functional Block Diagram
Loop MUX
DPWM0A
DPWM0
DPWM0B
EAP0
Front End 0
EAN0
PID Based
Filter 0
DPWM1A
DPWM1
DPWM1B
EAP1
Front End 1
EAN1
PID Based
Filter 1
DPWM2A
DPWM2
DPWM2B
PID Based
Filter 2
Front End 2
AFE
DPWM3A
DPWM3
DPWM3B
Constant Power Constant
Current
23-AFE
EAP2
EAN2
Front End Averaging
Digital Comparators
EADC
2AFE
SYNC
X
Avg()
SAR/Prebias
Ramp
DAC0
Input Voltage Feed Forward
A0
Filter x
CPCC
ꢀ
Value
Dither
Abs()
Peak Current Mode
Control Comparator
Advanced Power Control
Mode Switching, Burst Mode, IDE,
Synchronous Rectification soft on & off
PMBUS_ALERT
ADC_EXT
AD[13:0]
ADC12 Control
Sequencing, Averaging,
Digital Compare, Dual
Sample and hold
PMBUS_CTRL
PMBus
ADC12
PMBUS_DATA
AD00
AD01
PMBUS_CLK
Internal Temperature
Sensor
PWM0
Timers
4 œ 16 bit (PWM)
1 œ 24 bit
PWM1
AD02
AD13
Current Share
Analog, Average, Master/Slave
AGND
Oscillator
TCAP
SCI_TX0
SCI_RX0
SCI_TX1
SCI_RX1
EXT_INT
FAULT0
FAULT1
FAULT2
FAULT3
/RESET
TCK
UART0
UART1
ARM7TDMI-S
32 bit, 31.25 MHz
Analog
Comparators
AD02
AD03
A
B
Memory
DFLASH 2 kB
RAM 4 kB
ROM 8 kB
C
GPIO
Control
PFLASH 64 kB
AD04
AD13
AD06
AD07
Fault MUX &
Control
D
Bank 1
32 kB
Bank 2
32 kB
V33D
V33DIO
VREG
DGND
V33A
Cycle by Cycle
Current Limit
E
Power and
1.8 V Voltage
Regulator
Digital
Comparators
F
Power On Reset
JTAG
TDI
G
TMS
Brown Out Detection
AGND
TDO
SPI_MISO
SPI_MOSI
SPI_CLK
SPI_CS
I2C_DATA
I2C_CLK
SPI
I2C
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
9.3 Feature Description
9.3.1 System Module
The System Module contains the interface logic and configuration registers to control and configure all the
memory, peripherals and interrupt mechanisms. The blocks inside the system module are the address decoder,
memory management controller, system management unit, central interrupt unit, and clock control unit.
9.3.1.1 Address Decoder (DEC)
The Address Decoder generates the memory selects for the FLASH, ROM and RAM arrays. The memory map
addresses are selectable through configurable register settings. These memory selects can be configured from
1 kB to 16 MB. Power on reset uses the default addresses in the memory map for ROM execution, which is
then configured by the ROM code to the application setup. During access to the DEC registers, a wait state is
asserted to the CPU. DEC registers are only writable in the ARM privilege mode for user mode protection.
9.3.1.2 Memory Management Controller (MMC)
The MMC manages the interface to the peripherals by controlling the interface bus for extending the read and
write accesses to each peripheral. The unit generates eight peripheral select lines with 1 kB of address space
decoding.
9.3.1.3 System Management (SYS)
The SYS unit contains the software access protection by configuring user privilege levels to memory or
peripherals modules. It contains the ability to generate fault or reset conditions on decoding of illegal address or
access conditions. A clock control setup for the processor clock (MCLK) speed, is also available.
9.3.1.4 Central Interrupt Module (CIM)
The CIM accepts 32 interrupt requests for meeting firmware timing requirements. The ARM processor supports
two interrupt levels: FIQ and IRQ. FIQ is the highest priority interrupt. The CIM provides hardware expansion of
interrupts by use of FIQ/IRQ vector registers for providing the offset index in a vector table. This numerical index
value indicates the highest precedence channel with a pending interrupt and is used to locate the interrupt vector
address from the interrupt vector table. Interrupt channel 0 has the lowest precedence and interrupt channel 31
has the highest precedence. To remove the interrupt request, the firmware should clear the request as the first
action in the interrupt service routine. The request channels are maskable, allowing individual channels to be
selectively disabled or enabled.
Table 9-1. Interrupt Priority Table
MODULE COMPONENT OR
REGISTER
NAME
DESCRIPTION
PRIORITY
BRN_OUT_INT
EXT_INT
Brownout
Brownout interrupt
0 (Lowest)
External Interrupts
Watchdog Control
Interrupt on external input pin
Interrupt from watchdog exceeded (reset)
1
2
WDRST_INT
Wake-up interrupt when watchdog equals half of set watch
time
WDWAKE_INT
Watchdog Control
3
SCI_ERR_INT
SCI_RX_0_INT
SCI_TX_0_INT
SCI_RX_1_INT
SCI_TX_1_INT
PMBUS_INT
UART or SCI Control
UART or SCI Control
UART or SCI Control
UART or SCI Control
UART or SCI Control
UART or SCI error Interrupt. Frame, parity or overrun
UART0 RX buffer has a byte
4
5
UART0 TX buffer empty
6
UART1 RX buffer has a byte
7
UART1 TX buffer empty
8
PMBus related interrupt
9
DIG_COMP_SPI_I2C_INT 12-bit ADC Control, SPI, I2C
Digital comparator, SPI and I2C interrupt
10
“Prebias complete”, “Ramp Delay Complete”, “Ramp
Complete”, “Load Step Detected”,
FE0_INT Front End 0
11
“Over-Voltage Detected”, “EADC saturated”
Copyright © 2021 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
Table 9-1. Interrupt Priority Table (continued)
MODULE COMPONENT OR
REGISTER
NAME
DESCRIPTION
PRIORITY
“Prebias complete”, “Ramp Delay Complete”, “Ramp
Complete”, “Load Step Detected”,
“Over-Voltage Detected”, “EADC saturated”
FE1_INT
Front End 1
Front End 2
12
“Prebias complete”, “Ramp Delay Complete”, “Ramp
Complete”, “Load Step Detected”,
FE2_INT
13
“Over-Voltage Detected”, “EADC saturated”
PWM3_INT
16-bit Timer PWM 3
16-bit Timer PWM 2
16-bit Timer PWM 1
16-bit timer PWM 0
24-bit Timer Control
24-bit Timer Control
16-bit Timer PWM3 counter overflow or compare interrupt
16-bit Timer PWM2 counter Overflow or compare interrupt
16-bit Timer PWM1 counter overflow or compare interrupt
16-bit Timer PWM0 counter overflow or compare interrupt
24-bit Timer counter overflow interrupt
14
15
16
17
18
19
20
21
22
PWM2_INT
PWM1_INT
PWM0_INT
OVF24_INT
CAPTURE_1_INT
Reserved for future use
CAPTURE_0_INT
COMP_0_INT
24-bit Timer capture 1 interrupt
24-bit Timer Control
24-bit Timer Control
24-bit Timer capture 0 interrupt
24-bit Timer compare 0 interrupt
Constant Power Constant Current Mode switched in CPCC module Flag needs to be read for
CPCC_RTC_INT
ADC_CONV_INT
23
24
or Real Time Clock Output
details. RTC timer output generates an interrupt.
12-bit ADC Control
ADC end of conversion interrupt
Analog comparator interrupts, Over-Voltage detection,
Under-Voltage detection,
FAULT_INT
Fault Mux Interrupt
25
LLM load step detection
DPWM3
DPWM2
DPWM3
DPWM2
Same as DPWM1
Same as DPWM1
26
27
1) Every (1-256) switching cycles
2) Fault Detection
DPWM1
DPWM1
28
3) Mode switching
DPWM0
DPWM0
Same as DPWM1
29
30
EXT_FAULT_INT
SYS_SSI_INT
External Faults
System Software
Fault pin interrupt
System software interrupt
31 (highest)
9.3.2 Peripherals
9.3.2.1 Digital Power Peripherals
At the core of the UCD3138x controller are 3 Digital Power Peripherals (DPP). Each DPP can be configured to
drive from one to eight DPWM outputs. Each DPP consists of:
•
•
•
Differential input error ADC (EADC) with sophisticated controls
Hardware accelerated digital 2-pole/2-zero PID based filter
Digital PWM module with support for a variety of topologies
These can be connected in many different combinations, with multiple filters and DPWMs. They are capable of
supporting functions like input voltage feed forward, current mode control, and constant current/constant power,
etc.. The simplest configuration is shown in the following figure:
EAP
DPWMA
Digital
PWM
Error ADC
(Front End)
Filter
DPWMB
EAN
9.3.2.1.1 Front End
Figure 9-1 shows the block diagram of the front end module. It consists of a differential amplifier, an adjustable
gain error amplifier, a high speed flash analog to digital converter (EADC), digital averaging filters and a
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
precision high resolution set point DAC reference. The programmable gain amplifier in concert with the EADC
and the adjustable digital gain on the EADC output work together to provide 9 bits of range with 6 bits of
resolution on the EADC output. The output of the Front End module is a 9 bit sign extended result with a gain
of 1 LSB / mV. Depending on the value of AFE selected, the resolution of this output could be either 1, 2, 4 or
8 LSBs. In addition Front End 0 has the ability to automatically select the AFE value such that the minimum
resolution is maintained that still allows the voltage to fit within the range of the measurement. The EADC control
logic receives the sample request from the DPWM module for initiating an EADC conversion. EADC control
circuitry captures the EADC-9-bit-code and strobes the filter for processing of the representative error. The set
point DAC has 10 bits with an additional 4 bits of dithering resulting in an effective resolution of 14 bits. This
DAC can be driven from a variety of sources to facilitate things like soft start, nested loops, etc. Some additional
features include the ability to change the polarity of the error measurement and an absolute value mode which
automatically adds the DAC value to the error.
It is possible to operate the controller in a peak current mode control configuration. In this mode topologies like
the phase shifted full bridge converter can be controlled to maintain transformer flux balance. The internal DAC
can be ramped at a synchronously controlled slew rate to achieve a programmable slope compensation. This
eliminates the sub-harmonic oscillation as well as improves input voltage feed-forward performance. A0 is a
unity gain buffer used to isolate the peak current mode comparator. The offset of this buffer is specified in the
Section 8.5 table.
EAP
Front End Differential
Amplifier
REA
IOFFSET
AGND
EAN
REA
IOFFSET
AGND
Figure 9-1. Input Stage Of EADC Module
Copyright © 2021 Texas Instruments Incorporated
26
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
AFE_GAIN
23-AFE_GAIN
EAP0
EAN0
6 bit ADC
8mV/LSB
EADC
Signed 9 bit result
(error) 1 mV /LSB
2AFE_GAIN
X
Averaging
SAR/Prebias
Ramp
Filter x
CPCC
DAC0
A0
10 bit DAC
1.5625mV/LSB
ꢁ
Value
Dither
4 bit dithering gives 14 bits of effective resolution
97.65625ꢀV/LSB effective resolution
Absolute Value
Calculation
10 bit result
1.5625mV/LSB
Peak Current
Detected
Peak Current Mode
Comparator
Figure 9-2. Front End Module
9.3.2.1.2 DPWM Module
The DPWM module represents one complete DPWM channel with 2 independent outputs, A and B. Multiple
DPWM modules within the UCD3138x system can be configured to support all key power topologies. DPWM
modules can be used as independent DPWM outputs, each controlling one power supply output voltage rail. It
can also be used as a synchronized DPWM—with user selectable phase shift between the DPWM channels to
control power supply outputs with multiphase or interleaved DPWM configurations.
The output of the filter feeds the high resolution DPWM module. The DPWM module produces the pulse width
modulated outputs for the power stage switches. The filter calculates the necessary duty ratio as a 24-bit number
in Q23 fixed point format (23 bit integer with 1 sign bit). This represents a value within the range 0.0 to 1.0. This
duty ratio value is used to generate the corresponding DPWM output ON time. The resolution of the DPWM ON
time is 250 psec.
Each DPWM module can be synchronized to another module or to an external synchronization signal. An input
SYNC signal causes a DPWM ramp timer to reset. The SYNC signal outputs—from each of the four DPWM
modules—occur when the ramp timer crosses a programmed threshold. This allows the phase of the DPWM
outputs for multiple power stages to be tightly controlled.
The DPWM logic takes the output of the filter and converts it into the correct DPWM output for several power
supply topologies. It provides for programmable dead times and cycle adjustments for current balancing between
phases. It controls the triggering of the EADC. It can synchronize to other DPWMs or to external sources. It
can provide synchronization information to other DPWMs or to external recipients. In addition, it interfaces to
several fault handling circuits. Some of the control for these fault handling circuits is in the DPWM registers.
Fault handling is covered in the Fault Mux section.
Each DPWM module supports the following features:
•
•
•
Dedicated 14 bit time-base with period and frequency control
Shadow period register for end of period updates.
Quad-event control registers (A and B, rising and falling) (Events 1-4)
– Used for on/off DPWM duty ratio updates.
•
•
•
Phase control relative to other DPWM modules
Sample trigger placement for output voltage sensing at any point during the DPWM cycle.
Support for 2 independent edge placement DPWM outputs (same frequency or period setting)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
•
•
•
•
•
Dead-time between DPWM A and B outputs
High Resolution PWM capability – 250 ps
Pulse cycle adjustment of up to ±8.192 µs ( 32768 × 250 ps)
Active high/ active low output polarity selection
Provides events to trigger both CPU interrupts and start of ADC12 conversions.
9.3.2.1.3 DPWM Events
Each DPWM can control the following timing events:
1. Sample Trigger Count–This register defines where the error voltage is sampled by the EADC in relationship
to the DPWM period. The programmed value set in the register should be one fourth of the value calculated
based on the DPWM clock. As the DCLK (DCLK = 62.5 MHz max) controlling the circuitry runs at one
fourth of the DPWM clock (PCLK = 250MHz max). When this sample trigger count is equal to the DPWM
Counter, it initiates a front end calculation by triggering the EADC, resulting in a CLA calculation, and a
DPWM update. Over-sampling can be set for 2, 4 or 8 times the sampling rate.
2. Phase Trigger Count–count offset for slaving another DPWM (Multi-Phase/Interleaved operation).
3. Period–low resolution switching period count. (count of PCLK cycles)
4. Event 1–count offset for rising DPWM A event. (PCLK cycles)
5. Event 2–DPWM count for falling DPWM A event that sets the duty ratio. Last 4 bits of the register are for
high resolution control. Upper 14 bits are the number of PCLK cycle counts.
6. Event 3–DPWM count for rising DPWM B event. Last 4 bits of the register are for high resolution control.
Upper 14 bits are the number of PCLK cycle counts.
7. Event 4–DPWM count for falling DPWM B event. Last 4 bits of the register are for high resolution control.
Upper 14 bits are the number of PCLK cycle counts.
8. Cycle Adjust–Constant offset for Event 2 and Event 4 adjustments.
Basic comparisons between the programmed registers and the DPWM counter can create the desired edge
placements in the DPWM. High resolution edge capability is available on Events 2, 3 and 4.
Copyright © 2021 Texas Instruments Incorporated
28
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
Multi Mode Open Loop
Start of Period
Period
Start of Period
Period Counter
DPWM Output A
Event 1
Event 2 (High Resolution)
Cycle Adjust A (High Resolution)
Sample Trigger 1
To Other
Modules
Blanking A Begin
Blanking A End
DPWM Output B
Event 3 (High Resolution)
Event 4 (High Resolution)
Cycle Adjust B (High Resolution)
Sample Trigger 2
Blanking B Begin
To Other
Modules
Blanking B End
Phase Trigger
Events which change with DPWM mode:
DPWM A Rising Edge = Event 1
DPWM A Falling Edge = Event 2 + Cycle Adjust A
DPWM B Rising Edge = Event 3
DPWM B Falling Edge = Event 4 + Cycle Adjust B
Phase Trigger = Phase Trigger Register value
Events always set by their registers, regardless of mode:
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B Begin,
Blanking B End
Figure 9-3. Multi Mode Open Loop
Figure 9-3 is for multi-mode, open loop. Open loop means that the DPWM is controlled entirely by its own
registers, not by the filter output. In other words, the power supply control loop is not closed.
The Sample Trigger signals are used to trigger the Front End to sample input signals. The Blanking signals are
used to blank fault measurements during noisy events, such as FET turn on and turn off. Additional DPWM
modes are described below.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
29
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
9.3.2.1.4 High Resolution DPWM
Unlike conventional PWM controllers where the frequency of the clock dictates the maximum resolution of PWM
edges, the UCD3138x DPWM can generate waveforms with resolutions as small as 250 ps. This is 16 times the
resolution of the clock driving the DPWM module.
This is achieved by providing the DPWM mechanism with 16 phase shifted clock signals of 250 MHz each.
9.3.2.1.5 Over Sampling
The DPWM module has the capability to trigger an over sampling event by initiating the EADC to sample the
error voltage. The default “00” configuration has the DPWM trigger the EADC once based on the sample trigger
register value. The over sampling register has the ability to trigger the sampling 2, 4 or 8 times per PWM period.
Thus the time the over sample happens is at the divide by 2, 4, or 8 time set in the sampling register. The “01”
setting triggers 2X over sampling, the “10” setting triggers 4X over sampling, and the “11” triggers over sampling
at 8X.
9.3.2.1.6 DPWM Interrupt Generation
The DPWM has the capability to generate a CPU interrupt based on the PWM frequency programmed in the
period register. The interrupt can be scaled by a divider ratio of up to 255 for developing a slower interrupt
service execution loop. This interrupt can be fed to the ADC circuitry for providing an ADC12 trigger for
sequence synchronization. Table 9-2 outlines the divide ratios that can be programmed.
9.3.2.1.7 DPWM Interrupt Scaling/Range
Table 9-2. DPWM Interrupt Divide Ratio
NUMBER OF 32
INTERRUPT
DIVIDE
SETTING
INTERRUPT
DIVIDE
COUNT
INTERRUPT
DIVIDE
COUNT (HEX)
SWITCHING PERIOD
FRAMES (assume
1MHz loop)
MHZ
PROCESSOR
CYCLES
1
2
0
1
00
01
03
07
0F
1F
2F
3F
4F
5F
7F
9F
BF
DF
FF
1
2
32
64
3
3
4
128
4
7
8
256
5
15
31
47
63
79
95
127
159
191
223
255
16
32
48
64
80
96
128
160
192
224
256
512
6
1024
1536
2048
2560
3072
4096
5120
6144
7168
8192
7
8
9
10
11
12
13
14
15
9.3.3 Automatic Mode Switching
Automatic Mode switching enables the DPWM module to switch between modes automatically, with no firmware
intervention. This is useful to increase efficiency and power range. The following paragraphs describe phase-
shifted full bridge and LLC examples.
9.3.3.1 Phase Shifted Full Bridge Example
In phase shifted full bridge topologies, efficiency can be increased by using pulse width modulation, rather than
phase shift, at light load. This is shown below:
Copyright © 2021 Texas Instruments Incorporated
30
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
DPWM3A
(QB1)
DPWM3B
(QT1)
DPWM2A
(QT2)
DPWM2B
(QB2)
VTrans
DPWM1B
(QSYN1,3)
DPWM0B
(QSYN2,4)
IPRI
Figure 9-4. Phase-Shifted Full Bridge Waveforms
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
31
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
L1
T1
Q7
+12V
Q6
Q5
C1
RL
VBUS
I_pri
PRIM
CURRENT
ORING
CTL
T2
VOUT
C2
R2
D1
D2
QT2
QB2
QT1
VA
Lr
T1
Current
Sensing
QB1
DPWM0B
DPWM1B
Vref
DPWM0
Duty for mode
switching
Vout
Iout
CPCC
<
EADC0
EADC1
CLA0
DPWM1
DPWM2
CLA1
DPWM2A
DPWM2B
Load Current
DPWM3A
DPWM3B
I_pri
EADC2
DPWM3
PCM
AD00
AD01
ISOLATED
GATE Transformer
ACFAIL_IN
FAULT 0
FAULT 1
FAULT 2
SYNCHRONOUS
GATE DRIVE
ACFAIL_OUT
FAILURE
AD02/CMP0
AD03/CMP1/CMP2
AD04/CMP3
AD05/CMP4
AD06/CMP5
AD07/CMP6
AD08
I_SHARE
Vout
FAULT
GPIO1
GPIO2
GPIO3
ORING_CRTL
ON/OFF
Iout
I_pri
CBC
temp
P_GOOD
Vin
VA
WD
ARM7
AD09
PMBus
UART0
RST
OSC
Primary
UART1
Memory
Figure 9-5. Secondary-Referenced Phase-Shifted Full Bridge Control With Synchronous Rectification
9.3.3.2 LLC Example
In LLC, three modes are used. At the highest frequency, a pulse width modulated mode (Multi Mode) is used. As
the frequency decreases, resonant mode is used. As the frequency gets still lower, the synchronous MOSFET
drive changes so that the on-time is fixed and does not increase. In addition, the LLC control supports cycle-
by-cycle current limiting. This protection function operates by a comparator monitoring the maximum current
during the DPWMA conduction time. Any time this current exceeds the programmable comparator reference the
pulse is immediately terminated. Due to classic instability issues associated with half-bridge topologies it is also
possible to force DPWMB to match the truncated pulse width of DPWMA. Here are the waveforms for the LLC:
PWM
Mode
LLC Mode
fr
fs= fr_max
fs< fr
fs> fr
Q1T
Q1B
QSR1
QSR2
Tr= 1/fr
Tr= 1/fr
ISEC(t)
Figure 9-6. LLC Waveforms
Copyright © 2021 Texas Instruments Incorporated
32
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
VBUS
Q1T
ILR(t)
Transformer
QSR2
LRES
LK
NS
NS
Driver
DPWM1B
ISEC(t)
Oring Circuitry
RLRES
Q1B
ILM(t)
LM
VOUT
NP
RF1
RF2
AD03
EAP0
COUT1
COUT2
VOUT(t)
VBUS
ESR1
ESR2
CF
QSR1
EAN0
AD04
CRES
RS
Driver
DPWM1A
CS
CRES
VCR(t)
RS1
RS2
ADC13
EAP1
Driver
Driver
DPWM0B
DPWM0A
Figure 9-7. Secondary-Referenced Half-Bridge Resonant LLC Control With Synchronous Rectification
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
33
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
9.3.3.3 Mechanism For Automatic Mode Switching
The UCD3138x allows the customer to enable up to two distinct levels of automatic mode switching. These
different modes are used to enhance light load operation, short circuit operation and soft start. Many of the
configuration parameters for the DPWM are in DPWM Control Register 1. For automatic mode switching, some
of these parameters are duplicated in the Auto Config Mid and Auto Config High registers.
If automatic mode switching is enabled, the filter duty signal is used to select which of these three registers is
used. There are 4 registers which are used to select the points at which the mode switching takes place. They
are used as shown below.
Automatic Mode Switching
With Hysteresis
Filter Duty
Full Range
Auto Config High
High – Upper Threshold
High – Lower Threshold
Auto Config Mid
Low – Upper Threshold
Low – Lower Threshold
Control
Register 1
0
Figure 9-8. Automatic Mode Switching
As shown, the registers are used in pairs for hysteresis. The transition from Control Register 1 to Auto Config
Mid only takes place when the Filter Duty goes above the Low Upper threshold. It does not go back to Auto
Config Mid until the Low Lower Threshold is passed. This prevents oscillation between modes if the filter duty is
close to a mode switching point.
9.3.4 DPWMC, Edge Generation, Intramux
The UCD3138x has hardware for generating complex waveforms beyond the simple DPWMA and DPWMB
waveforms already discussed – DPWMC, the Edge Generation Module, and the IntraMux.
DPWMC is a signal inside the DPWM logic. It goes high at the Blanking A begin time, and low at the Blanking A
end time.
The Edge Gen module takes DPWMA and DPWMB from its own DPWM module, and the next one, and uses
them to generate edges for two outputs. For DPWM3, the DPWM0 is considered to be the next DPWM. Each
edge (rising and falling for DPWMA and DPWMB) has 8 options which can cause it.
The options are:
Copyright © 2021 Texas Instruments Incorporated
34
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
0 = DPWM(n) A Rising edge
1 = DPWM(n) A Falling edge
2 = DPWM(n) B Rising edge
3 = DPWM(n) B Falling edge
4 = DPWM(n+1) A Rising edge
5 = DPWM(n+1) A Falling edge
6 = DPWM(n+1) B Rising edge
7 = DPWM(n+1) B Falling edge
Where “n" is the numerical index of the DPWM module of interest. For example n=1 refers to DPWM1.
The Edge Gen is controlled by the DPWMEDGEGEN register. It also has an enable/disable bit.
The IntraMux is controlled by the Auto Config registers. Intra Mux is short for intra multiplexer. The IntraMux
takes signals from multiple DPWMs and from the Edge Gen and combines them logically to generate DPWMA
and DPWMB signals This is useful for topologies like phase-shifted full bridge, especially when they are
controlled with automatic mode switching. Of course, it can all be disabled, and DPWMA and DPWMB will
be driven as described in the sections above. If the Intra Mux is enabled, high resolution must be disabled, and
DPWM edge resolution goes down to 4 ns.
Here is a drawing of the Edge Gen/Intra Mux:
A/B/C (N)
A/B/C (N+1)
INTRAMUX
C (N+2)
C (N+3)
PWM A
PWM B
EDGE GEN
A(N)
B(N)
EGEN A
EGEN B
A(N+1)
B(N+1)
B SELECT
A SELECT
A ON SELECT
A OFF SELECT
B ON SELECT
B OFF SELECT
Figure 9-9. Edge Generation / IntraMux
Here is a list of the IntraMux modes for DPWMA:
0 = DPWMA(n) pass through (default)
1 = Edge-gen output, DPWMA(n)
2 = DPWNC(n)
3 = DPWMB(n) (Crossover)
4 = DPWMA(n+1)
5 = DPWMB(n+1)
6 = DPWMC(n+1)
7 = DPWMC(n+2)
8 = DPWMC(n+3)
and for DPWMB:
0 = DPWMB(n) pass through (default)
1 = Edge-gen output, DPWMB(n)
2 = DPWNC(n)
3 = DPWMA(n) (Crossover)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
35
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
4 = DPWMA(n+1)
5 = DPWMB(n+1)
6 = DPWMC(n+1)
7 = DPWMC(n+2)
8 = DPWMC(n+3)
The DPWM number wraps around just like the Edge Gen unit. For DPWM3 the following definitions apply:
DPWM(n)
DPWM3
DPWM0
DPWM1
DPWM2
DPWM(n+1)
DPWM(n+2)
DPWM(n+3)
9.3.5 Filter
The UCD3138x filter is a PID filter with many enhancements for power supply control. Some of its features
include:
•
•
•
•
•
•
•
•
•
•
•
Traditional PID Architecture
Programmable non-linear limits for automated modification of filter coefficients based on received EADC error
Multiple coefficient sets fully configurable by firmware
Full 24-bit precision throughout filter calculations
Programmable clamps on integrator branch and filter output
Ability to load values into internal filter registers while system is running
Ability to stall calculations on any of the individual filter branches
Ability to turn off calculations on any of the individual filter branches
Duty cycle, resonant period, or phase shift generation based on filter output.
Flux balancing
Voltage feed forward
Here is the first section of the Filter :
Copyright © 2021 Texas Instruments Incorporated
36
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
Limit Comparator
Limit 6
Limit 5
…..
PID Filter Branch Stages
Limit 0
Coefficient
select
EADC_DATA
Xn
16
24
9
24
X
P
9
9
24
16
24
24
9
9
24
24
9
+
+
X
I
24
24
Ki Low
9
24
24
X
32
9
Round
24
16
24
X –X
9
n
n-1
9
24
24
-
X
Clamp
+
D
Figure 9-10. First Section of the Filter
The filter input, Xn, generally comes from a front end. Then there are three branches, P, I. and D. Note that the D
branch also has a pole, Kd Alpha. Clamps are provided both on the I branch and on the D alpha pole.
The filter also supports a nonlinear mode, where up to 7 different sets of coefficients can be selected depending
on the magnitude of the error input Xn. This can be used to increase the filter gain for higher errors to improve
transient response.
Here is the output section of the filter (S0.23 means that there is 1 sign bit, 0 integer bits and 23 fractional bits).:
Filter Yn
Clamp High
Yn Scale
Shifter
24
24
24
P
I
24
24
24
S0.23
26
Filter Yn
Saturate
Yn
Clamp
+
D
S2.23
S0.23
S0.23
Filter Yn
Clamp Low
All are S0.23
Figure 9-11. Output Section of the Filter
This section combines the P, I, and D sections, and provides for saturation, scaling, and clamping.
There is a final section for the filter, which permits its output to be matched to the DPWM:
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
37
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
Filter Output
Clamp High
Round to
18 bits,
Clamp to
Positive
Truncate
low 4 bits
Filter Period
Bits [17:4]
Filter YN
38
18
14
X
S14.23
24
S0.23
14.4
14.0
Round to
18 bits,
Filter YN (Duty %)
18
Filter Duty
14.4
38
18
Clamp
X
Clamp to
Positive
KCompx 14.0
24
S0.23
S14.23
14.4
14
14.0
DPWMx Period 14.0
14.0
KCompx
DPWMx Period
Loop_VFF
14
Filter Output
Clamp Low
14.0
14.0
14.0
PERIOD_MULT_SEL
14.0
Resonant Duty
OUTPUT_MULT_SEL
Figure 9-12. Final Section for the Filter
This permits the filter output to be multiplied by a variety of correction factors to match the DPWM Period, to
provide for Voltage Feed Forward, or for other purposes. After this, there is another clamp. For resonant mode,
the filter can be used to generate both period and duty cycle.
9.3.5.1 Loop Multiplexer
The Loop Mux controls interconnections between the filters, front ends, and DPWMs. Any filter, front end, and
DPWM can be combined in a variety of configurations.
It also controls the following connections:
•
•
•
•
•
DPWM to Front End
Front End DAC control from Filters or Constant Current/Constant Power Module
Filter Special Coefficients and Feed Forward
DPWM synchronization
Filter to DPWM
The following control modules are configured in the Loop Mux:
•
•
•
•
•
Constant Power/Constant Current
Cycle Adjustment (Current and flux balancing)
Global Period
Light Load (Burst Mode)
Analog Peak Current Mode
9.3.5.2 Fault Multiplexer
In order to allow a flexible way of mapping several fault triggering sources to all the DPWMs channels, the
UCD3138x provides an extensive array of multiplexers that are united under the name Fault Mux module.
The Fault Mux Module supports the following types of mapping between all the sources of fault and all the
different fault response mechanisms inside each DPWM module.
•
Many fault sources may be mapped to a single fault response mechanism. For instance an analog
comparator in charge of over voltage protection, a digital comparator in charge of over current protection
and an external digital fault pin can be all mapped to a Fault-A signal connected to a single FAULT MODULE
and shut down DPWM1-A.
•
•
A single fault source can be mapped to many fault response mechanisms inside many DPWM modules.
For instance an analog comparator in charge of over current protection can be mapped to DPWM-0 through
DPWM-3 by way of several fault modules.
Many fault sources can be mapped to many fault modules inside many DPWM modules.
Copyright © 2021 Texas Instruments Incorporated
38
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
CBC_PWM_AB_EN
FAULT MUX
DPWM
Bit20 in DPWMCTRL0
CYCLE BY CYCLE
ANALOG PCM
FAULT- CBC
AB FLAG
FAULT MODULE
DISABLE PWM A AND B
CBC_FAULT_EN
Bit30 in DPWMFLTCTRL
FAULT- AB
FAULT-A
FAULT-B
AB FLAG
FAULT MODULE
DISABLE PWM A AND B
DCOMP– 4X
EXT GPIO– 4X
ACOMP – 7X
A FLAG
FAULT MODULE
DISABLE PWM A ONLY
B FLAG
FAULT MODULE
DISABLE PWM B ONLY
ALL_FAULT_EN
DPWM_EN
Bit 31 in DPWMFLTCTRL
Bit0 in DPWMCTRL0
Figure 9-13. Fault Mux Module
The Fault Mux Module provides a multitude of fault protection functions within the UCD3138x high-speed loop
(Front End Control, Filter, DPWM and Loop Mux modules). The Fault Mux Module allows highly configurable
fault generation based on digital comparators, high-speed analog comparators and external fault pins. Each of
the fault inputs to the DPWM modules can be configured to one or any combination of the fault events provided
in the Fault Mux Module.
Each one of the DPWM engines has four fault modules. The modules are called CBC fault module, AB fault
module, A fault module and B fault module.
The internal circuitry in all the four fault modules is identical, and the difference between the modules is limited to
the way the modules are attached to the DPWMs.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
39
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
FAULT FLAG
FAULT IN
FAULT MODULE
Figure 9-14. Fault Module
All fault modules provide immediate fault detection but only once per DPWM switching cycle. Each one of the
fault modules own a separate max_count and the fault flag will be set only if sequential cycle-by-cycle fault count
exceeds max_count.
Once the fault flag is set, DPWMs need to be disabled by DPWM_EN going low in order to clear the fault flags.
Please note, all four Fault Modules share the same DPWM_EN control, all fault flags (output of Fault Modules)
will be cleared simultaneously.
All four Fault Modules share the same global FAULT_EN as well. Therefore a specific Fault Module cannot be
enabled/ disabled separately.
FAULT - CBC
CLIM
CYCLE BY CYCLE
Figure 9-15. Cycle-By-Cycle Block
Unlike Fault Modules, only one Cycle by Cycle block is available in each DPWM module.
The Cycle by Cycle block works in conjunction with CBC Fault Module and enables DPWM reaction to signals
arriving from the Analog Peak current mode (PCM) module.
The Fault Mux Module supports the following basic functions:
•
•
•
•
4 digital comparators using the Front End EADCs with programmable thresholds and fault generation
Configuration for 7 high speed analog comparators with programmable thresholds and fault generation
External GPIO detection control with programmable fault generation
Configurable DPWM fault generation for DPWM Current Limit Fault, DPWM Over-Voltage Detection Fault,
DPWM A External Fault, DPWM B External Fault and DPWM IDE Flag
•
•
Clock Failure Detection for High and Low Frequency Oscillator blocks
Discontinuous Conduction Mode Detection
Copyright © 2021 Texas Instruments Incorporated
40
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
HFO/LFO
Fail Detect
DCM Detection
Analog Comparator 0
Control
Analog
Comparator 0
Digital Comparator 0
Control
Front End
Control 0
Analog Comparator 1
Control
Analog
Comparator 1
Digital Comparator 1
Control
Front End
Control 1
Analog Comparator 2
Control
Analog
Comparator 2
Digital Comparator 2
Control
Analog Comparator 3
Control
Analog
Comparator 3
Front End
Control 2
Digital Comparator 3
Control
Analog Comparator 4
Control
Analog
Comparator 4
fault[2:0]
External GPIO
Detection
Analog Comparator 5
Control
Analog
Comparator 5
DPWM 0
Fault Control
DPWM 1
Fault Control
DPWM 2
Fault Control
DPWM 3
Fault Control
Analog Comparator 6
Control
Analog
Comparator 6
DPWM 0
DPWM 1
DPWM 2
DPWM 3
Analog Comparator
Automated Ramp
Figure 9-16. Fault Mux Block Diagram
9.3.6 Communication Ports
9.3.6.1 SCI (UART) Serial Communication Interface
A maximum of two independent Serial Communication Interface (SCI) or Universal Asynchronous Receiver/
Transmitter (UART) interfaces are included within the device for asynchronous start-stop serial data
communication (see the pin out sections for details). Each interface has a 24 bit pre-scaler for supporting
programmable baud rates, a programmable data word and stop bit options. Half or full duplex operation is
configurable through register bits. A loop back feature can also be setup for firmware verification. Both SCI-TX
and SCI-RX pin sets can be used as GPIO pins when the peripheral is not being used.
9.3.6.2 PMBUS/I2C
The UCD3138x has two independent interfaces which both support PMBus and I2C in master and slave modes.
Only one of the interfaces has control of the address pin current sources as well as support for the optional
Control and Alert lines described in the PMBus specification. Other than these differences, the interfaces are
identical.
The PMBus/I2C interface is designed to minimize the processor overhead required for interface. It can
automatically detect and acknowledge addresses. It handles start and stop conditions automatically, and can
clock stretch until the processor has time to poll the PMBus status. It will automatically receive and send up
to 4 bytes at a time. It can automatically verify and generate a PEC. This means that a write byte command
can be received by the processor with only one function call. There is no need for any interrupts at all with this
PMBus/I2C interface. If it is polled every few milliseconds, it will work perfectly.
The interface also supports automatic ACK of two independent addresses. If both PMBus/I2C interfaces are
used at the same time a total of 4 independent addresses can be automatically detected.
Example: PMBus Address Decode via ADC12 Reading
The user can allocate 2 pins of the 12-bit ADC input channels, AD_00 and AD_01, for PMBus address decoding.
At power-up the device applies IBIAS to each address detect pin and the voltage on that pin is captured by the
internal 12-bit ADC.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
41
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
Vdd
AD00,
AD01
pin
On/Off Control
I
BIAS
Resistor to
set PMBus
Address
To ADC Mux
Figure 9-17. PMBUS Address Detection Method
PMBus/I2C address 0x7E is a reserved address and should not be used in a system using the UCD3138x. This
address is used for manufacturing test.
9.3.6.3 SPI
The SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed
length (1 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is
normally used for communication between the UCD3138x and external peripherals. Typical applications include
an interface to external I/O or peripheral expansion via devices such as shift registers, display drivers, SPI
EPROMs and analog-to-digital converters. The SPI allows serial communication with other SPI devices through
a 3-pin or 4-pin mode interface. The SPI typically is configured as a master for communicating to external
EEPROM.
Copyright © 2021 Texas Instruments Incorporated
42
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
SCS
tCSS
tWH
tWL
tCSH
SCK
tSU
tH
MISO
MOSI
VALID IN
tV
tHO
VALID OUT
PSCK
tWH
tWL
tSU
tH
tV
tHO
tCSS
Period SCK
2 ICLK
1/2 PSCK
1/2 PSCK
2 ns (typical)
4 ns (typical)
4 ns (typical)
2 ns (typical)
1 PSCK
SCK High Time
SCK Low Time
Data in setup
Data in hold
Ouput Valid
Ouput Data Hold
Chip Select Setup
Chip Select Hold
tCSH
1 PSCK
Figure 9-18. SPI Timing Diagram
9.3.7 Real Time Clock
The UCD3138x has an internal real time clock (RTC) function that can track time in seconds, minutes, hours and
days. This function requires an external precision 10 MHz clock.
•
Firmware writable time/day register which tracks the total number of days.
– The day counter will be able to count 4 years worth of days.
– Years and months and leap year calculation must be calculated in firmware.
•
•
•
•
Firmware programmable frequency correction of ±200 ppm in 0.8 ppm steps
The RTC function can provide interrupts to the IRQ or FIQ at 1, 10, 30, and 60 second intervals.
The clock from the RTC driver can be driven to an external pin through an internal multiplexor
The clock for the RTC function can come from an external clock through a dedicated GPIO pin.
9.3.8 Timers
External to the Digital Power Peripherals there are 3 different types of timers in UCD3138x. They are the 24-bit
timer, 16-bit timer and the watchdog timer
9.3.8.1 24-Bit Timer
There is one 24 bit timer which runs off the Interface Clock. It can be used to measure the time between two
events, and to generate interrupts after a specific interval. Its clock can be divided down by an 8-bit pre-scalar
to provide longer intervals. The timer has two compare registers (Data Registers). Both can be used to generate
an interrupt after a time interval. . Additionally, the timer has a shadow register (Data Buffer register) which can
be used to store CPU updates of the compare events while still using the timer. The selected shadow register
update mode happens after the compare event matches.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
43
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
The two capture pins TCAP0 and TCAP1 are inputs for recording a capture event. A capture event can be set
either to rising, falling, or both edges of the capture pin signal. Upon this event, the counter value is stored in
the corresponding capture data register. Five Interrupts from the 24 bit timer can be set, which are the counter
rollover event (overflow), capture events 0 and 1, and the two comparison match events. Each interrupt can be
disabled or enabled.
9.3.8.2 16-Bit PWM Timers
There are four 16 bit counter PWM timers which run off the Interface Clock and can further be divided down by
a 8-bit pre-scaler to generate slower PWM time periods. Each timer has two compare registers (Data Registers)
for generating the PWM set/unset events. Additionally, each timer has a shadow register (Data Buffer register)
which can be used to store CPU updates of compare events while still using the timer. The selected shadow
register update mode happens after the compare event matches.
The counter reset can be configured to happen on a counter roll over, a compare equal event, or by a software
controlled register. Interrupts from the PWM timer can be set due to the counter rollover event (overflow) or
by the two comparison match events. Each comparison match and the overflow interrupts can be disabled or
enabled.
Upon an event comparison, the PWM pin can be configured to set, clear, toggle or have no action at the output.
The value of PWM pin output can be read for status or simply configured as General Purpose I/O for reading the
value of the input at the pin.
9.3.8.3 Watchdog Timer
A watchdog timer is provided on the device for ensuring proper firmware loop execution. The timer is clocked
off of a separate low speed oscillator source. If the timer is allowed to expire, a reset condition is issued to the
ARM processor. The watchdog is reset by a simple CPU write bit to the watchdog key register by the firmware
routine. On device power-up the watchdog is disabled. Yet after it is enabled, the watchdog cannot be disabled
by firmware. Only a device reset can put this bit back to the default disabled state. A half timer flag is also
provided for status monitoring of the watchdog.
9.3.9 General Purpose ADC12
The ADC12 is a 12 bit, high speed analog to digital converter, equipped with the following options:
•
•
•
•
Typical conversion speed of 267 ksps
Conversions can consist from 1 to 16 ADC channel conversions in any desired sequence
Post conversion averaging capability, ranging from 4X, 8X, 16X or 32X samples
Configurable triggering for ADC conversions from the following sources: firmware, DPWM rising edge,
ADC_EXT_TRIG pin or Analog Comparator results
•
•
Interrupt capability to embedded processor at completion of ADC conversion
Six digital comparators on the first 6 channels of the conversion sequence using either raw ADC data or
averaged ADC data
•
•
•
Two 10 µA current sources for excitation of PMBus addressing resistors
Dual sample and hold for accurate power measurement
Internal temperature sensor for temperature protection and monitoring
The control module (Figure 9-19) contains the control and conversion logic for auto-sequencing a series of
conversions. The sequencing is fully configurable for any combination of 16 possible ADC channels through an
analog multiplexer embedded in the ADC12 block. Once converted, the selected channel value is stored in the
result register associated with the sequence number. Input channels can be sampled in any desired order or
programmed to repeat conversions on the same channel multiple times during a conversion sequence. Selected
channel conversions are also stored in the result registers in order of conversion, where the result 0 register
is the first conversion of a 16-channel sequence and result 15 register is the last conversion of a 16-channel
sequence. The number of channels converted in a sequence can vary from 1 to 16.
Unlike EADC0 through EADC2, which are primarily designed for closing high speed compensation loops, the
ADC12 is not usually used for loop compensation purposes. The EADC converters have a substantially faster
conversion rate, thus making them more attractive for closed loop control. The ADC12 features make it best
Copyright © 2021 Texas Instruments Incorporated
44
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
suited for monitoring and detection of currents, voltages, temperatures and faults. Please see the Section 8.10
for the temperature variation associated with this function.
ADC12 Block
ADC12 Registers
ADC
Averaging
12-bit SAR
S/H
ADC
ADC
Channels
ADC12
Control
Digital
Comparators
ADC Channel
ADC External Trigger (from pin)
Analog
Comparators
DPWM
Modules
Figure 9-19. ADC12 Control Block Diagram
9.3.10 Miscellaneous Analog
The Miscellaneous Analog Control (MAC) Registers are a catch-all of registers that control and monitor a wide
variety of functions. These functions include device supervisory features such as Brown-Out and power saving
configuration, general purpose input/output configuration and interfacing, internal temperature sensor control and
current sharing control.
The MAC module also provides trim signals to the oscillator and AFE blocks. These controls are usually used at
the time of trimming at manufacturing; therefore this document will not cover these trim controls.
9.3.11 Brownout
Brownout function is used to determine if the device supply voltage is lower than a threshold voltage, a condition
that may be considered unsafe for proper operation of the device.
The brownout threshold is higher than the reset threshold voltage; therefore, when the supply voltage is lower
than brownout threshold, it still does not necessarily trigger a device reset.
The brownout interrupt flag can be polled or alternatively can trigger an interrupt to service such case by an
interrupt service routine. Please see the Section 8.8.
9.3.12 Global I/O
Up to 32 pins in UCD3138x can be configured in the Global I/O register to serve as a general purpose input or
output pins (GPIO). This includes all digital input or output pins except for the RESET pin.
The pins that cannot be configured as GPIO pins are the supply pins, ground pins, ADC-12 analog input pins,
EADC analog input pins and the RESET pin. Additional digital pins not listed in this register can be configured
through their local configuration registers.
There are two ways to configure and use the digital pins as GPIO pins:
1. Through the centralized Global I/O control registers.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
45
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
2. Through the distributed control registers in the specific peripheral that shares it pins with the standard GPIO
functionality.
The Global I/O registers offer full control of:
1. Configuring each pin as a GPIO.
2. Setting each pin as input or output.
3. Reading the pin’s logic state, if it is configured as an input pin.
4. Setting the logic state of the pin, if it is configured as an output pin.
5. Connecting pin/pins to high rail through internal push/pull drivers or external pull up resistors.
The Global I/O registers include Global I/O EN register, Global I/O OE Register, Global I/O Open Drain Control
Register, Global I/O Value Register and Global I/O Read Register.
The following is showing the format of Global I/O EN Register (GLBIOEN) as an example:
BIT NUMBER
Bit Name
Access
31:0
GLOBAL_IO_EN
R/W
Default
0000_0000_0000_0000_0000_0000_0000_0000
Bits 29-0: GLOBAL_IO_EN – This register enables the global control of digital I/O pins
0 = Control of IO is done by the functional block assigned to the IO (Default)
1 = Control of IO is done by Global IO registers. Note that the effect of the GLBIO register is tied to the pin. If you
change the pin function using the IOMUX register the GLBIO setting does not move with the function but stays
with the pin.
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
PIN_NAME
PWM2
PWM3
FAULT3
ADC_EXT_TRIG
TCK
TDO
TMS
TDI
SCI_TX1
SCI_TX0
SCI_RX1
SCI_RX0
TCAP0
PWM1
PWM0
TCAP1
I2C_DATA
PMBUS_CTRL
PMBUS_ALERT
EXT_INT
FAULT2
FAULT1
FAULT0
SYNC
8
7
DPWM3B
DPWM3A
DPWM2B
6
5
Copyright © 2021 Texas Instruments Incorporated
46
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
BIT
4
PIN_NAME
DPWM2A
DPWM1B
DPWM1A
DPWM0B
DPWM0A
3
2
1
0
9.3.13 Temperature Sensor Control
Temperature sensor control register provides internal temperature sensor enabling and trimming capabilities.
The internal temperature sensor is disabled by default.
Figure 9-20. Internal Temp Sensor
Temperature sensor is calibrated at room temperature (25 °C) via a calibration register value.
The temperature sensor is measured using ADC12 (via channel 14). The temperature is then calculated using a
mathematical formula involving the calibration register (this effectively adds a delta to the ADC measurement).
The temperature sensor can be enabled or disabled.
9.3.14 I/O Mux Control
I/O Mux Control register may be used in order to choose a single specific functionality that is desired to be
assigned to a physical device pin for your application. See the UCD3138x programmer's manual for details on
the available configurations.
9.3.15 Current Sharing Control
UCD3138x provides three separate modes of current sharing operation.
•
•
•
•
Analog bus current sharing
PWM bus current sharing
Master/Slave current sharing
AD02 has a special ESD protection mechanism that prevents the pin from pulling down the current-share bus
if power is missing from the UCD3138x
The simplified current sharing circuitry is shown in the drawing below. The digital pulse connected to SW3
transforms SW3 into a pulse-width-modulated current source. Details on the frequency and resolution of this
feature are in the digital power fusion peripherals manual.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
47
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
3.3 V
ISHARE
SW3
Digital
3.3 V
3.3V
ESD
AD13
ESD
3.2 kΩ
400 Ω
250 Ω
AD02
ESD
SW2
SW1
250 Ω
EXT CAP
RSHARE
ADC12 and
CMP
ADC12 and
CMP
Figure 9-21. Simplified Current Sharing Circuitry
FOR TEST ONLY,
ALWAYS KEEP 00
CURRENT SHARING MODE
CS_MODE
EN_SW1
EN_SW2
DPWM
Off or Slave Mode (3-state)
PWM Bus
00
00
00
00
00 (default)
0
1
0
0
0
0
0
1
0
01
10
11
ACTIVE
Off or Slave Mode (3-state)
Analog Bus or Master
0
0
The period and the duty of 8-bit PWM current source and the state of the SW1 and SW2 switches can be
controlled through the current sharing control register (CSCTRL).
9.3.16 Temperature Reference
The temperature reference register (TEMPREF) provides the ADC12 count when ADC12 measures the internal
temperature sensor (channel 14) during the factory trim and calibration.
This information can be used by different periodic temperature compensation routines implemented in the
firmware. But it should not be overwritten by firmware, otherwise this factory written value will be lost until the
device is reset.
Copyright © 2021 Texas Instruments Incorporated
48
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
9.4 Device Functional Modes
9.4.1 DPWM Modes Of Operation
The DPWM is a complex logic system which is highly configurable to support several different power supply
topologies. The discussion below will focus primarily on waveforms, timing and register settings, rather than on
logic design.
The DPWM is centered on a period counter, which counts up from 0 to PRD, and then is reset and starts over
again.
The DPWM logic causes transitions in many digital signals when the period counter hits the target value for that
signal.
9.4.1.1 Normal Mode
In Normal mode, the Filter output determines the pulse width on DPWM A. DPWM B fits into the rest of the
switching period, with a dead time separating it from the DPWM A on-time. It is useful for buck topologies,
among others. Here is a drawing of the Normal Mode waveforms:
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
49
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
Normal Mode Closed Loop
Start of Period
Period
Start of Period
Period Counter
Filter controlled edge
DPWM Output A
Event 1
Filter Duty (High Resolution)
Cycle Adjust A (High Resolution)
Adaptive Sample Trigger A
Adaptive Sample Trigger B
Sample Trigger 1
Blanking A Begin
To Other
Modules
Blanking A End
DPWM Output B
Event 3 – Event 2 (High Res)
Event 4 (High Res)
Sample Trigger 2
Blanking B Begin
Blanking B End
Phase Trigger
To Other
Modules
Events which change with DPWM mode:
DPWM A Rising Edge = Event 1
DPWM A Falling Edge = Event 1 + Filter Duty + Cycle Adjust A
Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive Sample Register or
Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive Sample Register
DPWM B Rising Edge = Event 1 + Filter Duty + Cycle Adjust A + (Event 3 – Event 2)
DPWM B Falling Edge = Event 4
Phase Trigger = Phase Trigger Register value or Filter Duty
Events always set by their registers, regardless of mode:
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B
Begin, Blanking B End
Figure 9-22. Normal Mode - Closed Loop
Cycle adjust A can be used to adjust pulse widths on individual phases of a multi-phase system. This can be
used for functions like current balancing. The Adaptive Sample Triggers can be used to sample in the middle of
the on-time (for an average output), or at the end of the on-time (to minimize phase delay) The Adaptive Sample
Register provides an offset from the center of the on-time. This can compensate for external delays, such as
MOSFET and gate driver turn on times.
Blanking A-Begin and Blanking A-End can be used to blank out noise from the MOSFET turn on at the beginning
of the period (DPWMA rising edge). Blanking B could be used at the turn off time of DPWMB. The other edges
are dynamic, so blanking is more difficult.
Cycle Adjust B has no effect in Normal Mode.
Copyright © 2021 Texas Instruments Incorporated
50
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
9.4.1.2 Phase Shifting
In most modes, it is possible to synchronize multiple DPWM modules using the phase shift signal. The phase
shift signal has two possible sources. It can come from the Phase Trigger Register. This provides a fixed value,
which is useful for an application like interleaved PFC.
The phase shift value can also come from the filter output. In this case, the changes in the filter output causes
changes in the phase relationship of two DPWM modules. This is useful for phase shifted full bridge topologies.
The following figure shows the mechanism of phase shift:
Phase Shift
DPWM0 Start of Period
DPWM0 Start of Period
Period Counter
DPWM1 Start of Period
DPWM1 Start of Period
Period Counter
Phase Trigger = Phase Trigger Register value or Filter Duty
Figure 9-23. Phase Shifting
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
51
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
9.4.1.3 DPWM Multiple Output Mode
Multi mode is used for systems where each phase has only one driver signal. It enables each DPWM peripheral
to drive two phases with the same pulse width, but with a time offset between the phases, and with different
cycle adjusts for each phase.
The Multi-Mode diagram is shown in Figure 9-24.
Multi Mode Closed Loop
Start of Period
Start of Period
Period
Period Counter
Filter controlled edge
DPWM Output A
Event 1
Filter Duty (High Resolution)
Cycle Adjust A (High Resolution)
Adaptive Sample Trigger A
Adaptive Sample Trigger B
Sample Trigger 1
Blanking A Begin
To Other
Modules
Blanking A End
DPWM Output B
Event 3 (High Resolution)
Filter Duty (High Resolution)
Cycle Adjust B (High Resolution)
Sample Trigger 2
Blanking B Begin
Blanking B End
To Other
Modules
Phase Trigger
Events which change with DPWM mode:
DPWM A Rising Edge = Event 1
DPWM A Falling Edge = Event 1 + Filter Duty + Cycle Adjust A
Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive Sample Register or
Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive Sample Register
DPWM B Rising Edge = Event 3
DPWM B Falling Edge = Event 3 + Filter Duty + Cycle Adjust B
Phase Trigger = Phase Trigger Register value or Filter Duty
Events always set by their registers, regardless of mode:
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B
Begin, Blanking B End
Figure 9-24. DPWM Multi-Mode Close Loop
Event 2 and Event 4 are not relevant in Multi mode.
Copyright © 2021 Texas Instruments Incorporated
52
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
DPWMB can cross over the period boundary safely, and still have the proper pulse width, so full 100% pulse
width operation is possible. DPWMA cannot cross over the period boundary.
Since the rising edge on DPWM B is also fixed, Blanking B-Begin and Blanking B-End can be used for blanking
this rising edge.
And, of course, Cycle Adjust B is usable on DPWM B.
9.4.1.4 DPWM Resonant Mode
This mode provides a symmetrical waveform where DPWMA and DPWMB have the same pulse width. As the
switching frequency changes, the dead times between the pulses remain the same.
The equations for this mode are designed for a smooth transition from PWM mode to resonant mode, as
described in the Section 9.3.3.2. Here is a diagram of this mode:
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
53
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
Resonant Symmetrical Closed Loop
Start of Period Start of Period
Filter Period
Period Counter
Filter controlled edge
DPWM Output A
Event 1
Filter Duty – Average Dead Time
Adaptive Sample Trigger A
Adaptive Sample Trigger B
Sample Trigger 1
Blanking A Begin
To Other
Modules
Blanking A End
DPWM Output B
Event 3 - Event 2
Period Register – Event 4
Sample Trigger 2
Blanking B Begin
Blanking B End
Phase Trigger
To Other
Modules
Events which change with DPWM mode:
Dead Time 1 = Event 3 – Event 2
Dead Time 2 = Event 1 + Period Register – Event 4)
Average Dead Time = (Dead Time 1 + Dead Time 2)/2
DPWM A Rising Edge = Event 1
DPWM A Falling Edge = Event 1 + Filter Duty – Average Dead Time
Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive Sample Register
Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive Sample Register
DPWM B Rising Edge = Event 1 + Filter Duty – Average Dead Time + (Event 3 – Event 2)
DPWM B Falling Edge = Filter Period – (Period Register – Event 4)
Phase Trigger = Phase Trigger Register value or Filter Duty
Events always set by their registers, regardless of mode:
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B Begin,
Blanking B End
Figure 9-25. DPWM Resonant Symmetrical Mode
The Filter has two outputs, Filter Duty and Filter Period. In this case, the Filter is configured so that the Filter
Period is twice the Filter Duty. So if there were no dead times, each DPWM pin would be on for half of the
period. For dead time handling, the average of the two dead times is subtracted from the Filter Duty for both
DPWM pins. Therefore, both pins will have the same on-time, and the dead times will be fixed regardless of the
period. The only edge which is fixed relative to the start of the period is the rising edge of DPWM A. This is the
only edge for which the blanking signals can be used easily.
Copyright © 2021 Texas Instruments Incorporated
54
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
9.4.2 Triangular Mode
Triangular mode provides a stable phase shift in interleaved PFC and similar topologies. In this case, the PWM
pulse is centered in the middle of the period, rather than starting at one end or the other. In Triangular Mode,
only DPWM-B is available. Here is a diagram for Triangular Mode:
Triangular Mode Closed Loop
Start of Period
Period
Start of Period
Period Counter
DPWM Output A
Sample Trigger 1
Blanking A Begin
Blanking A End
To Other
Modules
Filter controlled edge
DPWM Output B
Cycle Adjust A (High Resolution)
Cycle Adjust B (High Resolution)
Filter Duty/2 (High Resolution)
Period/2
Sample Trigger 2
Blanking B Begin
Blanking B End
To Other
Phase Trigger
Modules
Events which change with DPWM mode:
DPWM A Rising Edge = None
DPWM A Falling Edge = None
Adaptive Sample Trigger = None
DPWM B Rising Edge = Period/2 - Filter Duty/2 + Cycle Adjust A
DPWM B Falling Edge = Period/2 + Filter Duty/2 + Cycle Adjust B
Phase Trigger = Phase Trigger Register value or Filter Duty
Events always set by their registers, regardless of mode:
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B
Begin, Blanking B End
Figure 9-26. Triangular Mode
All edges are dynamic in triangular mode, so fixed blanking is not that useful. The adaptive sample trigger is not
needed. It is very easy to put a fixed sample trigger exactly in the center of the FET on-time, because the center
of the on-time does not move in this mode.
9.4.3 Leading Edge Mode
Leading edge mode is similar to Normal mode, reversed in time. The DPWM A falling edge is fixed, and the
rising edge moves to the left, or backwards in time, as the filter output increases. The DPWM B falling edge
stays ahead of the DPWMA rising edge by a fixed dead time. Here is a diagram of the Leading Edge Mode:
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
55
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
Leading Edge Closed Loop
Start of Period
Period
Start of Period
Period Counter
DPWM Output A
Event 1
Filter Duty (High Resolution)
Cycle Adjust A (High Resolution)
Adaptive Sample Trigger A
Adaptive Sample Trigger B
Sample Trigger 1
Blanking A Begin
To Other
Modules
Blanking A End
DPWM Output B
Event 2 - Event 3 (High Resolution)
Event 4 (High Resolution)
Sample Trigger 2
Blanking B Begin
Blanking B End
Phase Trigger
To Other
Modules
Events which change with DPWM mode:
DPWM A Falling Edge = Event 1
DPWM A Rising Edge = Event 1 - Filter Duty + Cycle Adjust A
Adaptive Sample Trigger A = Event 1 - Filter Duty + Adaptive Sample Register or
Adaptive Sample Trigger B = Event 1 - Filter Duty/2 + Adaptive Sample Register
DPWM B Rising Edge = Event 4
DPWM B Falling Edge = Event 1 - Filter Duty + Cycle Adjust A -(Event 2 – Event 3)
Phase Trigger = Phase Trigger Register value or Filter Duty
Events always set by their registers, regardless of mode:
Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B
Begin, Blanking B End
Figure 9-27. Leading Edge Mode
As in the Normal mode, the two edges in the middle of the period are dynamic, so the fixed blanking intervals are
mainly useful for the edges at the beginning and end of the period.
Copyright © 2021 Texas Instruments Incorporated
56
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
9.5 Memory
9.5.1 Register Maps
9.5.1.1 CPU Memory Map and Interrupts
When the device comes out of power-on-reset, the data memories are mapped to the processor as follows:
9.5.1.1.1 Memory Map (After Reset Operation)
Address
Size (Bytes)
Module
0x0000_0000 – 0x0003_FFFF
In 32 repeated blocks of 8 k each
32 X 8 k
Boot ROM
0x0004_0000 – 0x0004_7FFF
0x0004_8000 – 0x0004_FFFF
0x0006_8800 – 0x0006_8FFF
0x0006_9000 – 0x0006_9FFF
32 k
32 k
2 k
Program Flash 1
Program Flash 2
Data Flash
4 k
Data RAM
9.5.1.1.2 Memory Map (Normal Operation)
Just before the boot ROM program gives control to flash program, the ROM configures the memory as follows:
Address
Size (Bytes)
Module
Program Flash 1 (or 2)
Program Flash 2 (or 1)
Boot ROM
0x0000_0000 – 0x0000_7FFF
0x0000_8000 – 0x0000_FFFF
0x0002_0000 – 0x0002_1FFF
0x0006_8800 – 0x0006_8FFF
0x0006_9000 – 0x0006_9FFF
32 k
32 k
8 k
2 k
Data Flash
4 k
Data RAM
9.5.1.1.3 Memory Map (System and Peripherals Blocks)
Address
Size
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
23
Module
0x0012_0000 - 0x0012_00FF
0x0013_0000 - 0x0013_00FF
0x0014_0000 - 0x0014_00FF
0x0015_0000 - 0x0015_00FF
0x0016_0000 - 0x0016_00FF
0x0017_0000 - 0x0017_00FF
0x0018_0000 - 0x0018_00FF
0x0019_0000 - 0x0019_00FF
0x001A_0000 - 0x001A_00FF
0x001B_0000 – 0x001B_00FF
0x001C_0000 - 0x001C_00FF
0x001D_0000 - 0x001D_00FF
0x001E_0000 - 0x001E_00FF
0xFFF7_EC00 - 0xFFF7_ECFF
0xFFF7_ED00 - 0xFFF7_EDFF
0xFFF7_F000 - 0xFFF7_F0FF
0xFFF7_F600 - 0xFFF7_F6FF
0xFFF7_FA00 - 0xFFF7_FAFF
0xFFF7_FD00 - 0xFFF7_FDFF
0xFFFF_FD00 - 0xFFFF_FDFF
0xFFFF_FE00 - 0xFFFF_FEFF
0xFFFF_FF20 - 0xFFFF_FF37
Loop Mux
Fault Mux
ADC
DPWM 3
Filter 2
DPWM 2
Front End/Ramp Interface 2
Filter 1
DPWM 1
Front End/Ramp Interface 1
Filter 0
DPWM 0
Front End/Ramp Interface 0
UART 0
UART 1
Miscellaneous Analog Control
PMBus Interface
GIO
Timer
MMC
DEC
CIM
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
57
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
Address
Size
16
Module
PSA
0xFFFF_FF40 - 0xFFFF_FF50
0xFFFF_FFD0 - 0xFFFF_FFEC
28
SYS
The registers and bit definitions inside the System and Peripheral blocks are detailed in the programmer’s guide
for each peripheral.
9.5.1.2 Boot ROM
The UCD3138064 incorporates a 8 kB boot ROM. This boot ROM includes support for:
•
•
•
•
•
•
Program download through the PMBus
Device initialization
Examining and modifying registers and memory
Verifying and executing program flash automatically
Jumping to a customer defined boot program
Checksum evaluation to facilitate program execution from either Program Flash 1 or Program Flash 2
The Boot ROM is entered automatically on device reset. It initializes the device and then performs checksums
on the program flash. If the first 2 kB of either program FLASH has a valid checksum, the program branches
to location 0 in the appropriate Program FLASH module. This permits the use of a custom boot program. If the
first checksum fails, it performs some additional checksum calculations to determine where the valid program
is located. This permits full automated program memory checking, when there is no need for a custom boot
program. The complete decision tree is located in Figure 9-28. "Branch to Program Flash 1" means Flash 1 is at
address 0x0000, and Flash 2 is at address 0x8000. "Branch to Program Flash 2" means Flash 2 is at address
0x0000, and Flash 1 is at address 0x8000.
Copyright © 2021 Texas Instruments Incorporated
58
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
Device Reset
Does Program Flash 1 have a
BRANCH instruction at the
beginning?
Yes
No
Is there a valid checksum on the
first 2 kB of Program Flash 1 or all
32 kB of Program Flash 1?
Does Program Flash 2 have a
BRANCH instruction at the
beginning?
Yes
No
Yes
No
Is there a valid checksum on the
first 2 kB of Program Flash 2 or all
32 kB of Program Flash 2?
Yes
No
BRANCH to
Program Flash 2
Is there a valid
checksum on all 64 kB?
Yes
No
BRANCH to
Program Flash 1
Stay in ROM
Figure 9-28. Check Sum Evaluation Flowchart
If neither checksum is valid, the Boot ROM stays in control, and accepts commands via the PMBus interface.
These functions can be used to read and write to all memory locations in the UCD3138064. Typically they are
used to download a program to Program Flash, and to command its execution.
9.5.1.3 Customer Boot Program
As described above, it is possible to generate a user boot program using 2 kB or more of the Program Flash.
This can support things which the Boot ROM does not support, including:
•
Program download via UART – useful especially for applications where the UCD3138064 is isolated from the
host (e.g., PFC)
•
•
Encrypted download – useful for code security in field updates.
PMBus download at different addresses
9.5.1.4 Flash Management
The UCD3138064 offers a variety of features providing for easy prototyping and easy flash programming. At the
same time, high levels of security are possible for production code, even with field updates. Standard firmware
will be provided for storing multiple copies of system parameters in data flash. This minimizes the risk of losing
information if data-flash programming is interrupted.
9.5.1.5 Synchronous Rectifier MOSFET Ramp and IDE Calculation
The UCD3138064 has built in logic for optimizing the performance of the synchronous rectifier MOSFETs. This
comes in two forms:
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
59
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
•
•
Synchronous Rectifier MOSFET ramp
Ideal Diode Emulation (IDE) calculation
When starting up a power supply, It is not uncommon for there to already be a voltage present on the output
– this is called pre-bias. It can be very difficult to calculate the ideal synchronous rectifier MOSFET on-time for
this case. If it is not calculated correctly, it may pull down the pre-bias voltage, causing the power supply to sink
current. To avoid this, the synchronous rectifier MOSFETs are not turned on until after the power supply has
ramped up to the nominal output voltage. The synchronous rectifier MOSFETs are then turned on slowly in order
to avoid an output voltage glitch. The synchronous rectifier MOSFET ramp logic can be used to turn them on at a
rate well below the bandwidth of the filter.
In discontinuous mode, the ideal on-time for the synchronous rectifier MOSFETs is a function of Vin, Vout, and
the primary side duty cycle (D). The IDE logic in the UCD3138064 takes Vin and Vout data from the firmware and
combines it with D data from the filter hardware. It uses this information to calculate the ideal on-time for the
synchronous rectifier MOSFETs.
Copyright © 2021 Texas Instruments Incorporated
60
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
10 Applications and Implementation
10.1 Application Information
The UCD3138x has an extensive set of fully-programmable, high-performance peripherals that make it suitable
for a wide range of power supply applications. In order to make the part easier to use, TI has prepared an
extensive set of materials to demonstrate the features of the device for several key applications. In each case
the following items are available:
1. Full featured EVM hardware that demonstrates classic power supply functionality.
2. An EVM user guide that contains schematics, bill-of-materials, layout guidance and test data showcasing the
performance and features of the device and the hardware.
Table 10-1. Application Information
APPLICATION
EVM DESCRIPTION
This EVM demonstrates a PSFB DC-DC power converter with digital control using the UCD3138x device. Control is
implemented by using PCMC with slope compensation. This simplifies the hardware design by eliminating the need
for a series blocking capacitors and providing the inherent input voltage feed-forward that comes from PCMC. The
controller is located on a daughter card and requires firmware in order to operate. This firmware, along with the entire
source code, is made available through TI. A free, custom function GUI is available to help the user experiment with
the different hardware and software enabled features. The EVM accepts a DC input from 350 VDC to 400 VDC, and
outputs a nominal 12 VDC with full load output power of 360 W, or full output current of 30 A.
Phase shifted full
bridge
This EVM demonstrates an LLC resonant half-bridge DC-DC power converter with digital control using the
UCD3138x device. The controller is located on a daughter card and requires firmware in order to operate. This
firmware, along with the entire source code, is made available through TI. A free, custom function GUI is available
to help the user experiment with the different hardware and software enabled features. The EVM accepts a DC input
from 350 VDC to 400 VDC, and outputs a nominal 12 VDC with full load output power of 340 W, or full output current
of 29 A.
LLC resonant
converter
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
61
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
10.2 Typical Application
This section summarizes the PSFB EVM DC-DC power converter.
L1
T1
Q7
+12V
Q6
Q5
C1
RL
VBUS
I_pri
PRIM
ORING
CTL
CURRENT
T2
VOUT
C2
R2
D1
T1
QT2
QB2
QT1
VA
Lr
Current
Sensing
QB1
D2
Vref
DPWM0
DPWM0B
DPWM1B
Duty for mode
switching
Vout
CPCC
<
EADC0
EADC1
CLA0
DPWM1
DPWM2
Iout
CLA1
DPWM2A
DPWM2B
Load Current
DPWM3A
DPWM3B
I_pri
EADC2
PCM
DPWM3
AD00
AD01
ISOLATED
GATE Transformer
ACFAIL_IN
FAULT0
FAULT1
FAULT2
SYNCHRONOUS
GATE DRIVE
ACFAIL_OUT
FAILURE
AD02/CMP0
AD03/CMP1/CMP2
AD04/CMP3
AD05/CMP4
AD06/CMP5
AD07/CMP6
AD08
I_SHARE
Vout
FAULT
UCD3138
GPIO1
GPIO2
GPIO3
ORING_CRTL
ON/OFF
Iout
I_pri
CBC
temp
P_GOOD
Vin
VA
WD
ARM7
AD09
PMBus
UART0
RST
OSC
Primary
UART1
Memory
Figure 10-1. Phase-Shifted Full-Bridge
Copyright © 2021 Texas Instruments Incorporated
62
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
10.2.1 Design Requirements
Table 10-2. Input Characteristics
PARAMETER
CONDITIONS
MIN
TYP MAX UNIT
ALL SPECIFICATIONS at Vin=400V and 25°C AMBIENT UNLESS OTHERWISE NOTED.
Vin
Input voltage range
Normal Operating
350
385
420
420
V
V
Vinmax Max input voltage
Continuous
Iin
Input current
Vin=350V, Full Load
1.15
30
A
Istby
Von
Vhys
Input no load current
Output current is 0A
mA
V
Vin Decreasing (input voltage is detected on secondary side)
Vin Increasing
340
360
Under voltage lockout
V
Table 10-3. Output Characteristics
PARAMETER
CONDITIONS
MIN
TYP
MAX UNIT
ALL SPECIFICATIONS at Vin=400V and 25°C AMBIENT UNLESS OTHERWISE NOTED.
VO
Output voltage setpoint
Line regulation
No load on outputs
12
V
Regline
All outputs; 360 ≤ Vin ≤ 420; IO = IOmax
All outputs; 0 ≤ IO ≤ IOmax; Vin = 400 V
5Hz to 20 MHz
0.5
1
%
%
Regload Load regulation
Vn
IO
η
Ripple and noise(1)
100
mVpp
A
Output current
0
30
Efficiency at phase-shift mode
Efficiency at PWM ZVS mode
Efficiency at hard switching mode
Output adjust range
Vo = 12 V, Io = 15 A
Vo = 12 V, Io = 15 A
Vo = 12 V, Io = 15 A
93%
93%
90%
η
η
Vadj
11.4
12.6
V
V
Transient response overshoot/
undershoot
Vtr
50% Load Step at 1AµS, min load at 2A
±0.36
tsettling
tstart
Transient response settling time
Output rise time
100
50
µS
mS
%
10% to 90% of Vout
At Startup
Overshoot
2
fs
Switching frequency
Current sharing accuracy
Loop phase margin
Loop gain margin
Over Vin and IO ranges
50% - full load
150
±5
kHz
%
Ishare
φ
10% - Full load
10% - Full load
45
degree
dB
G
10
(1) Ripple and noise are measured with 10µF Tantalum capacitor and 0.1µF ceramic capacitor across output.
10.2.2 Detailed Design Procedure
10.2.2.1 PCMC (Peak Current Mode Control) PSFB (Phase Shifted Full Bridge) Hardware Configuration
Overview
The hardware configuration of the UCD3138x PCMC PSFB converter contains two critical elements that are
highlighted in the subsequent sections.
•
DPWM initialization - This section will highlight the key register settings and considerations necessary for
the UCD3138x to generate the correct MOSFET waveforms for this topology. This maintains the proper
phase relationship between the MOSFETs and synchronous rectifiers as well as the proper set up required to
function correctly with PCMC.
•
PCMC initialization - This section will discuss the register settings and hardware considerations necessary to
modulate the DPWM pins with PCMC and internal slope compensation.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
63
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
10.2.2.2 DPWM Initialization for PSFB
The UCD3138x DPWM peripheral provides flexibility for a wide range of topologies. The PSFB configuration
utilizes the Intra-Mux and Edge Generation Modules of the DPWM. For a diagram showing these modules, see
the UCD3138x Digital Power Peripherals Manual.
Here is a schematic of the power stage of the PSFB:
L1
T1
VOUT
Q6
VBUS
I_pri
PRIM
CURRENT
Q5
T2
R2
D1
D2
QT2
QB2
QT1
QB1
Lr
T1
ISOLATED
GATE Transformer
SYNCHRONOUS
GATE DRIVE
Figure 10-2. Schematic – PSFB Power Stage
Copyright © 2021 Texas Instruments Incorporated
64
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
Here is an overview of the key PSFB signals:
3 A – QB1
( DPWM1C)
3 B – QT1
( DPWM2C)
2 A – QT2
( EDGEGEN)
X1
Y3
2 B – QB2
( EDGEGEN)
X3
Y2
Transformer
Voltage
X2
1 B –
QSYN 1,3
Y1
0 B –
QSYN 2,4
DPWM3AF
DPWM3BF
DPWM 2AF
DPWM 2BF
Current
Peak Level
X1, X2 ,X3 and Y1 , Y2 , Y3 are sets of moving edges
All other edges are fixed .
Figure 10-3. Key PSFB Signals
10.2.2.2.1 DPWM Synchronization
DPWM1 is synchronized to DPWM0, DPWM2 is synchronized to DPWM1, and DPWM3 is synchronized to
DPWM2, ½ period out of phase using these commands:
Dpwm1Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; //configured to slave
Dpwm2Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; // configured to slave
Dpwm3Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; // configured to slave
Dpwm0Regs.DPWMPHASETRIG.all = PWM_SLAVESYNC;
Dpwm1Regs.DPWMPHASETRIG.all = PWM_SLAVESYNC;
Dpwm2Regs.DPWMPHASETRIG.all = PWM_SLAVESYNC;
LoopMuxRegs.DPWMMUX.bit.DPWM1_SYNC_SEL = 0;
LoopMuxRegs.DPWMMUX.bit.DPWM2_SYNC_SEL = 1;
LoopMuxRegs.DPWMMUX.bit.DPWM3_SYNC_SEL = 2;
// Slave to dpwm-0
// Slave to dpwm-1
// Slave to dpwm-2
If the event registers on the DPWMs are the same, the two pairs of signals will be symmetrical. All code
examples are taken from the PSFB EVM code, unless otherwise stated.
10.2.2.3 Fixed Signals to Bridge
The two top signals in the above drawing have fixed timing. The DPWM1CF and DPWM2CF signals are used for
these pins. DPWMCxF refers to the signal coming out of the fault module of DPWMx, as shown in Figure 10-4.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
65
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
Figure 10-4. Fixed Signals to Bridge
These signals are actually routed to pins DPWM3A and 3B using the Intra Mux with these statements:
Dpwm3Regs.DPWMCTRL0.bit.PWM_A_INTRA_MUX = 7; // Send DPWM1C
Dpwm3Regs.DPWMCTRL0.bit.PWM_B_INTRA_MUX = 8; // Send DPWM2C
Since these signals are really being used as events in the timer, the #defines are called EV5 and EV6. Here are
the statements which initialize them:
Copyright © 2021 Texas Instruments Incorporated
66
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
// Setup waveform for DPWM-C (re-using blanking B regs)
Dpwm2Regs.DPWMBLKBBEG.all = PWM2_EV5 + (4 *16);
Dpwm2Regs.DPWMBLKBEND.all = PWM2_EV6;
Period End
Controlled by DPWM1 Blanking register
Period Start
Blank B Begin
Blank B End
3 A – QB1
Even 6
Even 5
( DPWM1C)
3 B – QT1
Even 6
Even 6
Even 5
( DPWM 2C)
Blank B Begin
Blank B End
Controlled by DPWM2 Blanking register
Figure 10-5. Blank B Timing Information
The statements for DPWM1 are the same. Remember that DPWMC reuses the Blank B registers for timing
information.
10.2.2.4 Dynamic Signals to Bridge
DPWM0 and 1 are set at normal mode. PCMC triggering signal (fault) chops DPWM0A and 1A cycle by cycle.
The corresponding DPWM0B and 1B are used for synchronous rectifier MOSFET control. The same PCMC
triggering signal is applied to DPWM2 and DPWM3. Both of these are set to normal mode as well. DPWM2
and 3 are chopped and their edges are used to generate the next two dynamic signals to the bridge. They
are generated using the Edge Generator Module in DPWM2. The Edge Generator sources are DPWM2 and
DPWM3. The edges used are:
DPWM2A turned on by a rising edge on DPWM2BF
DPWM2A turned off by a falling edge on DPWM3AF
DPWM2B turned on by a rising edge on DPWM3BF
DPWM2B turned off by a falling edge on DPWM2AF
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
67
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
Period Start
Period End
3 A – QB1
( DPWM 1C)
3 B – QT1
( DPWM 2C)
2 A – QT2
( EDGEGEN )
2 B – QB2
( EDGEGEN )
Y3
X3
1A
1 B –
QSYN 1,3
X2
Y2
Y1
0A
0 B –
QSYN 2,4
X1
DPWM 3AF
DPWM 3BF
DPWM 2AF
DPWM 2BF
Current
Peak Level
Chopping point
Chopping point
X1 , X2 , X3 and Y1 , Y2 , Y3 are sets of moving edges
All other edges are fixed .
Figure 10-6. Dynamic Signals to Bridge
The Edge Generator is configured with these statements:
Dpwm2Regs.DPWMEDGEGEN.bit.A_ON_EDGE = 2;
Dpwm2Regs.DPWMEDGEGEN.bit.A_OFF_EDGE = 5;
Dpwm2Regs.DPWMEDGEGEN.bit.B_ON_EDGE = 6;
Dpwm2Regs.DPWMEDGEGEN.bit.B_OFF_EDGE = 1;
Dpwm2Regs.DPWMCTRL0.bit.PWM_A_INTRA_MUX = 1; // EDGEGEN-A out the A output
Dpwm2Regs.DPWMCTRL0.bit.PWM_B_INTRA_MUX = 1; // EDGEGEN-B out the B output
Dpwm2Regs.DPWMEDGEGEN.bit.EDGE_EN = 1;
The EDGE_EN bits are set for all 4 DPWMs. This is done to ensure that all signals have the same timing delay
through the DPWM.
The finial 6 gate signals are shown in Figure 10-7.
Copyright © 2021 Texas Instruments Incorporated
68
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
Period Start
Period End
3 A – QB1
( DPWM 1C)
3 B – QT1
( DPWM 2C)
2 A – QT2
( EDGEGEN )
2 B – QB2
( EDGEGEN )
Y3
X3
1 B –
QSYN 1,3
Y2
Y1
X2
X1
0 B –
QSYN 2,4
Peak Level
Current
Chopping point
Chopping point
Figure 10-7. Final 6 Gate Signals
Note how the falling edge of DPWM2AF aligns with the X1 edge, and how the rising edge of DPWM2BF aligns
with the X3 edge. The falling edges on DPWM2AF and DPWM3AF are caused by the peak detection logic. This
is fed through the Cycle By Cycle logic. The Cycle By Cycle logic also has a special feature to control the rising
edges of DPWM2BF (X1 and X3) and DPWM3BF (Y1 and Y3). It uses the value of Event3 – Event2 to control
the time between the edges. The same feature is used with DPWM0 and DPWM1 to control the X2 and Y2
signals. Using the other 2 DPWMs permits these signals to have a different dead time.
The same setup can be used for voltage mode control. In this case, the Filter output sets the timing of the falling
edge on DPWMxAF.
All DPWMs are configured in Normal mode, with CBC enabled. If external slope compensation is used,
DPWM1A and DPWM1B are used to reset the external compensator at the beginning of each half cycle. If
no PCMC event occurs, the values of Events 2 and 3 determine the locations of the edges, just as in open loop
mode.
10.2.2.5 System Initialization for PCM
PCM (Peak Current Mode) is a specialized configuration for the UCD3138x which involves several peripherals.
This section describes how it works across the peripherals.
10.2.2.5.1 Use of Front Ends and Filters in PSFB
All three front ends are used in PSFB. The same signals are used in the same places for both PCMC and
voltage mode. The same hardware can be used for both control modes, with the mode determined by which
firmware is loaded into the device. FE0 and FE1 are used with their associated filters, but Filter 2 is not used at
all.
FE0 – Vout – voltage loop
FE1 – Iout – current loop
FE2 – Ipri – PCM
In PCMC mode, FE2 is used for PCMC, and the voltage loop is normally used to provide the start point for the
compensation ramp. If the CPCC firmware detects a need for constant current mode, it switches to the current
loop for the start point.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
69
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
10.2.2.5.2 Peak Current Detection
Peak current detection involves all the major modules of the DPPs, the Front End, Filter, Loop Mux, Fault Mux
and the DPWMs. A drawing of the major elements is shown in Figure 10-8.
Ipri
PCM
Comparator
Loop
Mux
Fault
Mux
DPWM
Voltage Loop
Filter
Loop
Mux
Ramp
Module
Loop
Mux
Vout
Front
End
Figure 10-8. Peak Current Detection Function
All signals without arrows flow from left to right. The voltage loop is used to select a peak current level. This
level is fed to the Ramp module to generate a compensation ramp. The compensation ramp is compared to the
primary current by the PCMC comparator in the Front End. When the ramp value is greater than the primary
current, the APCMC signal is sent to the DPWM, causing the events described in the previous sections.
The DPWM frame start and output pin signals can be used to trigger the Ramp Module. In this case, unlike in the
case of other ramp module functions, each DPWM frame triggers the start of the ramp. The ramp steps every 32
ns.
The Filter is configured normally, there is no real difference for PCMC. The PCM_FILTER_SEL bits in the
LoopMux.PCMCTRL register are used to select which filter is connected to the ramp module:
LoopMuxRegs.PCMCTRL.bit.PCM_FILTER_SEL =0; //select filter0
With Firmware Constant Power/Constant current, Filter 1 and Front End 1 are used as a current control loop,
with the EADCDAC set to high current. If the voltage loop value becomes higher than the current loop value,
then Filter 1 is used to control the PCM ramp start value:
LoopMuxRegs.PCMCTRL.bit.PCM_FILTER_SEL =1;
S P A C E //select filter1 for slope compensation source
In the ramp module, there are 2 bitfields in the RAMPCTRL register which must be configured. The
PCM_START_SEL must be set to a 1 to enable the Filter to be used as a ramp start source. The RAMP_EN bit
must be set, of course.
The DAC_STEP register sets the slope of the compensation ramp. The DAC value is in volts, of course, so it is
necessary to calculate the slope after the current to voltage conversion. Here is the formula for converting from
millivolts per microsecond to DACSTEP.
m = compensation slope in millivolts per microsecond
ACSTEP = 335.5 × M
In C, this can be written:
#define COMPENSATION_SLOPE 150 //compensation slope in millivolts per microsecond
#define DACSTEP_COMP_VALUE ((int) (COMPENSATION_SLOPE*335.5) )
S P A C E //value in DACSTEP for desired compensation slope
S P A C E FeCtrl0Regs.DACSTEP.all = DACSTEP_COMP_VALUE;
It may also be necessary to set a ramp ending value in the RAMPDACEND register.
Copyright © 2021 Texas Instruments Incorporated
70
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
In addition, it is necessary to set the D2S_COMP_EN bit in the EADCCTRL register. This is for enabling the
differential to single ended comparator function. The front end diagram leaves it out for simplicity, but the
connection between the DAC and the EADC amplifier is actually differential. The PCMC comparator, however, is
single ended. So a conversion is necessary as shown in Figure 10-9.
AFE_GAIN
23-AFE_GAIN
6 bit ADC
8mV/LSB
EAP0
2AFE_GAIN
EAN0
Signed 9 bit result
(error) 1 mV /LSB
EADC
X
Averaging
SAR/Prebias
Ramp
Filter x
CPCC
DAC0
10 bit DAC
1.5625mV/LSB
Σ
Value
Differential to
Single Ended
Dither
4 bit dithering gives 14 bits of effective resolution
97.65625μV/LSB effective resolution
Absolute Value
Calculation
10 bit result
1.5625mV/LSB
Peak Current
Detected
Peak Current Mode
Comparator
Figure 10-9. Differential to Single-Ended Comparator Function
The EADC_MODE bit in EADCCTRL should be set to a 5 for peak current mode.
The peak current detection signal next goes to the Loop Mux. The Fault Mux has only 1 APCM input, but there
are 3 front ends. So the PCM_FE_SEL bits in APCMCTRL must be used to select which front end is used:
LoopMuxRegs.APCMCTRL.bit.PCM_FE_SEL = 2; // use FE2 for PCM */
The PCM_EN bit must also be set.
LoopMuxRegs.APCMCTRL.bit.PCM_EN = 1; // Enable PCM
Next the Fault Mux is used to enable the APCM bit to the CLIM/CBC signal to the DPWM. There are 4
DPWMxCLIM registers, one for each DPWM. The ANALOG_PCM_EN bit must be set in each one to connect
the PCM detection signal to the CLIM/CBC signal on each DPWM. For the latest configuration information on all
of these bits, consult the appropriate EVM firmware. To avoid errors, it is best to configure your hardware design
using the same DPWMs, filters, and front ends for the same functions as the EVM.
DPWM timing is used to trigger the start of the ramp. This is selected by the FECTRLxMUX registers in the
Loop Mux. DPWMx_FRAME_SYNC_EN bits, when set, cause the ramp to be triggered at the start of the DPWM
period.
10.2.2.5.3 Peak Current Mode (PCM)
There is one peak current mode control module in the device however any front end can be configured to use
this module.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
71
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
10.2.3 Application Curves
30A Load
syncFETs off
1A-16A-1A
Vin =385V
Figure 10-11. VOUT Soft Start
Figure 10-10. Load Transient
Kp =14000 Ki =300
Kd =2000
Alpha = –2
Figure 10-12. Bode Plot
Copyright © 2021 Texas Instruments Incorporated
72
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
11 Power Supply Recommendations
For additonal power supply and layout recommendations, see the UCD3138 Family - Practical Design Guideline
SLUA779
11.1 Introduction To Power Supply and Layout Recommendations
This is an introduction for the sections on Power Supply and Layout.
There are multiple grounds and bias power pins for digital controllers such as the UCD3138 family products.
They are separated from each other because of the digital circuitry and analog circuitry inside the device.
Normally, digital circuits draw more current and generate more noise, but the digital signal is not sensitive to the
noise; while the analog circuit needs quiet power and grounding. A deliberate grounding and power separation
outside the controller can reduce the interference between analog circuits and digital circuits, and therefore, the
controller can have better performance. When they are separated from each other, take care of how the analog
circuit and digital circuit are grouped, respectively, and then how and where they are tied together. With improper
grounding, the device performance can be negatively impacted including DPWM abnormal, device reset, ADC
results, output voltage ripple, and so on.
These sections supersede all older guidelines on UCD family board design and layout. Older EVM designs may
not meet all of these guidelines.
In the PCB design, there are two options. One is to have two separate grounds - digital ground and analog
ground. The other is to use a single ground plane for both digital ground and analog ground. With two separate
ground planes, how to connect digital ground and analog ground is very important, and the PCB must be
designed very carefully. With a single ground plane, there is no concern regarding where two grounds are tied
together, and it makes the PCB design easier. Here, TI recommends using a single ground plane.
In these sections, digital ground is denoted as DGND; analog ground is denoted as AGND; a single ground
plane is denoted as SGND.
11.2 3.3-V Supply Pins
+3.3 V bias normally is produced by a LDO or Buck converter. +5 V (or +12 V) normally are generated by
a flyback converter and it is referenced to the Power Return. A 10 µF capacitor is locally used for LDO or
buck between +3.3 V and Power RTN node. From there, use a single plane (SGND) for both digital ground
and analog ground. A 1Ω resistor is needed between V33D and V33A. V33D and V33DIO should be shorted
externally if they are available and have a wider trace or preferably through its own power plane to connect
them. As an example, a 4.7-µF decoupling capacitor is used for V33A and V33D respectively and these
decoupling capacitors should be placed close to the device pins. In addition, a 10nF capacitor is used for
V33A, V33D and V33DIO respectively to filter out the high frequency noise and placed as close to the pin as
possible, for example the distance is less than 25mils from the capacitor to the pin V33D (or V33DIO) and from
the capacitor to the pin DGND. 10 nF uses smaller package such as 0402 and low ESR capacitor. Refer to
section Schematics and Layouts. There should not be any voltage delta between the DGND pins and AGND
pins. Multiple vias are required to connect the extended power pad (for example, copper plane under the device
power pad) to the internal single ground (SGND) plane layer. All digital and analog ground pins are directly
connected to the extended power pad and connected to the internal SGND plane through vias.
11.3 Recommendation for V33 Ramp up Slew Rate for UCD3138 and UCD3138064
UCD3138 and UCD3138064 need a 2.2-µF pullup capacitor from BP18 to V33 as described before. Capacitors
with a value of 2.2 µF and 1 µF create a capacitor divider which pull BP18 up as V33 rises. Ensure that as V33
rises, the slew rate is not fast enough to cause BP18 to overshoot, resulting in a reliability issue. TI requires that
the maximum voltage of BP18 does not exceed 1.95 V. By calculation, if V33 ramps up linearly, the maximum
V33 slew rate should be less than 6 V/ms.
Also, the internal BP18 regulator is enabled when V33 is higher than VGH and POR is activated. V33 charges the
capacitor of BP18 through the internal regulator. This charge causes a voltage dip in the V33 pin as shown in
V33 Voltage Dip When POR is Activated, and the charge may trigger a V33 undervoltage (POR) event, causing
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
73
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
a chip reset. To prevent POR trigger signal oscillation and successive chip resets, TI recommends a minimum
slew rate of 2.6 V/ms.
V33 (Volts)
3.6
3.3
3.0 (Vtarget
)
V3P3
VDROOP
VGH
POR (internal)
t
tPOR
Figure 11-1. V33 Voltage Dip When POR is Activated
From the V33 Voltage Dip When POR is Activated recommendations, the slew rate using the 2.2 uF/1uF
capacitor combination requires that the slew rate must be as follows:
6V /ms í SR í 2.6V /ms
(1)
11.4 Recommendation for RC Time Constant of RESET Pin for UCD3138 and UCD3138064
Ideally, the ARM core should begin execution of ROM code only after V33>3V. The ROM code reads trim
values and loads trim registers. Lack of sufficient voltage during this operation can result in unexpected device
functioning. Depending on V33 slew rate, the duration for which there is insufficient voltage on V33 is varied.
During this time, a reliable trim operation is not ensured. Applying an RC filter between V33 and the RESET pin
can increase the delay from V33 power up to the device coming out of reset.
Copyright © 2021 Texas Instruments Incorporated
74
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
Figure 11-2. Recommended Timing Diagram of V33 and RESET for UCD3138 and UCD3138064
Example Solution:
If the V33 supply slew rate is 0.6 V/ms, then the minimum τ required is calculated as follows:
Vtarget - VIL
tRESET
=
SR
(2)
(3)
3V - 1.1 V
0.6V /ms
tRESET _min
=
ö 3.16 ms
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
75
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
If R and C are 2.21 k and 2.2 uF, then τ evaluates as:
t = R ì C ö 2.21kW ì 2.2 mF = 4.862 ms
(4)
These values of 2.21 kΩ and 2.2 µF will ensure that the RESET will be a logic-0 until V33 crosses 3V. [τ >
τRESET_MIN]
Copyright © 2021 Texas Instruments Incorporated
76
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
12 Layout
12.1 Layout Guidelines
12.1.1 EMI and EMC Mitigation Guidelines
Every design is different in terms of EMI and EMC mitigation, and all designs require their own solution.
•
•
•
Apply multiple different capacitors for different frequency range on decoupling circuits. Each capacitor has
different ESL, capacitance and ESR, and different frequency responses.
Avoid long traces close to radiation sources, and place them into an internal layer. It is preferred to have
ground shielding and add a termination circuit at the end of the trace.
TI recommends single ground: SGND. A multilayer such as 4 layers board is recommended so that one solid
SGND is dedicated for return current path.
– Use one whole layer (L2) for SGND plane as shown in Figure 12-1. Use many vias (such as 9 vias) to
connect the extended power pad to the internal SGND plane layer. It is preferred to have the vias close to
AGND pins and DGND pins of the device.
Figure 12-1. Optional Ground Layer Assignment
•
•
•
Add LPF on analog signals close to the header connecting the control card and the power board.
Do not use a ferrite bead to connect V33A and V33D instead of using 1-Ω resistor.
Avoid negative current and negative voltage on all pins. Schottky diodes may be needed to clamp the
voltage; avoid the voltage spike on all pins to exceed 3.8 V or below –0.3 V; add Schottky diodes on the pins
which could have voltage spikes during surge test; be aware that Schottky diode has relatively higher leakage
current, which can affect the voltage sensing at high temperatures. The need for external Schottky diodes is
conditional. For example, the DPWM pins only need external Schottky diodes when there is a long distance,
for example, more than 3 inches, between the control card and main power stage because in this case, the
trace can pick up noise and cause electrical overstress on the device pins. The same is true for GPIO and
PMBus pins.
•
The auxiliary supply is normally a flyback converter, and its power transformer can generate a large
electromagnetic field which can interfere with other electronic circuitry. By shielding the primary side windings,
the EMI can be effectively reduced so that the surrounding circuits can have a quieter working environment.
12.1.2 BP18 Pin
Two parallel capacitors, 1µF and 10nF, are used between BP18 and SGND. The 10nF is placed closer to the
pin than 1uF. Please note that only for the UCD3138 (40-pin and 64-pin) and UCD3138064 (40-pin and 64-pin)
devices, it is required to have a 2.2-µF decoupling capacitor between V33D to BP18. The 2.2-µF capacitor is
required to ramp BP18 when V33D is ramping up. Place the capacitors close to the device pins, and keep the
return loop as small as possible.
12.1.3 Additional Bias Guidelines
•
Apply multiple different capacitors for different frequency range on decoupling circuits. Each capacitor has
different ESL, capacitance, ESR and different frequency response.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
77
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
•
•
•
Avoid long traces close to radiation components and place them into an internal layer. It is preferred to have
grounding shield and add a termination circuit at the end of long traces.
Do NOT use a ferrite bead or a resistor with a value of 3-Ω or larger resistor to connect between V33A and
V33D.
Avoid negative current/negative voltage (–0.3 V) on all pins. Avoid voltage spikes of more than 3.8V on all
pins. Schottky diodes may be required to clamp the voltage on any pins that could have voltage spikes during
surge tests. Note that Schottky diodes have relatively higher leakage current, which can affect the voltage
sensing at high temperature.
•
If the bias supply to the device is a switching supply, ripple should be minimized. The higher the peak-to-peak
magnitude and frequency of the ripple, the more the oscillator frequency changes.
UCD3138 Pin Connection Recommendation
The UCD3138 device is a highly integrated controller with a large number of mixed signals. It is important to
group each pin, select good components, have appropriate connections to each pin, and make good component
placement on the PCB to reduce noise coupling and to prevent chip mal-function. First, group all digital circuitry
and analog circuitry. Second, place digital circuitry close to each other, place analog circuitry close to each other,
and then make connections among them by a solid plane(SGND). To achieve a robust design, TI recommends
at least a 4-layer board.
Next, layout considerations and examples are provided for some critical pins or signals.
12.1.4.1 Current Amplifier With EADC Connection
As shown in Current Amplifier Connected With EADC, if a current amplifier is used for current sensing, a
differential input is recommended to suppress common mode noise. Then it is followed by a local low-pass filter
(LPF), LPF should be placed close to the EAP and EAN pins of the UCD device. Both filters must be connected
to the same ground plane (SGND).
Figure 12-2. Current Amplifier Connected With EADC
12.1.4.2 DPWM Synchronization
For half bridge or full-bridge converter, where more than one DPWM modules are used to drive multiple pairs of
MOSFETs, synchronization between DPWM modules is required. The synchronization can be achieved by using
Master-Slave mode. A slaved DPWM can be synchronized with other Master DPWM or Slave DPWM. Without
synchronization, the DPWM could go out of synchronization at large currents which can cause catastrophic
damage.
Please note: For UCD3138ARMH and UCD3138ARJA, if the system use case is below -30C, DPWM fixed edge
alignment should be avoided and at least a 4ns gap should be configured.
Copyright © 2021 Texas Instruments Incorporated
78
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
12.1.4.3 External Clock
On the UCD3138128A device, if the XTAL_IN (Pin 61) and XTAL_OUT (Pin 62) are not used for an external
crystal, tie each one to 1.8V (Pin BP18) through a separate 1kohm resistor.
12.1.4.4 GPIOS
GPIO is referenced to DGND internally. When GPIO pins are not used connect the pins to SGND. Alternatively,
they can be configured as output pins and set as low in the firmware. When GPIOs are used to drive other circuit
like LED, be aware that traces can pick up noise. A local resistor close to the signal receiver (like LED) is used to
terminate the coupled noise. If the big voltage swings, clamping diodes are needed for GPIO inputs, as shown in
Clamping Diodes for GPIO.
Figure 12-3. Clamping Diodes for GPIO
12.1.4.5 DPWM PINS
If DPWMs travel for a longer distance than 3 inches from the control card to a main power stage, a Schottky
clamping diode may be needed as shown in Clamping Diodes for DPWM to prevent electrical overstress on
the device during lightning test. The long trace may also pick up the noise from other switching sources. Avoid
DPWM signals to cross switching nodes.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
79
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
Figure 12-4. Clamping Diodes for DPWM
12.1.4.6 EAP and EAN Pins
There are three front-end ADCs to sense the feedback signals in the UCD family. These ADCs are dual-ended
sensing input circuitry with good common mode noise rejection. Keep the distance between the two traces as
short as possible when the differential sensing method is used. A local filter close to the EAP and EAN pins is
required as shown in Local Filter on EAPx and EANx Pins. Because EAP and EAN are used for feedback loop,
C must be selected from the range of 100 pF to 1000 pF. R is preferred to use low resistance.
Figure 12-5. Local Filter on EAPx and EANx Pins
12.1.4.7 ADC Pins
Use low ESL and ESR ceramic capacitors on ADC pins to decouple with SGND. The capacitor value is selected
such that the cut-off frequency is at least one tenth the sampling frequency if there is no dynamic requirement.
This can help reduce noise coupled during signal transmission.
ADC input is a single-ended signal. If the sensing trace is long, move it away from radiation sources and add
ground shielding between the signal and radiation sources. If there exists a resistor between signal output and
ADC input, the resistor should be located close to the ADC pin. The resistance needs to be less than 1 kΩ.
For example, the sampling frequency is 10 kHz. The cut off frequency of LPF is 1 kHz. With a 1-kΩ equivalent
resistor, select a 0.15-μF capacitor.
Copyright © 2021 Texas Instruments Incorporated
80
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
12.1.4.7.1 RESET Pin
The RESET pin must have one at least 2.2 µF low ESL capacitor locally decoupled with SGND plane. As
shown in RESET Pin Connection, this capacitor must be placed very close to the device RESET pin. TI highly
recommends using a small resistance (such as 2.2 kΩ) to connect the RESET pin (pin 11 for UCD3138RGC)
with V33DIO (pin 9 for UCD3138RGC). The resistor must be placed close to the RESET pin, as well. The
grounding point of the capacitor must be tied to SGND plane locally by a ground via, which is generally larger
than a signal via.
Figure 12-6. RESET Pin Connection
12.1.4 UART Communication Port
UART is used for communicating between the primary side and secondary side with isolation boundary.
Normally, the communication wires are long. These wires can easily be interfered by EMI and pick up noise
of switching power supplies. First, the wires must be routed without directly exposing the traces to the
switching noise source, and then a termination is needed at the end of the trace, as shown in Termination
for Communication Port (UART). For example, R = 50 Ω, C = 47 pF if they don’t significantly slow down the slew
rate of the signals. When the pins are not used, tie them to the single ground plane SGND.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
81
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
Figure 12-7. Termination for Communication Port (UART)
Special Considerations
•
The first thing that must be done in any layout is to set up the basic grounding strategy and the placement
of the decoupling capacitors. This needs to be prioritized over anything else, even the routing of sensitive
feedback signals.
•
If a gate driver device such as UCC27524 or UCC27511 is on the control card and there is a PGND
connection, a net-short resistor or large copper trace must be used to tie the PGND to the Power RTN by
multiple vias. Also, the net-short element between Power RTN and PGND must be close to the driver IC.
Unused ADC pins must be tied to SGND.
Avoid putting V33D and V33A long traces or planes close to radiation components. Place them into an
internal layer. It is preferred to have ground shielding.
•
•
•
Avoid putting bias supplies or SGND or Power RTN directly to across the switching power train where they
can couple switching noise. If the grounds are coupled with noise, the decoupling capacitors may not be
effective at filtering the noise out.
•
•
Local capacitors are preferred to provide a short path for switching current, and be careful to select a quiet
RETURN point to connect.
In a power module or a tiny PCB design, a single solid plane without the grounding separation is shown in
Single Ground Plane for a Power Module Design and has a single point connection with power RTN or SGND
near the connector. Ensure there is no current flow from power train into the signal ground plane.
Figure 12-8. Single Ground Plane for a Power Module Design
12.2 Layout Example
Figure 12-9.
Copyright © 2021 Texas Instruments Incorporated
82
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
12.2.1 UCD3138 and UCD3138064 40 Pin
Figure 12-10. Power and Ground Schematic for UCD3138 and UCD3138064 40 Pin
Table 12-1. Power and Ground Connection Components for UCD3138 and UCD3138064 40 Pin
COMPONENT
VALUE
C1
C3
1 µF
2.2 µF
2.2 kΩ
4.7 µF
10 nF
10 nF
1 µF
R1
C4
C5
C7
C8
C9
10 nF
4.7 µF
1 Ω
C10
R2
C11
C12
C13
10 µF
10 µF
2.2 µF
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
83
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
Figure 12-12. UCD3138 and UCD3138064 40 Pin
Layout Internal SGND Layer
Figure 12-11. UCD3138 and UCD3138064 40 Pin
Layout Top Layer
12.2.2 UCD3138 and UCD3138064 64 Pin
Figure 12-13. Power and Ground Schematic for UCD3138 and UCD3138064 64 Pin
Copyright © 2021 Texas Instruments Incorporated
84
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
Table 12-2. Power and Ground Connection Components for UCD3138 and UCD3138064 64 Pin
COMPONENT
VALUE
4.7 µF
10 nF
2.2 µF
2.2 kΩ
4.7 µF
10 nF
4.7 µF
10 nF
1 µF
C1
C2
C3
R1
C4
C5
C6
C7
C8
C9
10 nF
4.7 µF
1 Ω
C10
R2
C11
C12
C13
C14
10 µF
10 µF
2.2 µF
10 nF
Figure 12-15. 64 Pin UCD3138 and UCD3138064
Layout Internal SGND Layer
Figure 12-14. UCD3138 and UCD3138064 64 Pin
Layout Top Layer
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
85
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
If it is not possible to fit all the capacitors on the top layer, there is an alternative recommended layout with the
BP18 capacitors located on the bottom layer, directly underneath the UCD.
Figure 12-17. Alternative 64 Pin UCD3138 and
UCD3138064 Layout Bottom Layer
Figure 12-16. Alternative UCD3138 and
UCD3138064 64 Pin Layout Top Layer
Copyright © 2021 Texas Instruments Incorporated
86
Submit Document Feedback
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
13 Device and Documentation Support
13.1 Device Support
The application firmware for the UCD3138064 is developed on Texas Instruments Code Composer Studio (CCS)
integrated development environment. Version 6.2 is recommended for new designs. Designs done with Version
3.3 are still perfectly acceptable as well.
Device programming, real time debug and monitoring/configuration of key device parameters for certain
power topologies are all available through Texas Instruments’ Fusion Digital Power Studio Graphical User
Interface (http://www.ti.com/tool/FUSION-DIGITAL-POWER-STUDIO). The Fusion Digital Power Studio software
application uses the PMBus protocol to communicate with the device over a serial bus using an interface adaptor
known as the USB-TO-GPIO, available as an EVM from Texas Instruments (http://www.ti.com/tool/usb-to-gpio).
PMBUS-based real-time debug capability is available through the ‘Memory Debugger’ tool within the Device
GUI module of the Fusion Digital Power Studio GUI, which represents a powerful alternative over traditional
JTAG-based approaches’.
The software application can also be used to program the devices, with a version of the tool known as Fusion
Production Tool optimized for manufacturing and production environments (https://www.ti.com/tool/FUSION-
PRODUCTION-GUI). The Fusion Production Tool supports multiple devices on a board, and includes built-in
logging and reporting capabilities.
In terms of reference documentation, the following programmer’s manuals are available offering detailed
information regarding the application and usage of UCD3138064 digital controller:
1. UCD3138064 Programmer's Manual - This covers features added with the UCD3138064. For all other topics
see the UCD3138 Technical Reference Manual below.
2. UCD3138 Technical Reference Manual - Key topics covered in this manual include:
•
Digital Pulse Width Modulator (DPWM)
– Modes of Operation (Normal/Multi/Phase-shift/Resonant etc)
– Automatic Mode Switching
– DPWMC, Edge Generation & Intra-Mux
Front End
•
– Analog Front End
– Error ADC or EADC
– Front End DAC
– Ramp Module
– Successive Approximation Register Module
Filter
– Filter Math
•
•
Loop Mux
– Analog Peak Current Mode
– Constant Current/Constant Power (CCCP)
– Automatic Cycle Adjustment
Fault Mux
– Analog Comparators
– Digital Comparators
– Fault Pin functions
– DPWM Fault Action
– Ideal Diode Emulation (IDE), DCM Detection
– Oscillator Failure Detection
ADC12
•
•
– Control, Conversion, Sequencing & Averaging
– Digital Comparators
– Temperature Sensor
– PMBUS Addressing
– Dual Sample & Hold
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
87
Product Folder Links: UCD3138064
UCD3138064
SLUSB72D – MARCH 2013 – REVISED APRIL 2021
www.ti.com
•
•
•
•
•
•
Miscellaneous Analog Controls (Current Sharing, Brown-Out, Clock-Gating)
PMBUS Interface
General Purpose Input Output (GPIO)
Timer Modules
PMBus
Boot ROM & Boot Flash
– BootROM Function
– Memory Read/Write Functions
– Checksum Functions
– Flash Functions
– Avoiding Program Flash Lock-Up
ARM7 Architecture
•
– Modes of Operation
– Hardware/Software Interrupts
– Instruction Set
– Dual State Inter-working (Thumb 16-bit Mode/ARM 32-bit Mode)
Memory & System Module
– Address Decoder, DEC (Memory Mapping)
– Memory Controller (MMC)
– Central Interrupt Module
•
•
Register Map for all of the above peripherals in UCD3138
3. Fusion Digital Power Studio for Isolated Power Applications – User Guide
In addition to the tools and documentation described above, for the most up to date information regarding
evaluation modules, reference application firmware and application notes/design tips, visit http://www.ti.com/
product/ucd3138064.
13.2 Documentation Support
13.2.1 Related Documentation
1. UCD3138064 Programmer’s Manual (SLUUAD8)
2. UCD3138 Technical Reference Manual (SNIU028)
3. Fusion Digital Power Studio for Isolated Power Applications (SLUA676)
4. CCSv6 Getting Started Guide
5. ARM7TDMI-S Technical Reference Manual
6. System Management Bus (SMBus) Specification
7. PMBus™ Power System Management Prototcol Specification
13.3 Trademarks
PMBus™ is a trademark of SMIF, Inc..
All trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
88
Submit Document Feedback
Product Folder Links: UCD3138064
PACKAGE OPTION ADDENDUM
www.ti.com
29-May-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
UCD3138064RGCR
UCD3138064RGCT
UCD3138064RJAR
UCD3138064RMHR
UCD3138064RMHT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
WQFN
WQFN
RGC
RGC
RJA
64
64
40
40
40
2000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
UCD3138064
NIPDAU
NIPDAUAG
NIPDAU
UCD3138064
U3138064
3138064
3000 RoHS & Green
2000 RoHS & Green
RMH
RMH
250
RoHS & Green
NIPDAU
3138064
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-May-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-May-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCD3138064RGCR
UCD3138064RGCT
UCD3138064RJAR
UCD3138064RMHR
UCD3138064RMHT
VQFN
VQFN
VQFN
WQFN
WQFN
RGC
RGC
RJA
64
64
40
40
40
2000
250
330.0
180.0
330.0
330.0
180.0
16.4
16.4
16.4
16.4
16.4
9.3
9.3
6.3
6.3
6.3
9.3
9.3
6.3
6.3
6.3
1.1
1.1
1.1
1.1
1.1
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
Q2
Q2
Q2
Q2
Q2
3000
2000
250
RMH
RMH
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-May-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
UCD3138064RGCR
UCD3138064RGCT
UCD3138064RJAR
UCD3138064RMHR
UCD3138064RMHT
VQFN
VQFN
VQFN
WQFN
WQFN
RGC
RGC
RJA
64
64
40
40
40
2000
250
367.0
210.0
367.0
367.0
210.0
367.0
185.0
367.0
367.0
185.0
38.0
35.0
38.0
38.0
35.0
3000
2000
250
RMH
RMH
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGC 64
9 x 9, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224597/A
www.ti.com
PACKAGE OUTLINE
RGC0064B
VQFN - 1 mm max height
S
C
A
L
E
1
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
9.15
8.85
A
B
PIN 1 INDEX AREA
9.15
8.85
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
2X 7.5
SYMM
EXPOSED
THERMAL PAD
(0.2) TYP
17
32
16
33
65
SYMM
2X 7.5
4.25 0.1
60X
0.5
1
48
0.30
0.18
64X
49
64
PIN 1 ID
0.1
C A B
0.5
0.3
64X
0.05
4219010/A 10/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGC0064B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
4.25)
SEE SOLDER MASK
DETAIL
SYMM
64X (0.6)
49
64
64X (0.24)
1
48
60X (0.5)
(R0.05) TYP
(1.18) TYP
(8.8)
65
SYMM
(0.695) TYP
(
0.2) TYP
VIA
33
16
32
17
(0.695) TYP
(1.18) TYP
(8.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219010/A 10/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGC0064B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
64X (0.6)
64
49
64X (0.24)
1
48
60X (0.5)
(R0.05) TYP
9X ( 1.19)
65
SYMM
(8.8)
(1.39)
33
16
17
32
(1.39)
(8.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 10X
EXPOSED PAD 65
71% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219010/A 10/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
RJA0040A
VQFN - 1 mm max height
S
C
A
L
E
2
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
B
A
PIN 1 INDEX AREA
6.1
5.9
1 MAX
C
SEATING PLANE
0.08
0.05
0.00
2X 4.5
A3
4.15 0.1
(0.2) TYP
A2
4X ( 0.32)
11
20
36X 0.5
10
21
2.74
TYP
2X
4.5
41
EXPOSED
THERMAL PAD
30
0.30
0.18
1
40X
PIN 1 ID
(OPTIONAL)
0.1
C A B
A4
40
31
0.05
0.5
0.3
A1
40X
2.74 TYP
4222901/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RJA0040A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
4.15)
SYMM
4X ( 0.32)
31
40X (0.6)
40
A1
A4
1
30
40X (0.24)
(2.74)
TYP
(0.25) TYP
SYMM
41
(5.8)
(0.685)
TYP
36X (0.5)
(1.14)
TYP
(
0.2) TYP
VIA
10
21
A3
A2
(R0.05) TYP
20
11
(0.685)
TYP
(1.14)
TYP
(2.74) TYP
(5.8)
LAND PATTERN EXAMPLE
SCALE:12X
0.05 MIN
ALL SIDES
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222901/A 05/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RJA0040A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
9X ( 1.17)
(1.37) TYP
4X ( 0.32)
40X (0.6)
40X (0.24)
40
31
A1
A4
1
41
30
(1.37)
TYP
(0.25) TYP
36X (0.5)
SYMM
(5.8)
(R0.05) TYP
10
21
A3
A2
11
20
METAL
TYP
SYMM
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 41:
72% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:12X
4222901/A 05/2016
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
相关型号：
UCD3138064RGCT
具有 64kB 存储器、适用于隔离电源的高集成度数字控制器 | RGC | 64 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCD3138064RJAR
UCD3138064 Highly Integrated Digital Controller for Isolated Power With 64-kB Program Flash MemoryWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCD3138064RMHR
具有 64kB 存储器、适用于隔离电源的高集成度数字控制器 | RMH | 40 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCD3138064RMHT
具有 64kB 存储器、适用于隔离电源的高集成度数字控制器 | RMH | 40 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCD3138064_V01
UCD3138064 Highly Integrated Digital Controller for Isolated Power With 64-kB Program Flash MemoryWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCD3138128
UCD3138x Highly-Integrated Digital Controller For Isolated PowerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCD3138128A
适用于隔离电源的高集成度数字控制器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCD3138128APFC
适用于隔离电源的高集成度数字控制器 | PFC | 80 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCD3138128APFCR
适用于隔离电源的高集成度数字控制器 | PFC | 80 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCD3138128PFC
UCD3138x Highly-Integrated Digital Controller For Isolated PowerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCD3138128PFCR
UCD3138x Highly-Integrated Digital Controller For Isolated PowerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
UCD3138128_15
UCD3138x Highly-Integrated Digital Controller For Isolated PowerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
©2020 ICPDF网 联系我们和版权申明