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UCD90320U

ZHCSJE0 –SEPTEMBER 2018

UCD90320U 32 轨 PMBus™ 电源序列发生器和系统管理器

1 特性

非易失性事件记录功能可在电源断电后保存故障事件。

1

黑盒故障记录功能会在首次发生故障后保存所有电源轨

和 I/O 引脚的状态。凭借级联功能，通过一条

SYNC_CLK 引脚连接即可轻松管理多达 128 个电压

轨。

•

超低阿尔法 (ULA) 塑封料可减少由阿尔法粒子造成

的软错误

•

单粒子翻转 (SEU) 检测

可对 24 个电压轨和 8 个数字轨进行排序、监视和

裕度调节

器件信息⁽¹⁾

•

过压 (OV)、欠压 (UV)、过流 (OC)、欠流 (UC)、

过热、超时以及通用输入 (GPI) 触发的故障

器件型号

封装

BGA (169)

封装尺寸（标称值）

UCD90320U

12.0mm x 12.0mm

提供灵活的排序开启/关闭相关性、延时、布尔逻辑

和通用输入输出 (GPIO) 配置以支持复杂的排序应

用

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

•

四个适用于自适应电压识别 (AVID) 稳压器的电源

轨配置文件

简化应用

•

高精度闭环裕度调节

12-V OUT

12-V

OUT

主动微调功能，可改善电源轨输出电压精度

高级非易失性事件记录功能，可协助系统调试

Temp IC

12-V

Temp

12-V

Cur

INA196

3.3-V

Supply

VREF

(Recommended)

–

单一事件故障记录（100 个条目）

12-V

OUT

峰值记录

GATE

Hot Swap Control

EN

V33A V33D

AMON

黑盒故障记录，用于在首次发生故障时保存所有

电源轨和 I/O 引脚的状态

V_OUT

3.3 V

AMON

EN

V_OUT1.8 V

V_OUT0.8 V

Cur 12 V

3.3-V

OUT

•

可轻松级联多达 4 个电源序列发生器并加以协调以

提供故障响应

VIN

VOUT

EN

Temp 12 V

DC-DC1

Temp 0.8 V

VFB

可编程的看门狗定时器和系统复位

AMON

UCD90320U

DMON

POL‘s PWRGD

2 应用

VIN

V_OUT

1.8 V

•

工业和自动测试设备 (ATE)

EN

VOUT

LDO1

EN

WDI from main

processor

GPIO

LGPO

GPIO

电信及网络设备

WDO

服务器和存储系统

0.8 V

Temp IC

POWER_GOOD

需要对多个电源轨进行排序和监视的系统

VIN

VOUT

DC-DC2

VFB

WARN_OV_ 0.8 V

or WARN_OV_12 V

V_OUT

0.8 V

EN

3 说明

SYSTEM_RESET

Other sequencer

done (cascade input)

UCD90320U 器件是 32 轨 PMBus™可寻址电源序列

发生器和系统管理器，采用 0.8mm 间距 BGA 封装。

采用 ULA 塑封材料减少由阿尔法粒子造成的软错误。

该器件可通过扫描用户配置 SRAM 检测单粒子翻转

(SEU)。两种特性都可以为应用提供更高的可靠性提

供足够的间距。

I²C/PMBus

MARGIN

3.3-V

JTAG

GPIO

UCD90320U (Cascaded)

SYNC_CLK

SYNC-CLK

24 条集成 ADC 通道 (AMONx) 监视电源电压、电流和

温度。在 84 个 GPIO 引脚中，8 个可用作数字监视器

(DMONx)，32 个可支持电源 (ENx)，24 个用于裕量调

节 (MARx)，16 个用于逻辑 GPO，32 个 GPI 用于级

联和系统功能。

32 个 ENx 引脚和 16 个 LGPOx 引脚可配置为电平有

效驱动或开漏输出。

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSDC1

UCD90320U

ZHCSJE0 –SEPTEMBER 2018

www.ti.com.cn

8.3 Feature Description................................................. 14

8.4 Device Functional Modes........................................ 15

8.5 Device Configuration and Programming................. 41

Application and Implementation ........................ 44

9.1 Application Information............................................ 44

9.2 Typical Application ................................................. 44

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

说明（续）.............................................................. 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 8

7.1 Absolute Maximum Ratings ...................................... 8

7.2 ESD Ratings.............................................................. 8

7.3 Recommended Operating Conditions....................... 8

7.4 Thermal Information.................................................. 9

7.5 Electrical Characteristics........................................... 9

7.6 Non-Volatile Memory Characteristics ..................... 10

7.7 I²C/PMBus Interface Timing Requirements ............ 11

7.8 Typical Characteristics............................................ 12

Detailed Description ............................................ 13

8.1 Overview ................................................................. 13

8.2 Functional Block Diagram ....................................... 13

9

10 Power Supply Recommendations ..................... 47

11 Layout................................................................... 47

11.1 Layout Guidelines ................................................. 47

11.2 Layout Example .................................................... 48

12 器件和文档支持 ..................................................... 49

12.1 社区资源................................................................ 49

12.2 接收文档更新通知 ................................................. 49

12.3 商标....................................................................... 49

12.4 静电放电警告......................................................... 49

12.5 术语表 ................................................................... 49

13 机械、封装和可订购信息....................................... 49

8

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

日期

修订版本

说明

2018 年 9 月

*

初始发行版。

2

UCD90320U

www.ti.com.cn

ZHCSJE0 –SEPTEMBER 2018

5 说明（续）

FAULT 引脚可以协调级联器件，使其对故障做出同步响应。引脚选择电源轨状态功能使用多达 3 个 GPI 控制多达

八个用户定义的电源状态。这些状态可实现高级配置和电源接口 (ACPI) 规范中列出的系统低功耗模式。

TI Fusion Digital Power™设计软件是一款基于 PC 的直观图形用户界面 (GUI)，可对所有系统工作参数进行配置、

存储和监视。

6 Pin Configuration and Functions

ZWS Package

169-Pin BGA

Top View

1

2

3

4

5

6

7

8

9

10

11

12

13

Unused-

NC

AMON1 AMON1 AMON2 AMON2

JTAG_T JTAG_T

A

B

C

D

E

F

DVSS

AMON6 AMON8

LGPO3

LGPO2

LGPO1

DVSS

V33D

DVSS

V33D

EN6

GPIO4

GPIO2

MAR14

MAR17

MAR19

EN26

MAR15

MAR16

MAR18

A

B

C

D

E

F

0

2

4

MS

DO

AMON1 AMON1

AMON1 AMON2 AMON2

JTAG_T

DI

AMON5 AMON7 AMON9

GPIO1

5

6

1

3

AMON1 AMON1

JTAG_T

CK

AVSS

V33A

AVSS

LGPO8

MAR5

MAR6

LGPO6

LGPO5

DVSS

MAR7

DVSS

MAR10

MAR2

LGPO7

DVSS

LGPO4

GPIO3

3

4

PMBUS

_DATA

VREFA- VREFA+

AMON2 AMON1

BPCap

V33D

DVSS

BPCap

MAR4

MAR12

MAR11

MAR9

6

V33D

DVSS

V33D

EN13

EN14

EN12

EN11

7

MAR3

V33D

DVSS

EN10

EN9

DMON4 MAR13

PMBUS PMBUS

MAR20

EN25

_CLK

_CNTRL

PMB

ALERT#

AMON4 AMON3 DMON2 DMON1

AMON1 AMON1

V33D

Unused- Unused-

DVSS

G

H

J

DMON3

EN24

EN22

EN19

EN18

RESET

EN28

V33D

EN4

EN27

EN31

DVSS

G

H

J

8

7

NC

AMON1 AMON2

EN23

EN30

EN29

9

0

BPCap

EN20

EN21

MAR24

MAR1

BPCap

EN32

PMBUS SYNC_

_ADDR2 CLK

Unused- Unused-

DVSS V33D

K

L

EN17

K

L

PMBUS PMBUS

_ADDR1 _ADDR0

LGPO9 LGPO13

EN5

EN3

DMON5 MAR22

Unused-

DVSS

Unused-

M

N

LGPO10 LGPO11 LGPO12 LGPO15 MAR23

EN8

EN1

DMON8

NC

MAR21

M

N

Unused-

NC

Unused-

DVSS

LGPO14 LGPO16

EN16

3

EN15

4

MAR8

5

EN7

EN2

DMON7 DMON6

1

2

8

9

10

11

12

13

3

UCD90320U

ZHCSJE0 –SEPTEMBER 2018

www.ti.com.cn

Pin Functions

I/O

DESCRIPTION

NAME

NO.

ANALOG MONITOR PINS⁽¹⁾

AMON1

E2

E1

F2

F1

B3

A3

B4

A4

B5

A5

B6

A6

C1

C2

B1

B2

G2

G1

H1

H2

B7

A7

B8

A8

I

Analog input monitor pin

AMON2

Analog input monitor pin

AMON3

AMON4

AMON5

AMON6

AMON7

AMON8

AMON9

AMON10

AMON11

AMON12

AMON13

AMON14

AMON15

AMON16

AMON17

AMON18

AMON19

AMON20

AMON21

AMON22

AMON23

AMON24

ENABLE PINS

EN1(GPIO)

EN2(GPIO)

EN3(GPIO)

EN4(GPIO)

EN5(GPIO)

EN6(GPIO)

EN7(GPIO)

EN8(GPIO)

EN9(GPIO)

EN10(GPIO)

EN11(GPIO)

EN12(GPIO)

EN13(GPIO)

EN14(GPIO)

EN15(GPIO)

EN16(GPIO)

EN17(GPIO)

EN18(GPIO)

EN19(GPIO)

M9

N9

L10

K10

L9

I/O

Digital output, rail enable signal or GPIO⁽²⁾

Digital output, rail enable signal or GPIO

K9

N8

M8

L8

K8

N7

M7

K7

L7

N4

N3

K3

K4

J4

(1) TI recommends placing a 200-Ω resistor between analog input and monitor pins.

(2) GPIO: GPI, Command GPO, WDI, WDO, system reset (RESET), FAULT pin for multiple chip cascading

4

UCD90320U

www.ti.com.cn

ZHCSJE0 –SEPTEMBER 2018

Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

J2

EN20(GPIO)

EN21(GPIO)

EN22(GPIO)

EN23(GPIO)

EN24(GPIO)

EN25(GPIO)

EN26(GPIO)

EN27(GPIO)

EN28(GPIO)

EN29(GPIO)

EN30(GPIO)

EN31(GPIO)

EN32(GPIO)

I/O

Digital output, rail enable signal or GPIO

J3

H4

H3

G4

F13

F12

G11

H10

H13

H12

H11

L13

CLOSED-LOOP MARGIN PINS

MAR1(GPIO)

MAR2(GPIO)

MAR3(GPIO)

MAR4(GPIO)

MAR5(GPIO)

MAR6(GPIO)

MAR7(GPIO)

MAR8(GPIO)

MAR9(GPIO)

MAR10(GPIO)

MAR11(GPIO)

MAR12(GPIO)

MAR13(GPIO)

MAR14(GPIO)

MAR15(GPIO)

MAR16(GPIO)

MAR17(GPIO)

MAR18(GPIO)

MAR19(GPIO)

MAR20(GPIO)

MAR21(GPIO)

MAR22(GPIO)

MAR23(GPIO)

MAR24(GPIO)

J13

L5

I/O

Closed-loop margin PWM output or General GPIO

D8

K6

D4

E4

F5

N5

N6

K5

M6

L6

D11

C12

A13

B13

D12

C13

E12

E13

M13

L12

M5

J12

GPIO AND CASCADING PINS

DMON1(GPIO)

DMON2(GPIO)

DMON3(GPIO)

DMON4(GPIO)

DMON5(GPIO)

DMON6(GPIO)

DMON7(GPIO)

F4

F3

I/O

Digital input monitor pin or GPIO

G3

D10

L11

N12

N11

5

UCD90320U

ZHCSJE0 –SEPTEMBER 2018

www.ti.com.cn

Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

DMON8(GPIO)

GPIO

M11

I/O

Digital input monitor pin or GPIO

GPIO1

B11

B12

C11

A12

K2

I/O

GPIO

GPIO2

GPIO

GPIO3

GPIO

GPIO4

GPIO

SYNC_CLK

Synchronization clock I/O for multiple chip cascading

LOGIC GPO PINS

LGPO1(GPIO)

LGPO2(GPIO)

LGPO3(GPIO)

LGPO4(GPIO)

LGPO5(GPIO)

LGPO6(GPIO)

LGPO7(GPIO)

LGPO8(GPIO)

LGPO9(GPIO)

LGPO10(GPIO)

LGPO11(GPIO)

LGPO12(GPIO)

LGPO13(GPIO)

LGPO14(GPIO)

LGPO15(GPIO)

LGPO16(GPIO)

C9

B9

A9

C8

D5

C5

C6

C4

L3

I/O

Logic GPO or GPIO

M1

M2

M3

L4

N1

M4

N2

PMBus COMM INTERFACE

PMBUS_CLK

PMBUS_DATA

PMBALERT

PMBUS_CNTRL

PMBUS_ADDR0

PMBUS_ADDR1

PMBUS_ADDR2

JTAG

E10

D13

F11

E11

L2

I

PMBus clock (must pull up to V33D)

PMBus data (must pull up to V33D)

PMBus alert, active-low, open-drain output (must pull up to V33D)

PMBus control pin

I/O

O

I

PMBus digital address input. Bit 0

PMBus digital address input. Bit 1

PMBus digital address input. Bit 2

L1

I

K1

I

JTAG_TMS

A10

C10

A11

B10

I

Test mode select with internal pull-up

Test clock with internal pull-up

Test data out with internal pull-up

Test data in with internal pull-up

JTAG_TCK

JTAG_TDO

O

I

JTAG_TDI

INPUT POWER, GROUND, AND EXTERNAL REFERENCE PINS

RESET

G10

I

Active-low device reset input. Pull up to V33D.

Analog 3.3-V supply. Decouple from V33D to minimize the electrical noise contained on

V33D from affecting the analog functions.

V33A

D3

I

D7, E6, E8,

E9, F10, J7,

J9, J10

V33D

I

Digital 3.3-V supply for I/O and some logic.

Positive supply for most of the logic function, including the processor core and most

peripherals. The voltage on this pin is 1.2 V and is supplied by the on-chip LDO. The

BPCap pins should only be connected to each other and an external capacitor as specified

in On-Chip Low Drop-Out (LDO) Regulator section of the Electrical Characteristics table.

D6, J1, J6,

K13

BPCap

6

UCD90320U

www.ti.com.cn

ZHCSJE0 –SEPTEMBER 2018

Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

Analog ground. These are separated from DVSS to minimize the electrical noise contained

on V33D from affecting the analog functions.

AVSS

C3, E3

I

A1, C7, D9,

E5, F9, H5,

H9, J5, J8,

J11, H6,

H7, H8, G5,

G6, G7, G8,

G9, F6, F7,

F8, E7

DVSS

I

Ground reference for logic and I/O pins.

VREFA+

VREFA-

D2

D1

I

(Optional) positive node of external reference voltage

(Optional) negative node of external reference voltage

UNUSED PINS

A2, G13,

M12, N10

UNUSED-NC

–

Do not connect. Leave floating or isolated.

G12, K11,

M10, N13

UNUSED-DVSS

UNUSED-V33D

–

Tie to DVSS.

Tie to V33D.

K12

7

UCD90320U

ZHCSJE0 –SEPTEMBER 2018

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

0

MAX

UNIT

V

V33D to DVSS

Supply voltage

4

V33A to AVSS

0

V

on all I/O pins except PMBUS_CNTRL, PMBALERT, MARGIN19, and

–0.3

5.5

V

MARGIN20, regardless of whether the device is powered⁽²⁾

PMBUS_CNTRL, PMBALERT, MARGIN19, and MARGIN20

Maximum current per output pin

Input voltage

V_V33D

0.3

+

Output current

25

mA

°C

Operating junction temperature, T_J

Storage temperature, T_stg

TBD

–65

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those listed in the Recommended

Operating Conditions table. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Applies to static and dynamic signals including overshoot.

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

Electrostatic

discharge

V_(ESD)

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

3.15

2.97

–40

NOM

3.3

MAX

3.63

85

UNIT

V

V_V33D

V_V33A

T_A

Supply input voltage

(1)

3.3

V

Operating ambient temperature

Operating case temperature

Operating junction temperature

°C

T_C

90

T_J

93

(1) It is recommended to connect the V33A pin and the V33D pin to the same supply. V33A must be powered before V33D if sourced from

different supplies. There is no restriction on the ordering sequence for powering off.

8

UCD90320U

www.ti.com.cn

ZHCSJE0 –SEPTEMBER 2018

7.4 Thermal Information

UCD90320U

THERMAL METRIC⁽¹⁾

ZWS (BGA)

169 PINS

41.6

UNIT

R_θJA

Junction-to-ambient thermal resistance⁽²⁾⁽³⁾

Junction-to-case (top) thermal resistance⁽²⁾

Junction-to-board thermal resistance^(2)(4)(5)

Junction-to-top characterization parameter⁽⁶⁾

Junction-to-board characterization parameter⁽⁴⁾

Junction-to-case (bottom) thermal resistance

°C/W

R_θJC(top)

R_θJB

15.8

18.9

ψ_JT

0.3

ψ_JB

20.3

R_θJC(bot)

n/a

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2) Junction to ambient thermal resistance (θ_JA), junction to board thermal resistance (θ_JB), and junction to case thermal resistance (θ_JC

)

numbers are determined by a package simulator.

(3) T_J= T_A+ (P × θ_JA

)

(4) T_J= T_PCB+ (P × Ψ_JB

)

()

(5) T_J= T_B+ (P × θ_JB

)

(6) T_J= T_C+ (P × Ψ_JT

)

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY CURRENT

I_V33Supply Current

V_V33D= V_V33A= 3.3 V

31.4

54.9

mA

ON-CHIP LOW DROP-OUT (LDO) REGULATOR

External filter capacitor size for internal

C_LDO

2.5

4

µF

power supply⁽¹⁾

V_LDO

LDO output voltage

Inrush current

1.08

50

1.2

1.32

250

V

I_INRUSH

mA

ANALOG-TO-DIGITAL CONVERTER (ADC)⁽²⁾⁽³⁾

V33A

AVSS

ADC supply voltage

ADC ground voltage

2.97

3.3

0

3.63

V

Voltage reference decoupling capacitance

between V33A and AVSS (if using internal

reference)

C_V33A

1.01

µF

(4)

Positive external voltage reference on

VREFA+ pin

V_REFA+

V_REFA-

2.4

3

V

Negative external voltage reference on

VREFA– pin

V_AVSS

AVSS

1.01

0.3

Voltage reference decoupling capacitance

between VREFA+ and VREFA– (if using

external reference)⁽⁴⁾

Analog input range, internal reference⁽⁵⁾

Analog input range, external reference⁽⁶⁾

ADC input leakage current

C_REF

µF

V

0

V33A

V_VREFA+

2

V_ADCIN

V_VREFA–

I_L

µA

kΩ

pF

R_ADC

C_ADC

ADC equivalent input resistance

ADC equivalent input capacitance

2.5

10

ADC conversion rate (on each ADC

channel)⁽¹⁾

F_CONV

1

MSPS

(1) Connect the capacitor as close as possible to pin D6.

(2) Total of two ADC channels run independently during normal operation.

(3) Total unadjusted error is the maximum error at any one code versus the ideal ADC curve. It includes offset error, gain error, and INL at

any given ADC code.

(4) Two capacitors (1.0 µF and 0.01 µF) connected in parallel.

(5) Internal reference is connected directly between V33A and AVSS.

(6) External reference noise level must be under 12 bit (–74 dB) of full scale input, over input bandwidth, measured at VREFA+ - VREFA–.

9

UCD90320U

ZHCSJE0 –SEPTEMBER 2018

www.ti.com.cn

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

ADC resolution

TEST CONDITIONS

MIN

TYP

MAX

UNIT

N

12

bits

Total unadjusted error, over full input

rangea when using internal reference

±10

±30

±4

E_T

LSB

Total unadjusted error, over full input range

when using external reference

±2.5

DIGITAL INPUTS AND OUTPUTS (GPIO, Logic GPO, EN, AND MARGIN PINS)

0.65 ×

V_V33D

V_IH

V_IL

I/O high-level input voltage⁽⁷⁾

5.5

V

0.35 ×

V_V33D

I/O low-level input voltage

0

V_HYS

V_OH

V_OL

I_OH

I/O input hysteresis

0.2

2.4

V

I/O high-level output voltage

I/O low-level output voltage

High-level source current

Low-level sink current

0.4

2.6

V

V_OH= 2.4 V⁽⁸⁾

V_OL= 0.4 V⁽⁸⁾

4

mA

I_OL

RESET AND BROWNOUT

Minimum V33D slew rate between 2.8 V

and 3.2 V

V33DSlew

V_RESET

0.1

2

V/ms

V

Supply voltage at which device comes out

of reset

2.3

Supply voltage at which device enters

brownout

V_BOR

V_SHDN

t_RESET

t_IRT

2.93

2.7

3.02

2.78

250

9

3.11

2.87

V

Supply voltage at which device shuts down

Minimum low-pulse width needed at

ns

ms

RESET

̅

Internal reset time⁽⁹⁾

11.5

(7) PMBUS_CNTRL, PMBALERT, MARGIN19 and MARGIN20 pins have V_V33D+ 0.3 V as maximum input voltage rating.

(8) I_Ospecifications reflect the maximum current where the corresponding output voltage meets the V_OH/V_OLthresholds.

(9) If power-loss or brown-out event occurs during an EEPROM program or erase operation, and EEPROM needs to be repaired (which is a

rare case), the internal reset time may be longer.

7.6 Non-Volatile Memory Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CONFIGURATION FLASH MEMORY

Number of program and erase

cycles before failure

PE_CYC

100,000

20

Cycles

Years

T_RET

Data retention

–40°C ≤ T_J≤ 85°C

FAULT AND EVENT LOGGING EEPROM

Number of mass program and erase

EPE_CYC

500,000

20

Cycles

Years

cycles of a single word before failure

ET_RET

Data retention

–40°C ≤ T_J≤ 85°C

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7.7 I²C/PMBus Interface Timing Requirements

MIN

450

NOM

MAX

UNIT

ns

I1

I2

I3

I4

I5

I6

I7

I8

I9

I10

t_(HD:STA)

t_(LOW)

t_r

Start condition hold time

Clock low period⁽¹⁾

Clock rise time and data rise time⁽²⁾

ns

See⁽²⁾

125

ns

t_(HD:DAT)

t_f

Data hold time

25

ns

Clock fall time and data fall time⁽³⁾

Clock high time

112.5

ns

t_(HIGH)

t_(SU:DAT)

t_(SU:STA)

t_(SU:STO)

t_(DV)

300

225

450

300

ns

Data setup time

ns

Start condition setup time (repeated start only)

Stop condition setup time

Data valid

ns

25

ns

(1) PMBus host must support clock stretching per PMBus Power System Management Protocol Specification Part I General Requirements,

Transport and Electrical Interface, Revision 1.2, Section 5.2.6.

(2) Because the I2CSCL signal and the I2CSDA signal operate as open-drain-type signals, which the controller can actively drive only

"Low", the time that either signal takes to reach a high level depends on external signal capacitance and pull-up resistor values.

(3) Specified at a nominal 50-pF load.

I2

I10

I6

I5

I2CSCL

I2CSDA

I1

I7

I8

I3

I9

I4

Figure 1. I²C/PMBus Timing Diagram

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7.8 Typical Characteristics

1

0.8

0.6

0.4

0.2

0

1

0.8

0.6

0.4

0.2

0

INL Minimum

INL Maximum

DNL Minimum

DNL Maximum

-0.2

-0.4

-0.6

-0.8

-1

-0.2

-0.4

-0.6

-0.8

-1

-40 -25 -10

5

20

35

50

65

80

95 110

-40 -25 -10

5

20

35

50

65

80

95 110

Junction Temperature (°C)

D001

Figure 2.

Figure 3.

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8 Detailed Description

8.1 Overview

Electronic systems such as CPU, DSP, microcontroller, FPGA, and ASIC can have multiple voltage rails and

require certain power-ON and power-OFF sequences in order to function correctly. The UCD90320U device can

control up to 32 voltage rails and ensure correct power sequences during normal condition and fault conditions.

In addition to sequencing, the device can continuously monitor rail voltages, currents, temperatures, fault

conditions, and report the system health information to upper computers through a PMBus interface, improving

long term reliability.

The device can protect electronic systems by responding to power system faults. The fault responses are

conveniently configured by users through Fusion Digital Power Designer software . Fault events are stored in on-

chip nonvolatile flash memory in order to assist failure analysis. A Black Box Fault Log feature stores

comprehensive system statuses at the moment when the first fault occurs. With this feature, failure analysis can

be more effective.

System reliability can be improved through four-corner testing during system verification. During four-corner

testing, each voltage rail is required to operate at the minimum and maximum output voltages, commonly known

as margining. The device can perform accurate closed-loop margining for up to 24 voltage rails. During normal

operation, UCD90320U can also actively trim DC output voltages using the same margining circuitry. This feature

allows tuning rail voltages to an optimal level.

The UCD90320U device supports control environments via both PMBus interface and pin-based interface. The

device functions as a PMBus slave. It can communicate with upper computers with PMBus commands, and

control voltage rails accordingly. In addition to rail enable (EN) pins, up to 32 GPIO pins can be configured as

GPOs and directly controlled by PMBus commands. The device can be controlled by up to 32 GPIO configured

GPI pins. The GPIs can be used as fault inputs which can shut down rails. The GPIs can be also used as

Boolean logic input to control the 16 Logic GPO outputs. Each of the 16 Logic GPO pins has a flexible Boolean

logic builder. Input signals of the Boolean logic builder can include GPIs, other GPOs, and selectable system

flags such as POWER_GOOD, faults, warnings, and so forth. A simple state machine is also available for each

Logic GPO pin.

The device provides additional features such as cascading, pin-selected states, system watchdog, system reset,

run time clock, peak value log, reset counter, and so forth. Cascading feature offers convenient ways to cascade

up to 4 UCD90320U devices and manage up to 128 voltage rails through one SYNC_CLK pin connection. Pin-

selected states feature allows users to define up to 8 rail states. These states can implement system low-power

modes as set out in the Advanced Configuration and Power Interface (ACPI) specification. The Feature

Description section of this datasheet describes other device features.

8.2 Functional Block Diagram

Digital I/O

PMBus

Slave

JTAG

Rail Enables(32 max)

Rail Margining (24 max)

32

Sequencing Engine

84

24ch ADC (12bit,

2x1MSPS) + 8

Digital Mon

Programmable Logic GPO

(16 max)

Configurable GPIO( GPI,

GPO, Fault Pin, watchdog/

system reset, 32 max)

Boolean

Logic

Builder

Nonvolatile

Event

Logging

Digital Mon Rail(8 max)

Sync Clock

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8.3 Feature Description

8.3.1 TI Fusion Digital Power Designer software

The Texas Instruments Fusion Digital Power Designer software allows the user to configure the device. This PC-

based graphic user interface (GUI) offers an intuitive I²C and PMBus interface to the device. The Fusion Digital

Power Designer software allows the design engineer to configure the system operating parameters for the

application without directly using PMBus commands, store the configuration to on-chip nonvolatile memory, and

observe system status (voltage, current, temperature, faults, and so forth). This data sheet references the Fusion

Digital Power Designer software is as Fusion Digital Power Designer software and many sections include

screenshots. Download the Fusion Digital Power Designer software from TI here. After configuration, the device

can perform all designed functions independently without further need for the Fusion GUI.

8.3.2 PMBUS Interface

PMBus refers to a serial interface specifically designed to support power management. The PMBus interface is

based on the SMBus interface that is built on the I²C physical specification. The UCD90320U device supports

revision 1.2 of the PMBus standard. Wherever possible, standard PMBus interface commands support the

function of the device. Unique features of the device are defined to configure or activate via the MFR_SPECIFIC

commands. These commands are defined in the, UCD90320U Sequencer and System Health Controller PMBUS

Command Reference. The most current UCD90320U PMBus™ Command Reference can be found within the TI

Fusion Digital Power Designer software through the Help Menu (Help, Documentation & Help Center,

Sequencers tab, Documentation section).

This data sheet makes frequent mention of the PMBus specification. Specifically, this document is PMBus Power

System Management Protocol Specification Part II – Command Language, Revision 1.2, dated 6 September

2010. The specification is published by the Power Management Bus Implementers Forum and is available from

www.pmbus.org.

The UCD90320U device meets all of the requirements of the Compliance section of the PMBus specification.

The firmware complies with the SMBus 1.2 specification, including support for the SMBus ALERT function. The

hardware supports either 100-kHz or 400-kHz PMBus operation.

8.3.3 Rail Setup

Power rails are defined under the Pin Assignment tab, as shown in Figure 4. Click corresponding buttons to add

or delete a rail. After a rail is added, AMON, DMON, EN, and MARGIN pins can be assigned to the rail.

UCD90320U has 24 AMON pins, 8 DMON pins, 32 EN pins, and 24 MARGIN pins, thus can support up to 32

rails.

Figure 4. Fusion Digital Power Designer software Rail Setup Window (Configure ►Pin Assignment tab)

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8.4 Device Functional Modes

8.4.1 Rail Monitoring Configuration

After rails are set up in the Pin Assignment tab, they are visible under the Vout Config tab, as shown in

Figure 5. The initial voltage values are 0.

Figure 5. Rail Selection Window (Rail Configuration)

Configure the voltage monitoring parameters of the selected rail under the Vout Config tab. Figure 6 shows the

configuration window..

Figure 6. Rail Voltage Configuration Window (Rail Configure, Vout Config tab)

When a AMON pin is assigned in Figure 4 to monitor the voltage of a particular a rail, a fault or warn event

occurs when the monitored rail voltage exceeds the voltage window defined by the Over and Under Warn/Fault

thresholds. When a fault is detected, the device responds with user-defined actions. See also the Fault

Responses Configuration section for more details.

Rail Profile is composed of a group of nine thresholds set by: VOUT_COMMAND, VOUT_OV_FAULT_LIMIT,

VOUT_OV_WARNING_LIMIT,

VOUT_MARGIN_HIGH,

POWER_GOOD_ON,

VOUT_MARGIN_LOW,

POWER_GOOD_OFF, VOUT_UV_WARNING_LIMIT and VOUT_UV_FAULT_LIMIT.

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Device Functional Modes (continued)

Figure 7. Rail Profile Configurations (Rail Config ► Edit Rail Profiles)

The device offers 50 individual profiles shared among all 24 AMON voltage rails. Each AMON voltage rail can

have at least one but no more than 4 profiles. The profiles are controlled by 2 GPIs as shown in Figure 8. A

programmable block-out period is used to block all voltage related faults on the given rail when profile is

changed.

Figure 8. Rails Profile Selection Through GPIs (Rail Config ► Edit Rail Profiles)

The device supports digital monitor. If a DMON pin is assigned in Figure 7 to monitor POWER_GOOD of POL.

The DMON rail has no rail profile. If the DMON input is logic HIGH, the rail is POWER_GOOD, otherwise the

rails has UV fault or warns and is at POWER_NOT_GOOD.

Figure 9. Digital Rail Configuration Window

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Device Functional Modes (continued)

Vout Exponent defines the voltage value resolution according to PMBus linear data format. Fusion Digital Power

Designer software can automatically select optimal Vout Exponent value to cover the required voltage range with

the finest possible resolution. For more information regarding PMBus linear data format, refer to PMBus

specification mentioned at the beginning of this section.

On/Off Config defines a rail turn-ON and turn-OFF command:

•

None (Auto enable). Rail always seeks to turn-ON as long as UCD90320U is powered.

CONTROL Pin Only. Rail seeks to turn-ON and turn-OFF according to PMBus CONTROL line (asserted/de-

asserted).

•

OPERATION Only. Rail seeks to turn-ON and turn-OFF according to PMBus OPERATION command (On/

Off).

Both CONTROL pin and OPERATION. Rail seeks to turn-ON when CONTROL pin is asserted, AND PMBus

OPERATION command sets the rail to On. Rail seeks to turn-OFF when OPERATION command sets the rail

to OFF, OR when CONTROL line is de-asserted.

After receiving a turn ON or turn OFF command, a rail examines a series of conditions before asserting or de-

asserting its EN pin. Conditions include Rail Sequence On/Off Dependency, GPI Sequence On/Off

Dependency, Turn-On/Off Delay, as shown in Rail Sequence Configuration section.

Fixed percentage voltages setpoint, when checked, configures a rail into adaptive voltage scaling technology

(AVS) mode. The Vout Setpoint can be dynamically set by PMBus during operation in order to achieve

energy saving. The rail warn and fault voltage thresholds maintain fixed ratios with respect to the Vout

Setpoint. Due to the fact that the power supply and UCD90320U device may not change Vout Setpoint

simultaneously or with the same slew rate, the device takes the following steps to avoid false-triggering warn

and fault. If the new Vout Setpoint is higher than the current Vout Setpoint , the OV warn and fault thresholds

are immediately set to their respective new levels. Other thresholds are initially maintained, and then increase

by 20-mV step size in every 400 µs until the new levels are reached. If the new Vout Setpoint is lower than

the current Vout Setpoint, the UV warn and fault and Power Good On and Power Good Off thresholds are

immediately set to their respective new levels. Other thresholds are initially maintained, and then decrease by

20-mV step size every 400 µs until the new levels are reached. Table 1 summarizes the thresholds

adjustment scheme in AVS mode.. This feature is not available for DMON pin.

Table 1. Thresholds Adjustment Scheme in AVS Mode

TRANSITION

IMMEDIATE UPDATE

ADJUSTMENT⁽¹⁾

UV fault and warn notification, Margin High

and Margin Low, Power Good On and Power

Good Off

OV fault and warn notification

New Vout Setpoint to Current Vout Setpoint

UV fault and warn notification, Power Good

On and Power Good Off

OV fault and warn notification, Margin High

and Margin Low,

(1) Gradual adjustment towards new levels with 2-0mV step size and 400-µs step interval

Current and temperature monitoring parameters of the selected rail can be configured under the Fault

Responses and Limits tab. First select a rail in the top-right corner of the Fusion Digital Power Designer

software , and then edit the current and temperature monitoring parameters as shown in Figure 10.

Figure 10. Current and Temperature Limits Configuration Window

(Rail Config ► IOUT and Temperature Limits)

Each rail has a Power Good status determined by the following rules.

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•

If rail voltage is monitored by an AMON pin, the Power Good status is solely determined by Power Good On

and Power Good Off thresholds as shown in Figure 6. A rail is given Power Good status if its rail voltage is

above the Power Good On threshold. Otherwise, the rail is given Not Power Good status if the rail voltage is

below the Power Good Off threshold. The rail remains in the current status if its voltage is neither above

Power Good On nor below Power Good Off thresholds.

•

If rail voltage is not monitored by a AMON or DMON pin, the Power Good status is determined by the turn-

ON and turn-OFF eligibility of the rail. A rail is immediately given Power Good status when the rail meets all

the turn-on conditions set by the user, such as On and Off Config, dependencies and delays. Similarly, a rail

is immediately given Not Power Good status when the rail meets all the turn-off conditions set by the user.

The behavior is the same regardless whether a physical EN pin is assigned to the rail.

The Power Good status is not affected by any warnings and faults unless the fault response is to turn OFF the

rail.

UV fault and warn notification is ignored when a rail is off. UV fault and warn notification is also ignored during

start up until the rail enters Power Good status for the first time. This mechanism avoids false-triggering UV fault

and warn notification when the rail voltage is expected to be below UV thresholds.

A Graceful Shutdown feature is enabled by checking the Configured as VIN Monitor checkbox. When enabled,

the rail is configured to monitor VIN. When VIN drops below Power Good Off threshold, the device ignores any

UV fault and warn notifications on any other rail.

8.4.2 GPI Configuration

Up to 32 of the 84 GPIO pins of the UCD90320U device can be configured as GPI. The GPI configuration

window is under the Pin Assignment tab. Figure 11 shows an example.

Figure 11. GPI Configuration Window (Hard Configuration ► Monitors and GPIO Pins Assignment)

The polarity of GPI pins can be configured to be either active high or active low. Each GPI can be used as a

source of sequence dependency. (See also the Rail Sequence Configuration section). The GPI pins can be also

used for cascading function. (See also the Cascading Multiple Devices section). The first defined 3 GPIs

regardless of their main purpose are assigned to the pin selected states function. (See also the Pin Selected Rail

States Configuration section).

In addition hard configuration functions, four special behaviors can be assigned to each GPI pin using the

dropdown window shown in Figure 12:

•

GPI Fault The de-assertion of this pin is treated as a fault, which can trigger shut-down actions for any

voltage rails. (See also the Fault Responses Configuration section).

Latched Statuses Clear Source This pin can be used to clear latched-type statuses (_LATCH). (See also

the GPO Configuration section).

Input Source for Margin Enable When this pin is asserted, all rails with margining enabled enter into a

margined state (low or high). This special behavior can be assigned to only one GPI.

Input Source for Margin Low and Not-High When this pin is asserted, all margined rails are set to Margin

Low as long as the Margin Enable is asserted. When this pin is de-asserted the rails are set to Margin High

as long as the Margin Enable is asserted. This special behavior can be assigned to only one GPI.

•

Configured as Debug Pin When the pin is asserted, the device does not alert the PMBALERT pin, and

neither responds to, nor logs any faults as defined in Table 2. The device ignores the rail sequence ON and

OFF dependency conditions. As soon as the sequence ON and OFF timeout expires, the rails are sequenced

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ON or OFF accordingly regardless of the timeout action. If the sequence ON or OFF timeout value is set to 0,

the rails are sequenced ON or OFF immediately. The fault pins do not pull the fault bus low. LGPOs affected

by these events return to the original states.

•

Configured as Fault Pin GPI fault enable functionality must be set to enable this feature. When set, if there

is no fault on a fault bus. The FAULT pin is digital input pin and it monitors the fault bus. When one or more

UCD90329 devices detect a rail fault, the corresponding FAULT pin is turned into active driven low state,

pulling down the fault bus voltage and informing all other UCD90320U devices of the corresponding fault.

This behavior allows a coordinated action to be taken across multiple devices. After the fault is cleared, the

state of the FAULT pin reverts to that of an input pin.(See also the Cascading Multiple Devices section).

Figure 12. GPI Configuration Dropdown Window

(Hardware Configuration ► Monitor and GPIO Pins Assignment)

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Table 2. List of Events Affected by Debug Mode

Events

Description

VOUT_OV_FAULT

VOUT_OV_WARNING

VOUT_UV_FAULT

VOUT_UV_WARNING

TON_MAX

Voltage rail is over OV fault threshold

Voltage rail is over OV warning threshold

Voltage rail is under UV fault threshold

Voltage rail is under UV warning threshold

Voltage rail fails to reach power good threshold in predefined period.

TOFF_MAX Warning

Voltage rail fails to reach power not good threshold in predefined

period

IOUT_OC_FAULT

IOUT_OC_WARNING

IOUT_UC

Current rail is over OC fault threshold

Current rail is under OC warning threshold

Current rail is under UC fault threshold

Temperature rail is over OT fault threshold

Temperature rail is over OT warning threshold

OT_FAULT

OT_WARNING

All GPI de-asserted

No logging and fault response, but the function of the GPI is not

ignored.

SYSTEM_WATCHDOG_TIMEOUT

RESEQUENCE_ERROR

SEQ_ON_TIMEOUT

System watch timeout

Rail fails to resequence

Rail fails to meeting sequence on dependency in predefined period

Rail is shut down due to that its master has fault

SEU is detected on the configuration SRAM

SEQ_OFF_TIMEOUT

SLAVE_FAULT

SINGLE_EVENT_UPSET

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8.4.3 Rail Sequence Configuration

Rail sequences can be configured via the Vout Config tab. First, select a rail in the top-right corner of the Fusion

Digital Power Designer software , and then edit the rail sequence as shown in Figure 13.

Figure 13. Rail Sequence Configuration Window (Rail Config)

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When a rail receives a turn-ON or turn-OFF command as defined in On/Off Config , it checks its dependency

conditions. When all dependencies are fulfilled, the rail then waits for a Turn ON Delay time or a Turn OFF Delay

time, and then asserts or de-asserts the EN pin.

The device fulfills a Rail Sequence On Dependency status when the rail is in Power Good status. The device

fulfills a Rail Sequence Off Dependency status when the rail is in Not Power Good status. The device fulfills a

GPI Sequence On Dependency status when the GPI pin is asserted. The device fulfills a GPI Sequence Off

Dependency status when the GPI pin is de-asserted. The device fulfills a GPO Sequence On Dependency status

when the logical sate of the GPO is TRUE. The device fulfills a GPO Sequence Off Dependency status when the

logic state of the GPO is FALSE.

After the EN pin of a rail is asserted, if the rail voltage does not rise above Power Good On threshold within the

Maximum Turn-ON time, a Time On Max fault occurs. Similarly, after the EN pin of a rail is de-asserted, if the rail

voltage does not fall below 12.5% nominal output voltage within Maximum Turn-OFF time, a Time Off Max

warning occurs.

Each rail can include a Fault Shutdown Slaves function. When a rail shuts down as a result of a fault, the

associated slave rails also shut down. The device continues to monitor delays and dependencies of the slave

rails during the shutdown process. Fault Shutdown Slaves cannot cascade. In other words, if a rail that is acting

as a slave shuts down, the associated slave rails does not shut down.

Each rail can set Sequencing On/Off Timeout periods. The timeout periods begin to increment when a rail

receives a turn-ON or a turn-OFF command as defined in On/Off Config . When the Sequencing On/Off Timeout

period elapsed, the rail executes one of 3 actions including:

•

Wait Indefinitely

Enable or Disable Rail

Re-sequence (Sequencing On only)

Re-sequence is a series of actions that shuts down a rail and the Fault Shutdown Slaves, and then re-enables

the rails according to sequence-on delay times and dependencies. The re-sequencing parameters can be

configured in the Other Config tab, as shown in Figure 14.

Figure 14. Re-Sequencing Options (Global Configuration ► Misc Config)

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A re-sequencing event can be repeated for one to approximately four times or unlimited times. The Time

Between Re-Sequences period begins to increment when all the relevant rails are given Not Power Good

statuses. When the time period elapses, a re-sequence event begins. When the Enable Re-Sequence Abort is

checked, the re-sequence event aborts if any relevant rail triggers a Max Turn Off warning. However, the Max

Turn Off warning does not stop an ongoing re-sequence event. If any rails at the re-sequence state are caused

by a GPI fault response, the device suspends the entire re-sequence event until the GPI fault is physically clear.

It is also configurable to ignore the POWER_GOOD_OFF and TOFF_MAX_WARN status of a rail when

performing re-sequencing if the corresponding bits are set.

After the Rail Sequence is configured, the GUI displays simulated sequence timing in the Vout Config tab. It

demonstrates the dependencies among the rails. An example is shown in Figure 15. The rails power-on and

power-off slew rates in Figure 15 are for demonstration purpose only.

Figure 15. Simulated Sequence Timing Window (Rail Config)

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8.4.4 Fault Responses Configuration

In the previous sections, various fault and warn notification thresholds have been configured to monitor voltage,

current, temperature, and turn-ON time and turn-OFF time. When a fault threshold is reached, a fault event

occurs. The device performs the following three actions in response of a fault event.

•

Asserts the PMBus ALERT line

Logs the fault event into nonvolatile memory (data flash), set status register bit

Executes fault responses defined by users

The Fault Responses can be configured under the Fault Responses and Limits tab. Figure 16 shows an example

configuration window.

Figure 16. Fault Responses Configuration Window (Rail Configure ► Fault Responses)

A programmable glitch filter can be enabled or disabled for each type of fault. When a fault remains present after

the glitch filter time expires, the device performs of the three selectable actions:

•

Log the fault and take no further action

Log the fault and shut down the rail immediately

Log the fault and shut down the rail with Turn Off Delay

After shutting down the rail, the device performs one of the three selectable actions:

•

Do not restart the rail until a new turn-on command is received

Restart the rail. If the restart is unsuccessful, retry up to a user-defined number of times (up to a maximum of

14) and then remain off until the fault is cleared

•

Restart the rail. If the restart is unsuccessful, retry for an unlimited number of times unless the rail is

commanded off by a signal defined in On/Off Config .

After the rail exhausts the restart attempts, Re-sequence can be initiated. (See also the Rail Sequence

Configuration section).

Voltage, current, and temperature monitoring are based on results from the 12-bit ADC(AMON) and 8 DMON. All

the voltage monitoring AMON and DMON channels are monitored every 400 µs for up to 32 channels. Current

monitoring ADC channels are monitored at 200 µs per channel. Temperature monitoring ADC channels are

monitored at approximately 4.17 ms per channel. The ADC results are compared with the programmed

thresholds. The time to respond to an individual event is determined by when the event occurs within the ADC

conversion cycle and the configured fault responses (glitch filters, time delays, and so forth).

GPI pins can also trigger faults if the GPI Fault Enable checkbox in Figure 12 is checked. The GPI Fault

Responses options are the same as the Fault Responses discussed earlier in this section, with one exception:

the GPI Fault Responses option does not support the retry action. An example configuration window is shown in

Figure 17.

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Figure 17. GPI Fault Responses Configuration Window (Rail Configure ► Fault Responses)

8.4.5 GPO Configuration

8.4.5.1 Command Controlled GPO

The UCD90320U device has 84 GPIO pins, all of which can be configured as Command Controlled GPOs.

These GPOs are controlled by PMBus commands (GPIO_SELECT and GPIO_CONFIG) and can be used to

control LEDs, enable switches, and so forth. Details on controlling a GPO using PMBus commands can be found

in the UCD90320U Sequencer and System Health Controller PMBus Command Reference. The configuration

window of Command Controlled GPO is under Pin Assignment tab. An example configuration window is shown

in Figure 18.

Figure 18. Command Controlled GPO Configuration Window (Hardware Configure ► Monitor and GPIO

Pins Assignment)

8.4.5.2 Logic GPO

UCD90320U also has 16 dedicated Logic GPO (LGPO) pins. The configuration window is under Pin Assignment

tab, as shown in Figure 19.

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Figure 19. Logic GPO Configuration Window (Hardware Configure ► Monitor and GPIO Pins

Assignment)

Each LGPO is controlled by an internal Boolean logic builder. Figure 20 shows the configuration interface of the

Boolean logic builder. As shown, each Boolean logic builder has a top-level logic gate, which can be configured

as AND, OR, or NOR gate with optional time delay. The inputs of the top-level logic gate are two AND paths.

Each AND path can select a variety of inputs including GPI states, LGPO states, rails' enable pin states,and rail

statuses, as shown in Figure 21. The selectable rail statuses are summarized in Table 3. In Table 3, _LATCH

type statuses stay asserted until cleared by a MFR PMBus command or by a specially configured GPI pin shown

in Figure 12. See the UCD90320U Sequencer and System Health Controller PMBus Command Reference for

complete definitions of rail-status types.

Figure 20. Boolean Logic Builder Interface

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Figure 21. AND Path Configuration

Table 3. Selectable Rail Statuses in Boolean Logic Builder

Rail-Status Types

POWER_GOOD

IOUT_OC_FAULT

TON_MAX_FAULT

MARGIN_EN

IOUT_OC_WARN

TOFF_MAX_WARN

MRG_LOW_nHIGH

VOUT_OV_FAULT

VOUT_OV_WARN

VOUT_UV_WARN

VOUT_UV_FAULT

VOUT_OV_FAULT_LATCH

VOUT_OV_WARN_LATCH

IOUT_UC_FAULT

TON_MAX_FAULT_LATCH

TOFF_MAX_WARN_LATCH

SEQ_ON_TIMEOUT

IOUT_OC_FAULT_LATCH

IOUT_OC_WARN_LATCH

IOUT_UC_FAULT_LATCH

TEMP_OT_FAULT

SEQ_OFF_TIMEOUT

SEQ_ON_TIMEOUT_LATCH

SEQ_OFF_TIMEOUT_LATCH

SYSTEM_WATCHDOG_TIMEOUT

TEMP_OT_WARN

TEMP_OT_FAULT_LATCH

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Table 3. Selectable Rail Statuses in Boolean Logic Builder (continued)

Rail-Status Types

TEMP_OT_WARN_LATCH

SINGLE_EVENT_UPSET

VOUT_UV_WARN_LATCH

VOUT_UV_FAULT_LATCH

SYSTEM_WATCHDOG_TIMEOUT_LATCH

The POWER_GOOD status used by GPO evaluation is based on actual monitoring result from AMON or DMON

pins. For a rail that does not have a voltage monitor pin, the POWER_GOOD status is used by sequencing

purpose only, and is not used by GPO evaluation. Therefore during GPO evaluation, a rail without an AMON or

DMON pin never reports POWER_GOOD status.

Each LGPO can be also configured as a simple state machine, as shown in Figure 16. In state machine mode,

the top-level logic gate is omitted and only one of the two AND paths is evaluated. The output of the state

machine is the result of the active AND path. The evaluation initially starts with AND Path #1. If the evaluation

result is TRUE, AND Path #1 remains active until its evaluation result becomes FALSE. When the output

associates with AND Path#1 becomes FALSE, AND Path #2 becomes active in the next evaluation cycle. AND

Path #2 remains active until its evaluation result becomes TRUE, then AND Path #1 becomes active in the next

evaluation cycle. An evaluation cycle is triggered when any input signal to the state machine changes state.

GPO1 to GPO8 outputs are internally synchronized to the same clock edge to enable them to change states

together. GPO9 to GPO16 outputs are internally synchronized to enable them to change states together. GPO1

through GPIO8 and GPO9 through GPIO16 outputs status are updated within an time window between

approximately 1 µs and 3 µs.

8.4.6 Margining Configuration

The UCD90320U device provides accurate closed-loop margining for up to 24 voltage rails. System reliability is

improved through four-corner testing during system verification. During four-corner testing, the system operates

at the minimum and maximum expected ambient temperature and with each power supply set to the minimum

and maximum output voltage, commonly referred to as margining. Margining can be controlled via the PMBus

interface using the OPERATION command or by configuring two GPI pins as margin-EN and margin-UP/DOWN

inputs. The MARGIN_CONFIG command in the UCD90320U Sequencer and System Health Controller PMBus

Command Reference user guide describes several margining options, including ignoring faults while margining

and using closed-loop margining to trim the rail output voltage.

The device provides 24 PWM output pins for closed-loop margining. Figure 22 shows the block diagram of

margining circuit. An external R-C network converts the PWM pulses into a DC margining voltage. The margining

voltage is connected to the power supply feedback node through a resistor. The feedback node voltage is thus

slightly pulled up or down by the margining voltage, causing the rail output voltage to change. The UCD90320U

device monitors the rail output voltage. The device adjusts the margining PWM duty cycle accordingly such that

the rail output voltage is regulated at the margin-high or margin-low voltages defined by the user. Effectively,

margin control loop of the UCD90320U device overwrites the DC set point of the margined power supply. The

margin control loop is extremely slow in order in order to not interfere with the power supply control loop.

V_REF

R3

V_IN

Power Supply

UCD90320U

MARxx

+

R4

V_OUT

R1

R2

C1

AMONxx

C2

V_FB

Figure 22. Block Diagram of Margining Circuit

Margining pins can be configured under the Pin Assignment tab, as shown in Figure 23. When not margining,

the margin pin can operate in one of three modes:

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•

tri-state

active trim

active duty cycle

Tri-state mode sets the margin pin to high-impedance. Active Trim mode performs a continuously trim the DC

output voltage. Active Duty Cycle mode provides a user-defined fixed PWM duty cycle as shown in Figure 23.

Figure 23. Margining Configuration Dropdown Window (Hardware Configuration ► Monitor and GPIO Pin

Assignment)

8.4.7 Pin Selected Rail States Configuration

UCD90320U allows users to use up to 3 GPI pins to control up to 8 rail states. Each rail state enables and

disables certain rails. This feature is useful to implement system low-power modes, such as those compliant with

the Advanced Configuration and Power Interface (ACPI) specification. The Pin Selected States function can be

configured under the Pin Selected States tab, as shown in Figure 24.

When a new state is presented on the GPI pins, and a rail is commanded to turn ON, it does so according to its

sequence-on dependencies and delays. If a rail is commanded to turn OFF by a new state, it can be configured

either immediately turn-OFF (Immediate OFF), or turn-OFF with its sequence-off dependencies and delays (Soft

Off). If a rail is commanded to remain in the same ON state or OFF state, no action occurs.

The Pin Selected Rail States function is implemented by modifying OPERATION command. Therefore, in order

to use this function to control rail states, the related rails must be configured to use OPERATION command in

On/Off Config (shown in Figure 6).

The Pin Selected States feature always uses the first 3 configured GPI pins to select system states. When

selecting a new system state, state changes on GPI pins must be completed within 1 µs, otherwise an

unintended system state may be selected. See the UCD90320U Sequencer and System Health Controller

PMBus Command Reference for complete configuration settings of Pin Selected States.

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Figure 24. Pin Selected States Configuration Window (Global Configuration ►Pin Selected Rail States)

8.4.8 Watchdog Timer

The UCD90320U device provides a watchdog timer (WDT). The WDT can be reset by toggling a watchdog input

(WDI) pin. If WDI is not toggled within a programmed period, the WDT times out. As a result, a watchdog output

(WDO) pin is asserted (generates a pulse) in order to provide a system-reset signal.

The WDI and WDO pins are GPIO pins and are only optional. The WDI can be replaced by

SYSTEM_WATCHDOG_RESET command sent over PMBus. The WDO can be manifested through the Boolean

Logic defined GPOs, or its function can be integrated into the system reset pin (RESET) configured in the system

reset function. See also the System Reset Function section.

The WDT timer is programmable from 0.001 s to 258.048 s. See also the UCD90320U Sequencer and System

Health Controller PMBus Command Reference user guide for details on configuring the watchdog timer.

After

a

timeout, the WDT can be restarted by toggling the WDI pin or by writing

a

SYSTEM_WATCHDOG_RESET command over PMBus. Figure 25 shows the watchdog timing waveforms.

<t_WDI

t_WDI

<t_WDI

WDI

WDO

Figure 25. Watchdog Timer Operation Timing Diagram

The WDT can be active immediately at power up or after an initial wait time. These are the programmable wait

times options that determine when the WDT operation begins.

•

100 ms

200 ms

400 ms

800 ms

1.6 s

3.2 s

6.4 s

12.8 s

25.6 s

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•

51.2 s

102.4 s

204.8 s

409.6 s

819.2 s

1638.4 s

8.4.9 System Reset Function

The system reset function can generate a programmable system reset signal through a GPIO pin. The system

reset signal is de-asserted when the selected rail voltages reach their respective Power Good On thresholds and

the selected GPIs are asserted, plus a programmable delay time. These are the available options for the system-

reset delay times.

•

0 ms

1 ms

2 ms

4 ms

8 ms

16 ms

32 ms

64 ms

128 ms

256 ms

512 ms

1.02 s

2.05 s

4.10s

8.19 s

16.38 s

32.8 s

The System Reset signal can be asserted immediately when any of the selected rail voltage falls below Power

Good Off threshold, or any selected GPI is de-asserted. Alternatively, the System Reset signal can be configured

as a pulse once Power Good On is achieved. An example in Figure 26 illustrates the difference of the two

configurations. The pulse width can be configured between 0.001 s to 32.256 s. See the UCD90320U Sequencer

and System Health Controller PMBus Command Reference for pulse width configuration details.

Power Good On

Power Good Off

POWER GOOD

Delay

SYSTEM RESET

configured without pulse

Pulse

SYSTEM RESET

configured with pulse

Figure 26. System Reset With and Without Pulse Setting (Active Low)

The System Reset signal can also integrate watchdog timer. An example is shown in Figure 27. In Figure 27, the

first delay on System Reset is for the initial reset release that would enable the CPU once all necessary voltage

rails are Power Good. The watchdog is configured with a Start Time and a Reset Time. If these times expire and

timeout occurs, it means that the CPU providing the WDI signal is not operating. The System Reset signal is then

toggled either using a Delay or GPI Tracking Release Delay to determine if the CPU recovers.

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Power Good On

POWER GOOD

Watchdog

Reset Time

Watchdog

Start Time

Watchdog

Start Time

WDI

Delay

Watchdog

Reset Time

SYSTEM RESET

Delay or

GPI Tracking Release Delay

Figure 27. System Reset With Watchdog

The default state of the system reset pin (RESET) is assert. When the system reset function is configured in-

circuit through PMBus commands during normal operation, the (RESET) pin is briefly asserted by default, even if

conditions for de-assert are present. This is because the firmware requires a finite time to examine the de-assert

conditions.

8.4.10 Cascading Multiple Devices

Multiple UCD90320U devices can work together and coordinate to determine fault notification.

Up to 4 GPI pins can be configured as Fault Pins . Each Fault Pin is connected to a Fault Bus . Each Fault Bus

is pulled up to 3.3 V by a 10-kΩ resistor. All the UCD90320U devices on the same Fault Bus are informed of the

same fault condition. An example of Fault Pin connections is shown in Figure 28.

When there is no fault on a Fault Bus , the Fault Pins are digital input pins and listen to the Fault Bus . When one

or multiple UCD90320U devices detect a rail fault, the corresponding Fault Pin is turned into active driven low

state, pulling down the Fault Bus and informing all other UCD90320U devices of the corresponding fault. This

way, a coordinated action can be taken across multiple devices. After the fault is cleared, the state of the Fault

Pin is turned back to an input pin.

Any of the 24 rails can be assigned to one or multiple Fault Pins . The configuration window is shown in

Figure 29.

UCD90320

Fault Fault

Pin 1 Pin 2

Fault

Pin 3

Fault

Pin 4

Fault Fault

Pin 1 Pin 2

Fault

Pin 3

Fault

Pin 4

3.3V

Fault Bus 4

Fault Bus 3

Fault Bus 2

Fault Bus 1

Fault

Pin 1

Fault

Pin 1

Fault

Pin 2

Fault Fault

Pin 3 Pin 4

Fault

Pin 2

Fault Fault

Pin 3 Pin 4

UCD90320

Figure 28. Example of Fault Pin Connections

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Figure 29. Example Fault Pins Configuration Window (Global Configuration ►Fault Pins Config)

These listed page-related faults have impact on the fault pin output. SYSTEM_WATCHDOG_TIMEOUT and

RESEQUENCE_ERROR are optional to have impact on the fault pins.

•

IOUT_OC_FAULT

IOUT_UC_FAULT

OT_FAULT

SEQ_OFF_TIMEOUT

SEQ_ON_TIMEOUT

TON_MAX_FAULT

VOUT_OV_FAULT

VOUT_UV_FAULT

A SYNC_CLK pin is used as a single-wire time synchronization method. A master chip constantly drives a 5-kHz

clock to the slave devices. This function offers a precise time base for multiple UCD90320U devices to respond

to the same fault event at the same time. The configuration window is shown in Figure 30. If the system uses

only one UCD90320U device, it is recommended to configure this pin as master clock output. The SYNC_CLK

output can be used as a time base for other purposes if needed.

Figure 30. SYNC_CLK Pin Configuration (Global Configuration ► Misc Config)

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8.4.11 Rail Monitoring

UCD90320U monitors up to 24 analog inputs including voltages, current, and temperature and eight digital inputs

for POWER_GOOD. Use either the Fusion GUI or a PMBus interface host to poll data from UCD90320U. The

Fusion GUI displays monitored rail voltage, current, and temperature information on the Monitor page, as shown

in Figure 31. Use polling to debug system-level issues.

Figure 31. Fusion Digital Power Designer software Monitor Page

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Table 4. Rail State Value Descriptions

RAIL STATE

VALUE

CONDITION FOR ENTERING RAIL STATE

When a turn-ON condition is not met, or when rail is shut down due to a fault, or when the rail is waiting for

the turn-ON period to resequence

IDLE

1

SEQ_ON

2

3

Waits for the dependency to be met to assert the enable signal

TON_DELAY to assert the enable signal

START_DELAY

Enable signal is asserted and rail is approaching the power good threshold. If the power good threshold is

set to 0 V, the rail stays at this state even if the monitored voltage is higher than 0 V.

RAMP_UP

4

When the monitoring voltage is higher than the power good threshold when the enable signal is asserted,

rails stay at this state even if the voltage is below the power good threshold and continues as long as there

is no fault action taken.

REGULATION

5

SEQ_OFF

6

7

Wait for the dependency to be met to de-assert the enable signal

TOFF_DELAY to de-assert the enable signal

STOP_DELAY

The enable signal is de-asserted and rail is ramping down. This state is available only if

TOFF_MAX_WARN_LIMIT is not set to unlimited, or if the turn-off sequence is triggered by a fault action.

The rail must not be under fault retry sequence to show this RAMP_DOWN state. Otherwise, the IDLE

state is present.

RAMP_DOWN

8

8.4.12 Status Monitoring

The UCD90320U has status registers for each rail. Faults and warnings are logged into EEPROM memory to

assist system troubleshooting. The status registers (Figure 32) and the fault log (Figure 33) can be accessed

from Fusion Digital Power Designer software as well as the PMBus interface. See the UCD90320U Sequencer

and System Health Controller PMBus Command Reference , and the PMBus Specification for detailed

descriptions of each status register and supported PMBus commands.

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Figure 32. Fusion Digital Power Designer software Rail Status Registers (Status ►Status Registers tab)

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Figure 33. Fusion Digital Power Designer software Logged Faults(Status ►Logged Faults tab)

8.4.13 Data and Error Logging to EEPROM Memory

The UCD90320U provides fault log, device reset counter, and peak readings for each rail. To reduce stress on

the EEPROM memory, a 30-second timer is started if a measured value exceeds the previously logged value.

Only the highest value from the 30-second interval is written from RAM to EEPROM.

Faults are stored in EEPROM memory and are accessible over PMBus. Each logged fault includes the following

information:

•

Rail number

Fault type

Fault time since previous device reset

Last measured rail voltage

The total number of device resets is also stored to EEPROM memory. The value can be reset using PMBus.

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The run time clock value is logged into EEPROM when a power down is detected. This allows UCD90320U to

preserve the run-time clock value through resets or power cycles.

It is also possible to update and calibrate the UCD90320U internal run-time clock via a PMBus host. For

example, a host processor with a real-time clock could periodically update the UCD90320U run-time clock to a

value that corresponds to the actual date and time. The host must translate the UCD90320U timer value back

into appropriate units, based on the usage scenario chosen. See the REAL_TIME_CLOCK command in the

UCD90320U Sequencer and System Health Controller PMBus Command Reference for more details.

8.4.14 Black Box First Fault Logging

The first fault in a system failure event is usually critical to diagnose the root cause. An innovative Black Box

Fault Logging feature is introduced in UCD90320U to accelerate the debugging process. When UCD90320U

detects the first fault, the device records and saves the status of each rail and I/O pin in a special area of the

EEPROM reserved for this function. The device does not save the subsequent faults and monitoring statuses

into the Black Box Fault Log, but instead records them into the standard fault log. The Black Box Fault Log must

be cleared in order to acknowledge the next fault.

Figure 34. Black Box Fault Logging Window (Status ►Blackbox Info tab)

8.4.15 PMBus Address Selection

Three digital input pins are allocated to decode the PMBus address. At power up, UCD90320U detects the logic

inputs of the three address pins to determine the configured PMBus address.

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Table 5. PMBus Address Configuration

PMBUS_ADDR2

PMBUS_ADDR1

PMBUS_ADDR0

PMBus Address Selected

L

H

L

17d

19d

0010001b

0010011b

0010111b

0110001b

0110011b

1110001b

1110011b

1110111b

L

H

L

23d

L

H

L

49d

H

51d

L

H

L

113d

115d

119d

H

8.4.16 ADC Reference

Using the V33A pin as ADC reference voltage by default provides a cost-effective solution. However, internal

voltage reference has a higher Total Unadjusted Error. Also, voltage variations on the V33A pin affect ADC

readings, such as when the device is powered down. In order to achieve better ADC accuracy, an external

voltage reference can be connected to the VREFA+ and VREFA- pins. Ensure that the external reference

voltage stays in regulation whenever V33D is above VBOR threshold. This limitation allows accurate ADC

readings in full V33D operating range.

The external reference voltage level must be configured into the Fusion Digital Power Designer software to give

correct ADC readings.

Figure 35. ADC Reference Configuration Window (Global Configuration ► Misc Config)

8.4.17 Device Reset

The UCD90320U device has an integrated power-on reset (POR) circuit which monitors the supply voltage. At

power up, the POR detects the V33D pin voltage rise. When the V33D voltage is greater than V_RESET, the device

comes out of reset.

The device can be forced into the reset state by an external circuit connected to the RESET

voltage on this pin for longer than t_RESETsets the device into reset state. The device comes out of reset within t_IRT

after RESET is released to logic-high level.

̅

pin. A logic-low

̅

Any time the device comes out of reset, it begins an initialization routine that lasts typically 40 ms. A data flash

checksum verification is performed at power up. If the checksum verification does not match, the device

configuration settings are cleared , the PMBALERT pin is asserted, and a flag is set in the status register. A fault-

log checksum verification in the EEPROM is also performed at power up. Each log entry includes the checksum

verification status. Only a corrupted log entry is discarded. During the initialization routine, all I/O pins are held at

high impedance state. At the end of initialization, the device begins normal operation as defined by the device

configuration.

8.4.18 Brownout

The UCD90320U device triggers brownout event when the V33D pin voltage drops below the brownout threshold

voltage, (V_BOR). During a brownout event, the device continues to write fault logs into the EEPROM that occurred

before the brownout event. As the supply voltage continues to drop, the device fully shuts down when the V33D

pin voltage is below the shutdown threshold voltage (V_SHDN). Any fault event that has not been written into the

EEPROM before the device shutdown is lost.

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In the scenario where several faults happen immediately before the brownout event, the device requires a

capacitance of 500 µs in order to write the first fault event into the EEPROM. The write function requires an

additional 4 ms to write the Black Box fault log into the EEPROM. Therefore, in order to preserve at least the first

fault log, user must provide enough local capacitance to maintain the V33D rail above VSHDN for 500 µs (or

4.5ms with the Black Box fault log). Longer holdup time allows more fault events to be written into the EEPROM

during brownout.

NOTE

The hold-up time is affected by V33D rail capacitance, the UCD90320U supply current

and external circuits that source current from the rail (such as LEDs, load current on I/O

pins, and other devices powered by the same rail).

V

V33D(min)

V

BOR

V_RESET

SHDN

Time

Figure 36. Reset and Brownout Thresholds

8.4.19 Internal Fault Management

The UCD90320U device verifies the firmware by using a checksum algorithm at each power up. If the checksum

does not match, the device resets. If the device continues to reset, the SYNC_CLK pin outputs repeated pulses

with an approximate 250-ms pulse width that can be observed externally.

The device performs a configuration checksum verification at power up. If the checksum does not match, the

device discards all the configuration data. The PMBALERT pin is asserted and a flag is set in the status register.

A fault-log checksum verification in EEPROM is also performed at power up. Each log entry has a checksum.

The device discards corrupted log entries.

If the internal firmware watchdog timer times out, the device resets. If the firmware program is corrupted, the

device returns to a known state. This return function is normal, so all of the I/O pins are held in high-impedance

while the device is in reset. The process confirms each parameter to ensure it falls within the acceptable range.

8.4.20 Single Event Upset

A single event upset (SEU) is a change-of-state caused by the free charge created by the ionization. The

UCD90320U device uses ULA particle emission mold compound to reduce the soft errors - FIT(failure in time)

number caused by the Alpha Particles. Moreover the following algorithm is adopted to detect SEU in the SRAM

containing the static user configuration configured from Fusion Digital Power Designer software. Both ULA mold

compound and SEU detection provide higher reliability for the applications.

The device scans configuration memory within approximately six seconds. When the device detects an SEU, the

device takes these actions.

•

A device attempts to correct this change-of-state by copying the data stored in the data flash. But if the

customer changes the settings on-the-fly and has not saved those changes into the data flash, the correction

may not be successful.

•

The device uses MFR_STATUS bit 14 to indicate an SEU event and a PMBUS_ALERT bit triggers when it

detects an SEU. The Fusion Digital Power Designer software has an option to prevent this event from

triggering a PMBUS_ALERT signal.

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•

The SEU bit in the MFR_STATUS does not clear automatically even after the SEU state corrects. The bit

clears only when the device is resets, when the device cycles power or when the host issues a clear fault

command. The device sets the status bit again if the SEU remains present after the host issues a clear fault

command.

•

The device logs an SEU event with the corrupted memory address. The application has the option to disable

the detail logging for an SEU event.

The device logs one SEU event per device reset or device reboot. The device does not re-log an SEU event

after the application issues clear fault command to clear existing fault log.

8.5 Device Configuration and Programming

UCD90320U devices include factory-installed sequencing and monitoring firmware. All I/O pins are pre-

configured ad high-impedance, with no sequencing or fault-response operation. Use the Fusion Digital Power

Designer software to configure the device on-line or off-line. Generate a configuration file after configuring the

device and import that configuration into other UCD90320U devices.

The Configuration Programming of UCD Devices section of the Documentation & Help Center offers

configuration and programming details and can be accessed under the Fusion Digital Power Designer software

Help menu. In general, UCD90320U supports two programming methods:

•

The PMBus command over PMBus and I²C method uses a PMBus host to program the device. The PMBus

host can be either a host microcontroller or Fusion Digital Power Designer software tools. Each PMBus

command sends a corresponding parameter(s) into the device. The new parameters are stored in its

associated memory (RAM) location. After all the parameters are sent into the device, the PMBus host issues

a special command, STORE_DEFAULT_ALL, which writes the RAM data into nonvolatile memory (data

flash). Fusion GUI normally uses this method to configure a device. If using Fusion Digital Power Designer

software tools for on-board programming, the Fusion Digital Power Designer software tools must have

ownership of the PMBus/I²C bus of the target board. This method may cause unexpected behaviors on GPIO

pins which can disable rails that provide power to device. It is not recommended for production programming.

•

The data flash image over PMBus and I²C method uses the Fusion Digital Power Designer software to

export a data flash image in Intel Hex, CSV or S-record format. The image file can be directly downloaded

into the device’s data flash via PMBus and I²C using Fusion Digital Power Designer software tools or a

dedicated device programmer. The new configuration takes effect after a device reset. It is recommended to

use for production programming since GPIO pins are under controlled state.

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Device Configuration and Programming (continued)

Figure 37. Fusion Digital Power Designer software Configuration Export Tool

The UCD90320U must be powered when it is being programmed via the PMBus or I²C interface. The PMBus

clock and data pins must be accessible and must be pulled high to the same V33D supply that powers the

device, with pullup resistors between 1 kΩ and 2 kΩ. Do not introduce additional bus capacitance less than 100

pF. When programming multiple UCD90320U devices over I²C, programming must be done individually.

Specifically, the clock and data lines must be multiplexed such that only one device is written by the programmer

at a time.

To update the device configuration in an operating system, the PMBus command method can be used to update

thresholds, timeout periods, and dependencies while the system is operating. Because the new configuration is

written into RAM, it takes effect immediately. However, pin-function-related configurations (change of rails,

change of GPI/GPO functions for example) may not work correctly until after a device reset. This delay may

indicate a problem in an operating system. For example, undesired states in the GPI, GPO, or RESET pin may

disable rails that provide power to the UCD90320U, and thus terminate the programming process before it is

completed. Using the data flash image method can overcomes this problem by directly writing new configuration

into the data flash. This method allows a full configuration while the system is operating. It is not required to reset

the device immediately but the UCD90320U continues to operate based on previous configuration until a device

reset.

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Device Configuration and Programming (continued)

The JTAG port is compatible with IEEE Standard 1149.1-1990, Test-Access Port and Boundary Scan

Architecture specification. The UCD90320U device supports boundary scan. The UCD90320U device supports

does not support configuration programming via JTAG.

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The UCD90320U device can be used to sequence, monitor up to 32 rails and margin up to 24 voltage rails. With

the cascading feature, up to four UCD90320U devices can manage up to 128 rails and record synchronized fault

responses. Typical applications include automatic test equipment, telecommunication and networking equipment,

servers and storage systems. Device configuration can be performed using the Fusion Digital Power Designer

software provided by TI. No coding skill is required.

9.2 Typical Application

Figure 38 shows a simplified system diagram. For simplification, this diagram shows only three rails, but each

UCD90320U device can manage up to 32 rails.

44

UCD90320U

www.ti.com.cn

ZHCSJE0 –SEPTEMBER 2018

Typical Application (continued)

12-V OUT

12-V

OUT

Temp IC

VREF

12-V

Temp

12-V

INA196

Cur

3.3-V

Supply

(Recommended)

12-V

OUT

GATE

V33A V33D

AMON

Hot Swap Control

EN

V_OUT

3.3 V

AMON

EN

V_OUT1.8 V

V_OUT0.8 V

Cur 12 V

Temp 12 V

Temp 0.8 V

3.3-V

OUT

VIN

VOUT

EN

DC-DC1

VFB

AMON

UCD90320U

DMON

POL‘s PWRGD

VIN

V_OUT

1.8 V

EN

VOUT

LDO1

EN

WDI from main

processor

GPIO

LGPO

GPIO

WDO

0.8 V

Temp IC

POWER_GOOD

VIN

VOUT

DC-DC2

VFB

WARN_OV_ 0.8 V

or WARN_OV_12 V

V_OUT

0.8 V

EN

SYSTEM_RESET

Other sequencer

done (cascade input)

I²C/PMBus

MARGIN

3.3-V

JTAG

GPIO

UCD90320U (Cascaded)

SYNC_CLK

SYNC-CLK

Figure 38. Simplified System Diagram

45

UCD90320U

ZHCSJE0 –SEPTEMBER 2018

www.ti.com.cn

Typical Application (continued)

9.2.1 Design Requirements

UCD90320U requires decoupling capacitors on the V33D, V33A, BPCAP, and (if applicable) VREFA+ pins. The

capacitance values for V33A, BPCAP and VREFA+ are specified in the Electrical Characteristics table. Consider

these capacitor design configurations as options.

•

Three 1-μF X7R ceramic capacitors in parallel with two 0.1-μF X7R ceramic capacitors for BPCAP decoupling

Two 1-μF X7R ceramic capacitors in parallel with four 0.1-μF X7R ceramic capacitors and two 0.01-μF X7R

ceramic capacitors for V33D decoupling

•

One 1-μF X7R ceramic capacitor in parallel with one 0.1-μF X7R ceramic capacitor and one 0.01-μF X7R

ceramic capacitor for V33A decoupling. A 1-Ω resistor can placed between V33D and V33A to decouple the

noise on V33D from V33A.

One 1-μF X7R ceramic capacitor in parallel with one 0.01-μF X7R ceramic capacitor for VREFA+ decoupling

(if used)

•

Place decoupling capacitors as close to the device as possible.

If an application does not use the RESET signal, the RESET pin must be tied to V33D, either by direct

connection to the nearest V33D pin (Pin F10), or by a R-C circuit as shown in Figure 39. The R-C circuit in

Figure 39 can be also used to delay reset at power up. If an application uses the RESET external pin, the

trace of the RESET signal must be kept as short as possible. Be sure to place any components connected to

the RESET signal as close to the device as possible.

•

TI recommends to maintain at least 200-Ω resistance between a low-impedance analog input and a AMON

pin. For example, when monitoring a rail voltage without resistor divider, it is recommended to place a 200-Ω

resistor at the AMON pin, as shown in Figure 40.

PMBus commands(project file , PMBus write script file) method is not recommended for the production

programming since GPIO pins may have unexpected behaviors which can disable rails that provide power to

device. Data flash hex file or data flash script file shall be used for production programming since GPIO pins

are under controlled state.

•

It is mandatory that the V33D power shall be stable and no device reset shall be fired during the device

programming. Data flash may be corrupted if failed to follow these rules.

V33D

Analog Input

10 kΩ

200 Ω

RESET

AMONx

1 nF

Figure 39. RESET Pin With R-C Network

9.2.2 Detailed Design Procedure

Figure 40. Example of Analog Inputs

The Fusion Digital Power Designer software can be used to design the device configuration online or offline (with

or without a UCD90320U device connected to the computer). In offline mode, the software prompts the user to

create or open a project file (.xml) at launch. In online mode, the software automatically detects the device via

the PMBus interface and extracts the configuration data from the device. A USB Interface Adapter EVM available

from TI is required to connect Fusion Digital Power Designer software to PMBus.

The general design steps include. Details of the steps are described in the Detailed Description section, and are

easily accessed within the Fusion Digital Power Designer software .

1. Rail setup

2. Rail monitoring configuration

3. GPI configuration

4. Rail sequence configuration

5. Fault response configuration

6. GPO configuration

46

UCD90320U

www.ti.com.cn

ZHCSJE0 –SEPTEMBER 2018

Typical Application (continued)

7. Margining configuration

8. Other configurations including but not limited to

–

Pin Selected Rail States

Watchdog Timer

System Reset

Sync Clock

Fault Pins

Click Write to Hardware to apply the changes. In online mode, the then click Store RAM to Flash to

permanently store the new configuration into the data flash of the device.

9.2.3 Application Curves

PMBus control pin de-assertion

Rail 1 EN with 5-ms turn-off delay

PMBus control pin assertion

Rail 1 EN with 5-ms turn-on delay

Rail 2 EN with 10-ms turn-off delay

Rail 2 EN with 10-ms turn-on delay

Rail 3 EN with 15-ms turn-off delay

Rail 3 EN with 15-ms turn-on delay

Time

Figure 42. Shut-Down Waveforms

Figure 41. Start-Up Waveforms

10 Power Supply Recommendations

Power the UCD90320U device from a 3.3-V power supply.

If internal reference is used, V33A acts as ADC reference and is assumed to be exactly 3.3 V. Any input voltage

deviation from 3.3 V introduces an error to ADC reference and to the ADC results. Therefore, the 3.3-V power

supply must be tightly regulated and allow only a very small voltage fluctuation (including voltage ripple and

voltage deviation caused by load transients).

If external reference is used, the 3.3-V power supply needs to meet only the minimum requirements specified in

the Recommended Operating Conditions table and the Electrical Characteristics table.

11 Layout

11.1 Layout Guidelines

•

Place the decoupling capacitors as close as possible to the device.

Connect the BPCAP decoupling capacitors as close as possible to pin D6.

MARGIN pins output PWM signals that have fast-edges. Route these signals away from sensitive analog

signals. It is a good practice to place resistor R4 and capacitor C1 (as shown in Figure 22) as close as

possible to the MARGIN pin, minimizing the propagation distance of the fast-edge PWM signals on the PCB.

•

Resistor R3 can be placed near the power supply feedback node to isolate the feedback node from noise

sources on the PCB. If resistor R4 and capacitor C1 cannot be located close to the MARGIN pin, add a

termination resistor in series with a value between 20-Ω and 33-Ω. Locate it near the MARGIN pin.

47

UCD90320U

ZHCSJE0 –SEPTEMBER 2018

www.ti.com.cn

11.2 Layout Example

The UCD90320U device is available in a 169-pin BGA package. If the design calls for the device to be mounted

on the top layer, decoupling capacitors can be placed on the bottom layer to allow room for top-layer trace

routing. The layout example below describes this strategy. Figure 43 shows bottom-layer component placement

from top-view. In addition to Figure 43, consider these important suggestions.

1. Use a uniform ground plane to connect DVSS, AVSS, and VREFA– pins.

2. Connect all four BPCAP pins to a common internal-layer copper area.

3. AVSS and VREFA– pins can be connected to a common internal-layer copper area.

Figure 43 shows a typical application with the UCD90320U device mounted on the top layer and the components

placed on the bottom layer.

V33D

R

C

GND

MO

N1

A1

MO

2

N1

1

JT

AG

_T

MO

N1

3

LG LG

GP MR MR

IO2 GN GN

V33A

VREFA+

DV

SS

PO PO

MR

GN

MR

PM

4

1

3

14 18

DV GP

PM

CK

GN

C

BU

SS IO8

BU

C

3

13

S

PM

S

_C

MR

GN

7

B

GP

_C

LK

MO MO

N4 N3

MO MO

N1 N1

DV

SS

NT

AL

IO1

Un

RE GP

RL

ER

3

use

V33D

SE IO1

T#

d-

NC

GP GP

8

7

T

5

DV

SS

IO1 IO1

SS

6

9

DV

Un

DV

SS

EN EN EN EN

SS

MR

SS

use

BPCAP

GN

d-

13 10

6

4

MR

10

GP

DV

EN EN EN EN GP

Un

C

GN

IO2

SS

3 IO9

use GP

14

9

5

LG LG

PO PO

MR

2

MR

0

EN EN EN

Un

GN

d- IO1

DV

SS

12

8

1

MR

23

GP

IO1

use

21

10 11

2

GP GP

UCD90320U

IO2 IO4

GN

8

d-

1

DV

SS

BPCAP

C

GND

V33D

V33A

BPCAP

VREFA+

BPCAP to be connected to decoupling capacitors through an internal-layer copper area

Figure 43. Layout Example

48

UCD90320U

www.ti.com.cn

ZHCSJE0 –SEPTEMBER 2018

12 器件和文档支持

12.1 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 商标

Fusion Digital Power, E2E are trademarks of Texas Instruments.

PMBus is a trademark of SMIF, Inc..

All other trademarks are the property of their respective owners.

12.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.5 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

49

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Feb-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

UCD90320UZWSR

UCD90320UZWST

NFBGA

ZWS

169

1000

250

330.0

24.4

12.35 12.35

2.3

16.0

24.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Feb-2019

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

UCD90320UZWSR

UCD90320UZWST

NFBGA

ZWS

169

1000

250

336.6

41.3

Pack Materials-Page 2

PACKAGE OUTLINE

ZWS0169A

NFBGA - 1.4 mm max height

SCALE 1.100

PLASTIC BALL GRID ARRAY

12.1

11.9

B

A

BALL A1 CORNER

12.1

11.9

(0.9)

0.45

1.4 MAX

C

SEATING PLANE

0.12 C

BALL TYP

TYP

0.35

9.6 TYP

SYMM

(1.2) TYP

N

M

L

K

J

H

G

F

SYMM

9.6

TYP

E

D

C

0.55

169X

0.45

0.15

0.05

C A B

C

B

A

0.8 TYP

1

2

3

4

5

6

7

8

9 10 11 12 13

0.8 TYP

BALL A1 CORNER

4221886/C 05/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

ZWS0169A

NFBGA - 1.4 mm max height

PLASTIC BALL GRID ARRAY

(0.8) TYP

169X ( 0.4)

1

2

5

6

8

9

12 13

3

4

7

10 11

A

B

C

(0.8) TYP

D

E

F

SYMM

G

H

J

K

L

M

N

SYMM

LAND PATTERN EXAMPLE

SCALE:8X

METAL UNDER

SOLDER MASK

0.05 MAX

0.05 MIN

(

0.4)

METAL

(

0.4)

SOLDER MASK

OPENING

SOLDER MASK

OPENING

SOLDER MASK

DEFINED

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4221886/C 05/2021

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For information, see Texas Instruments literature number SSZA002 (www.ti.com/lit/ssza002).

www.ti.com

EXAMPLE STENCIL DESIGN

ZWS0169A

NFBGA - 1.4 mm max height

PLASTIC BALL GRID ARRAY

(

0.4) TYP

(0.8) TYP

1

2

5

6

8

9

12 13

3

4

7

10 11

A

B

C

(0.8) TYP

D

E

F

SYMM

G

H

J

K

L

M

N

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.15 mm THICK STENCIL

SCALE:8X

4221886/C 05/2021

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

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型号：	UCD90320UZWSR
厂家：	TEXAS INSTRUMENTS
描述：	具有 SEU 检测功能的 32 轨 PMBus 电源序列发生器和系统管理器 \| ZWS \| 169 \| -40 to 85
文件：	总57页 (文件大小：2112K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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