UCD9080RHBTG4_技术文档

UCD9080

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SLVS692A–SEPTEMBER 2006–REVISED DECEMBER 2006

8-CHANNEL POWER SUPPLY SEQUENCER AND MONITOR

FEATURES

APPLICATIONS

•

Telecommunications Switches

Servers

Networking Equipment

Test Equipment

Any System Requiring Sequencing of Multiple

Voltage Rails

•

Single Supply Voltage: 3.3 V

Low Power Consumption

Sequences and Monitors up to 8 Voltage Rails

Rail Voltages Sampled Every 50 µs With

3.2-mV Resolution

•

Four Configurable Digital Outputs for

Power-On-Reset and Other Functions

DESCRIPTION

•

Configurable Rail Enable Output Polarity

The UCD9080 Power Supply Sequencer controls the

enable sequence of up to 8 independent voltage rails

and provides four general purpose digital outputs.

The device operates from a 3.3-V supply, provides

3.2-mV resolution of voltage rails, and requires no

external memory or clock. The UCD9080 monitors

the voltage rails independently at more than a 20

kHz rate and has a high degree of rail sequence and

rail error response configurability. The sequencing of

rails can be based on timed events, or timed events

in conjunction with other rails achieving regulation or

Flexible Rail Sequencing: Timeline (ms),

Parent Rail Regulation Window, Parent Rail

Achieving Defined Threshold

•

Under and Overvoltage Thresholds: Settable

Per-Rail

•

Regulation Expiration Time: Settable Per-Rail

Flexible Rail Shutdown: Parent Rail Shutdown

can Shutdown Child Rails, Independent Rail

Configuration

a

voltage threshold. In addition, each rail is

•

Per-Rail Alarm Conditions, with Timestamp:

Under and Overvoltage Glitch, Sustained

Under and/or Overvoltage, Rail Did Not Start

I²C Interface for Configuration and Monitoring

monitored for undervoltage and overvoltage glitches

and thresholds. Each rail the UCD9080 monitors can

be configured to shutdown a user-defined set of

other rails, and alarm conditions are monitored on a

per-rail basis.

•

Microsoft Windows™ GUI for Configuration

and Monitoring

Figure

1 shows the UCD9080 Power Supply

Sequencer in a typical application

MON [1:8]

V_OUT1

10 kW

EN[1:7]

Power

Supply

3.3 V

RST

XIN

EN

1

0.01 mF

3.3 V

V_OUT2

TEST

Power

Supply

2

UCD9080

100 kW

3.3 V

ROSC

SCL

VCC

VSS

3.3 V

1 mF

10 kW

SDA

EN8/

V_OUTX

ADDR1/ ADDR2/ ADDR3/ ADDR4/

GPO1 GPO2 GPO3 GPO4

To I²

Master Device

C

Power

Supply

X

3.3 V

EN

A1

A2

A3

A4

Slave I²

Address

C

Digital

Outputs

Figure 1. Typical Application Diagram

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TMS320 is a trademark of Texas Instruments.

Microsoft Windows is a trademark of Microsoft Corporation.

PRODUCT PREVIEW information concerns products in the

formative or design phase of development. Characteristic data and

other specifications are design goals. Texas Instruments reserves

the right to change or discontinue these products without notice.

UCD9080

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SLVS692A–SEPTEMBER 2006–REVISED DECEMBER 2006

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

(1)(2)

T_A

PACKAGED DEVICES

UCD9080RHBR

MSOP SYMBOL

–40°C to 85°C

RHB

UCD9080RHBT

(1) The package is available taped and reeled. Add the R suffix for reeled quantities. Add the T suffix for

taped quantities.

(2) For the most current package and ordering information, see the Package Option Addendum at the end

of this document, or see the TI Web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

VALUE

–0.3 to 4.1

–0.3 to V_CC+ 0.3

±2

UNIT

V

Voltage applied at VCC to VSS

Voltage applied to any pin⁽²⁾

Diode current at any device terminal

Storage temperature

V

mA

°C

T_stg

–40 to 85

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to V_SS

.

RECOMMENDED OPERATING CONDITIONS

MIN

3

NOM

3.3

MAX

3.6

85

UNIT

V

Supply voltage during operation

V_CC

Supply during configuration changes

3

3.3

T_A

Operating free-air temperature range

–40

°C

ELECTRICAL CHARACTERISTICS

These specifications are over recommended ranges of supply voltage and operating free-air temperature, unless otherwise

noted

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

SUPPLY CURRENT

Supply current into V_CCexcluding external V_CC= 3 V

current

300

350

7

I_S

I_C

µA

Supply current during configuration

2.5 V / 3.6 V

3

mA

STANDARD INPUTS (RST, TEST)

V_IL

V_IH

Low-level input voltage

High-level input voltage

V_CC= 3 V

V_SS

V_SS+0.6

V_CC

V

0.8×V_CC

SCHMITT TRIGGER INPUTS (SDA, SCL, ADDR1, ADDR2, ADDR3, ADDR4)

V_IT+

V_IT–

V_hys

Positive-going input threshold voltage

Negative-going input threshold voltage

V_CC= 3 V

1.5

0.9

0.5

1.9

1.3

1

V

Input voltage hysteresis, (V_IT+– V_IT–

)

RST, TEST, SDA, SCL, ADDR1, ADDR2,

ADDR3, ADDR4

I_lkg

High impedance leakage current

±50

nA

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ELECTRICAL CHARACTERISTICS (continued)

These specifications are over recommended ranges of supply voltage and operating free-air temperature, unless otherwise

noted

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

ANALOG INPUTS (MON1, MON2, MON3, MON4, MON5, MON6, MON7, MON8, ROSC)

V_CC

Analog supply voltage

V_SS= 0 V

1.8

2.35

0

3.6

V

V_CC(min)

V_CCminimum voltage when sampling

Internal voltage reference

2.5

V_(R<1..8>)

Analog input voltage

V

External voltage reference

(V_CC= 3.3 V used as reference)

0

V_CC

Only one terminal can be selected at a time

(MON1–MON8)

C_I⁽¹⁾

Input capacitance

27

pF

R_I⁽¹⁾

I_lkg

Input MUX ON resistance

0 V ≤ VAx ≤ VCC, V_CC= 3 V

2000

Ω

High-impedance leakage current

MON1–MON8

±50

nA

REF2_5V = 1 for 2.5 V

V_CC= 3 V

2.35

1.41

2.5

1.5

2.65

1.59

V

I

_(VREF+)≤ I_(VREF+)max

VREF+

Positive internal reference voltage output

REF2_5V = 0 for 1.5 V

_(VREF+)≤ I_(VREF+)max

V_CC= 3 V

I

REF2_5V = 0, I_(VREF+)≤ 1 mA

2.2

V_REF++ 0.15

±6.8

V

VCC minimum voltage, Positive built-in

reference active

V_CC(min)

REF2_5V = 1, I_(VREF+)≤ 0.5 mA

REF2_5V = 1, I_(VREF+)≤ 1 mA

Internal reference (2.5 V)

±12

±17.4

±6.8

V_(acc)

Accuracy of voltage sampling from rails

mV

External reference (3.3 V/V_CC

)

±0.2

±1.6

Temperature coefficient of built-in

reference

I_(VREF+)is a constant in the range of

0 mA ≤ I_(VREF+)≤ 1 mA, VCC = 3 V

(1)

±100 ppm/°C

T_REF+

DCO OPERATING PERIOD

t_(PERIOD)

V_CC= 3 V, T_A= 25°C, R_OSC= 100 kΩ

T_J= 25°C

227

100

204

185

nS

MISCELLANEOUS

T_retention

Retention of configuration parameters

Years

(2)(3)

POR, Brownout, Reset (see

)

t_d(BOR)

2000

µs

V

VCC_(start)

0.7×V(B_IT-)

V_{(B_IT–)}

dVCC/dt ≤ 3 V/s

1.71

180

V

Brownout

V_{hys(B_IT–)}

t_(reset)

70

2

130

mV

Pulse length needed at RST pin to accept

reset internally, V_CC= 3 V

µs

DIGITAL OUTPUTS (EN8/GPO1, GPO2, GPO3, GPO4, EN1, EN2, EN3, EN4, EN5, EN6, EN7, SDA)

I_OH(max) = –1.5 mA,⁽⁴⁾V_CC= 3 V

V_CC– 0.25

V_CC– 0.6

V_SS

V_CC

V_OH

High-level output voltage

V

I_OH(max) = –6 mA,⁽⁵⁾V_CC= 3 V

I_OH(max)= –1.5 mA,⁽⁴⁾V_CC= 3 V

I_OH(max) = –6 mA,⁽⁵⁾V_CC= 3 V

V_CC= 3 V

V_SS+ 0.25

V_SS+ 0.6

±50

V_OL

I_lkg

VOL Low-level output voltage

V

V_SS

High-impedance leakage current

nA

(1) Not production tested. Limits verified by design.

(2) The current consumption of the brown-out module is already included in the I_CCcurrent consumption data.

(3) During power up, device initialization starts following a period of t_d(BOR)after V_CC= V_{(B_IT–)}+ V_{hys(B_IT–)}

.

(4) The maximum total current, I_OHmax and I_OLmax, for all outputs combined, should not exceed ±12 mA to hold the maximum voltage drop

specified.

(5) The maximum total current, I_OHmax and I_OLmax, for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop

specified.

The UCD9080 is compatible with 3.3-V IO ports of microcontrollers, TMS320™ DSP Family as well as ASICs.

The UCD9080 is available in a plastic 32-pin QFN package (RHB).

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DIGITAL OUTPUTS (only one output is loaded at a time)

TYPICAL LOW-LEVEL OUTPUT CURRENT

TYPICAL HIGH-LEVEL OUTPUT CURRENT

vs

LOW-LEVEL OUTPUT VOLTAGE

HIGH-LEVEL OUTPUT VOLTAGE

50

0

V_CC= 3 V

P1.0

V_CC= 3 V

P1.0

T_A= 25^oC

T_A= 85^oC

-10

-20

-30

-40

-50

-60

40

30

20

10

0

T_A= 85^oC

T_A= 25^oC

0

0.5

V

1

1.5

2

2.5

3

3.5

0

0.5

1

1.5

2

2.5

3

3.5

− High-Level Output Voltage − V

V

− Low-Level Output Voltage − V

OH

OL

Figure 2.

Figure 3.

V

CC

V

hys(B_IT-)

V

(B_IT-)

V

CC(start)

1

Set signal for

POR circuitry

0

t

d(BOR)

Figure 4. POR/Brownout Reset (BOR) vs Supply Voltage

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V

CC

t

pw

2

V

= 3 V

3 V

CC

Typical Conditions

1.5

1

V

CC(min)

0.5

0

1

1000

0.001

1 ns

t

1 ns

- Pulse Width - mS

t

- Pulse Width - mS

pw

Figure 5. V_CC(min)Level With a Square Voltage Drop to Generate a POR/Brownout Signal

V

CC

3 V

t

pw

2

1.5

1

V

= 3 V

CC

Typical Conditions

V

CC(min)

0.5

0

t

= t

fall rise

t

1

1000

0.001

fall

rise

t

- Pulse Width - mS

pw

t

- Pulse Width - ms

pw

Figure 6. V_CC(min)Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal

I²C TIMING

The UCD9080 supports the same timing parameters as “Standard-Mode” I²C. See the timing diagram and timing

parameters below for more information.

SDA

t

f

t

LOW

SU;DAT

t

BUF

SP

HD;STA

r

t

r

SCL

t

HIGH

t

HD;STA

t

SU;STA

SU;STO

t

HD;DAT

S

Sr

P

S

Figure 7. Timing Diagram for I²C Interface

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TIMING PARAMETERS FOR I²C INTERFACE

PARAMETER

MIN

MAX

UNIT

t_of

Output fall time from V_OHto V_OL⁽¹⁾with a bus capacitance from 10 pF to 400 pF.

250⁽²⁾

ns

pF

kHz

µs

ns

µs

pF

V

C_I

Capacitance for each pin.

10

f_SCL

t_HD;STA

t_LOW

t_HIGH

t_SU;STA

t_SU;DAT

t_r

SCL Clock Frequency

10

4

100

Hold time (repeated) START condition. After this period, the first clock pulse is generated.

LOW period of the SCL clock

4.7

4

HIGH period of the SCL clock

Set-up time for repeated start condition

4.7

250

Data set-up time

Rise time of both SDA and SCL signals

1000

300

t_f

Fall time of both SDA and SCL signals

t_SU;STO

t_BUF

C_(b)

Set-up time for STOP condition

4

Bus free time between a STOP and START condition

Capacitive load for each bus line

4.7

400

V_nL

Noise margin at the LOW level for each connected device (including hysteresis)

Noise margin at the HIGH level for each connected device (including hysteresis)

0.1 VDD

0.2 VDD

V_nH

V

(1) See the Electrical Characteristics section of this data sheet.

(2) The maximum t_ffor the SDA and SCL bus lines (300 ns) is longer than the specified maximum t_offor the output stages (250 ns). This

allows series protection resistors (R_s) to be connected between the SDA/SCL pins and the SDA/SCL bus lines without exceeding the

maximum specified t_f.

RHB PACKAGE

(TOP VIEW)

32 31 30 29 28 27 26 25

24

23

22

21

20

19

VSS

NC

1

2

3

4

5

6

EN2

EN1

SCL

SDA

NC

XIN

NC

RST

MON1

MON2

MON3

MON5

MON4

NC

18

17

7

8

9

10 11 12 13 14 15 16

6

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TERMINAL FUNCTIONS

TERMINAL

I/O DESCRIPTION

NAME

NO.

VSS

1

Ground reference

2, 4,17,

20, 31

NC

Not connected internally. Connect to VSS.

XIN

3

Connect to VCC

RST

5

I

Reset input.

MON1

MON2

MON3

MON6

EN4

6

Analog input for voltage rail 1.

Analog input for voltage rail 2.

Analog input for voltage rail 3.

Analog input for voltage rail 6.

Voltage rail 4 enable (digital output).

Voltage rail 3 enable (digital output).

Voltage rail 5 enable (digital output).

Voltage rail 6 enable (digital output).

Voltage rail 7 enable (digital output).

Analog input for voltage rail 7.

Analog input for voltage rail 8.

Analog input for voltage rail 4.

Analog input for voltage rail 5.

7

I

8

I

9

I

10

11

12

13

14

15

16

18

19

21

22

23

24

O

I

EN3

EN5

EN6

EN7

MON7

MON8

MON4

MON5

SDA

I

I/O I²C data (bi-directional). Must pull-up to 3.3 V.

SCL

I

I²C clock. Must pull-up to 3.3 V.

Voltage rail 1 enable (digital output).

Voltage rail 2 enable (digital output).

EN1

O

EN2

EN8 /ADDR1/

GPO1

25

I/O Voltage rail 8 enable (digital output), I²C address select 1, general-purpose digital output 1

ADDR2/GPO2

ADDR3/GPO3

ADDR4/GPO4

TEST

26

27

28

29

30

I/O I²C address select 2, general-purpose digital output 2.

I/O I²C address select 3, general-purpose digital output 3.

I/O I²C address select 4, general-purpose digital output 4.

I

Connect to VSS

Supply voltage.

VCC

Internal oscillator frequency adjust. Must use 100 K pull-up to VCC for minimum drift and maximum

frequency when sampling voltage rails.

ROSC

32

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FUNCTIONAL BLOCK DIAGRAM

MON1

MON2

MON3

MON4

MON5

MON6

MON7

MON8

EN1

Oscillator

EN2

EN3

EN4

Analog

Inputs

Power

EN5

Enables

Sequencing

Engine

EN6

EN7

EN8/GPO1

General

Purpose

Outputs

GPO2

GPO3

GPO4

10-bit

SAR ADC

Config

Memory

Status

Registers

I2C

Engine

SCL SDA

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FUNCTIONAL DESCRIPTION

POWER SUPPLY SEQUENCING

The UCD9080 can be configured to sequence the power rails using the enable signals or the general-purpose

outputs in one of three ways:

The first way is to specify a delay time after a sequence event. A sequence event includes a device reset

(including power-on-reset), a RESET command, or a resequence action. The enable/GPO is asserted after the

sequence event plus specified delay.

The second way is to specify a delay time after another (parent) rail has achieved regulation (Vrail is within

specified under and overvoltage settings). The enable/GPO is asserted after the (parent) rail is in regulation plus

specified delay.

The third way is to specify a (parent) rail voltage. The enable/GPO is asserted after the (parent) rail voltage is

greater than or equal to the specified voltage.

Of course, a rail does not have to be sequenced. This could be used in the case of a backplane voltage which is

not under the control of the UCD9080, but is being monitored.

POWER SUPPLY ENABLES

The UCD9080 can sequence and enable/disable up to 8 power supplies through the ENx (EN1 to EN8) signals

on the device. These signals can be configured for either active high or active low, to support power supplies

that use either polarity.

The enable signals for up to 8 power supplies can be sequenced by the UCD9080 as described below. Note that

the EN8 is used for I²C address selection, General-purpose output as well as the enable signal for the voltage

rail 8. This means that this signal is unavailable until the UCD9080 has selected its I²C address. If the system

requires the GPO1 signal, then this signal is not available for power supply enable sequencing.

The enable signals on the UCD9080 are not intended to drive the gate of N-channel MOSFET. These pins are

LVCMOS level only, providing the capability of driving either logic high or low (3.3 V or 0 V).

Note that while the UCD9080 is not operating, the state of the enable signals is not defined. If these signals

need to be defaulted to the disabled state, according to the power supply definition, then they should be pulled

up or down accordingly on the board.

VOLTAGE REFERENCE

The UCD9080 has a voltage reference that is selectable via the I²C interface and parameter configuration

section. The voltage reference can either be an internally generated 2.5-V reference or an external 3.3-V

reference. If the external voltage reference is selected, then the 3.3-V reference is from the V_CCsupply to the

UCD9080.

Depending on the voltage reference that is being used, the accuracy of reading voltages is affected. The internal

reference is not as accurate as the external reference and affects the accuracy of the sampled voltages of the

monitored rails. See the Electrical Characteristics for information on voltage reading accuracy for use with each

of the references.

The section on Configuring the UCD9080 details how to select the internal or external voltage reference.

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FUNCTIONAL DESCRIPTION (continued)

VOLTAGE MONITORING

The UCD9080 can monitor 8 voltage rails through the MONx terminals of the device (MON1–MON8). The

UCD9080 samples these 8 input channels using either an internal 2.5-V reference or V_CC(3.3 V) as a voltage

reference for conversion of the voltage to digital values, which are accessible via the I²C interface for each rail.

When monitoring a voltage rail that has a nominal voltage larger than 2.5 V (internal reference) or 3.3 V

(external reference), a resistor divider network is typically used. The design must ensure that the source

impedance of that resistor network is not too high, as it causes the UCD9080 A/D converter to take longer to

perform the sample and hold conversion. This causes the frequency of the sampling of voltage rails to slow

below 20 KHz

Using a higher-valued resistor network lowers the overall power dissipation of the solution, which is desirable. In

order to keep the source impedance low, a buffer circuit is typically used. The UCD9080 analog inputs require

that a source impedance of less than 20 kΩ be used in order to maintain the high sampling rate of the voltages.

The UCD9080 allows each monitored rail to specify over voltage threshold, under voltage threshold as well as

out of regulation width, to account for glitches on the voltage rails. Each rail can be specified as a critical rail,

which marks it to have its alarm error log copied to persistent memory on the UCD9080 for later failure analysis.

Any voltage rail can also be marked to not be monitored, in which case all checks and alarm conditions are

disabled.

RAIL SHUTDOWN

Each rail that the UCD9080 supports can be shutdown for different reasons (sustained overvoltage or

undervoltage, rail did not start). The UCD9080 provides a configurable response to this type of scenario for each

rail that it is sequencing or monitoring,

The options for rail shutdown are as follows:

•

Ignore

Retry forever

Re-sequence (immediate)

Retry n times, then shutdown after user-specified delay

Shutdown after user-specified delay

If the system does not care if a monitored rail enters a sustained error condition, the UCD9080 can be

configured to ignore this type of error on a voltage rail. The UCD9080 ignores the errors and keep monitoring

the voltage of this rail. In this event, the UCD9080 logs this error event, but takes no action.

The UCD9080 also allows a rail to be configured to retry enabling the rail continuously. When the UCD9080

detects that the rail should be shutdown, the rail is disabled, then there is a fixed 5-ms delay and then the rail is

re-enabled. This process repeats continuously for this voltage rail.

The UCD9080 can also be configured to re-sequence the entire system immediately in response to the

sustained error condition. In this event, the UCD9080 disables all rails, then it performs a re-sequencing of all

configured rails and GPOs, as defined by the current sequencer configuration after a fixed 5-ms delay.

The UCD9080 can also be configured to retry up to n times in response to the sustained error condition. If the

error condition still exists after sampling this many times, then this voltage rail (and any other rails specified in

the dependency mask) are shutdown in the specified number of milliseconds.

The last option that the UCD9080 allows is a shutdown of the configured rail (and its dependent rails) when

entering the sustained error condition. A rail is shutdown after a user-specified delay.

Each rail that the UCD9080 is monitoring also has a flag that marks the selected rail to re-sequence the system

if it happens to be a dependency of another rail in the system that was shut down. For example, if rail 1 is

configured to re-sequence after shutdown (re-sequence flag set), and rail 2 has rail 1 in its dependency mask,

then if rail 2 is shutdown, the system will be re-sequenced.

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FUNCTIONAL DESCRIPTION (continued)

GENERAL-PURPOSE OUTPUTS

The UCD9080 can control up to 4 general-purpose digital outputs through the same sequencing mechanisms as

described below. These general-purpose outputs (referred to as GPO1–GPO4) can be used for digital signals

such as RESET signals or LEDs on a board. Note that these signals are multiplexed with other functions

(primarily I²C address selection) so be sure to consult the pin functions section to make sure that these are used

properly by the application. Also note that the GPO1 signal is multiplexed with EN8, so both of these cannot be

used at the same time.

BROWNOUT

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on

and power off.

I²C INTERFACE

The UCD9080 Power Supply Sequencer has an I²C slave interface for communication with an I²C master for

configuration and monitoring of the power supply sequencer and rails. The UCD9080 supports slave-mode

operation for a 100 kHz I²C bus. This interface is used for configuring the UCD9080 as well as monitoring each

of the voltage rails and reporting the voltage of each independently

I²C Address Selection

The UCD9080 supports 7-bit I²C addressing. The UCD9080 supports selection of an I²C address by sampling of

4 digital inputs to the device (ADDR1–ADDR4) and selecting an I²C address, based on the digital state of each

of these signals. When the UCD9080 is released from reset, these four signals are sampled. Based on the state

of these four signals, the I²C slave address is assigned to the UCD9080 as shown in Figure 8.

A7 = 1

A6 = 1

A5 = 0

A4 = ADDR4/GPO4

A3 =ADDR3/GPO3

A2 = ADDR2/GPO2

A1 = EN8/ADDR1/GPO1

Figure 8. I²C ADDRESS = 0x60–0x6F

External pull-up/pull-down resistors are required to configure the I²C address; the UCD9080 does not have

internal bias resistors. Note that the 7-bit I²C address refers to the address bits only, not the read/write (8^th) bit in

the first byte of the I²C protocol. The base I²C address is 0x60 and the I²C general call address (0x00) is not

supported.

After the initialization process of the UCD9080 is complete, these four digital signals can be used for

general-purpose outputs of the sequencer. They can be programmed and sequenced as described later in this

document.

I²C Transactions

The UCD9080 can be configured and monitored via I²C memory-mapped registers. Registers that are

configurable (can be written) via an I²C write operation are implemented using an I²C unidirectional data

transfer, from the master to slave, with a stop bit between transactions

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I²C Unidirectional Transfer

1

7

1

8

1

8

1

SLAVE

REGISTER

ADDRESS

S

A

DATA

P

R/W

A/A

ADDRESS

Data transferred

(n bytes +

acknowledge)

‘0’ (write)

From master to slave

A = acknowledge (SDA low)

= Not acknowledge (SDA high)

A

S = START condition

P = STOP condition

From slave to master

Figure 9. I²C Register Access With START/STOP

Registers that can be read are implemented using an I²C read operation, which uses the I²C combined format

that changes data direction during the transaction. This transaction uses an I²C restart during the direction

change.

I²C Combined Format

1

7

1

8

1

7

1

8

1

SLAVE

REGISTER

ADDRESS

SLAVE

S

A

Sr

A

DATA

P

R/W

A/A

ADDRESS

A

(n bytes + ack)

‘0’ (write)

‘1’ (read)

A = acknowledge (SDA low)

= Not acknowledge (SDA high)

From master to slave

From slave to master

A

S = START condition

P = STOP condition

Sr = Repeated START

Figure 10. I²C Register Access with RESTART

The UCD9080 also supports a feature that auto-increments the register address pointer for increased efficiency

when accessing sequential blocks of data. It is not necessary to issue separate I²C transactions..

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CONFIGURING AND MONITORING THE UCD9080

The UCD9080 supports both configuration and monitoring using its I²C slave interface.

For monitoring of the sequencer, there is an I²C memory map that is used that allows an I²C host to perform

memory mapped reads (and in some cases writes) that reports status information from the UCD9080. For

instance, all rails can report their voltage through the I²C memory map. For information on which parameters are

available via the I²C memory map, see the Monitoring the UCD9080 section.

To change configuration parameters of the sequencer, a different mechanism is used. The entire set of

configuration parameters must be written at one time to the device as one large transaction over the I²C

interface. This ensures that the configuration of the device is consistent at any given time. The process for

configuring the UCD9080 is described below in the section titled Configuring the UCD9080 section.

MONITORING THE UCD9080

Register Map

The UCD9080 allows all monitoring of the system through the I²C interface on the device. The following is the

memory map of the supported registers in the system. The detail of each of these registers is given in the next

section as well.

Note that the UCD9080 supports functionality to automatically increment the I²C register address value when a

register is being accessed, to more efficiently access blocks of like registers. The table below also shows the

amount that the register address is incremented for each register access.

REGISTER NAME

RAIL1H

ADDRESS

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x28

0x29

0x2E

0x2F

ACCESS

ADJUSTMENT AFTER ACCESS

+1 (0x01)

+1 (0x02)

+1 (0x03)

+1 (0x04)

+1 (0x05)

+1 (0x06)

+1 (0x07)

+1 (0x08)

+1 (0x09)

+1 (0x0A)

+1 (0x0B)

+1 (0x0C)

+1 (0x0D)

+1 (0x0E)

+1 (0x0F)

–15 (0x00)

+1 (0x21)

+1 (0x22)

+1 (0x23)

+1 (0x24)

+1 (0x25)

–5 (0x20)

r

RAIL1L

RAIL2H

r

RAIL2L

r

RAIL3H

r

RAIL3L

r

RAIL4H

r

RAIL4L

r

RAIL5H

r

RAIL5L

r

RAIL6H

r

RAIL6L

r

RAIL7H

r

RAIL7L

r

RAIL8H

r

RAIL8L

r

ERROR1

ERROR2

ERROR3

ERROR4

ERROR5

ERROR6

STATUS

RAILSTATUS1

RAILSTATUS2

FLASHLOCK

RESTART

r

+0 (0x26)

+1 (0x29)

–1 (0x28)

r

rw

w

0 (0x2E)

+0 (0x2F)

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REGISTER NAME

WADDR1

ADDRESS

ACCESS

ADJUSTMENT AFTER ACCESS

0x30

0x31

0x32

0x33

rw

w

+1 (0x31)

– 1 (0x30)

+1 (0x33)

–1 (0x32)

WADDR2

WDATA1

WDATA2

w

Register Descriptions

The following are the detailed descriptions of each of the UCD9080 I²C registers.

The register bit conventions below are used. Each register is shown with a key indicating the accessibility of

each bit, and the initial condition after device initialization.

KEY

rw

ACCESS

Read/Write

r

Read only

r0

Read as 0

r1

Read as 1

w

Write only

w0

w1

rc

Write as 0

Write as 1

Read clears bit after read

Read sets bit after read

Condition after initialization

rs

–0, –1

RAIL

Each of the 8 voltage rails that the UCD9080 supports has two registers that contains the rolling average voltage

for the associated rail as measured by the device. This average voltage is maintained in real-time by the

UCD9080 and is calculated as the output of a 4-TAP FIR filter. There are two registers for each voltage rail. One

holds the least-significant 8 bits of the voltage and the other the most-significant 2 bits of the voltage. This is

shown below.

Register Name

RAIL1H

RAIL1L

RAIL2H

RAIL2L

RAIL3H

RAIL3L

RAIL4H

RAIL4L

RAIL5H

RAIL5L

RAIL6H

RAIL6L

RAIL7H

RAIL7L

RAIL8H

RAIL8L

Address

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

Register Contents

RAIL1 Voltage, bits 9:8

RAIL1 Voltage, bits 7:0

RAIL2 Voltage, bits 9:8

RAIL2 Voltage, bits 7:0

RAIL3 Voltage, bits 9:8

RAIL3 Voltage, bits 7:0

RAIL4 Voltage, bits 9:8

RAIL4 Voltage, bits 7:0

RAIL5 Voltage, bits 9:8

RAIL5 Voltage, bits 7:0

RAIL6 Voltage, bits 9:8

RAIL6 Voltage, bits 7:0

RAIL7 Voltage, bits 9:8

RAIL7 Voltage, bits 7:0

RAIL8 Voltage, bits 9:8

RAIL8 Voltage, bits 7:0

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A rail voltage is read with a 16b access. The auto-increment feature of the UCD9080 allows multiple rail voltages

to be read with a single access.

A rail voltage is provided as a 10-bit binary value in an un-signed format, as shown below.

15

14

13

12

11

10

9

8

7

6

5

4

3

r

2

r

1

r

0

r

RAILVn

r0

r

The following formulas can be used to calculate the actual measured rail voltage:

Without external voltage divider:

RAILVn

1024

V

+

V

REF

RAILn

(1)

(2)

With external voltage divider:

R

) R

PULLUP

PULLDOWN

RAILVn

V

+

V

RAILn

REF

1024

R

PULLDOWN

ERROR

Error conditions are logged by the UCD9080 and are accessible to the user via reading the ERROR registers.

This is a 6-byte register and it has the following format:

0x20

0x21

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Data (dependent on error code)

Error Code

RAIL

RAIL: Rail #(n) - 1, RAIL = 0 through 7

Error Code

Meaning

Data

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Null Alarm

0x0000

Supply did not start Average voltage on Rail

Sustained overvoltage detected Average voltage on Rail

Sustained undervoltage detected Average voltage on Rail

Overvoltage glitch detected

Undervoltage glitch detected

Reserved

Glitch voltage level on Rail

Reserved

0x22

0x23

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Hour

Minutes

0x24

0x25

6

5

4

3

4

3

Seconds

Milliseconds

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Error conditions encountered during processing will post error logs to this register. There are some exceptions.

This register is internally managed as a FIFO where errors are posted to the FIFO as they occur and read out of

the FIFO via I²C accesses. The FIFO is only posted to by the UCD9080 if it has room to write, due to the

unknown latency of the system reading out of this FIFO. Note that there is no real-time impact to the processing

of the UCD9080 if this FIFO is full and cannot be posted to.

The device time is reset by the following conditions:

1. Device Reset

2. A restart command issued to the device by the host via I2C.

3. A Resequence action is taken.

STATUS

The STATUS is an 8-bit read-only register. This register provides real-time status information about the state of

the UCD9080. The following bits are defined.

7

6

5

4

3

2

1

0

NVERRLOG

IIC Error RAIL error

rc-0 rc-0

Register Status

rc-0

r

r-0

Register

Status Meaning

IIC Error Meaning

0

1

No I2C PHY layer error

I2C PHY layer error

00

01

10

11

No Error

Invalid Address

Read Access Error

Write Access Error

RAIL Error Meaning

0

1

No RAIL error pending

RAIL error pending

NVERRLOG Meaning

0

1

ERROR points to run-time logs

ERROR points to non-volatile logs

Reading of the STATUS register clears the register except for the NVERRLOG bit, which is maintained until the

device is reset. Descriptions of the different errors are below.

The IICERROR bit is set when an I²C access fails. This is most often a case where the user has accessed an

invalid address, or performed an illegal number of operations for a given register (for example, reading 3 bytes

of a 2-byte register). In the event of an I²C error when the I2CERROR is set, bits 1:0 of the STATUS register

further define the nature of the error as shown above.

The RAIL error bit is set to alert the user to an issue with one of the voltage rails. When this bit is set, the user is

advised to then query the RAILSTATUS register to further ascertain which RAIL input(s) have an issue. The

user may then query the ERROR<n> registers to get further information about the nature of the error condition.

The NVERRLOG bit is set to 1 upon device initialization if the UCD9080 was restarted from a shutdown

sequence of a RAIL declared as critical. The purpose of this bit is to allow the user to differentiate between

stored error logs and real time error logs, and is useful for a post-mortem debug. Note that this bit is the only bit

that is not automatically cleared by a read of the STATUS register; this bit is only cleared at device reset if the

non-volatile error logs are empty.

When the IICERROR bit is set, the Register Status bits provide further information about the type of I²C error

that has been detected, as indicated above.

RAILSTATUS

The RAILSTATUS1 and RAILSTATUS2 registers are two 8-bit read-only registers that provide a bit-mask that

represent the error status of the rails as indicated in the diagram below.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RAIL8 RAIL7 RAIL6 RAIL5 RAIL4 RAIL3 RAIL2 RAIL1

rc-0 rc-0 rc-0 rc-0 rc-0 rc-0 rc-0 rc-0

rc-0

RAILn Meaning

0 => No Alarm Pending for RAILn

1 => Alarm Pending for RAILn

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Bits 15:8 are RAILSTATUS1 and bits 7:0 are RAILSTATUS2. These are read as two 8-bit registers or as a

single 16-bit register.

If a bit is set in these registers, then the ERROR register is read to further ascertain the specific error. Bits in the

RAILSTATUS1 and RAILSTATUS2 registers are cleared when read.

FLASHLOCK

The FLASHLOCK I²C command is used to lock and unlock the configuration memory on the UCD9080 when

updating the configuration. The section below (Configuring the UCD9080) details this process.

The format for the FLASHLOCK command is as follows:

7

6

5

4

3

2

1

0

FLASHLOCK

rw-0 rw-0

rw-0

FLASHLOCK

0x00

0x01

0x02

FLASH is locked (default)

FLASH is being updated

Unlock flash (before configuration)

RESTART

The RESTART register provides the capability for the I²C host to force a re-initialization and restart of the

UCD9080. This is an 8-bit register and when written to with a 0, the UCD9080 is restarted and the rails are

resequenced. This is useful for restarting the sequencer after the configuration for the system is changed. In

order to properly restart the system, this register must be written to a 0.

Note that in order to respond to this I²C request properly, there is a 50-µs delay before the system is restarted,

so that the I²C ACK can take place.

WADDR and WDATA

In order to update the configuration on the UCD9080, two primitive commands are provided in the I²C memory

map, WADDR and WDATA (see NOTE). Each of these registers are 8-bits and there are two of each (e.g.,

WADDR1, WADDR2 and WDATA1, WDATA2) to be able to write addresses and data of up to 16b.

NOTE:

In addition to updating the WADDR and WDATA commands, users can use the

FLASHLOCK command to perform configuration updates to the UCD9080.

The format for the WADDR command is as follows:

15

8

7

0

Address

rw-0x00

WADDR2

(0x31)

WADDR1

(0x30)

To set the address in the UCD9080 to write, write the LSB of the address to the WADDR1 register and the MSB

of the address to the WADDR2 register. For example, to write the address 0x1234 to the device, set WADDR1 =

0x34 and WADDR2 = 0x12. Note that since these addresses support the auto-increment feature, the user can

perform a single 16b write to WADDR1 to write the entire address.

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The format for the WDATA command is as follows:

15

8

7

0

Data

w

WDATA2

(0x33)

WDATA1

(0x32)

To set the data in the UCD9080 to write, write the LSB of the data to the WDATA1 register and the MSB of the

data to the WDATA2 register. For example, to write the data 0xBEEF to the device, set WDATA1 = 0xEF and

WDATA2 = 0xBE. Note that since these addresses support the auto-increment feature, the user can perform a

single 16b write to WDATA1 to write the entire data.

These two commands are used for updating the UCD9080 configuration, explained in the next section

(Configuring the UCD9080).

RESETTING THE FLASH ERROR LOGS

The UCD9080 can be configured to log critical errors on a voltage rail to flash. This can be configured via the

SaveRailLog register, described later in this document. If the SaveRailLog bit is set for a voltage rail and an

error is detected on that voltage rail, then the error logs for that rail are written to flash memory instead of

operating memory. This mechanism permits the error logs to be read after the device has been reset and

operating memory cleared.

Once the system is in the state where the error logs are pointing to flash, the NVERRLOG bit in the STATUS

register is set to a 1 when it is read from the I²C interface. To clear this condition, take the following steps:

•

Write FLASHLOCK register to a value of 0x02

Write WADDR register to a value of 0x1000

Write WDATA register to a value of 0xBADC

Write WADDR register to a value of 0x107E

Write WDATA register to a value of 0xBADC

Write FLASHLOCK register to a value of 0x00

Write RESTART register to a value of 0x00

This points the error logs back to operating memory, and restarts the sequencer.

CONFIGURING THE UCD9080

The UCD9080 has many different configurable parameters such as sequencing policies, shutdown policies and

dependency masks. The UCD9080 can configure all of its parameters via the I²C interface while the device is

operational; however sequencing, shutdown and rail monitoring is not performed during this time.

The configuration information can not be read from the device.

NOTE:

During runtime, if the UCD9080 is configured, there is a delay in voltage monitoring

while the new configuration parameters are applied to the device.

To configure the UCD9080, a large block of configuration information is sent to the device via the I²C interface.

This block is 512 bytes and contains all the configuration information that the device requires for any function of

the UCD9080.

This 512 byte block of configuration information is sent to the device in multiple segments. The segment size

can range from 2 to 32 bytes at one time, and must be a multiple of 2 bytes. That is, a master can send 256

2-byte segments or 32 16-byte segments, and so on. All the segments must be sent back-to-back in the proper

sequence and this operation must be completed by sending the last segment so that the last byte of the 512

byte block is written. If this is not done, the UCD9080 is in an unknown state and does not function as designed.

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CONFIGURING THE UCD9080 (continued)

The process for sending the configuration information to the UCD9080 is as shown in Figure 11:

I2CWrite:

FLASHSTATE=

UNLOCK(0x02)

I2CWrite:

WDATA=

Data(16b)

I2CWrite:

WDATA=

Data(16b)

I2CWrite:

FLASHSTATE=

LOCK(0x00)

I2CWrite:

WADDR=

0xE000

I2CWrite:

WDATA=

0xBADC

I2CWrite:

WADDR=

0xE000

. . .

Up to 16 times (32bytes)

- OR -

Repeat as necessary with WADDR updated

to write 512 bytes

Figure 11. Configuration Information

As shown in Figure 11, the process for updating the configuration of the UCD9080 is as follows:

1. Unlock flash memory by sending the UNLOCK command (FLASHSTATE = 0x02)

2. Write the address of the configuration section of memory (WADDR = 0xE000)

3. Write the constant 0xBADC to update memory (WDATA = 0xBADC)

4. Write the address of the configuration section of memory again (WADDR = 0xE000)

5. Write the data (WDATA = <varies>). Repeat steps 4 and 5 as necessary, depending on the data segment

size used to write 512 bytes. Increment the address as necessary.

6. Lock flash memory after the last byte of the last segment is written (FLASHSTATE = 0x00)

At the conclusion of this process, the configuration of the UCD9080 is updated with the configuration changes,

as represented by the values from the data segments. The sequencer can then be reset using the RESTART

I²C command, and then the application restarts.

The memory map for the 512 byte configuration segment is defined in the section below.

Configuration Parameters Memory Map

Table 1 shows the 512 byte configuration parameters memory map. Each of the fields at each of the addresses

in this memory map either represents a configuration parameter for the UCD9080 that is changed by changing

its value, or it must be hard-coded to the given literal value.

Table 1. Configuration Parameters Memory Map

ADDRESS

0xE000

0xE008

0xE010

0xE018

0xE020

0xE028

0xE030

0xE038

0xE040

0xE048

0xE050

0xE058

0xE060

0xE068

0xE070

0xE078

0xE080

0xE088

+0

+1

+2

+3

+4

+5

+6

+7

0x00

0xFF

0x00

0x7F

0x00

0x0E

0x00

0xC0

0x00

0xF0

0x50

0x20

0x00

0x01

0x00

0x02

0x00

0xA8

0x00

0xC0

0x00

0xDC

0x00

0x02

0x00

0xBA

SequenceEventParameters

SequenceEventParameters (continued)

SequenceEventLink

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CONFIGURING THE UCD9080 (continued)

Table 1. Configuration Parameters Memory Map (continued)

ADDRESS

0xE090

0xE098

0xE0A0

0xE0A8

0xE0B0

0xE0B8

0xE0C0

0xE0C8

0xE0D0

0xE0D8

0xE0E0

0xE0E8

0xE0F0

0xE0F8

0xE100

0xE108

0xE110

0xE118

0xE120

0xE128

0xE130

0xE138

0xE140

0xE148

0xE150

0xE158

0xE160

0xE168

0xE170

0xE178

0xE180

0xE188

0xE190

0xE198

0xE1A0

0xE1A8

0xE1B0

0xE1B8

0xE1C0

0xE1C8

0xE1D0

0xE1D8

0xE1E0

0xE1E8

0xE1F0

0xE1F8

+0

+1

+2

+3

+4

+5

+6

+7

SequenceEventLink (continued)

SequenceEventData

0xFF

0x00

0x7F

0x00

0xFF

0x00

0x7F

0x00

0xFF

0x00

0x7F

0x00

0xFF

0x00

0x7F

0x00

DependencyMasks

UnderVoltageThreholds

OverVoltageThresholds

RampTime

OutOfRegulationWidth

UnsequenceTime

EnablePolarity

SaveRailLog

0xF9

0x05

0x00

0xC0

0x00

0x94

0x32

0x00

0x02

0x00

ReferenceSelect

LastUnusedSeq

0x00

0x10

0x00

0x07

0x00

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CONFIGURATION PARAMETERS DETAIL

The following section details the format and meaning of the configuration parameters from the configuration

parameters memory map (Table 1).

SequenceEventParameters

The SequenceEventParameters field in the configuration parameters specifies the rail identification, monitoring

status and sequencing options for each rail. The address map for all these registers is as follows:

ADDRESS

0xE080

0xE081

0xE082

0xE083

0xE084

0xEx85

0xE086

0xE087

0xE088

0xE089

0xE08A

0xE08B

SIZE

1

DEFAULT VALUE

0x50

DESCRIPTION

Rail 1 identification, monitoring status and sequencing options.

Rail 2 identification, monitoring status and sequencing options.

Rail 3 identification, monitoring status and sequencing options.

Rail 4 identification, monitoring status and sequencing options.

Rail 5 identification, monitoring status and sequencing options.

Rail 6 identification, monitoring status and sequencing options.

Rail 7 identification, monitoring status and sequencing options.

Rail 8 identification, monitoring status and sequencing options.

GPO1 identification, sequencing options.

1

0x51

1

0x52

1

0x53

1

0x54

1

0x55

1

0x56

1

0x07

1

0x08

1

0x49

GPO2 identification, sequencing options.

1

0x4A

GPO3 identification, sequencing options.

1

0x4B

GPO4 identification, sequencing options.

The format of each register is as follows:

7

6

5

0

4

3

2

1

0

ENABLE

RAIL

MON

RAIL/GPO

Rail #(n) - 1, RAIL = 0 through 7

GPO

GPO # (n) + 7, GPO = 8, 9, 0xA, 0xB

MON

Meaning

0

1

Do not monitor rail status (for event sequencing of GPOs)

Monitor rail status

ENABLE

Meaning

00

01

10

11

Sequence is disabled

Sequence is triggered after delay after sequence event

Sequence is triggered after parent rails achieves voltage level

Sequence is triggered after delay after parent rail achieves voltage regulation

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SequenceEventLink

The SequenceEventLink field in the configuration parameters specifies each rail’s parent rail as well as whether

or not to sequence it after shutdown. The address map for all these registers is as follows:

ADDRESS

0xE08C

0xE08D

0xE08E

0xE08F

0xE090

0xE091

0xE092

0xE093

0xE094

0xE095

0xE096

0xE097

SIZE

1

DEFAULT VALUE

0x01

DESCRIPTION

Rail 1 parent identifier and resequence indicator.

Rail 2 parent identifier and resequence indicator.

Rail 3 parent identifier and resequence indicator.

Rail 4 parent identifier and resequence indicator.

Rail 5 parent identifier and resequence indicator.

Rail 6 parent identifier and resequence indicator.

Rail 7 parent identifier and resequence indicator.

Rail 8 parent identifier and resequence indicator.

GPO1 parent rail identifier and resequence indicator.

GPO2 parent rail identifier and resequence indicator.

GPO3 parent rail identifier and resequence indicator.

GPO4 parent rail identifier and resequence indicator.

1

0x00

1

0x01

1

0x04

1

0x01

1

0x04

1

0x05

1

0x06

1

0x00

1

0x00

1

0x00

1

0x00

The format of each register is as follows:

7

6

5

4

3

2

1

0

RESEQ

0

PARENTRAIL

RESEQ

Meaning

0

1

Do not resequence after shutdown

Resequence after shutdown

PARENTRAIL

Meaning

0x0000

0x0001

0x0010

0x0011

0x0100

0x0101

0x0110

0x0111

Sequence is dependent on RAIL1 achieving the specified event

Sequence is dependent on RAIL2 achieving the specified event

Sequence is dependent on RAIL3 achieving the specified event

Sequence is dependent on RAIL4 achieving the specified event

Sequence is dependent on RAIL5 achieving the specified event

Sequence is dependent on RAIL6 achieving the specified event

Sequence is dependent on RAIL7 achieving the specified event

Sequence is dependent on RAIL8 achieving the specified event

22

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SLVS692A–SEPTEMBER 2006–REVISED DECEMBER 2006

SequenceEventData

The SequenceEventData field in the configuration parameters specifies each rail’s sequencing parameters. The

address map for all these registers is as follows:

ADDRESS

0xE098

0xE09A

0xE09C

0xE09E

0xE0A0

0xE0A2

0xE0A4

0xE0A6

0xE0A8

0xE0AA

0xE0AC

0xE0AE

SIZE

2

DEFAULT VALUE

0xE005

DESCRIPTION

Rail 1 sequencing and shutdown parameters.

2

0xA005

Rail 2 sequencing and shutdown parameters.

Rail 3 sequencing and shutdown parameters.

Rail 4 sequencing and shutdown parameters.

Rail 5 sequencing and shutdown parameters.

Rail 6 sequencing and shutdown parameters.

Rail 7 sequencing and shutdown parameters.

Rail 8 sequencing and shutdown parameters.

GPO1 sequencing and shutdown parameters.

GPO2 sequencing and shutdown parameters.

GPO3 sequencing and shutdown parameters.

GPO4 sequencing and shutdown parameters.

2

0xE032

2

0xE033

2

0xE033

2

0xE035

2

0xE035

2

0x0000

2

0x0000

2

0x0000

2

0x0000

2

0x0000

The format for each register is as follows:

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

SEQPARAM

RAILDATA

SEQPARAM

Meaning

RAILDATA Meaning

ENABLE in SequenceEventParameters register

000

001

010

Ignore

Resequence after shutdown

Retry 4 times

01

10

11

Delay (ms)

Volatge (V)

Delay (mS)

011

100

101

110

Retry 3 times

Retry 2 times

Retry 1 time

Shutdown

111

Retry forever

23

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DependencyMasks

The DependencyMasks field in the configuration parameters specifies each rail’s dependency masks which are

used for rail shutdown. This mask represents the set of other rails and GPOs that should be shutdown when this

rail shuts down. Note that since only rails are monitored, this table only has entries for rails that are shutdown. In

the dependency mask itself, there are bits that allow for the shutting down of a GPO.

The address map for all these registers is as follows:

ADDRESS

0xE100

0xE102

0xE104

0xE106

0xE108

0xE10A

0xE10C

0xE10E

SIZE

DEFAULT VALUE

0x007F

DESCRIPTION

2

Dependency mask for rail 1.

Dependency mask for rail 2.

Dependency mask for rail 3.

Dependency mask for rail 4.

Dependency mask for rail 5.

Dependency mask for rail 6.

Dependency mask for rail 7.

Dependency mask for rail 8.

0x0001

0x0002

0x0004

0x0008

0x0010

0x0020

0x0040

The format for each register is as follows:

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

GPO4 GPO3 GPO2 GPO1 RAIL8 RAIL7 RAIL6 RAIL5 RAIL4 RAIL3 RAIL2 RAIL1

RAILn or GPOn

Meaning

0

1

Shutdown of this rail will not shutdown RAILn or GPOn

Shutdown of this rail will shutdown RAILn or GPOn

UnderVoltageThresholds

The UnderVoltageThresholds field in the configuration parameters specifies each rail’s undervoltage thresholds

that are used when monitoring this rail. The address map for all these registers is as follows:

ADDRESS

0xE110

0xE112

0xE114

0xE116

0xE118

0xE11A

0xE11C

0xE11E

SIZE

DEFAULT VALUE

0x0000

DESCRIPTION

2

Undervoltage threshold for rail 8.

Undervoltage threshold for rail 7.

Undervoltage threshold for rail 6.

Undervoltage threshold for rail 5.

Undervoltage threshold for rail 4.

Undervoltage threshold for rail 3.

Undervoltage threshold for rail 2.

Undervoltage threshold for rail 1.

0x0000

The format for each register is as follows:

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Vraw

The voltage conversion is dependent upon the configured voltage reference and the pull-up and pull-down

resistors used on the board for each rail. The voltage reference is selected as either 2.5 V (internal) or 3.3 V

(external via V_CC). The formula to convert the desired Rail's UnderVoltageThreshold to Vraw follows:

Without external rail voltage divider:

1024 x V

RAILUV

Vraw =

V

REF

(3)

24

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With external rail voltage divider:

1024 x V

R

PULLDOWN

RAILUV

Vraw =

x

V

R

+ R

PULLUP

REF

PULLDOWN

(4)

OverVoltageThresholds

The OverVoltageThreholds field in the configuration parameters specifies each rail’s over voltage thresholds that

are used when monitoring this rail. The address map for all these registers is as follows:

ADDRESS

0xE120

0xE122

0xE124

0xE126

0xE128

0xE12A

0xE12C

0xE12E

SIZE

DEFAULT VALUE

0x0400

DESCRIPTION

2

Overvoltage threshold for rail 8.

Overvoltage threshold for rail 7.

Overvoltage threshold for rail 6.

Overvoltage threshold for rail 5.

Overvoltage threshold for rail 4.

Overvoltage threshold for rail 3.

Overvoltage threshold for rail 2.

Overvoltage threshold for rail 1.

0x0400

The format for each register is as follows:

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Vraw

The voltage conversion is dependent upon the configured voltage reference and the pull-up and pull-down

resistors used on the board for each rail. The voltage reference is selected as either 2.5 V (internal) or 3.3 V

(external via V_CC). The formula to convert the desired Rail's OverVoltageThreshold to Vraw follows:

Without external rail voltage divider:

1024 x V

RAILOV

Vraw =

V

REF

(5)

With external voltage divider:

1024 x V

Vraw =

R

PULLDOWN

RAILOV

x

V

R

+ R

PULLUP

REF

PULLDOWN

(6)

RampTime

The RampTime field in the configuration parameters specifies the maximum amount of time for each rail to

achieve regulation. The address map for all these registers is as follows:

ADDRESS

0xE130

0xE132

0xE134

0xE136

0xE138

0xE13A

0xE13C

0xE13E

SIZE

DEFAULT VALUE

0x0FA0

DESCRIPTION

Maximum voltage ramp time for rail 1.

2

0x0FA0

Maximum voltage ramp time for rail 2.

Maximum voltage ramp time for rail 3.

Maximum voltage ramp time for rail 4.

Maximum voltage ramp time for rail 5.

Maximum voltage ramp time for rail 6.

Maximum voltage ramp time for rail 7.

Maximum voltage ramp time for rail 8.

0x0FA0

The 16b value of this register is the number of milliseconds that this rail has to achieve regulation without an

error.

25

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OutOfRegulation Width

The OutOfRegulationWidth field in the configuration parameters specifies the maximum amount of time that the

rail is allowed to be out of regulation before an error is declared (glitch width). The address map for all these

registers is as follows:

ADDRESS

0xE140

0xE142

0xE144

0xE146

0xE148

0xE14A

0xE14C

0xE14E

SIZE

DEFAULT VALUE

0x0010

DESCRIPTION

2

The out of regulation width permissible without flagging error for Rail 1.

The out of regulation width permissible without flagging error for Rail 2.

The out of regulation width permissible without flagging error for Rail 3.

The out of regulation width permissible without flagging error for Rail 4.

The out of regulation width permissible without flagging error for Rail 5.

The out of regulation width permissible without flagging error for Rail 6.

The out of regulation width permissible without flagging error for Rail 7.

The out of regulation width permissible without flagging error for Rail 8.

0x0010

The contents of this register are as follows:

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

OORW

OORW= RAILn Out of regulation glitch width (in units of 1/10 mS)

UnsequenceTime

The UnsequenceTime field in the configuration parameters specifies the amount of time that each rail should

delay before unsequencing. The address map for all these registers is as follows:

ADDRESS

0xE150

0xE152

0xE154

0xE156

0xE158

0xE15A

0xE15C

0xE15E

0xE160

0xE162

0xE164

0xE166

SIZE

2

DEFAULT VALUE

0xC0FF

0xC1FF

0xC2FF

0xC3FF

0xC4FF

0xC5FF

0xC6FF

0xC7FF

0xC000

DESCRIPTION

Unsequence delay for Rail 1.

Unsequence delay for Rail 2.

Unsequence delay for Rail 3.

Unsequence delay for Rail 4.

Unsequence delay for Rail 5.

Unsequence delay for Rail 6.

Unsequence delay for Rail 7.

Unsequence delay for Rail 8.

Unsequence delay for GPO1.

Unsequence delay for GPO2.

Unsequence delay for GPO3.

Unsequence delay for GPO4.

2

0xC000

2

0xC000

2

0xC000

The contents of this register are as follows:

15

1

14

1

13

0

12

11

10

9

8

7

6

5

4

3

2

1

0

USTIME

USTIME = RAILn UnsequenceTime (in units of mS).

26

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SLVS692A–SEPTEMBER 2006–REVISED DECEMBER 2006

EnablePolarity

The EnablePolarity field in the configuration parameters specifies whether each power supply enable or GPO is

to be configured active high or active low.. The address map for all these registers is as follows:

ADDRESS

0xE168

0xE16A

0xE16C

0xE16E

0xE170

0xE172

0xE174

0xE176

0xE178

0xE17A

0xE17C

0xE17E

SIZE

2

DEFAULT VALUE

0x2004

DESCRIPTION

Polarity for Rail 1 enable.

Polarity for Rail 2 enable.

Polarity for Rail 3 enable.

Polarity for Rail 4 enable.

Polarity for Rail 5 enable.

Polarity for Rail 6 enable.

Polarity for Rail 7 enable.

Polarity for Rail 8 enable.

Polarity for GPO1.

2

0x2008

2

0x1804

2

0x1802

2

0x1808

2

0x1810

2

0x1820

2

0x2010

2

0x1800

2

0x2020

Polarity for GPO2.

2

0x2040

Polarity for GPO3.

2

0x2080

Polarity for GPO4.

The contents of this register are as follows:

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

DEFAULT VALUES as specified above

POL

Meaning

POL

Railn enable or GPOn is active low

Railn enable or GPOn is active high

0

1

SaveRailLog

The SaveRailLog field in the configuration parameters specifies whether each rail is marked to write the error log

to flash upon rail failure. If the rail is marked this way, then a shutdown of this rail is logged info non-volatile

memory.

The contents of this register are as follows:

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

RAIL8 RAIL7 RAIL6 RAIL5 RAIL4 RAIL3 RAIL2 RAIL1

0

Meaning

RAILn

Shutdown of this rail will not log this event.

Shutdown of this rail will log this event.

0

1

The default value for this register is 0x0000.

27

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ReferenceSelect

The ReferenceSelect field in the configuration parameters specifies which voltage reference is used on the

UCD9080. The selected reference can be internal (2.5-V), or external via V_CC(3.3 V). The contents of this

register are as follows:

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

SELREF

0x8F2

Meaning

SELREF

000

External Reference Selected (VCC).

Internal Reference Selected (2.5 V).

001

The default value for this register is 0x8F2, which selects the external reference.

LastUnusedSeq

The LastUnusedSeq field in the configuration parameters specifies the amount of time for the last rail to be

shutdown without creating an error.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

LUTIME

LUTIME = Maximum value USTIME + 255 (in units of mS)

The default value for this register is 0x08FF.

28

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APPLICATION INFORMATION

Typical Application Diagram

Figure 12 illustrates a typical power supply sequencing configuration. Power Supply 1 and Power Supply X

require active low enables while Power Supply 2 and Power Supply 3 require active high enables. V_OUT1and

V_OUT3exceed the selected A/D reference voltage so their outputs are divided before being sampled by the

MON1 and MON3 inputs. V_OUT2and V_OUTXare within the selected A/D reference voltage so their outputs can be

sampled directly by the MON2 and MON7 inputs. Figure 12 illustrates the use of the GPO digital output pins to

provide status and power on reset to other system devices.

Figure 12. Typical Power Supply Sequencing Application

29

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PACKAGE OPTION ADDENDUM

www.ti.com

13-Nov-2006

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

QFN

Drawing

UCD9080RHBR

UCD9080RHBT

PREVIEW

RHB

32

3000

250

TBD

Call TI

RHB

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process

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Use of such information may require a license from a third party under the patents or other intellectual property

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Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products

Applications

Audio

Amplifiers

amplifier.ti.com

www.ti.com/audio

Data Converters

dataconverter.ti.com

Automotive

www.ti.com/automotive

DSP

dsp.ti.com

Broadband

Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

Low Power Wireless www.ti.com/lpw

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265


型号：	UCD9080RHBTG4
厂家：	TEXAS INSTRUMENTS
描述：	电源序列发生器和监控器 \| RHB \| 32 \| -40 to 85 监控电源管理电路电源电路
文件：	总32页 (文件大小：559K)
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