UCD9090ARGZR [TI]
支持 ACPI 的 10 轨电源序列发生器和监视器 | RGZ | 48 | -40 to 125;型号: | UCD9090ARGZR |
厂家: | TEXAS INSTRUMENTS |
描述: | 支持 ACPI 的 10 轨电源序列发生器和监视器 | RGZ | 48 | -40 to 125 监视器 |
文件: | 总62页 (文件大小:3624K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
UCD9090A
ZHCSFJ6B –AUGUST 2016 –REVISED MARCH 2022
UCD9090A 支持ACPI 的10 轨电源排序器和监视器
器件信息(1)
1 特性
封装尺寸(标称值)
器件型号
UCD9090A
封装
• 可对10 个电压轨进行监控和排序
VQFN (48)
7.00mm × 7.00mm
– 所有电压轨每400 μs 进行一次采样
– 具有2.5V、0.5% 内部VREF 的12 位ADC
– 排序基于时间、电压轨及引脚相关性
– 每个监控器具有4 个可编程欠压和过压阈值
• 每个监控器可提供非易失性误差及峰值日志记录
(多达26 个故障详细条目)
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
12-V OUT
TEMP12V
V
V
OUT 12 V
IN 12 V
3.3-V Supply
INA196
Temp IC
V33A
V33D
GPIO
• 可对10 个电压轨进行闭环裕度调节
V
OUT 12 V
VMON
– 裕度输出可调节轨电压以匹配用户定义的裕度阈
值
VOUT
3.3 V
UCD9090A
VIN
VOUT
DC-DC1
VFB
• 可编程的看门狗计时器和系统复位
• 灵活的数字I/O 配置
• 响应并监视由GPI 触发的故障
• 可轻松级联多个电源序列发生器并加以协调以提供
故障响应
• 引脚选择电压轨状态
• 可级联多个器件
• 多相位PWM 时钟发生器
EN
GPIO
VMON
VMON
VMON
VMON
VMON
VMON
VMON
V
V
V
OUT 3.3 V
OUT 1.8 V
OUT 0.8 V
V
IN 0.8
Temp 0.8 V
IN 12 V
V
VIN
Temp 12 V
VOUT
1.8 V
GPIO
WDI from main
processor
EN
VOUT
LDO1
GPIO
WDO
GPIO
GPIO
– 时钟频率为15.259 kHz 至
125 MHz
– 能够为同步开关模式电源配置独立的时钟输出
• JTAG 和I2C/SMBus/PMBus™ 接口
POWER_GOOD
TEMP0.8V
WARN_OV_ 0.8 V
or
WARN_OV_12 V
GPIO
VOUT
0.8 V
VIN
VOUT
DC-DC2
VFB
SYSTEM_RESET
GPIO
GPIO
V
IN 0.8V
GPIO
PWM
EN
Other
sequencer done
(cascade input)
2 应用
INA196
I2C/PMBus
• 工业和自动测试设备(ATE)
• 电信及网络设备
• 服务器和存储系统
VMARG
2 MHz
JTAG
Closed loop margining
• 任何需要对多个电源轨进行排序和监控的系统
3 说明
典型应用
UCD9090A 是一款 10 轨 PMBus/I2C 可寻址电源排序
器和监视器。该器件集成一个 12 位 ADC,用于监测
多达 10 个电源电压输入。通用输入输出 (GPIO) 引脚
共有 23 个,分别可用于电源使能、上电复位信号、外
部中断、级联或者其他系统功能。其中的 10 个 GPIO
引脚提供 PWM 功能。利用这些引脚,UCD9090A 支
持裕度调节以及通用PWM 功能。
运用引脚选择电压轨状态功能可实现特定的电源状态。
该功能允许使用多达 3 个 GPI 来启用和停用任意电压
轨。对于执行系统低功耗模式及用于硬件器件的高级配
置和电源接口 (ACPI) 规范而言,这一点是很有用处
的。
TI Fusion Digital Power™ 设计师软件供器件配置之
用。这款基于PC 的图形用户界面 (GUI) 提供了一种用
于配置、存储和监视所有系统操作参数的直观界面。
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLVSDD7
UCD9090A
ZHCSFJ6B –AUGUST 2016 –REVISED MARCH 2022
www.ti.com.cn
Table of Contents
7.5 Programming............................................................ 43
8 Application and Implementation..................................47
8.1 Application Information............................................. 47
8.2 Typical Application.................................................... 47
9 Power Supply Recommendations................................50
10 Layout...........................................................................51
10.1 Layout Guidelines................................................... 51
10.2 Layout Example...................................................... 51
11 Device and Documentation Support..........................53
11.1 Documentation Support.......................................... 53
11.2 接收文档更新通知................................................... 53
11.3 支持资源..................................................................53
11.4 Trademarks............................................................. 53
11.5 Electrostatic Discharge Caution..............................53
11.6 术语表..................................................................... 53
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................7
6.6 I2C/Smbus/PMBus Timing Requirements...................8
6.7 Typical Characteristics................................................9
7 Detailed Description......................................................10
7.1 Overview...................................................................10
7.2 Functional Block Diagram.........................................10
7.3 Feature Description...................................................11
7.4 Device Functional Modes..........................................16
Information.................................................................... 53
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
Changes from Revision A (February 2019) to Revision B (December 2020)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 更新了图3-1 ...................................................................................................................................................... 1
• Corrected typographical error in test condition for Internal oscillator frequency specification............................7
• Updated Voltage Monitoring section to specify 11 monitoring pins. .................................................................18
• Updated 图7-7 ................................................................................................................................................ 18
Changes from Revision * (September 2016) to Revision A (February 2019)
Page
• Updated 节7.5 section, Step 1.........................................................................................................................43
• Added Steps 6, 7, 8, and 9 to 节8.2.1 section................................................................................................. 48
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5 Pin Configuration and Functions
备注
The number of configurable rails is a maximum of ten. The maximum number of configurable GPIs is
eight. The maximum number of configurable boolean logic GPOs is ten.
33 34 35
27
28
29
30
31
MON1
MON2
MON3
MON4
MON5
MON6
MON7
MON8
MON9
MON10
MON11
TCK/GPIO18
TDO/GPIO19
TDI/GPIO20
TMS/GPIO21
TRST
1
2
38
39
40
41
42
45
46
48
37
GPIO1
GPIO2
4
5
6
GPIO3
GPIO4
7
UCD9090A
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
18
21
24
25
26
PMBUS_CLK
8
9
PMBUS_DATA
PMBUS_ALERT
19
20
44
43
PMBUS_CNTRL
PMBUS_ADDR0
PMBUS_ADDR1
FPWM1/GPIO5
FPWM2/GPIO6
FPWM3/GPIO7
FPWM4/GPIO8
FPWM5/GPIO9
FPWM6/GPIO10
FPWM7/GPIO11
FPWM8/GPIO12
10
11
12
13
14
15
16
17
PWM1/GPI1
PWM2/GPI2
22
23
RESET
3
32 36 47
图5-1. Pin Assignments for the VQFN Package
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MON1
1
36
35
34
33
32
31
30
29
28
27
26
25
AVSS1
2
MON2
RESET
BPCap
3
V33A
4
GPIO1
V33D
5
GPIO2
DVSS
6
GPIO3
TRST
7
GPIO4
TMS/GPIO21
TDI/GPIO20
TDO/GPIO19
TCK/GPIO18
PMBus_CLK
PMBus_DATA
8
9
10
11
12
FPWM1/GPIO5
FPWM2/GPIO6
FPWM3/GPIO7
GPIO17
GPIO16
图5-2. RGZ Package, 48-Pin VQFN With Exposed Thermal Pad (Top View)
表5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
ANALOG MONITOR INPUTS
MON1
MON2
MON3
MON4
MON5
MON6
MON7
MON8
MON9
MON10
MON11
GPIO
1
I
I
I
I
I
I
I
I
I
I
I
Analog input (0 V–2.5 V)
Analog input (0 V–2.5 V)
Analog input (0 V–2.5 V)
Analog input (0 V–2.5 V)
Analog input (0 V–2.5 V)
Analog input (0 V–2.5 V)
Analog input (0 V–2.5 V)
Analog input (0 V–2.5 V)
Analog input (0 V–2.5 V)
Analog input (0 V–2.5 V)
Analog input (0.2 V–2.5 V)
2
38
39
40
41
42
45
46
48
37
GPIO1
GPIO2
GPIO3
GPIO4
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
4
5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose discrete I/O
General-purpose discrete I/O
General-purpose discrete I/O
General-purpose discrete I/O
General-purpose discrete I/O
General-purpose discrete I/O
General-purpose discrete I/O
General-purpose discrete I/O
General-purpose discrete I/O
6
7
18
21
24
25
26
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NAME
表5-1. Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NO.
PWM OUTPUTS
FPWM1/GPIO5
FPWM2/GPIO6
FPWM3/GPIO7
FPWM4/GPIO8
FPWM5/GPIO9
FPWM6/GPIO10
FPWM7/GPIO11
FPWM8/GPIO12
PWM1/GPI1
10
11
12
13
14
15
16
17
22
23
I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
I/PWM
I/PWM
PWM (0.93 Hz to 7.8125 MHz) or GPI
PWM (0.93 Hz to 7.8125 MHz) or GPI
PWM2/GPI2
PMBus COMM INTERFACE
PMBus_CLK
PMBus_DATA
PMBus_ALERT
PMBus_CNTRL
PMBus_ADDR0
PMBus_ADDR1
JTAG
8
I/O
PMBus clock (must have pullup to 3.3 V)
9
I/O
PMBus data (must have pullup to 3.3 V)
19
20
44
43
O
I
PMBus alert, active-low, open-drain output (must have pullup to 3.3 V)
PMBus control
I
PMBus analog address input. Least-significant address bit
PMBus analog address input. Most-significant address bit
I
TCK/GPIO18
TDO/GPIO19
TDI/GPIO20
TMS/GPIO21
TRST
27
28
29
30
31
I/O
I/O
I/O
I/O
I
Test clock or GPIO
Test data out or GPIO
Test data in (tie to Vdd with 10-kΩresistor) or GPIO
Test mode select (tie to Vdd with 10-kΩresistor) or GPIO
Test reset –tie to ground with 10-kΩresistor
INPUT POWER AND GROUNDS
RESET
V33A
3
Active-low device reset input. Hold low for at least 2 μs to reset the device.
Analog 3.3-V supply. Refer to the 节10.1 section.
Digital core 3.3-V supply. Refer to the 节10.1 section.
1.8-V bypass capacitor. Refer to the 节10.1 section.
Analog ground
—
—
—
—
—
—
—
—
34
33
35
36
47
32
V33D
BPCap
AVSS1
AVSS2
DVSS
Analog ground
Digital ground
Thermal pad
QFN ground pad. Tie to ground plane.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–55
MAX
3.8
UNIT
V
Voltage applied at V33D to DVSS
Voltage applied at V33A to AVSS
Voltage applied to any other pin (2)
3.8
V
V33A + 0.3
150
V
Storage temperature (Tstg
)
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltages referenced to VSS
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2500
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
3
NOM
MAX
3.6
UNIT
V
Supply voltage during operation (V33D, V33DIO, V33A
Operating free-air temperature, TA
Junction temperature, TJ
)
3.3
110
125
°C
–40
°C
6.4 Thermal Information
UCD9090A
THERMAL METRIC(1)
RGZ (VQFN)
UNIT
48 PINS
25
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
8.9
5.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJT
1.5
ψJB
RθJC(bot)
1.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
IV33A
VV33A = 3.3 V
VV33DIO = 3.3 V
VV33D = 3.3 V
8
2
mA
mA
mA
IV33DIO
Supply current(1)
IV33D
IV33D
ANALOG INPUTS (MON1–MON11)
40
VV33D = 3.3 V, storing configuration parameters in flash
memory
50
mA
0
0.2
–4
-2
2.5
2.5
4
V
MON1–MON10
VMON
Input voltage range
MON11
V
INL
ADC integral non-linearity
ADC differential non-linearity
Input leakage current
LSB
LSB
nA
DNL
Ilkg
2
3 V applied to pin
100
5
IOFFSET
Input offset current
1-kΩ source impedance
MON1–MON10, ground reference
MON11, ground reference
–5
8
μA
MΩ
MΩ
pF
RIN
Input impedance
0.5
1.5
3
CIN
Input capacitance
10
tCONVERT
ADC sample period
400
12 voltages sampled, 3.89 μs/sample
0°C ≤TA ≤125°C
μs
0.5%
1%
–0.5%
–1%
VREF
ADC 2.5 V, internal reference accuracy
–40°C ≤TA ≤125°C
ANALOG INPUT (PMBus_ADDRx)
IBIAS
Bias current for PMBus Addr pins
9
11
μA
V
VADDR_OPEN
VADDR_SHORT
PMBus_ADDR0, PMBus_ADDR1 open
2.26
Voltage –open pin
PMBus_ADDR0, PMBus_ADDR1 short to ground
0.124
V
Voltage –shorted pin
DIGITAL INPUTS AND OUTPUTS
VOL Low-level output voltage
VOH
Dgnd +
0.25
IOL = 6 mA(2), V33DIO = 3 V
V
V
V33DIO
–0.6
IOH = –6 mA(3), V33DIO = 3 V
High-level output voltage
VIH
VIL
High-level input voltage
Low-level input voltage
V33DIO = 3 V
2.1
3.6
1.4
V
V
V33DIO = 3.5 V
MARGINING OUTPUTS
FPWM1-8
PWM1-2
15.260
0.001
0%
125000
7800
TPWM_FREQ MARGINING-PWM frequency
kHz
DUTYPWM
MARGINING-PWM duty cycle range
100%
SYSTEM PERFORMANCE
VDDSlew
VRESET
Minimum VDD slew rate
VDD slew rate between 2.3 V and 2.9 V
For power-on reset (POR)
0.25
V/ms
V
Supply voltage at which device comes
out of reset
2.4
tRESET
Low-pulse duration needed at RESET pin To reset device during normal operation
2
240
100
20
μS
MHz
f(PCLK)
Internal oscillator frequency
TA = 25°C
TJ = 25°C
250
260
tretention
Retention of configuration parameters
Years
K cycles
Write_Cycles
Number of nonvolatile erase/write cycles TJ = 25°C
(1) Typical supply current values are based on device programmed but not configured, and no peripherals connected to any pins.
(2) The maximum total current, IOLmax, for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified.
(3) The maximum total current, IOHmax, for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified.
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MAX UNIT
6.6 I2C/Smbus/PMBus Timing Requirements
TA = –40°C to 85°C, 3 V < VDD < 3.6 V; typical values at TA = 25°C and VCC = 2.5 V (unless otherwise noted)
MIN
NOM
FSMB
FI2C
SMBus/PMBus operating frequency
I2C operating frequency
Bus free time between start and stop
Hold time after (repeated) start
Repeated-start setup time
Stop setup time
Slave mode, SMBC 50% duty cycle
Slave mode, SCL 50% duty cycle
10
400
400
kHz
kHz
μs
μs
μs
μs
ns
10
t(BUF)
1.3
0.6
0.6
0.6
0
t(HD:STA)
t(SU:STA)
t(SU:STO)
t(HD:DAT)
t(SU:DAT)
t(TIMEOUT)
t(LOW)
Data hold time
Receive mode
See(1)
Data setup time
100
ns
Error signal/detect
35
ms
μs
μs
ms
Clock low period
1.3
0.6
t(HIGH)
Clock high period
See (2)
See (3)
See (4)
t(LOW:SEXT)
tf
Cumulative clock low slave extend time
Clock/data fall time
25
20 +
0.1 Cb
300
ns
tr
Clock/data rise time
See (5)
20 +
0.1 Cb
300
400
ns
Cb
Total capacitance of one bus line
pF
(1) The device times out when any clock low exceeds t(TIMEOUT)
.
(2) t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction that is in progress. This
specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0] = 0).
(3) t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(4) Fall time tf = 0.9 VDD to (VILMAX –0.15)
(5) Rise time tr = (VILMAX –0.15) to (VIHMIN + 0.15)
图6-1. I2C/SMBus Timing Diagram
Start
Stop
T
LOW:SEXT
T
T
T
LOW:MEXT
LOW:MEXT
LOW:MEXT
PMB_Clk
Clk
ACK
Clk
ACK
PMB_Data
图6-2. Bus Timing in Extended Mode
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6.7 Typical Characteristics
1.2
1
2.5
2.498
2.496
2.494
2.492
2.49
0.8
0.6
0.4
0.2
0
DNLmin
DNL max
-0.2
-0.4
-0.6
-0.8
2.488
2.486
2.484
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
D001
D001
图6-3. ADC Reference Voltage vs Temperature
图6-4. ADC Differential Nonlinearity vs
Temperature
3
2.5
2
1.5
1
INL min
INL max
0.5
0
-0.5
-1
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
D001
图6-5. ADC Integral Nonlinearity vs Temperature
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7 Detailed Description
7.1 Overview
Electronic systems that include CPU, DSP, microcontroller, FPGA, ASIC, and so forth can have multiple voltage
rails and require certain power on/off sequences in order to function correctly. The UCD9090A can control up to
10 voltage rails and ensure correct power sequences during normal condition and fault conditions.
In addition to sequencing, UCD9090A can continuously monitor rail voltages, currents, temperatures, fault
conditions, and report the system health information to a PMBus host, improving systems’long term reliability.
The Fault Pin feature enables easily cascading multiple devices and coordinates among those devices to take
synchronized fault responses.
Also, UCD9090A can protect electronic systems by responding to power system faults. The fault responses are
conveniently configured by users through Fusion GUI. Fault events are stored in on-chip nonvolatile flash
memory with time stamp in order to assist failure analysis.
System reliability can be improved through four-corner testing during system verification. During four-corner
testing, each voltage rail is required to operate at the minimum and maximum output voltages, commonly known
as margining. UCD9090A can perform closed-loop margining for up to 10 voltage rails. During normal operation,
UCD9090A can also actively trim DC output voltages using the same margining circuitry.
UCD9090A supports both PMBus-based and pin-based control environments. UCD9090A functions as a PMBus
slave. It can communicate with PMBus host with PMBus commands, and control voltage rails accordingly. Also,
UCD9090A can be controlled by up to 8 GPIO configured GPI pins. One GPI pin can be used as the fault input
which can shut down rails. The GPIs can be used as Boolean logic input to control up to 10 Logic GPO outputs.
Each Logic GPO has a flexible Boolean logic builder. Input signals of the Boolean logic builder can include GPIs,
other Logic GPO outputs, and selectable system flags such as POWER_GOOD, faults, warnings, etc. A simple
state machine is also available for each Logic GPO pin.
UCD9090A provides additional features such as cascading, pin-selected states, system watchdog, system reset,
runtime clock, peak value log, reset counter, and so on. Pin-selected states feature allows users to use up to 3
GPIs to define up to 8 rail states. These states can implement system low-power modes as set out in the
Advanced Configuration and Power Interface (ACPI) specification. Other features will be introduced in the
following sections of this data sheet.
7.2 Functional Block Diagram
JTAG
Or
GPIO
General Purpose I/O
(GPIO)
I2C/PMBus
Comparators
Rail Enables (10 max)
6
Digital Outputs (10 max)
Digital Inputs (8 max)
Monitor
Inputs
23
SEQUENCING ENGINE
11
12-bit
200ksps,
Multi-phase PWM (8 max)
Margining Outputs (10 max)
ADC
(0.5% Int. Ref)
FLASH Memory
BOOLEAN
Logic Builder
User Data, Fault
and Peak Logging
48-pin QFN
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7.3 Feature Description
7.3.1 TI Fusion GUI
The Texas Instruments Fusion Digital Power Designer is provided for device configuration. This PC-based
graphical user interface (GUI) offers an intuitive I2C/PMBus interface to the device. It allows the design engineer
to configure the system operating parameters for the application without directly using PMBus commands, store
the configuration to on-chip nonvolatile memory, and observe system status (voltage, etc). Fusion Digital Power
Designer is referenced throughout the data sheet as Fusion GUI and many sections include screenshots. The
Fusion GUI can be downloaded from www.ti.com.
7.3.2 PMBus Interface
The PMBus is a serial interface specifically designed to support power management. It is based on the SMBus
interface that is built on the I2C physical specification. The UCD9090A supports revision 1.1 of the PMBus
standard. Wherever possible, standard PMBus commands are used to support the function of the device. For
unique features of the UCD9090A, MFR_SPECIFIC commands are defined to configure or activate those
features. These commands are defined in the UCD90xxx Sequencer and System Health Controller PMBus
Command Reference (SLVU352). The most current UCD90xxx PMBus™ Command Reference can be found
within the TI Fusion Digital Power Designer software via the Help Menu (Help, Documentation & Help Center,
Sequencers tab, Documentation section).
This document makes frequent mention of the PMBus specification. Specifically, this document is PMBus Power
System Management Protocol Specification Part II – Command Language, Revision 1.1, dated 5 February
2007. The specification is published by the Power Management Bus Implementers Forum and is available from
www.PMBus.org.
The UCD9090A is PMBus compliant, in accordance with the Compliance section of the PMBus specification.
The firmware is also compliant with the SMBus 1.1 specification, including support for the SMBus ALERT
function. The hardware can support either 100-kHz or 400-kHz PMBus operation.
7.3.3 Rail Configuration
A rail includes voltage, a power supply enable and a margining output. At least one must be included in a rail
definition. Once the user has defined how the power supply rails should operate in a particular system, analog
input pins and GPIOs can be selected to monitor and enable each supply (图7-1).
图7-1. Fusion GUI Pin-Assignment Tab
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After the pins have been configured, other key monitoring and sequencing criteria are selected for each rail from
the VOUT Config tab (图7-2):
• Nominal operating voltage (VOUT
)
• Undervoltage (UV) and overvoltage (OV) warning and fault limits
• Margin-low and margin-high values
• Power-good on and power-good off limits
• PMBus or pin-based sequencing control (On/Off Config)
• Rails, GPOs, and GPIs for Sequence On dependencies
• Rails, GPOs, and GPIs for Sequence Off dependencies
• Turn-on and turn-off delay timing
• Maximum time allowed for a rail to reach POWER_GOOD_ON or POWER_GOOD_OFF after being enabled
or disabled
• Other rails to turn off in case of a fault on a rail (fault-shutdown slaves)
图7-2. Fusion GUI VOUT-Config Tab
The Synchronize margins/limits/PG to Vout checkbox is an easy way to change the nominal operating voltage
of a rail and also update all of the other limits associated with that rail according to the percentages shown to the
right of each entry.
The plot in the upper left section of 图 7-2 shows a simulation of the overall sequence-on and sequence-off
configuration, including the nominal voltage, the turnon and turnoff delay times, the power-good on and power-
good off voltages and any timing dependencies between the rails.
After a rail voltage has reached its POWER_GOOD_ON voltage and is considered to be in regulation, it is
compared against two UV and two OV thresholds in order to determine if a warning or fault limit has been
exceeded. If a fault is detected, the UCD9090A responds based on a variety of flexible, user-configured options.
Faults can cause rails to restart, shut down immediately, sequence off using turnoff delay times or shut down a
group of rails and sequence them back on. Different types of faults can result in different responses.
Fault responses, along with a number of other parameters including user-specific manufacturing information and
external scaling and offset values, are selected in the different tabs within the Configure function of the Fusion
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GUI. Once the configuration satisfies the user requirements, it can be written to device SRAM if Fusion GUI is
connected to a UCD9090A using an I2C/PMBus. SRAM contents can then be stored to data flash memory so
that the configuration remains in the device after a reset or power cycle.
The Fusion GUI Monitor page has a number of options, including a device dashboard and a system dashboard,
for viewing and controlling device and system status.
图7-3. Fusion GUI Monitor Page
The UCD9090A also has rail state for each rail to debug the system.
表7-1. Rail State
RAIL STATE
VALUE
DESCRIPTION
On condition is not met, or
IDLE
1
rail is shut down due to fault, or
rail is waiting for the resequence
SEQ_ON
2
3
Wait the dependency to be met to assert ENABLE signal
TON_DELAY to assert ENABLE signal
START_DELAY
Enable is asserted and rail is on the way to reach power good threshold. If the
power good threshold is set to 0 V, the rail stays at this state even if the monitored
voltage is bigger than 0 V.
RAMP_UP
4
5
Once the monitoring voltage is over POWER_GOOD when enable signal is
asserted, rails stay at this state even if the voltage is below POWER_GOOD late
as long as there is no fault action taken.
REGULATION
SEQ_OFF
6
7
Wait the dependency to be met to de-assert ENABLE signal
TOFF_DELAY to de-assert ENABLE signal
STOP_DELAY
Enable signal is de-asserted and rail is ramping down. This state is only available
if TOFF_MAX_WARN_LIMIT is not set to unlimited; or If the turn off is triggered by
a fault action, rail must not be under fault retry to show RAMP DOWN state.
Otherwise, IDLE state is present.
RAMP_DOWN
8
The UCD9090A also has status registers for each rail and the capability to log faults to flash memory for use in
system troubleshooting. This is helpful in the event of a power supply or system failure. The status registers (图
7-4) and the fault log (图7-5) are available in the Fusion GUI. See the UCD90xxx Sequencer and System Health
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Controller PMBus Command Reference (SLVU352) and the PMBus Specification for detailed descriptions of
each status register and supported PMBus commands.
图7-4. Fusion GUI Rail-Status Register
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图7-5. Fusion GUI Flash-Error Log (Logged Faults)
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7.4 Device Functional Modes
7.4.1 Power Supply Sequencing
The UCD9090A can control the turn-on and turn-off sequencing of up to 10 voltage rails by using a GPIO to set
a power supply enable pin high or low. In PMBus-based designs, the system PMBus master can initiate a
sequence-on event by asserting the PMBus_CNTRL pin or by sending the OPERATION command over the I2C
serial bus. In pin-based designs, the PMBus_CNTRL pin can also be used to sequence-on and sequence-off.
The auto-enable setting ignores the OPERATION command and the PMBus_CNTRL pin. Sequence-on is
started at power up after any dependencies and time delays are met for each rail. A rail is considered to be on or
1
within regulation when the measured voltage for that rail crosses the power-good on (POWER_GOOD_ON )
limit. The rail is still in regulation until the voltage drops below power-good off (POWER_GOOD_OFF). In the
case that there isn't voltage monitoring set for a given rail, that rail is considered ON if it is commanded on
(either by OPERATION command, PMBus CNTRL pin, or auto-enable) and (TON_DELAY
+
TON_MAX_FAULT_LIMIT) time passes. Also, a rail is considered OFF if that rail is commanded OFF and
(TOFF_DELAY + TOFF_MAX_WARN_LIMIT) time passes.
7.4.1.1 Turn-On Sequencing
The following sequence-on options are supported for each rail:
• Monitor only –do not sequence-on
• Fixed delay time (TON_DELAY) after an OPERATION command to turn on
• Fixed delay time after assertion of the PMBus_CNTRL pin
• Fixed time after one or a group of parent rails achieves regulation (POWER_GOOD_ON)
• Fixed time after a designated GPI has reached a user-specified state
• Fixed time after a designated GPO has reached a user-specified state
• Any combination of the previous options
The maximum TON_DELAY time is 3276 ms.
7.4.1.2 Turn-Off Sequencing
The following sequence-off options are supported for each rail:
• Monitor only –do not sequence-off
• Fixed delay time (TOFF_DELAY) after an OPERATION command to turn off
• Fixed delay time after deassertion of the PMBus_CNTRL pin
• Fixed time after one or a group of parent rails drop below regulation (POWER_GOOD_OFF)
• Fixed delay time in response to an undervoltage, overvoltage, or max turn-on fault on the rail
• Fixed delay time in response to a fault on a different rail when set as a fault shutdown slave to the faulted rail
• Fixed delay time in response to a GPI reaching a user-specified state
• Fixed time after a designated GPO has reached a user-specified state
• Any combination of the previous options
The maximum TOFF_DELAY time is 3276 ms.
1
In this document, configuration parameters such as Power Good On are referred to using Fusion GUI names. The UCD90xxx
Sequencer and System Health Controller PMBus Command Reference name is shown in parentheses (POWER_GOOD_ON) the first
time the parameter appears.
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Rail 1 and Rail 2 are both sequenced “ON”
and “OFF” by the PMBUS_CNTRL pin
only
PMBUS_CNTRL PIN
RAIL 1 EN
TON_DELAY[1]
TOFF_DELAY[1]
Rail 2 has Rail 1 as an “ON” dependency
Rail 1 has Rail 2 as an “OFF” dependency
POWER_GOOD_ON[1]
POWER_GOOD_OFF[1]
RAIL 1 VOLTAGE
RAIL 2 EN
TON_DELAY[2]
TOFF_DELAY[2]
RAIL 2 VOLTAGE
TON_MAX_FAULT_LIMIT[2]
TOFF_MAX_WARN_LIMIT[2]
图7-6. Sequence-On and Sequence-Off Timing
7.4.1.3 Sequencing Configuration Options
In addition to the turn-on and turn-off sequencing options, the time between when a rail is enabled and when the
monitored rail voltage must reach its power-good-on setting can be configured using max turn-on
(TON_MAX_FAULT_LIMIT). Max turn-on can be set in 1-ms increments. A value of 0 ms means that there is no
limit and the device can try to turn on the output voltage indefinitely.
Rails can be configured to turn off immediately or to sequence-off according to rail and GPI dependencies, and
user-defined delay times. A sequenced shutdown is configured by selecting the appropriate rail and GPI
dependencies, and turn-off delay (TOFF_DELAY) times for each rail. The turn-off delay times begin when the
PMBus_CNTRL pin is deasserted, when the PMBus OPERATION command is used to give a soft-stop
command, or when a fault occurs on a rail that has other rails set as fault-shutdown slaves.
Shutdowns on one rail can initiate shutdowns of other rails or controllers. In systems with multiple UCD9090As, it
is possible for each controller to be both a master and a slave to another controller.
7.4.2 Pin-Selected Rail States
This feature allows with the use of up to 3 GPIs to enable and disable any rail. This is useful for implementing
system low-power modes and the Advanced Configuration and Power Interface (ACPI) specification that is used
for operating system directed power management in servers and PCs. In up to 8 system states, the power
system designer can define which rails are on and which rails are off. If a new state is presented on the input
pins, and a rail is required to change state, it will do so with regard to its sequence-on or sequence-off
dependencies.
The OPERATION command is modified when this function causes a rail to change its state. This means that the
ON_OFF_CONFIG for a given rail must be set to use the OPERATION command for this function to have any
effect on the rail state. The first 3 pins configured with the GPI_CONFIG command are used to select 1 of 8
system states. Whenever the device is reset, these pins are sampled and the system state, if enabled, will be
used to update each rail state. When selecting a new system state, changes to the status of the GPIs must not
take longer than 1 microsecond. See the UCD90xxx Sequencer and System Health Controller PMBus Command
Reference for complete configuration settings of PIN_SELECTED_RAIL_STATES.
表7-2. GPI Selection of System States
SYSTEM
STATE
GPI 2 STATE
GPI 1 STATE
GPI 0 STATE
NOT Asserted
NOT Asserted
NOT Asserted
NOT Asserted
Asserted
NOT Asserted
NOT Asserted
Asserted
NOT Asserted
Asserted
0
1
2
3
4
5
6
NOT Asserted
Asserted
Asserted
NOT Asserted
NOT Asserted
Asserted
NOT Asserted
Asserted
Asserted
Asserted
NOT Asserted
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表7-2. GPI Selection of System States (continued)
SYSTEM
STATE
GPI 2 STATE
GPI 1 STATE
GPI 0 STATE
Asserted
Asserted
Asserted
7
7.4.3 Monitoring
The UCD9090A has 11 monitor input pins (MONx) that are multiplexed into a 2.5V referenced 12-bit ADC. The
monitor pins can be configured so that they can measure voltage signals to report voltage, current and
temperature type measurements. A single rail can include all three measurement types, each monitored on
separate MON pins. If a rail has both voltage and current assigned to it, then the user can calculate power for
the rail. Digital filtering applied to each MON input depends on the type of signal. Voltage inputs have no filtering.
Current and temperature inputs have a low-pass filter.
7.4.3.1 Voltage Monitoring
Up to 11 voltages can be monitored using the analog input pins. The input voltage range is 0 V–2.5 V for all
MONx inputs except MON11 (pin 37) which operates in the range between 0.2 V and 2.5 V. Any voltage
between 0 V and 0.2 V on this pin is read as 0.2 V. External resistors can be used to attenuate voltages higher
than 2.5 V.
The ADC operates continuously, requiring 3.89 μs to convert a single analog input. Each rail is sampled by the
sequencing and monitoring algorithm every 400 μs. The maximum source impedance of any sampled voltage
should be less than 4 kΩ. The source impedance limit is particularly important when a resistor-divider network is
used to lower the voltage applied to the analog input pins.
MON1 - MON6 can be configured using digital hardware comparators, which can be used to achieve faster fault
responses. Each hardware comparator has four thresholds (two UV (Fault and Warning) and two OV (Fault and
Warning)). The hardware comparators respond to UV or OV conditions in about 80 μs (faster than 400 µs for
the ADC inputs) and can be used to disable rails or assert GPOs. The only fault response available for the
hardware comparators is to shut down immediately.
An internal 2.5-V reference is used by the ADC. The ADC reference has a tolerance of ±0.5% between 0°C and
125°C and a tolerance of ±1% between –40°C and 125°C. An external voltage divider is required for monitoring
voltages higher than 2.5 V. The nominal rail voltage and the external scale factor can be entered into the Fusion
GUI and are used to report the actual voltage being monitored instead of the ADC input voltage. The nominal
voltage is used to set the range and precision of the reported voltage according to 表7-3.
MON1
MON2
MON3
MON1 through MON6
MON4
200 kSPS
Fast digital
comparators
MON5
Analog
inputs
12-bit
SAR ADC
MON6
MON7
MON8
MON9
MON10
MON11
MUX
Glitch filter
MON1 through MON11
Internal 2.5-V
reference (0.5%)
图7-7. Voltage Monitoring Block Diagram
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表7-3. Voltage Range and Resolution
VOLTAGE RANGE (V)
0 to 127.99609
0 to 63.99805
0 to 31.99902
0 to 15.99951
0 to 7.99976
RESOLUTION (mV)
3.90625
1.95313
0.97656
0.48824
0.24414
0 to 3.99988
0.12207
0 to 1.99994
0.06104
0 to 0.99997
0.03052
Although the monitor results can be reported with a resolution of approximately 15 μV, the true conversion
resolution of 610 μV is fixed by the 2.5-V reference and the 12-bit ADC.
7.4.3.2 Current Monitoring
Current can be monitored using the analog inputs. External circuitry, see 图7-8, must be used in order to convert
the current to a voltage within the range of the UCD9090A MONx input being used.
If a monitor input is configured as a current, the measurements are smoothed by a sliding-average digital filter.
The current for 1 rail is measured every 200μs. If the device is programmed to support 10 rails (independent of
current not being monitored at all rails), then each rail's current will get measured every 2ms. The current
calculation is done with a sliding average using the last 4 measurements. The filter reduces the probability of
false fault detections, and introduces a small delay to the current reading. If a rail is defined with a voltage
monitor and a current monitor, then monitoring for undercurrent warnings begins once the rail voltage reaches
POWER_GOOD_ON. If the rail does not have a voltage monitor, then current monitoring begins after
TON_DELAY.
The device supports multiple PMBus commands related to current, including READ_IOUT, which reads external
currents from the MON pins; IOUT_OC_FAULT_LIMIT, which sets the overcurrent fault limit;
IOUT_OC_WARN_LIMIT, which sets the overcurrent warning limit; and IOUT_UC_FAULT_LIMIT, which sets the
undercurrent fault limit. The UCD90xxx Sequencer and System Health Controller PMBus Command Reference
contains a detailed description of how current fault responses are implemented using PMBus commands.
IOUT_CAL_GAIN is a PMBus command that allows the scale factor of an external current sensor and any
amplifiers or attenuators between the current sensor and the MON pin to be entered by the user in milliohms.
IOUT_CAL_OFFSET is the current that results in 0 V at the MON pin. The combination of these PMBus
commands allows current to be reported in amperes. The example below using the INA196 would require
programming IOUT_CAL_GAIN to Rsense(mΩ)×20.
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UCD9090A
MONx
INA196
VOUT
Vin+
Vin-
Rsense
AVSS1
GND
V+
3.3V
Gain = 20V/V
Copyright © 2016, Texas Instruments Incorporated
图7-8. Current Monitoring Circuit Example Using the INA196
7.4.3.3 Remote Temperature Monitoring and Internal Temperature Sensor
The UCD9090A has support for internal and remote temperature sensing. The internal temperature sensor
requires no calibration and can report the device temperature via the PMBus interface. The remote temperature
sensor can report the remote temperature by using a configurable gain and offset for the type of sensor that is
used in the application such as a linear temperature sensor (LTS) connected to the analog inputs.
External circuitry must be used in order to convert the temperature to a voltage within the range of the
UCD9090A MONx input being used.
If an input is configured as a temperature, the measurements are smoothed by a sliding average digital filter. The
temperature for 1 rail is measured every 100ms. If the device is programmed to support 10 rails (independent of
temperature not being monitored at all rails), then each rail's temperature will get measured every 1s. The
temperature calculation is done with a sliding average using the last 16 measurements. The filter reduces the
probability of false fault detections, and introduces a small delay to the temperature reading. The internal device
temperature is measured using a silicon diode sensor with an accuracy of ±5°C and is also monitored using the
ADC. Temperature monitoring begins immediately after reset and initialization.
The device supports multiple PMBus commands related to temperature, including READ_TEMPERATURE_1,
which reads the internal temperature; READ_TEMPERATURE_2, which reads external temperatures; and
OT_FAULT_LIMIT and OT_WARN_LIMIT, which set the overtemperature fault and warning limit. The UCD90xxx
Sequencer and System Health Controller PMBus Command Reference contains a detailed description of how
temperature-fault responses are implemented using PMBus commands.
TEMPERATURE_CAL_GAIN is a PMBus command that allows the scale factor of an external temperature
sensor and any amplifiers or attenuators between the temperature sensor and the MON pin to be entered by the
user in °C/V. TEMPERATURE_CAL_OFFSET is the temperature that results in 0 V at the MON pin. The
combination of these PMBus commands allows temperature to be reported in degrees Celsius.
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UCD9090A
TMP20
MONx
VOUT
AVSS1
GND
V+
3.3V
Vout = -11.67mV/°C x T + 1.8583
at -40°C < T < 85°C
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图7-9. Remote Temperature Monitoring Circuit Example Using the TMP20
7.4.3.4 Temperature by Host Input
If the host system has the option of not using the temperature-sensing capability of the UCD9090A, it can still
provide the desired temperature to the UCD9090A through PMBus. The host may have temperature
measurements available through I2C or SPI interfaced temperature sensors. The UCD9090A would use the
temperature given by the host in place of an external temperature measurement for a given rail. The temperature
provided by the host would still be used for detecting overtemperature warnings or faults, logging peak
temperatures, input to Boolean logic-builder functions, and feedback for the fan-control algorithms. To write a
temperature associated with a rail, the PMBus command used is the READ_TEMPERATURE_2 command. If the
host writes that command, the value written will be used as the temperature until another value is written. This is
true whether a monitor pin was assigned to the temperature or not. When there is a monitor pin associated with
the temperature, once READ_TEMPERATURE_2 is written, the monitor pin is not used again until the part is
reset. When there is not a monitor pin associated with the temperature, the internal temperature sensor is used
for the temperature until the READ_TEMPERATURE_2 command is written.
UCD9090A
TMP20
MONx
VOUT
AVSS1
GND
V+
3.3V
Vout = -11.67mV/°C x T + 1.8583
at -40°C < T < 85°C
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图7-10. Temperature Provided by Host
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7.4.4 Fault Responses and Alert Processing
The UCD9090A monitors whether the rail stays within a window of normal operation.. There are two
programmable warning levels (under and over) and two programmable fault levels (under and over). When any
monitored voltage goes outside of the warning or fault window, the PMBALERT# pin is asserted immediately,
and the appropriate bits are set in the PMBus status registers (see 图 7-4). Detailed descriptions of the status
registers are provided in the UCD90xxx Sequencer and System Health Controller PMBus Command Reference
and the PMBus Specification.
A programmable glitch filter can be enabled or disabled for each MON input. A glitch filter for an input defined as
a voltage can be set between 0 and 102 ms with 400-μs resolution. The glitch filter only applies to fault
responses; a fault condition that is filtered by the glitch filter will still be recorded in the fault log.
Fault-response decisions are based on results from the 12-bit ADC. The device cycles through the ADC results
and compares them against the programmed limits. The time to respond to an individual event is determined by
when the event occurs within the ADC conversion cycle and the selected fault response.
PMBUS_CNTRL PIN
TIME BETWEEN
RESTARTS
TIME BETWEEN
RESTARTS
TIME BETWEEN
RESTARTS
TON_DELAY[1]
TOFF_DELAY[1]
MAX_GLITCH_TIME
RAIL 1 EN
VOUT_OV_FAULT_LIMIT
MAX_GLITCH_TIME +
TOFF_DELAY[1]
MAX_GLITCH_TIME +
TOFF_DELAY[1]
VOUT_UV_FAULT_LIMIT
POWER_GOOD_ON[1]
MAX_GLITCH_TIME
MAX_GLITCH_TIME
TOFF_DELAY[1]
RAIL 1 VOLTAGE
TON_DELAY[2]
TOFF_DELAY[2]
RAIL 2 EN
RAIL 2 VOLTAGE
Rail 1 and Rail 2 are both sequenced “ON” and
“OFF” by the PMBUS_CNTRL pin only
Rail 1 is set to use the glitch filter for UV or OV events
Rail 1 is set to RESTART 3 times after a UV or OV event
Rail 1 is set to shutdown with delay for a OV event
Rail 2 has Rail 1 as an “ON” dependency
Rail 1 has Rail 2 as a Fault Shutdown Slave
图7-11. Sequencing and Fault-Response Timing
PMBUS_CNTRL PIN
TON_DELAY[1]
Rail 1 and Rail 2 are both sequenced
“ON” and “OFF” by the PMBUS_CNTRL
pin only
RAIL 1 EN
Time Between Restarts
Rail 2 has Rail 1 as an “ON” dependency
Rail 1 is set to shutdown immediately
and RESTART 1 time in case of a Time
On Max fault
POWER_GOOD_ON[1]
POWER_GOOD_ON[1]
RAIL 1 VOLTAGE
TON_MAX_FAULT_LIMIT[1]
TON_DELAY[2]
TON_MAX_FAULT_LIMIT[1]
RAIL 2 EN
RAIL 2 VOLTAGE
图7-12. Maximum Turn-On Fault
The configurable fault limits are:
TON_MAX_FAULT – Flagged if a rail that is enabled does not reach the POWER_GOOD_ON limit within the
configured time
VOUT_UV_WARN – Flagged if a voltage rail drops below the specified UV warning limit after reaching the
POWER_GOOD_ON setting
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VOUT_UV_FAULT – Flagged if a rail drops below the specified UV fault limit after reaching the
POWER_GOOD_ON setting
VOUT_OV_WARN – Flagged if a rail exceeds the specified OV warning limit at any time during startup or
operation
VOUT_OV_FAULT – Flagged if a rail exceeds the specified OV fault limit at any time during startup or
operation
MAX_TOFF_WARN – Flagged if a rail that is commanded to shut down does not reach 12.5% of the nominal
rail voltage within the configured time
Faults are more serious than warnings. The PMBALERT# pin is always asserted immediately if a warning or
fault occurs. If a warning occurs, the following takes place:
Warning Actions
Immediately assert the PMBALERT# pin
Status bit is flagged
—
—
—
—
Assert a GPIO pin (optional)
Warnings are not logged to flash
A number of fault response options can be chosen from:
Fault Responses
Continue Without Interruption: Flag the fault and take no action
—
—
—
Shut Down Immediately: Shut down the faulted rail immediately
Shut Down using TOFF_DELAY: If a fault occurs on a rail, schedule the shutdown of this rail and all fault-shutdown
slaves. All selected rails, including the faulty rail, are sequenced off according to their sequence-off dependencies and
T_OFF_DELAY times.
Restart
Do Not Restart: Do not attempt to restart a faulted rail after it has been shut down.
—
—
Restart Up To N Times: Attempt to restart a faulted rail up to 14 times after it has been shut down. The time between
restarts is measured between when the rail enable pin is deasserted (after any glitch filtering and turn-off delay times, if
configured to observe them) and then reasserted. It can be set between 0 and 1275 ms in 5-ms increments.
Restart Continuously: Same as Restart Up To N Times except that the device continues to restart until the fault goes
away, it is commanded off by the specified combination of PMBus OPERATION command and PMBus_CNTRL pin status,
the device is reset, or power is removed from the device.
—
—
Shut Down Rails and Sequence On (Re-sequence): Shut down selected rails immediately or after continue-operation time
is reached and then sequence-on those rails using sequence-on dependencies and T_ON_DELAY times.
One GPI pin can also trigger faults if the GPI Fault Enable checkbox in 图7-17 is checked and proper responses
are set in 图7-18. Refer to 节7.4.9 for more details.
7.4.5 Shut Down All Rails and Sequence On (Resequence)
In response to a fault, or a RESEQUENCE command, the UCD9090A can be configured to turn off a set of rails
and then sequence them back on. To sequence all rails in the system, then all rails must be selected as fault-
shutdown slaves of the faulted rail. The rails designated as fault-shutdown slaves will do soft shutdowns
regardless of whether the faulted rail is set to stop immediately or stop with delay. Shut-down-all-rails and
sequence-on are not performed until retries are exhausted for a given fault.
While waiting for the rails to turn off, an error is reported if any of the rails reaches its TOFF_MAX_WARN_LIMIT.
There is a configurable option to continue with the resequencing operation if this occurs. After the faulted rail and
fault-shutdown slaves sequence-off, the UCD9090A waits for a programmable delay time between 0 and 1275
ms in increments of 5 ms and then sequences-on the faulted rail and fault-shutdown slaves according to the
start-up sequence configuration. This is repeated until the faulted rail and fault-shutdown slaves successfully
achieve regulation or for a user-selected 1, 2, 3, 4 or unlimited times. If the resequence operation is successful,
the resequence counter is reset if all of the rails that were resequenced maintain normal operation for one
second.
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Once shut-down-all-rails and sequence-on begin, any faults on the fault-shutdown slave rails are ignored. If
there are two or more simultaneous faults with different fault-shutdown slaves, the more conservative action is
taken. For example, if a set of rails is already on its second resequence and the device is configured to
resequence three times, and another set of rails enters the resequence state, that second set of rails is only
resequenced once. Another example – if one set of rails is waiting for all of its rails to shut down so that it can
resequence, and another set of rails enters the resequence state, the device now waits for all rails from both sets
to shut down before resequencing.
If any rails at resequence state are caused by a GPI fault response, the whole resequence is suspended until
the GPI fault is clear.
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7.4.6 GPIOs
The UCD9090A has 21 GPIO pins that can function as either inputs or outputs. Each GPIO has configurable
output mode options including open-drain or push-pull outputs that can be actively driven to 3.3 V or ground.
There are an additional two pins that can be used as either inputs or PWM outputs but not as GPOs. 表 7-4 lists
possible uses for the GPIO pins and the maximum number of each type for each use. GPIO pins can be
dependents in sequencing and alarm processing. They can also be used for system-level functions such as
external interrupts, power-goods, resets, or for the cascading of multiple devices. GPOs can be sequenced up or
down by configuring a rail without a MON pin but with a GPIO set as an enable.
表7-4. GPIO Pin Configuration Options
RAIL EN
(10 MAX)
GPI
(8 MAX)
GPO
(10 MAX)
PWM OUT
(10 MAX)
MARGIN PWM
(10 MAX)
PIN NAME
PIN
FPWM1/GPIO5
FPWM2/GPIO6
FPWM3/GPIO7
FPWM4/GPIO8
FPWM5/GPIO9
FPWM6/GPIO10
FPWM7/GPIO11
FPWM8/GPIO12
GPI1/PWM1
GPI2/PWM2
GPIO1
10
11
12
13
14
15
16
17
22
23
4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
GPIO2
5
GPIO3
6
GPIO4
7
GPIO13
18
21
24
25
26
27
28
29
30
GPIO14
GPIO15
GPIO16
GPIO17
TCK/GPIO18
TDO/GPIO19
TDI/GPIO20
TMS/GPIO21
7.4.7 GPO Control
The GPIOs when configured as outputs can be controlled by PMBus commands or through logic defined in
internal Boolean function blocks. Controlling GPOs by PMBus commands (GPIO_SELECT and GPIO_CONFIG)
can be used to have control over LEDs, enable switches, etc. with the use of an I2C interface. See the
UCD90xxx Sequencer and System Health Controller PMBus Command Reference for details on controlling a
GPO using PMBus commands.
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7.4.8 GPO Dependencies
GPIOs can be configured as outputs that are based on Boolean combinations of up to two ANDs all ORed
together (图7-13). Inputs to the logic blocks can include the first 8 defined GPOs, GPIs and rail-status flags. One
rail status type is selectable as an input for each AND gate in a Boolean block. For a selected rail status, the
status flags of all active rails can be included as inputs to the AND gate. _LATCH rail-status types stay asserted
until cleared by a MFR PMBus command or by a specially configured GPI pin. The different rail-status types are
shown in 表 7-5. See the UCD90xxx Sequencer and System Health Controller PMBus Command Reference for
complete definitions of rail-status types. The GPO response can be configured to have a delayed assertion or
deassertion. The first 8 GPOs can be chosen as Rail Sequence on/off Dependency. The logic state of the GPO
instead of actual pin output is used as dependency condition.
Sub block repeated for each of GPI(1:7)
GPI_INVERSE(0)
GPI_POLARITY(0)
GPI_ENABLE(0)
AND_INVERSE(0)
1
_GPI(0)
GPI(0)
_GPI(1:7)
_STATUS(0:8)
_GPO(1:7)
_STATUS(9)
There is one STATUS_TYPE_SELECT for each of the two AND
boolean block
gates in
a
STATUS_TYPE_SELECT
STATUS(0)
STATUS(1)
OR_INVERSE(x)
Status Type 1
Sub block repeated for each of STATUS(0:8)
GPOx
STATUS_INVERSE(9)
STATUS_ENABLE(9)
Status Type 31
ASSERT_DELAY(x)
DE-ASSERT_DELAY(x)
1
STATUS(9)
AND_INVERSE(1)
_GPI(0:7)
_STATUS(0:9)
_GPO(0:7)
Sub block repeated for each of GPO(1:7)
GPO_INVERSE(0)
GPO_ENABLE(0)
1
_GPO(0)
GPO(0)
图7-13. Boolean Logic Combinations
图7-14. Fusion Boolean Logic Builder
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表7-5. Rail-Status Types For Boolean Logic
Rail-Status Types
POWER_GOOD
MARGIN_EN
IOUT_UC_FAULT
TEMP_OT_FAULT
TEMP_OT_WARN
SEQ_ON_TIMEOUT
SEQ_OFF_TIMEOUT
TOFF_MAX_WARN_LATCH
SEQ_ON_TIMEOUT_LATCH
SEQ_OFF_TIMEOUT_LATCH
SYSTEM_WATCHDOG_TIMEOUT_LATCH
IOUT_OC_FAULT_LATCH
MRG_LOW_nHIGH
VOUT_OV_FAULT
VOUT_OV_WARN
VOUT_UV_WARN
VOUT_UV_FAULT
TON_MAX_FAULT
TOFF_MAX_WARN
IOUT_OC_FAULT
IOUT_OC_WARN
SYSTEM_WATCHDOG_TIMEOUT
VOUT_OV_FAULT_LATCH
VOUT_OV_WARN_LATCH
VOUT_UV_WARN_LATCH
VOUT_UV_FAULT_LATCH
TON_MAX_FAULT_LATCH
IOUT_OC_WARN_LATCH
IOUT_UC_FAULT_LATCH
TEMP_OT_FAULT_LATCH
TEMP_OT_WARN_LATCH
When GPO is set to POWER_GOOD, this POWER_GOOD state is based on the actual voltage measurement
on the monitor pins assigned to those rails. For a rail that does not have a monitor pin, or have a monitor pin but
without voltage monitoring, its POWER_GOOD state is used by sequencing purpose only, and is not be used by
the GPO logic evaluation.
7.4.8.1 GPO Delays
The GPOs can be configured so that they manifest a change in logic with a delay on assertion, deassertion, both
or none. GPO behavior using delays will have different effects depending if the logic change occurs at a faster
rate than the delay. On a normal delay configuration, if the logic for a GPO changes to a state and reverts back
to previous state within the time of a delay then the GPO will not manifest the change of state on the pin. In 图
7-15 the GPO is set so that it follows the GPI with a 3ms delay at assertion and also at de-assertion. When the
GPI first changes to high logic state, the state is maintained for a time longer than the delay allowing the GPO to
follow with appropriate logic state. The same goes for when the GPI returns to its previous low logic state. The
second time that the GPI changes to a high logic state it returns to low logic state before the delay time expires.
In this case the GPO does not change state. A delay configured in this manner serves as a glitch filter for the
GPO.
3ms
3ms
GPI
GPO
1ms
图7-15. GPO Behavior When Not Ignoring Inputs During Delay
The Ignore Input During Delay bit allows to output a change in GPO even if it occurs for a time shorter than the
delay. This configuration setting has the GPO ignore any activity from the triggering event until the delay expires.
图 7-16 represents the two cases for when ignoring the inputs during a delay. In the case in which the logic
changes occur with more time than the delay, the GPO signal looks the same as if the input was not ignored.
Then on a GPI pulse shorter than the delay the GPO still changes state. Any pulse that occurs on the GPO when
having the Ignore Input During Delay bit set will have a width of at least the time delay.
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3ms
3ms
3ms
3ms
GPI
GPO
1ms
图7-16. GPO Behavior When Ignoring Inputs During Delay
7.4.8.2 State Machine Mode Enable
When this bit within the GPO_CONFIG command is set, only one of the AND path will be used at a given time.
When the GPO logic result is currently TRUE, AND path 0 will be used until the result becomes FALSE. When
the GPO logic result is currently FALSE, AND path 1 will be used until the result becomes TRUE. This provides a
very simple state machine and allows for more complex logical combinations.
7.4.9 GPI Special Functions
Special input functions for which GPIs can be used. There can be no more than one pin assigned to each of
these functions.
• GPI Fault Enable - When set, the de-assertion of the GPI is treated as a fault.
• Latched Statuses Clear Source - When a GPO uses a latched status type (_LATCH), a correctly configured
GPI clears the latched status.
• Input Source for Margin Enable - When this pin is asserted, all rails with margining enabled will be put in a
margined state (low or high).
• Input Source for Margin Low/Not-High - When this pin is asserted all margined rails will be set to Margin
Low as long as the Margin Enable is asserted. When this pin is de-asserted the rails will be set to Margin
High.
• Fault Shutdown Rails - See 节7.4.9.1.
• Configured as Sequencing Debug Pin - See 节7.4.9.2.
• Configured as Fault Pin - See 节7.4.9.2.
• Enable Cold Boot Mode - See 节7.4.9.4.
The polarity of GPI pins can be configured to be either Active Low or Active High. The first 3 GPIs that are
defined regardless of their main purpose will be used for the PIN_SELECTED_RAIL_STATES command.
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图7-17. GPI Configurations
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7.4.9.1 Fault Shutdown Rails
GPI Fault Enable must be set to enable this feature. When set, the de-assert of the assigned GPI trigger a
number of fault response options (see 图7-18). Retry action is not supported.
图7-18. GPI Fault Response
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7.4.9.2 Configured as Sequencing Debug Pin
When the pin is asserted, device does not alert PMBUS_Alert pin, not response for faults, log faults defined in
the 表 7-6. The rail sequence on/off dependency conditions are ignored, as soon as the sequence on/off timeout
is expired, the rails will be sequenced on or off accordingly regardless of the timeout action, if the sequence
on/off timeout value is set to 0, the rails is sequenced on or off immediately. The fault pins do not pull the fault
bus low. The LGPOs affected by these events should be back to it original states.
表7-6. List of Events Affected by Debug Mode
Events
Description
VOUT_OV_FAULT
VOUT_OV_WARNING
VOUT_UV_FAULT
VOUT_UV_WARNING
TON_MAX
Voltage Rail is over OV fault threshold
Voltage Rail is over OV warning threshold
Voltage Rail is under UV fault threshold
Voltage Rail is under UV warning threshold
Voltage Rail fails to reach power good threshold in predefined period.
Voltage rail fails to reach power not good threshold in predefined period
Current Rail is over OC fault threshold
TOFF_MAX Warning
IOUT_OC_FAULT
IOUT_OC_WARNING
IOUT_UC
Current Rail is under OC warning threshold
Current Rail is under UC fault threshold
OT_FAULT
Temperature Rail has over OT fault threshold
Temperature Rail has over OT warning threshold
No logging and fault response, but the function of the GPI is not ignored.
System watch timeout
OT_WARNING
All GPI de-asserted
SYSTEM_WATCHDOG_TIMEOUT
RESEQUENCE_ERROR
SEQ_ON_TIMEOUT
SEQ_OFF_TIMEOUT
SLAVE_FAULT
Rail fails to resequence
Rail fails to meeting sequence on dependency in predefined period
Rail fails to meeting sequence on dependency in predefined period
Rail is shut down due to that its master has fault
7.4.9.3 Configured as Fault Pin
GPI Fault Enable must be set to enable this feature. When set, if there is no fault on a Fault Bus, the Fault Pin is
digital input pin and listen to the Fault Bus. When one or multiple UCD90160A devices detect a rail fault (see 表
7-7), the corresponding Fault Pin is turned into active driven low state, pulling down the Fault Bus and informing
all other UCD90160A devices of the corresponding fault. This way, a coordinated action can be taken across
multiple devices. After the fault is cleared, the state of the Fault Pin is turned back to an input pin.
表7-7. Events Affecting Fault Pin
Events
Description
RESEQUENCE_ERROR
SEQ_ON_TIMEOUT
SEQ_OFF_TIMEOUT
OT_FAULT
Rail fails to resequence
Rail fails to meeting sequence on dependency in predefined period
Rail fails to meeting sequence on dependency in predefined period
Temperature Rail has over temperature
Current Rail is below UC threshold
IOUT_UC_FAULT
IOUT_OC_FAULT
VOUT_UV_FAULT
VOUT_OV_FAULT
TON_MAX_FAULT
Current Rail is over OC threshold
Voltage Rail is under UV threshold
Voltage Rail is over OV threshold
Voltage rail fails to reach power good threshold in predefined period.
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7.4.9.4 Cold Boot Mode Enable
Cold boot mode is used to heat-up a system by turning on cold boot rails for certain amounts of time when it is
under an extreme code temperature. UCD device is communicated with the system via particular GPI (thermal
state GPI) which is output from a thermal device. Cold boot mode is only entering once per UCD reset. There is
no system watch dog Reset during the cold boot mode.
Device reads the thermal state GPI to determine whether it should start cold boot or not when it is out of reset.
When the input of thermal state GPI is DE-ASSERTED, device enters cold boot mode and log the GPI fault if the
GPI fault log enable bit is set, otherwise device enters normal mode. The following changes on the thermal state
GPI do not introduce any logging. Only one GPI can be assigned for this function and one it is assigned, it
cannot be used for any other GPI functions.
The rails used in the cold boot mode are configurable. For those rails with Sequence On Dependency on the
thermal state GPI, they (non-cold boot rails) are not powered-up during the cold boot since the dependency is
not met. But non-cold boot rails will be power-on under normal mode since thermal state GPI is treated as
ASSERTED when cold boot mode is over. For those rails without sequence on dependency on the thermal state
GPI, they (cold boot rails) are power-on under both cold boot and normal mode. It is application’s responsibility
to set the proper ON_OFF_CONFIG for those cold boot rails. Cold boot rails are not power-on if their
ON_OFF_CONFIG settings are not met under cold boot mode. Cold boot mode timeout is used to tell how long
the device shall stay at the cold boot before it stops monitoring the thermal state GPI and shutdown all cold boot
rails with EN control. Normal Boot Start Delay is used to tell how long device should wait to ramp up the powers
after all cold boot rails with EN are below POWER_GOOD_OFF.
spacer
- If system temperature is < threshold degree C (Thermal State GPI)
o
Yes(DE_ASSERTED):
§ Log GPI fault
§ Start Cold Boot Timeout
§ No System Watchdog output
§ Ramp up the power supplies based on ON_OFF_CONFIG
§ Wait for thermal state GPI ASSERTED OR “Cold Boot Mode Timeout expired”
§ Disable the thermostat input listening mode
§ Force to shutdown down all cold boot rails with EN control immediately
§ Wait all cold boot rails with EN control below POWER_GOOD_OFF
§ Start and Wait “Normal boot Start Delay expired”
- Disable the thermostat input listening mode
- Treated Thermal State GPI as ASSERTED
- Ramp up power supplies based on ON_OFF_CONFIG
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7.4.10 Power Supply Enables
Each GPIO can be configured as a rail-enable pin with either active-low or active-high polarity. Output mode
options include open-drain or push-pull outputs that can be actively driven to 3.3 V or ground. During reset, the
GPIO pins are high-impedance except for FPWM/GPIO pins 17–24, which are driven low. External pulldown or
pullup resistors can be tied to the enable pins to hold the power supplies off during reset. The UCD9090A can
support a maximum of 10 enable pins.
备注
GPIO pins that have FPWM capability (pins 10-17) should only be used as power supply enable
signals if the signal is active high.
7.4.11 Cascading Multiple Devices
A GPIO pin can be used to coordinate multiple controllers by using it as a power good-output from one device
and connecting it to the PMBus_CNTRL input pin of another. This imposes a master/slave relationship among
multiple devices. During startup, the slave controllers initiate their start sequences after the master has
completed its start sequence and all rails have reached regulation voltages. During shutdown, as soon as the
master starts to sequence-off, it sends the shut-down signal to its slaves.
A shutdown on one or more of the master rails can initiate shutdowns of the slave devices. The master
shutdowns can be initiated intentionally or by a fault condition. This method works to coordinate multiple
controllers, but it does not enforce interdependency between rails within a single controller.
Another method to cascade multiple devices is to connect the power-good output of the first device to a MON pin
of the second device; connect the power-good output of the second device to a MON pin of the third device, and
so on. Optionally, connect the power-good output of the last device to a MON pin of the first device. The rails
controlled by a device have dependency on the previous device’s power-good output. This way, the rails
controlled by multiple devices can be sequenced. Also, the de-assertion of a power-good output can trigger a UV
fault of the next device. The UV fault response can be configured to shut down other rails controlled by the same
device. This way, when one rail has fault shutdown, other rails controlled by other devices can be shut down
accordingly.
The PMBus specification implies that the power-good signal is active when ALL the rails in a controller are
regulating at their programmed voltage. The UCD9090A allows GPIOs to be configured to respond to a desired
subset of power-good signals.
Multiple UCD9090A devices can also work together and coordinate when faults happen with a fault pin
connection. One GPI pin can be configured as a Fault pin. The Fault pin is connected to a Fault Bus. Each Fault
Bus is pulled up to 3.3 V by a 10-kΩ resistor. All the UCD9090A devices on the same Fault Bus are informed of
the same fault condition. An example of Fault Pin connections is shown in 图7-19.
UCD9090A
Fault Pin
3.3V
Fault Bus
Fault Pin
UCD9090A
图7-19. Fault Pin Connection
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7.4.12 PWM Outputs
7.4.12.1 FPWM1-8
Pins 10-17 can be configured as fast pulse-width modulators (FPWMs). The frequency range is 15.260 kHz to
125 MHz. FPWMs can be configured as closed-loop margining outputs, fan controllers or general-purpose
PWMs.
Any FPWM pin not used as a PWM output can be configured as a GPIO. One FPWM in a pair can be used as a
PWM output and the other pin can be used as a GPO. The FPWM pins are actively driven low from reset when
used as GPOs.
The frequency settings for the FPWMs apply to pairs of pins:
• FPWM1 and FPWM2 –same frequency
• FPWM3 and FPWM4 –same frequency
• FPWM5 and FPWM6 –same frequency
• FPWM7 and FPWM8 –same frequency
If an FPWM pin from a pair is not used while its companion is set up to function as a PWM, it is recommended to
configure the unused FPWM pin as an active-low open-drain GPO so that it does not disturb the rest of the
system. By setting an FPWM, it automatically enables the other FPWM within the pair if it was not configured for
any other functionality.
The frequency for the FPWM is derived by dividing down a 250MHz clock. To determine the actual frequency to
which an FPWM can be set, must divide 250MHz by any integer between 2 and (214-1).
The FPWM duty cycle resolution is dependent on the frequency set for a given FPWM. Once the frequency is
known the duty cycle resolution can be calculated as 方程式1.
Change per Step (%)FPWM = frequency / (250 × 106 × 16) × 100
(1)
Take for an example determining the actual frequency and the duty cycle resolution for a 75MHz target
frequency.
1. Divide 250 MHz by 75 MHz to obtain 3.33.
2. Round off 3.33 to obtain an integer of 3.
3. Divide 250 MHz by 3 to obtain actual closest frequency of 83.333 MHz.
4. Use 方程式1 to determine duty cycle resolution to obtain 2.0833% duty cycle resolution.
7.4.12.2 PWM1-2
Pins 22 and 23 can be used as GPIs or PWM outputs. These PWM outputs have an output frequency of 0.93 Hz
to 7.8125 MHz.
The frequency for PWM1 and PWM2 is derived by dividing down a 15.625-MHz clock. To determine the actual
frequency to which these PWMs can be set, must divide 15.625 MHz by any integer between 2 and (224-1). The
duty cycle resolution will be dependent on the set frequency for PWM1 and PWM2.
The PWM1 or PWM2 duty cycle resolution is dependent on the frequency set for the given PWM. Once the
frequency is known the duty cycle resolution can be calculated as 方程式2
Change per Step (%)PWM1/2 = frequency / 15.625 × 106 × 100
(2)
To determine the closest frequency to 1MHz that PWM1 can be set to calculate as the following:
1. Divide 15.625 MHz by 1 MHz to obtain 15.625.
2. Round off 15.625 to obtain an integer of 16.
3. Divide 15.625 MHz by 16 to obtain actual closest frequency of 976.563 kHz.
4. Use 方程式2 to determine duty cycle resolution to obtain 6.25% duty cycle resolution.
All frequencies below 238 Hz will have a duty cycle resolution of 0.0015%.
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7.4.13 Programmable Multiphase PWMs
The FPWMs can be aligned with reference to their phase. The phase for each FPWM is configurable from 0° to
360°. This provides flexibility in PWM-based applications such as power supply controller, digital clock
generation, and others. See an example of four FPWMs programmed to have phases at 0°, 90°, 180° and 270°
(图7-20).
图7-20. Multiphase PWMs
7.4.14 Margining
Margining is used in product validation testing to verify that the complete system works properly over all
conditions, including minimum and maximum power supply voltages, load range, ambient temperature range,
and other relevant parameter variations. Margining can be controlled over PMBus using the OPERATION
command or by configuring two GPIO pins as margin-EN and margin-UP/DOWN inputs. The MARGIN_CONFIG
command in the UCD90xxx Sequencer and System Health Controller PMBus Command Reference describes
different available margining options, including ignoring faults while margining and using closed-loop margining
to trim the power supply output voltage one time at power up.
7.4.14.1 Open-Loop Margining
Open-loop margining is done by connecting a power supply feedback node to ground through one resistor and
to the margined power supply output (VOUT) through another resistor. The power supply regulation loop
responds to the change in feedback node voltage by increasing or decreasing the power supply output voltage
to return the feedback voltage to the original value. The voltage change is determined by the fixed resistor
values and the voltage at VOUT and ground. Two GPIO pins must be configured as open-drain outputs for
connecting resistors from the feedback node of each power supply to VOUT or ground.
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MON(1:10)
3.3V
UCD9090A
POWER
SUPPLY
10kW
out
V
GPIO(1:10)
/EN
VOUT
VFB
3.3V
Rmrg_HI
VFB
“0” or “1”
“0” or “1”
GPIO
GPIO
VOUT
Rmrg_LO
3.3V
POWER
SUPPLY
Vout
W
10k
/EN
VOUT
VFB
VFB
Rmrg_HI
Rmrg_LO
VOUT
.
3.3V
Open Loop Margining
Copyright © 2016, Texas Instruments Incorporated
图7-21. Open-Loop Margining
7.4.14.2 Closed-Loop Margining
Closed-loop margining uses a PWM or FPWM output for each power supply that is being margined. An external
RC network converts the FPWM pulse train into a DC margining voltage. The margining voltage is connected to
the appropriate power supply feedback node through a resistor. The power supply output voltage is monitored,
and the margining voltage is controlled by adjusting the PWM duty cycle until the power supply output voltage
reaches the margin-low and margin-high voltages set by the user. The voltage setting resolutions will be the
same that applies to the voltage measurement resolution (表 7-3). The closed loop margining can operate in
several modes (表 7-8). Given that this closed-loop system has feed back through the ADC, the closed-loop
margining accuracy will be dominated by the ADC measurement. The relationship between duty cycle and
margined voltage is configurable so that voltage increases when duty cycle increases or decreases. For more
details on configuring the UCD9090A for margining, see the Voltage Margining Using the UCD9012x application
note (SLVA375).
表7-8. Closed Loop Margining Modes
MODE
DESCRIPTION
DISABLE
Margining is disabled.
ENABLE_TRI_STATE
When not margining, the PWM pin is set to high impedance state.
When not margining, the PWM duty-cycle is continuously adjusted to keep the voltage at
VOUT_COMMAND.
ENABLE_ACTIVE_TRIM
ENABLE_FIXED_DUTY_CYCLE
When not margining, the PWM duty-cycle is set to a fixed duty-cycle.
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MON(1:10)
3.3V
UCD9090A
POWER
SUPPLY
/EN
Vout
W
10k
GPIO
VOUT
VFB
R1
R2
250 kHz – 1MHz
Vmarg
V
FB
FPWM1
R3
R4
Closed
Loop
Margining
C1
Copyright © 2016, Texas Instruments Incorporated
图7-22. Closed-Loop Margining
7.4.15 Run Time Clock
The Run-Time clock is given in milliseconds and days. Both are 32-bit numbers. This value is saved in
nonvolatile memory whenever a STORE_DEFAULT_ALL command is issued. It can also be saved when a
power-down condition is detected (See 节7.4.19).
The Run-Time clock may also be written. This allows the clock to be periodically corrected by the host. It also
allows the clock to be initialized to the actual, absolute time in years (e.g., March 23, 2010). The user must
translate the absolute time to days and milliseconds.
The three usage scenarios for the Run-Time Clock are:
1. Time from restart (reset or power-on) –the Run-Time Clock starts from 0 each time a restart occurs
2. Absolute run-time, or operating time –the Run-Time Clock is preserved across restarts, so you can keep
up with the total time that the device has been in operation (Note: “Boot time”is not part of this. Only
normal operation time is captured here.)
3. Local time –an external processor sets the Run-Time Clock to real-world time each time the device is
restarted.
The Run-Time clock value is used to timestamp any faults that are logged.
7.4.16 System Reset Signal
The UCD9090A can generate a programmable system-reset pulse as part of sequence-on. The pulse is created
by programming a GPIO to remain deasserted until the voltage of a particular rail or combination of rails reach
their respective POWER_GOOD_ON levels plus a programmable delay time. The system-reset delay duration
can be programmed as shown in 表 7-9. See an example of two SYSTEM RESET signals 图 7-23. The first
SYSTEM RESET signal is configured so that it de-asserts on Power Good On and it asserts on Power Good Off
after a given common delay time. The second SYSTEM RESET signal is configured so that it sends a pulse after
a delay time once Power Good On is achieved. The pulse width can be configured between 0.001s to 32.256s.
See the UCD90xxx Sequencer and System Health Controller PMBus Command Reference for pulse width
configuration details.
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Power Good On
Power Good On
Power Good Off
POWER GOOD
Delay
Delay
Delay
SYSTEM RESET
configured without pulse
Pulse
Pulse
SYSTEM RESET
configured with pulse
图7-23. System Reset With and Without Pulse Setting
The system reset can react to watchdog timing. In 图 7-24 The first delay on SYSTEM RESET is for the initial
reset release that would get a CPU running once all necessary voltage rails are in regulation. The watchdog is
configured with a Start Time and a Reset Time. If these times expire without the WDI clearing them then it is
expected that the CPU providing the watchdog signal is not operating. The SYSTEM RESET is toggled either
using a Delay or GPI Tracking Release Delay to see if the CPU recovers.
Power Good On
POWER GOOD
Watchdog
Reset Time
Watchdog
Start Time
Watchdog
Start Time
WDI
Delay
Watchdog
Reset Time
SYSTEM RESET
Delay or
GPI Tracking Release Delay
图7-24. System Reset With Watchdog
表7-9. System-Reset
Delay
DELAY
0 ms
1 ms
2 ms
4 ms
8 ms
16 ms
32 ms
64 ms
128 ms
256 ms
512 ms
1.02 s
2.05 s
4.10 s
8.19 s
16.38 s
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表7-9. System-Reset
Delay (continued)
DELAY
32.8 s
7.4.17 Watch Dog Timer
A GPI and GPO can be configured as a watchdog timer (WDT). The WDT can be independent of power supply
sequencing or tied to a GPIO functioning as a watchdog output (WDO) that is configured to provide a system-
reset signal. The WDT can be reset by toggling a watchdog input (WDI) pin or by writing to
SYSTEM_WATCHDOG_RESET over I2C. The WDI and WDO pins are optional when using the watchdog timer.
The WDI can be replaced by SYSTEM_WATCHDOG_RESET command and the WDO can be manifested
through the Boolean Logic defined GPOs or through the System Reset function.
The WDT can be active immediately at power up or set to wait while the system initializes. 表 7-10 lists the
programmable wait times before the initial timeout sequence begins.
表7-10. WDT Initial Wait
Time
WDT INITIAL WAIT TIME
0 ms
100 ms
200 ms
400 ms
800 ms
1.6 s
3.2 s
6.4 s
12.8 s
25.6 s
51.2 s
102 s
205 s
410 s
819 s
1638 s
The watchdog timeout is programmable from 0.001s to 32.256s. See the UCD90xxx Sequencer and System
Health Controller PMBus Command Reference for details on configuring the watchdog timeout. If the WDT times
out, the UCD9090A can assert a GPIO pin configured as WDO that is separate from a GPIO defined as system-
reset pin, or it can generate a system-reset pulse. After a timeout, the WDT is restarted by toggling the WDI pin
or by writing to SYSTEM_WATCHDOG_RESET over I2C.
<tWDI
<tWDI
<tWDI
tWDI
<tWDI
WDI
WDO
图7-25. Timing of GPIOs Configured for Watchdog Timer Operation
7.4.18 Data and Error Logging to Flash Memory
The UCD9090A can log faults and the number of device resets to flash memory. Peak voltage measurements
are also stored for each rail. To reduce stress on the flash memory, a 30-second timer is started if a measured
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value exceeds the previously logged value. Only the highest value from the 30-second interval is written from
RAM to flash. Data and Error logging to flash memory can be disabled by user so that the data and error are
only stored in the SRAM.
Multiple faults can be stored in flash memory and can be accessed over PMBus to help debug power supply
bugs or failures. Each logged fault includes:
• Rail number
• Fault type
• Fault time since previous device reset
• Last measured rail voltage
The total number of device resets is also stored to flash memory. The value can be reset using PMBus.
With the brownout function enabled, the run-time clock value, peak monitor values, and faults are only logged to
flash when a power-down is detected. The device run-time clock value is stored across resets or power cycles
unless the brownout function is disabled, in which case the run-time clock is returned to zero after each reset.
It is also possible to update and calibrate the UCD9090A internal run-time clock via a PMBus host. For example,
a host processor with a real-time clock could periodically update the UCD9090A run-time clock to a value that
corresponds to the actual date and time. The host must translate the UCD9090A timer value back into the
appropriate units, based on the usage scenario chosen. See the REAL_TIME_CLOCK command in the
UCD90xxx Sequencer and System Health Controller PMBus Command Reference for more details.
7.4.19 Brownout Function
The UCD9090A can be enabled to turn off all nonvolatile logging until a brownout event is detected. A brownout
event occurs if VCC drops below 2.9 V. In order to enable this feature, the user must provide enough local
capacitance to deliver up to 80 mA (consider additional load based on GPOs sourcing external circuits such as
LEDs) on for 5 ms while maintaining a minimum of 2.6 V at the device. If using the brownout circuit (图 7-26),
then a schottky diode should be placed so that it blocks the other circuits that are also powered from the 3.3 V
supply.
With this feature enabled, the UCD9090A saves faults, peaks, and other log data to SRAM during normal
operation of the device. Once a brownout event is detected, all data is copied from SRAM to Flash if the log is
not disabled. Use of this feature allows the UCD9090A to keep track of a single run-time clock that spans device
resets or system power down (rather than resetting the run time clock after device reset). It can also improve the
UCD9090A internal response time to events, because Flash writes are disabled during normal system operation.
This is an optional feature and can be enabled using the MISC_CONFIG command. For more details, see the
UCD90xxx Sequencer and System Health Controller PMBus Command Reference.
3.3 V
V33A
V33D
AVSS1
AVSS2
DVSS
C
图7-26. Brownout Circuit
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7.4.20 PMBus Address Selection
Two pins are allocated to decode the PMBus address. At power up, the device applies a bias current to each
address-detect pin, and the voltage on that pin is captured by the internal 12-bit ADC. The PMBus address is
calculated as follows.
PMBus Address = 12 × bin(VAD01) + bin(VAD00
)
(3)
where
• bin(VAD0x) is the address bin for one of eight addresses as shown in 表7-11
The address bins are defined by the MIN and MAX VOLTAGE RANGE (V). Each bin is a constant ratio of 1.25
from the previous bin. This method maintains the width of each bin relative to the tolerance of standard 1%
resistors.
表7-11. PMBus Address Bins
RPMBus
PMBus RESISTANCE (kΩ)
ADDRESS BIN
open
—
11
10
9
200
154
118
8
90.9
69.8
53.6
41.2
31.6
7
6
5
4
short
—
A low impedance (short) on either address pin that produces a voltage below the minimum voltage causes the
PMBus address to default to address 126 (0x7E). A high impedance (open) on either address pin that produces
a voltage above the maximum voltage also causes the PMBus address to default to address 126 (0x7E).
Address 0 is not used because it is the PMBus general-call address. Addresses 11 and 127 can not be used by
this device or any other device that shares the PMBus with it, because those are reserved for manufacturing
programming and test. It is recommended that address 126 not be used for any devices on the PMBus, because
this is the address that the UCD9090A defaults to if the address lines are shorted to ground or left open. 表 7-12
summarizes which PMBus addresses can be used. Other SMBus/PMBus addresses have been assigned for
specific devices. For a system with other types of devices connected to the same PMBus, see the SMBus device
address assignments table in Appendix C of the latest version of the System Management Bus (SMBus)
specification. The SMBus specification can be downloaded at http://smbus.org/specs/smbus20.pdf.
表7-12. PMBus Address Assignment Rules
ADDRESS
STATUS
Prohibited
Avoid
REASON
0
SMBus generaladdress call
11
Causes conflicts with other devices during program flash updates.
PMBus alert response protocol
12
Prohibited
For JTAG Use
Prohibited
126
127
Default value; may cause conflicts with other devices.
Used by TI manufacturing for device tests.
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VDD
UCD9090A
10uA
Ibias
On/Off Control
To 12-bit ADC
PMBUS_ADDR0
PMBUS_ADDR1
Resistors to set
PMBus address
Copyright © 2016, Texas Instruments Incorporated
图7-27. PMBus Address-Detection Method
备注
Address 126 (0x7E) is not recommended to be selected as a permanent PMBus address for any given
application design. Leaving the address in default state as 126 (0x7E) will enable the JTAG and not
allow using the JTAG compatible pins (27-30) as GPIOs. The UCD9090A runs at 10% slower
frequency while the JTAG is enabled to ensure best JTAG operation.
7.4.21 Device Reset
The UCD9090A has an integrated power-on reset (POR) circuit which monitors the supply voltage. At power up,
the POR detects the V33D rise. When V33D is less than VRESET, the device comes out of reset.
The device can be forced into the reset state by an external circuit connected to the RESET pin. A logic low
voltage on this pin for longer than tRESET holds the device in reset. it comes out of reset within 1 ms after RESET
is released, and can return to a logic-high level. To avoid an erroneous trigger caused by noise, connect RESET
to a 10-kΩpullup resistor (from RESET to 3.3 V) and 1000-pF capacitor (from RESET to AVSS).
Any time the device comes out of reset, it begins an initialization routine that lasts about 20 ms. During the
Initialization routine, the FPWM pins are held low. and all other GPIO and GPI pins are open-circuit. At the end of
initialization, the device begins normal operation as defined by the device configuration.
7.4.22 JTAG Interface
The JTAG port can be used for production programming. Four of the six JTAG pins can also be used as GPIOs
during normal operation. See Pin Functions and 表 7-4 for a list of the JTAG signals and which can be used as
GPIOs. The JTAG port is compatible with the IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and
Boundary Scan Architecture specification. Boundary scan is not supported on this device. The UCD9090A runs
at 10% slower frequency while the JTAG is enabled to ensure best JTAG operation.
The JTAG interface can provide an alternate interface for programming the device. It is disabled by default in
order to enable the GPIO pins with which it is multiplexed. There are two conditions under which the JTAG
interface is enabled:
1. On power-up if the data flash is blank, allowing JTAG to be used for writing the configuration parameters to a
programmed device with no PMBus interaction
2. When address 126 (0x7E) is detected at power up. A short to ground or an open condition on either address
pin will cause an address 126 (0x7E) to be generated which enables JTAG mode.
The UCD9090A system clock runs at 90% of nominal speed while in JTAG mode. For this reason it is important
that the UCD9090A is not left in JTAG mode for normal application operation.
The Fusion GUI can create SVF files (See 节 7.5) based on a given data flash configuration which can be used
to program the desired configuration by JTAG. For Boundary Scan Description Language (BSDL) file that
supports the UCD9090A see the product folder in www.ti.com.
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There are many JTAG programmers in the market and they all do not function the same. If you plan to use JTAG
to configure the device, confirm that you can reliably configure the device with your JTAG tools before
committing to a programming solution.
7.4.23 Internal Fault Management and Memory Error Correction (ECC)
The UCD9090A verifies the firmware checksum at each power up. If it does not match, then the device waits for
I2C commands but does not execute the firmware. A device configuration checksum verification is also
performed at power up. If it does not match, the factory default configuration is loaded. The PMBALERT# pin is
asserted and a flag is set in the status register. The error-log checksum validates the contents of the error log to
make sure that section of flash is not corrupted.
There is an internal firmware watchdog timer. If it times out, the device resets so that if the firmware program is
corrupted, the device goes back to a known state. This is a normal device reset, so all of the GPIO pins are
open-drain and the FPWM pins are driven low while the device is in reset. Checks are also done on each
parameter that is passed, to make sure it falls within the acceptable range.
Error-correcting code (ECC) is used to improve data integrity and provide high-reliability storage of Data Flash
contents. ECC uses dedicated hardware to generate extra check bits for the user data as it is written into the
Flash memory. This adds an additional six bits to each 32-bit memory word stored into the Flash array. These
extra check bits, along with the hardware ECC algorithm, allow for any single-bit error to be detected and
corrected when the Data Flash is read.
7.5 Programming
From the factory, the device contains the sequencing and monitoring firmware. It is also configured so that all
GPOs are high-impedance (except for FPWM/GPIO pins 10-17, which are driven low), with no sequencing or
fault-response operation. See Configuration Programming of UCD Devices, available from the Documentation &
Help Center that can be selected from the Fusion GUI Help menu, for full UCD9090A configuration details.
After the user has designed a configuration file using Fusion GUI, there are three general device-configuration
programming options:
1. Devices can be programmed in-circuit by a host microcontroller using PMBus commands over I2C (see the
UCD90xxx Sequencer and System Health Controller PMBus Command Reference).
Each parameter write replaces the data in the associated memory (RAM) location. After all the required
configuration data has been sent to the device, it is transferred to the associated nonvolatile memory (data
flash) by issuing a special command, STORE_DEFAULT_ALL. This method is how the Fusion GUI normally
reads and writes a device configuration. This method may cause unexpected behaviors on GPIO pins which
can disable rails that provide power to device. It is not recommended for production programming.
This method may cause unexpected behaviors on GPIO pins which can disable rails that provide power to
device. This method is not recommended for production programming.
2. The Fusion GUI (图7-28) can create a PMBus or I2C command script file that can be used by the I2C master
to configure the device. This method may cause unexpected behaviors on GPIO pins which can disable rails
that provide power to device. It is not recommended for production programming.
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图7-28. Fusion GUI PMBus Configuration Script Export Tool
3. Another in-circuit programming option is for the Fusion GUI to create a data flash image from the
configuration file (图7-29). The configuration files can be exported in Intel Hex, data flash script, Serial
Vector Format (SVF) and S-record. The image file can be downloaded into the device using I2C or JTAG.
The Fusion GUI tools can be used on-board if the Fusion GUI can gain ownership of the target board I2C
bus. It is recommended to use Intel Hex file or data flash script file for production programming because the
GPIOs are under controlled states.
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图7-29. Fusion GUI Device Configuration Export Tool
For small runs, a ZIF socketed board with an I2C header can be used with the standard Fusion GUI or
manufacturing GUI. The TI Evaluation Module for UCD9090A 10-Channel Sequencer and System Health
Monitor (UCD90SEQ48EVM-560) can be used for this purpose. The Fusion GUI can also create a data flash file
that can then be loaded into the UCD9090A using a dedicated device programmer.
To configure the device over I2C or PMBus, the UCD9090A must be powered. The PMBus clock and data pins
must be accessible and must be pulled high to the same VDD supply that powers the device, with pullup resistors
between 1 kΩ and 2 kΩ. Care should be taken to not introduce additional bus capacitance (<100 pF). The user
configuration can be written to data flash using a gang programmer via JTAG or I2C before the device is installed
in circuit. To use I2C, the clock and data lines must be multiplexed or the device addresses must be assigned by
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socket. The Fusion GUI tools can be used for socket addressing. Pre-programming can also be done using a
single device test fixture.
表7-13. Configuration Options
DATA FLASH VIA
DATA FLASH VIA JTAG
Data Flash Export (.svf type file)
Dedicated programmer
PMBus COMMANDS VIA I2C
I2C(Recommend)
Data Flash Export (.srec or hex,
data flash script type file)
Project file I2C/PMBus script
Off-Board Configuration
On-Board Configuration
Fusion tools (with exclusive bus
access via USB to I2C adapter)
Fusion tools (with exclusive bus
access via USB to I2C adapter)
Data flash export
IC
Fusion tools (with exclusive bus
access via USB to I2C adapter)
Fusion tools (with exclusive bus
access via USB to I2C adapter)
The advantages of off-board configuration include:
• Does not require access to device I2C bus on board.
• Once soldered on board, full board power is available without further configuration.
• Can be partially reconfigured once the device is mounted.
7.5.1 Full Configuration Update While in Normal Mode
Although performing a full configuration of the UCD9090A in a controlled test setup is recommended, there may
be times in which it is required to update the configuration while the device is in an operating system. Updating
the full configuration based on methods listed in Device Configuration and Programming section while the device
is in an operating system can be challenging because these methods do not permit the device to operate as
required by application during the programming. During described methods the GPIOs may not be in the desired
states which can disable rails that provide power to the device. To overcome this, the device has the capability to
allow full configuration update while still operating in normal mode.
Updating the full configuration while in normal mode consists of disabling data flash write protection, erasing the
data flash, writing the data flash image and reset the device. It is not required to reset the device immediately but
make note that the UCD9090A continues to operate based on previous configuration with fault logging disabled
until reset. See Configuration Programming of UCD Devices, available from the Documentation & Help Center
that can be selected from the Fusion GUI Help menu, for details. The data flash script file generated from Fusion
Digital Power Designer software has all the required PMBus commands. This is the recommended method for
production programming.
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8 Application and Implementation
备注
以下应用部分中的信息不属于 TI 元件规格,TI 不担保其准确性和完整性。TI 的客户负责确定元件是否
适合其用途,以及验证和测试其设计实现以确认系统功能。
8.1 Application Information
The UCD9090A device can be used to sequence, monitor and margin up to 10 voltage rails. Typical applications
include automatic test equipment, telecommunication and networking equipment, servers and storage systems,
and so forth. Device configuration can be performed in Fusion GUI without coding effort.
8.2 Typical Application
12V
12V OUT
TEMP12V
TEMP IC
3.3V
Supply
I12V
INA196
12V OUT
VIN
5V OUT
VOUT
GPIO1
/EN
VMON1
VMON2
VMON3
DC-DC 1
VFB
5V OUT
VIN
3.3V OUT
3.3V OUT
2.5V OUT
VOUT
GPIO2
GPIO3
GPIO4
/EN
VMON4
VMON5
VMON6
DC-DC 2
VFB
1.8V OUT
0.8V OUT
I0.8V
TEMP0.8V
I12V
VMON7
VMON8
VMON9
VMON10
VIN
2.5V OUT
VOUT
/EN
DC-DC 3
GPIO5
TEMP12V
VIN
VFB
1.8V OUT
/EN VOUT
LDO1
TEMP0.8V
UCD9090A
TEMP IC
WDI from main
processor
GPI1
0.8V OUT
VIN
VOUT
GPIO6
/EN
GPIO18
GPIO12
GPIO13
GPIO14
GPIO17
DC-DC 4
WDO
VFB
POWER_GOOD
I0.8V
INA196
Vmarg
2MHz
WARN_OC_0.8V_
OR_12V
FPWM5
Closed Loop
Margining
SYSTEM RESET
OTHER
SEQUENCER DONE
(CASCADE INPUT)
I2C/
PMBUS
JTAG
Copyright © 2016, Texas Instruments Incorporated
图8-1. Typical Application Schematic
备注
图8-1 is a simplified application schematic. Voltage dividers such as the ones placed on VMON1 input
have been omitted for simplifying the schematic. All VMONx pins which are configured to measure a
voltage that exceeds the 2.5-V ADC reference are required to have a voltage divider.
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8.2.1 Design Requirements
1. The TRST pin must have a 10-kΩpulldown resistor to ground.
2. The RESET pin should have a 10-kΩpullup resistor to V33D and a 1-nF decoupling capacitor to ground.
The components should be placed as close to the RESET pin as possible.
3. Depending on application environment, the PMBus signal integrity may be compromised at times. This will
cause the UCD9090A to receive incorrect PMBus commands. In a particular case, if (D9h) ROM_MODE
command is erroneously received by a UCD9090A device, it will cause the device to enter ROM mode, in
which mode the device will not function unless Fusion GUI is connected to the device. To avoid such
accidents in a running system, it is suggested to enable Packet Error Checking (PEC) in the PMBus host.
UCD9090A can automatically detect and work with PMBus hosts both with and without PEC enabled.
4. The fault log in UCD9090A is checksum protected. After new log entries are written into the fault log, the
checksum will be updated accordingly. After each device reset, UCD9090A recalculates the fault log
checksum and compare it with the existing checksum. If the two checksums are not the same, the device will
deem the fault log as corrupted and will erase the fault log as a result.
In the event that the V33D power is dropped before the device finish writing the fault log, the checksum will
not be updated correctly, thus the fault log will be erased at the next power-up. The results is no new faults
logged. Such an event usually happens when the main power of the board drops and no standby power can
stay alive for V33D. If such a scenario can be anticipated in an application, it is strongly suggested to use the
brown-out function and circuit as described in the previous section.
5. Do not use the RESET pin to power cycle the rails. Instead, use the PMBus_CNTRL pin as described in 节
7.4.1, or use Pin-Selected Rail States function described in 节7.4.2.
6. When a pair of FPWM pins are configured as both Rail Enable and PWM (either margining or general
purpose PWM) functions, there can be glitches on the pin that is configured as rail enable when the device is
out of reset and under initialization. These glitches may impact the connected power rail. It is not
recommended to have such a configuration.
7. PMBus commands (project file, PMBus write script file) method is not recommended for the production
programming because GPIO pins may have unexpected behaviors which can disable rails that provide
power to device. Data flash hex file or data flash script file shall be used for production programming
because GPIO pins are under controlled state.
8. It is mandatory that the V33D power shall be stable and no device reset shall be fired during the device
programming. Data flash may be corrupted if failed to follow these rules.
9. When a pair of FPWM pins are both used for margining, after device is out of reset, the even FPWM pin may
output some pulse which is up to the configured duty cycle and frequency. These pulses may cause
unexpected behaviors on the margining rail if that rail is regulated before UCD is out of reset. It is
recommended to use the even FPWM pin to margin rails that are directly controlled by the device.
8.2.2 Detailed Design Procedure
Fusion GUI can be used to design the device configuration online or offline (with or without a UCD9090A device
connected to the computer). In offline mode, Fusion GUI will prompt user to create or open a project file (.xml) at
launch. In online mode, Fusion GUI will automatically detect the device on PMBus and read the configuration
data from the device. An USB-to-GPIO Adapter EVM (HPA172) from Texas Instruments is required to connect
Fusion GUI to PMBus.
The general design steps include the following:
1. Rail setup
2. Rail monitoring configuration
3. GPI configuration
4. Rail sequence configuration
5. Fault response configuration
6. GPO configuration
7. Margining configuration
8. Other configurations such as Pin Selected Rail States, Watchdog Timer, System Reset, and so on
The details of the steps are self-explanatory in the Fusion GUI.
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After configuration changes, the user should click the Write to Hardware button to apply the changes. In online
mode, user can then click the Store RAM to Flash button to permanently store the new configuration into the
device’s data flash.
8.2.2.1 Estimating ADC Reporting Accuracy
The UCD9090A uses a 12-bit ADC and an internal 2.5-V reference (VREF) to convert MON pin inputs into
digitally reported voltages. The least significant bit (LSB) value is VLSB = VREF / 2N where N = 12, resulting in a
VLSB = 610 μV. The error in the reported voltage is a function of the ADC linearity errors and any variations in
VREF. The total unadjusted error (ETUE) for the UCD9090A ADC is ±5 LSB, and the variation of VREF is ±0.5%
between 0°C and 125°C and ±1% between –40°C and 125°C. VTUE is calculated as VLSB × ETUE. The total
reported voltage error is the sum of the reference-voltage error and VTUE. At lower monitored voltages, VTUE
dominates reported error, whereas at higher monitored voltages, the tolerance of VREF dominates the reported
error. Reported error can be calculated using 方程式 4, where REFTOL is the tolerance of VREF, VACT is the
actual voltage being monitored at the MON pin, and VREF is the nominal voltage of the ADC reference.
æ
ç
è
ö
÷
ø
V
REF ´ETUE
1+REFTOL
æ
ö
RPTERR
=
´
+ VACT -1
ç
÷
VACT
4096
è
ø
(4)
From 方程式4, for temperatures between 0°C and 125°C, if VACT = 0.5 V, then RPTERR = 1.11%. If VACT = 2.2 V,
then RPTERR = 0.64%. For the full operating temperature range of –40°C to 125°C, if VACT = 0.5 V, then
RPTERR = 1.62%. If VACT = 2.2 V, then RPTERR = 1.14%.
8.2.3 Application Curves
PMBus Control Pin Assertion
PMBus Control Pin De-assertion
Rail 1 EN with 5ms turn-off delay
Rail 1 EN with 5ms turn-on delay
Rail 2 EN with 10ms turn-on delay
Rail 2 EN with 10ms turn-off delay
Rail 3 EN with 15ms turn-on delay
Rail 3 EN with 15ms turn-off delay
图8-2. Example Power-On Sequence
图8-3. Example Power-Off Sequence
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9 Power Supply Recommendations
Power the UCD9090A with a 3.3-V power supply. During the power-up sequence, the voltage on the V33D pin
must ascend from 2.3 V to 2.9 V monotonically with a minimum slew rate of 0.25 V/ms.
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10 Layout
10.1 Layout Guidelines
The thermal pad provides a thermal and mechanical interface between the device and the printed circuit board
(PCB). Connect the exposed thermal pad of the PCB to the device VSS pins and provide at least a 4 × 4 pattern
of PCB vias to connect the thermal pad and VSS pins to the circuit ground on other PCB layers.
For supply-voltage decoupling, provide power supply pin bypass to the device as follows:
• 1-μF, X7R ceramic in parallel with 0.01-μF, X7R ceramic at pin 35 (BPCAP)
• 0.1-μF, X7R ceramic in parallel with 4.7-μF, X5R ceramic at pin 33 (V33D)
• 0.1-μF, X7R ceramic in parallel with 4.7-μF, X5R ceramic at pin 34 (V33A)
• Connect V33D (pin 33) to 3.3V supply directly. Connect V33A (pin 34) to V33D through a 4.99-Ωresistor.
This resistor and V33A decoupling capacitors form a low-pass filter to reduce noise on V33A.
Depending on use and application of the various GPIO signals used as digital outputs, some impedance control
may be desired to quiet fast signal edges. For example, when using the FPWM pins for fan control or voltage
margining, the pin is configured as a digital clock signal. Route these signals away from sensitive analog signals.
It is also good design practice to provide a series impedance of 20 Ω to 33 Ω at the signal source to slow fast
digital edges.
10.2 Layout Example
BPCAP 10nF
V33A 0.1µF
Thermal pad vias to
GND plane layer
V33D 0.1µF
图10-1. UCD9090A Layout Example, Top Layer
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BPCAP 1µF
Resistors to set
PMBus address
V33A 4.7µF
nRESET 10kO pull-up
and 1nF decoupling
V33D 4.7µF
3.3V supply
4.99O between
V33D and V33A
nTRST 10kO pull-down
图10-2. UCD9090A Layout Example, Bottom Layer
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• Monitoring Voltage, Current, and Temperature Using the UCD90xxx Devices, SLVA385
• UCD90xxx Sequencer and System Health Controller PMBus™ Command Reference, SLVU352
• UCD90SEQ48EVM-560: 48-Pin Sequencer Development Board, SLVU464
• Voltage Margining Using the UCD90120, SLVA375
11.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
11.4 Trademarks
PMBus™ is a trademark of SMIF, Inc.
Fusion Digital Power™ is a trademark of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Mar-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
UCD9090ARGZR
UCD9090ARGZT
ACTIVE
ACTIVE
VQFN
VQFN
RGZ
RGZ
48
48
2500 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
UCD9090A
UCD9090A
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Mar-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCD9090ARGZR
UCD9090ARGZT
VQFN
VQFN
RGZ
RGZ
48
48
2500
250
330.0
180.0
16.4
16.4
7.3
7.3
7.3
7.3
1.1
1.1
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
UCD9090ARGZR
UCD9090ARGZT
VQFN
VQFN
RGZ
RGZ
48
48
2500
250
367.0
210.0
367.0
185.0
38.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGZ 48
7 x 7, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A
www.ti.com
PACKAGE OUTLINE
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
A
7.1
6.9
B
(0.1) TYP
7.1
6.9
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
PIN 1 INDEX AREA
(0.45) TYP
CHAMFERED LEAD
CORNER LEAD OPTION
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 5.5
5.15±0.1
(0.2) TYP
13
24
44X 0.5
12
25
SEE SIDE WALL
DETAIL
SYMM
2X
5.5
1
36
0.30
0.18
PIN1 ID
(OPTIONAL)
48X
48
37
SYMM
0.1
C A B
C
0.5
0.3
48X
0.05
SEE LEAD OPTION
4219044/D 02/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
5.15)
SYMM
(
48X (0.6)
37
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(1.26)
2X
(1.065)
(R0.05)
TYP
25
12
21X (Ø0.2) VIA
TYP
24
13
2X (1.065)
2X (1.26)
2X (5.5)
LAND PATTERN EXAMPLE
SCALE: 15X
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219044/D 02/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
SYMM
(
1.06)
37
48X (0.6)
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(0.63)
2X
(1.26)
(R0.05)
TYP
25
12
24
13
2X
(1.26)
2X (0.63)
2X (5.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
67% PRINTED COVERAGE BY AREA
SCALE: 15X
4219044/D 02/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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