V62/03608-01XE_技术文档

THS1401-EP THS1403-EP THS1408-EP

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SGLS129A – JULY 2002 – REVISED NOVEMBER 2002

Integral Nonlinearity (INL) ±1.5 LSB Typ

features

Internal Reference

Controlled Baseline

– One Assembly/Test Site, One Fabrication

Differential Inputs

Site

Programmable Gain Amplifier

µP Compatible Parallel Interface

Timing Compatible With TMS320C6000 DSP

3.3-V Single Supply

Extended Temperature Performance up to

–55°C to 125°C

Enhanced Diminishing Manufacturing

Sources (DMS) Support

Power-Down Mode

Enhanced Product Change Notification

Monolithic CMOS Design

†

Qualification Pedigree

14-Bit Resolution

applications

1, 3, and 8 MSPS Speed Grades

Differential Nonlinearity (DNL) ±0.6 LSB Typ

xDSL Front Ends

Communication

†

Component qualification in accordance with JEDEC and industry

standards to ensure reliable operation over an extended

temperature range. This includes, but is not limited to, Highly

Accelerated Stress Test (HAST) or biased 85/85, temperature

cycle, autoclave or unbiased HAST, electromigration, bond

intermetallic life, and mold compound life. Such qualification

testing should not be viewed as justifying use of this component

beyond specified performance and environmental limits.

Industrial Control

Instrumentation

Automotive and Selected Military

PHP PACKAGE

(TOP VIEW)

48 47 46 45 44 43 42 41 40 39 38 37

36

35

34

33

32

31

30

29

28

27

26

25

WR

OE

DGND

CLK

IN–

1

2

3

4

5

6

7

8

9

AV

DD

VBG

CML

REF+

REF–

AGND

DGND

DV

DD

DV

DD

D0

D1

D2

OV 10

D13 11

D12 12

DV

DD

DGND

13 14 15 16 17 18 19 20 21 22 23 24

NC – No internal connection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1401-EP THS1403-EP THS1408-EP

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SGLS129A – JULY 2002 – REVISED NOVEMBER 2002

description

The THS1401, THS1403, and THS1408 are 14-bit, 1/3/8 MSPS, single supply analog-to-digital converters with an

internal reference, differential inputs, programmable input gain, and an on-chip sample and hold amplifier.

Implemented with a CMOS process, the device has outstanding price/performance and power/speed ratios. The

THS1401, THS1403, and THS1408 are designed for use with 3.3-V systems, and with a high-speed µP compatible

parallel interface, making them the first choice for solutions based on high-performance DSPs like the TI

TMS320C6000 series.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

T

A

–40°C to 125°C

–55°C to 125°C

PQFP – PHP

THS1401QPHPEP

THS1403QPHPEP

THS1408MPHPEP

THS1401QE

THS1403QE

THS1408ME

†

Packagedrawings, standardpackingquantities, thermaldata, symbolization, andPCBdesign

guidelines are available at www.ti.com/sc/package.

functional block diagram

VBG

REF+

REF

REF–

1.5 V

BG

IN+

14

15

PGA

14-Bit

ADC

D[13:0] + OV bit

Buffer

0..7 dB

IN–

6

A[1:0]

CLK

CONTROL

LOGIC

CS

WR

OE

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1401-EP THS1403-EP THS1408-EP

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SGLS129A – JULY 2002 – REVISED NOVEMBER 2002

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

A[1:0]

40, 41

I

Address input

Analog ground

AGND

7,8, 44,

45, 46

AV

DD

2, 43, 47

Analog power supply

Clock input

CLK

CML

CS

32

4

I

Reference midpoint. This pin requires a 0.1-µF capacitor to AGND.

Chip select input. Active low

37

DGND

9, 15, 25,

33, 34

Digital ground

DV

14, 20, 26,

30, 31, 42

Digital power supply

DD

D[13:0] 11, 12, 13, I/O Data inputs/outputs

16, 17, 18,

19, 21, 22,

23, 24, 27,

28, 29

NC

38, 39

48

1

No connection, do not use. Reserved

IN+

I

Positive differential analog input

IN–

Negative differential analog input

OE

35

10

5

I

Output enable. Active low

OV

O

I

Out of range output

REF+

REF–

VBG

WR

Positive reference output. This pin requires a 0.1-µF capacitor to AGND.

Negative reference output. This pin requires a 0.1-µF capacitor to AGND.

Reference input. This pin requires a 1-µF capacitor to AGND.

Write signal. Active low

6

3

36

I

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1401-EP THS1403-EP THS1408-EP

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SGLS129A – JULY 2002 – REVISED NOVEMBER 2002

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage, (AV

Supply voltage, (DV

to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V

to DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4V

DD

Reference input voltage range, VBG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to AV

Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to AV

Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to DV

+ 0.3 V

DD

Operating free-air temperature range, T : Q suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C

A

M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C

Storage temperature range, T

Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

TYP

28.8

0.79

UNIT

°C/W

Thermal resistance, junction-to-ambient, Θ

JA

Thermal resistance, junction-to-case, Θ

JC

Thermal resistance is modeled data, is not production tested, and is given for informational purposes only.

†

recommended operating conditions

MIN NOM

MAX

UNIT

V

Supply voltage, AV , DV

DD DD

3

2

3.3

0

3.6

High level digital input, V

IH

V

Low level digital input, V

IL

V

0.8

15

Load capacitance, C

5

pF

L

THS1401

THS1403

THS1408

0.1

1

3

MHz

Clock frequency, f

3

CLK

0.1

8

Clock duty cycle

45%

–40

–55

50%

25

55%

125

Q suffix

M suffix

Operating free-air temperature

°C

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1401-EP THS1403-EP THS1408-EP

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SGLS129A – JULY 2002 – REVISED NOVEMBER 2002

electrical characteristics over recommended operating free-air temperature range,

AV

= DV

= 3.3 V (unless otherwise noted)

DD

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Power Supply

I

Analog supply current

Digital supply current

Power

AV

DD

= 3.6 V

81

5

90

10

mA

mW

µA

DDA

DDD

I

DV

DD

AV

= DV

= 3.6 V

270

20

360

DD

Power down current

DC Characteristics

Resolution

14

±0.6

±1.5

±2

Bits

DNL

INL

Differential nonlinearity

±1

±2.5

±3

LSB

THS1401

THS1403

THS1408

Integral nonlinearity

Best fit

LSB

±3.5

±7.5

Offset error

Gain error

IN+ = IN–, PGA = 0 dB

0.3 %FSR

1.75 %FSR

PGA = 0 dB

AC Characteristics

ENOB

Effective number of bits

11.2

11.5

–81

–78

–77

72

Bits

dB

THS1401/3/8

THS1403/8

THS1408

f = 100 kHz

i

THD

Total harmonic distortion

Signal-to-noise ratio

f = 1 MHz

i

f = 4 MHz

i

THS1401/3/8

THS1403/8

THS1408

f = 100 kHz

i

SNR

f = 1 MHz

i

70

69

71

72

dB

f = 4 MHz

i

71

THS1401/3/8

THS1403/8

THS1408

f = 100 kHz

i

70

SINAD Signal-to-noise ratio + distortion

f = 1 MHz

i

70

f = 4 MHz

i

70

THS1401/3/8

THS1403, THS1408

THS1408

f = 100 kHz

i

80

SFDR

Spurious free dynamic range

Analog input bandwidth

f = 1 MHz

i

80

dB

f = 4 MHz

i

80

140

MHz

5

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THS1401-EP THS1403-EP THS1408-EP

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SGLS129A – JULY 2002 – REVISED NOVEMBER 2002

electrical characteristics over recommended operating free-air temperature range,

AV

= DV

= 3.3 V (unless otherwise noted) (continued)

DD

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Reference Voltage

Bandgap voltage, internal mode

Input impedance

1.425

1.5 1.575

V

kΩ

V

VBG

40

2.5

0.5

2

Positive reference voltage, REF+

Negative reference voltage, REF–

Reference difference, ∆REF, REF+ – REF–

Accuracy, internal reference

Temperature coefficient

V

5%

40

ppm/°C

Voltage coefficient

200

ppm/V

Analog Inputs

Positive analog input, IN+

0

AV

V

DD

Negative analog input, IN–

Analog input voltage difference

Input impedance

DD

∆Ain = IN+ – IN–, V = REF+ – REF–

ref

–V

V

ref

25

1

kΩ

dB

PGA range

0

7

PGA step size

PGA gain error

±0.25

Digital Inputs

V

High-level digital input

Low-level digital input

Input capacitance

Input current

2

V

IH

IL

V

0.8

5

pF

µA

±1

Digital Outputs

V

High-level digital output

I

= 50 µA

2.6

V

OH

Low-level digital output

0.4

OL

I

Output current, high impedance

±10

µA

OZ

Clock Timing (CS low)

†

THS1401

THS1403

THS1408

0.1

1

3

8

1

3

MHz

ns

f

t

Clock frequency

CLK

8

Output delay time

Latency

25

d

9.5

Cycles

†

This parameter is not production tested.

6

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THS1401-EP THS1403-EP THS1408-EP

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SGLS129A – JULY 2002 – REVISED NOVEMBER 2002

PARAMETER MEASUREMENT INFORMATION

sample timing

The THS1401/3/8 core is based on a pipeline architecture with a latency of 9.5 samples. The conversion results

appear on the digital output 9.5 clock cycles after the input signal was sampled.

S11

S12

S9

S10

Analog

Input

t

w(CLK)

CLK

t

d

Data

Out

C3

C1

C2

Figure 1. Sample Timing

The parallel interface of the THS1401/3/8 ADC features 3-state buffers, making it possible to directly connect it to

a data bus. The output buffers are enabled by driving the OE input low.

Besides the sample results, it is also possible to read back the values of the control register, the PGA register, and

the offset register. Which register is read is determined by the address inputs A[1,0]. The ADC results are available

at address 0.

The timing of the control signals is described in the following sections.

7

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THS1401-EP THS1403-EP THS1408-EP

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SGLS129A – JULY 2002 – REVISED NOVEMBER 2002

PARAMETER MEASUREMENT INFORMATION

read timing (15-pF load)

PARAMETER

Address and chip select setup time

MIN

TYP

MAX

UNIT

ns

t

4

su(OE–ACS)

Output enable

15

ns

en

Output disable

10

ns

dis

Address hold time

Chip select hold time

1

0

ns

h(A)

h(CS)

ns

NOTE: All timing parameters refer to a 50% level.

CS

t

h(CS)

OE

t

en

t

su(OE–ACS)

dis

DATA

D[13:0]

O V

t

h(A)

A[1:0]

X

ADDRESS

X

Figure 2. Read Timing

8

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THS1401-EP THS1403-EP THS1408-EP

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SGLS129A – JULY 2002 – REVISED NOVEMBER 2002

PARAMETER MEASUREMENT INFORMATION

write timing (15-pF load)

PARAMETER

MIN

4

TYP

MAX

UNIT

ns

t

Chip select setup time

su(WE–CS)

Data and address setup time

Data and address hold time

Chip select hold time

29

0

ns

su(DA)

ns

h(DA)

0

ns

h(CS)

Write pulse duration high

15

ns

wH(WE)

NOTE: All timing parameters refer to a 50% level.

CS

t

h(CS)

WE

t

su(WE–CS)

t

su(DA)

X

DATA

D[13:0]

t

h(DA)

X

A

ADDRESS

Figure 3. Write Timing

9

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THS1401-EP THS1403-EP THS1408-EP

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SGLS129A – JULY 2002 – REVISED NOVEMBER 2002

TYPICAL CHARACTERISTICS

POWER

vs

SUPPLY CURRENT

vs

FREQUENCY

TIME

90

80

70

60

50

40

30

20

10

0

284

282

280

278

276

274

272

270

268

0

50

100

150

200

250

300

0.1

1

10

f – Frequency – MHz

t – Time – ns

Figure 4

Figure 5

FAST FOURIER TRANSFORM

0

f

= 1 MSPS,

s

–20

f = 100 kHz,

I

–1 dB

–40

–60

–80

–100

–120

–140

0

100

200

300

400

500

f – Frequency – kHz

Figure 6

10

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THS1401-EP THS1403-EP THS1408-EP

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SGLS129A – JULY 2002 – REVISED NOVEMBER 2002

TYPICAL CHARACTERISTICS

FAST FOURIER TRANSFORM

0

f

= 3 MSPS,

s

–20

–40

f = 1 MHz,

I

–1 dB

–60

–80

–100

–120

–140

0.1

0.4

0.7

1

1.3

f – Frequency – MHz

Figure 7

FAST FOURIER TRANSFORM

0

f

= 8 MSPS,

s

–20

f = 1 MHz,

I

–1 dB

–40

–60

–80

–100

–120

–140

2.2

0.1

0.4

0.7

1

1.3

1.6

1.9

2.5

2.8

3.1

3.4

3.7

4

f – Frequency – MHz

Figure 8

INTEGRAL NONLINEARITY

2

f

= 1 MSPS

s

1.5

1

0.5

0

–0.5

–1

–1.5

–2

0

2048

4096

6144

8192

10240

12288

14336

16384

Samples

Figure 9

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1401-EP THS1403-EP THS1408-EP

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SGLS129A – JULY 2002 – REVISED NOVEMBER 2002

TYPICAL CHARACTERISTICS

INTEGRAL NONLINEARITY

2

f

= 3 MSPS

1.5

s

1

0.5

0

–0.5

–1

–1.5

–2

0

2048

4096

6144

8192

10240

12288

14336

16384

Samples

Figure 10

INTEGRAL NONLINEARITY

4

3

2

1

0

f

= 8 MSPS

s

–1

–2

–3

–4

0

2048

4096

6144

8192

10240

12288

14336

16384

Samples

Figure 11

DIFFERENTIAL NONLINEARITY

1

0.8

0.6

0.4

0.2

f

= 1 MSPS

s

0

–0.2

–0.4

–0.6

–0.8

–1

0

2048

4096

6144

8192

10240

12288

14336

16384

Samples

Figure 12

12

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THS1401-EP THS1403-EP THS1408-EP

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SGLS129A – JULY 2002 – REVISED NOVEMBER 2002

TYPICAL CHARACTERISTICS

DIFFERENTIAL NONLINEARITY

1

f

= 3 MSPS

0.8

0.6

0.4

0.2

s

0

–0.2

–0.4

–0.6

–0.8

–1

0

2048

4096

6144

8192

10240

12288

14336

16384

Samples

Figure 13

DIFFERENTIAL NONLINEARITY

1

f

= 8 MSPS

0.8

0.6

0.4

0.2

s

0

–0.2

–0.4

–0.6

–0.8

–1

0

2048

4096

6144

8192

10240

12288

14336

16384

Samples

Figure 14

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1401-EP THS1403-EP THS1408-EP

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SGLS129A – JULY 2002 – REVISED NOVEMBER 2002

TYPICAL CHARACTERISTICS

TOTAL HARMONIC DISTORTION

vs

FREQUENCY

–70

–72

–74

–76

–78

–80

–82

–84

–86

–88

–90

–70

–72

–74

–76

–78

–80

–82

–84

–86

–88

–90

f

= 8 MSPS,

f

= 3 MSPS,

s

I

s

I

f at –1 dB

10

100

1000

4000

10

100

1000 1500

f – Frequency – Hz

Figure 15

Figure 16

SIGNAL-TO-NOISE RATIO

vs

FREQUENCY

80

78

76

74

72

70

68

66

64

62

60

80

78

76

74

72

70

68

66

64

62

60

f

= 3 MSPS,

f = 8 MSPS,

s

I

s

I

f at –1 dB

100

10

1000 1500

100

4000

10

1000

f – Frequency – Hz

Figure 17

Figure 18

14

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THS1401-EP THS1403-EP THS1408-EP

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SGLS129A – JULY 2002 – REVISED NOVEMBER 2002

PRINCIPLES OF OPERATION

registers

The device contains several registers. The A register is selected by the values of bits A1 and A0:

A1

0

A0

0

Register

Conversion result

PGA

0

1

0

Offset

1

Control

Tables 1 and 2 describe how to read the conversion results and how to configure the data converter. The default

values (were applicable) show the state after a power-on reset.

Table 1. Conversion Result Register, Address 0, Read

BIT

D13

D12

...

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Function

MSB

…

LSB

The output can be configured for two’s complement or straight binary format (see D11/control register).

The output code is given by:

2s complement:

Straight binary:

–8192 at ∆IN = –∆REF

0

at ∆IN = –∆REF

0

at ∆IN = 0

8192 at ∆IN = 0

8191 ∆IN = –∆REF – 1 LSB

16383 at ∆IN = –∆REF – 1 LSB

2 REF

1 LSB

16384

Table 2. PGA Gain Register, Address 1, Read/Write

BIT

D13

X

D12

X

D11

X

D10

X

D9

X

D8

X

D7

X

D6

X

D5

X

D4

X

D3

X

D2

G2

0

D1

G1

0

D0

G0

0

Function

Default

0

The PGA gain is determined by writing to G2–0.

Gain (dB) = 1dB × G2–0. max = 7dB. The range of G2–0 is 0 to 7.

Table 3. Offset Register, Address 2, Read/Write

BIT

D13

X

D12

X

D11

X

D10

X

D9

X

D8

X

D7

MSB

0

D6

…

0

D5

…

0

D4

…

0

D3

…

0

D2

…

0

D1

…

0

D0

LSB

0

Function

Default

0

The offset correction range is from –128 to 127 LSB. This value is added to the conversion results from the ADC.

15

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14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SGLS129A – JULY 2002 – REVISED NOVEMBER 2002

PRINCIPLES OF OPERATION

Table 4. Control Register, Address 3, Read

BIT

D13

D12

REF

D11

D10

TM2

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Function

PWD

FOR

TM1

TM0

OFF

RES

Table 5. Control Register, Address 3, Write

BIT

D13

PWD

0

D12

REF

0

D11

FOR

0

D10

TM2

0

D9

TM1

0

D8

TM0

0

D7

OFF

0

D6

RES

0

D5

RES

0

D4

RES

0

D3

RES

0

D2

RES

0

D1

RES

0

D0

RES

0

Function

Default

PWD:

REF:

FOR:

Power down

0 = normal operation

0 = internal reference

0 = straight binary

1 = power down

Reference select

Output format

1 = external reference

1 = 2s complement

TM2–0: Test mode

000 = normal operation

001 = both inputs = REF–

010 = IN+ at V /2, IN– at REF–

ref

011 = IN+ at REF+, IN– at REF–

100 = normal operation

101 = both inputs = REF+

110 = IN+ at REF–, IN– at V /2

ref

111 = IN+ at REF–, IN– at REF+

OF:

Offset correction

Reserved

0 = enable

1 = disable

RES

Must be set to 0.

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1401-EP THS1403-EP THS1408-EP

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SGLS129A – JULY 2002 – REVISED NOVEMBER 2002

APPLICATION INFORMATION

driving the analog input

The THS1401/3/8 ADCs have a fully differential input. A differential input is advantageous with respect to SNR,

SFDR, and THD performance because the signal peak-to-peak level is 50% of a comparable single-ended input.

There are three basic input configurations:

Fully differential

Transformer coupled single-ended to differential

Single-ended

fully differential configuration

In this configuration, the ADC converts the difference (∆IN) of the two input signals on IN+ and IN–.

22 Ω

IN+

100 pF

THS1401/3/8

22 Ω

IN–

100 pF

Figure 19. Differential Input

The resistors and capacitors on the inputs decouple the driving source output from the ADC input and also serve

as first order low pass filters to attenuate out of band noise.

The input range on both inputs is 0 V to AV . The full-scale value is determined by the voltage reference. The

DD

positive full-scale output is reached, if ∆IN equals ∆REF, the negative full-scale output is reached, if ∆IN equals

–∆REF.

∆IN [V]

–∆REF

0

OUTPUT

– full scale

0

∆REF

+ full scale

17

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THS1401-EP THS1403-EP THS1408-EP

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SGLS129A – JULY 2002 – REVISED NOVEMBER 2002

APPLICATION INFORMATION

transformer coupled single-ended to differential configuration

If the application requires the best SNR, SFDR, and THD performance, the input should be transformer coupled.

The signal amplitude on both inputs of the ADC is one half as high as in a single-ended configuration thus increasing

the ADC ac performance.

22 Ω

IN+

100 pF

R

THS1401/3/8

22 Ω

IN–

CML

100 pF

+

1 µF

0.1 µF

Figure 20. Transformer Coupled

Thefollowingtableshowstheinputvoltagesfornegativefull-scaleoutput, zerooutput, andpositivefull-scaleoutput:

IN [V

PEAK

–∆REF

]

OUTPUT [ ]

PEAK

†

– full scale

0

†

∆REF

n = 1 (winding ratio)

+ full scale

†

The resistor R of the transformer coupled input configuration must be set to match the signal source impedance R

2

= n Rs, where Rs is the source impedance and n is the transformer winding ratio.

18

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14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SGLS129A – JULY 2002 – REVISED NOVEMBER 2002

APPLICATION INFORMATION

single-ended configuration

In this configuration, the input signal is level shifted by ∆REF/2.

10 kΩ + 10 kΩ

REF+

IN+

10 kΩ 10 kΩ

100 pF

THS1401/3/8

22 Ω

–

IN–

REF–

100 pF

+

10 kΩ

Figure 21. Single-Ended With Level Shift

Thefollowingtableshowstheinputvoltagesfornegativefull-scaleoutput, zerooutput, andpositivefull-scaleoutput:

∆IN+ [V]

–∆REF

0

OUTPUT

– full scale

0

∆REF

+ full scale

Note that the resistors of the op-amp and the op-amp all introduce gain and offset errors. Those errors can be

trimmed by varying the values of the resistors.

Because of the added offset, the op-amp does not necessarily operate in the best region of its transfer curve (best

linearity around zero) and therefore may introduce unacceptable distortion. For ac signals, an alternative is

described in the following section.

19

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14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SGLS129A – JULY 2002 – REVISED NOVEMBER 2002

APPLICATION INFORMATION

AC-coupled single-ended configuration

If the application does not require the signal bandwidth to include dc, the level shift shown in Figure 4 is not

necessary.

10 kΩ

REF+

IN+

10 kΩ

100 pF

THS1401/3/8

10 nF

–

IN–

REF–

22 Ω

+

10 kΩ

Figure 22. Single-Ended With Level Shift

Because the signal swing on the op-amp is centered around ground, it is more likely that the signal stays within the

linear region of the op-amp transfer function, thus increasing the overall ac performance.

IN [V

PEAK

–∆REF

]

OUTPUT [ ]

PEAK

– full scale

0

∆REF

+ full scale

Compared to the transformer-coupled configuration, the swing on IN– is twice as big, which can decrease the ac

performance (SNR, SFD, and THD).

20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS1401-EP THS1403-EP THS1408-EP

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SGLS129A – JULY 2002 – REVISED NOVEMBER 2002

APPLICATION INFORMATION

internal/external reference operation

The THS1401/3/8 ADC can either be operated using the built-in band gap reference or using an external precision

reference in case very high dc accuracy is needed.

The REF+ and REF+ outputs are given by:

2

3

2

3

REF

VBG 1

and REF–

VBG 1–

If the built-in reference is used, VBG equals 1.5 V which results in REF+ = 2.5 V, REF– = 0.5 V and ∆REF = 2 V.

The internal reference can be disabled by writing 1 to D12 (REF) in the control register (address 3). The band gap

reference is then disconnected and can be substituted by a voltage on the VBG pin.

programmable gain amplifier

The on-chip programmable gain amplifier (PGA) has eight gain settings. The gain can be changed by writing to the

PGA gain register (address 1). The range is 0 to 7dB in steps of one dB.

out of range indication

The OV output of the ADC indicates an out of range condition. Every time the difference on the analog inputs

exceeds the differential reference, this signal is asserted. This signal is updated the same way as the digital data

outputs and therefore subject to the same pipeline delay.

offset compensation

With the offset register it is possible to automatically compensate system offset errors, including errors caused by

additional signal conditioning circuitry. If the offset compensation is enabled (D7 (OFF) in the control register), the

value in the offset register (address 2) is automatically subtracted from the output of the ADC.

In order to set the correct value of the offset compensation register, the ADC result when the input signal is 0 must

be read by the host processor and written to the offset register (address 2).

test modes

TheADCcoreoperationcanbetestedbyselectingoneoftheavailabletestmodes(seecontrolregisterdescription).

The test modes apply various voltages to the differential input depending on the setting in the control register.

digital I/O

The digital inputs and outputs of the THS1401/3/8 ADC are 3-V CMOS compatible. In order to avoid current feed

back errors, the capacitive load on the digital outputs should be as low as possible (50 pF max). Series resistors

(100 Ω) on the digital outputs can improve the performance by limiting the current during output transitions.

The parallel interface of the THS1401/3/8 ADC features 3-state buffers, making it possible to directly connect it to

a data bus. The output buffers are enabled by driving the OE input low.

Refer to the read and write timing diagrams in the parameter measurement information section for information on

read and write access.

21

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THS1401-EP THS1403-EP THS1408-EP

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SGLS129A – JULY 2002 – REVISED NOVEMBER 2002

MECHANICAL DATA

PHP (S-PQFP-G48)

PowerPAD PLASTIC QUAD FLATPACK

0,27

0,17

M

0,50

36

0,08

25

37

24

Thermal Pad

(see Note D)

48

13

0,13 NOM

1

12

5,50 TYP

Gage Plane

7,20

SQ

6,80

0,25

9,20

SQ

8,80

0,15

0,05

0°–7°

1,05

0,95

0,75

0,45

Seating Plane

0,08

1,20 MAX

4146927/A 01/98

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion.

D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.

This pad is electrically and thermally connected to the backside of the die and possibly selected leads.

E. Falls within JEDEC MS-026

PowerPAD is a trademark of Texas Instruments.

22

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

5-Feb-2007

PACKAGING INFORMATION

Orderable Device

THS1401QPHPEP

THS1403QPHPEP

THS1408MPHPEP

V62/03608-01XE

V62/03608-02XE

V62/03608-03XE

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

HTQFP

PHP

48

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

HTQFP

PHP

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

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RF/IF and ZigBee® Solutions www.ti.com/lprf

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	V62/03608-01XE
厂家：	TEXAS INSTRUMENTS
描述：	14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH INTERNAL REFERENCE AND PGA 14位1/3/8 MSPS DSP兼容模拟数字转换器具有内部参考和PGA 转换器
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V62/03608-01XE [TI]

相关型号：

V62/03608-02XE

V62/03608-03XE

V62/03609-01XE

V62/03610-01XE

V62/03610-02YA

V62/03611-01XE

V62/03612-01XE

V62/03612-02XE

V62/03613-01XE

V62/03613-02XE

V62/03614-01XE

V62/03614-02YE