V62/04712-01YE [TI]
具有三态输出的增强型产品 3.3V Abt 16 位透明 D 类锁存器 | DL | 48 | -40 to 85;
| 型号： | V62/04712-01YE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有三态输出的增强型产品 3.3V Abt 16 位透明 D 类锁存器 | DL | 48 | -40 to 85 驱动 锁存器 总线驱动器 总线收发器 |
| 文件： | 总12页 (文件大小：462K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCBS778A − NOVEMBER 2003 − REVISED MARCH 2004
D
D
D
D
D
Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D
D
D
Flow-Through Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 500 mA Per
JESD 17
Enhanced Diminishing Manufacturing
Sources (DMS) Support
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
Enhanced Product-Change Notification
†
Qualification Pedigree
Member of the Texas Instruments
Widebus Family
DGG OR DL PACKAGE
(TOP VIEW)
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Q1
1Q2
GND
1Q3
1Q4
1LE
1D1
1D2
GND
1D3
1D4
2
3
4
D
Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
5
6
3.3-V V
)
CC
7
V
V
CC
CC
D
D
D
D
Supports Unregulated Battery Operation
Down to 2.7 V
8
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
9
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
= 3.3 V, T = 25°C
A
I
and Power-Up 3-State Support Hot
off
Insertion
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Distributed V
High-Speed Switching Noise
and GND Pins Minimize
CC
V
V
CC
CC
†
2Q5
2Q6
GND
2Q7
2Q8
2OE
2D5
2D6
GND
2D7
2D8
2LE
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
description/ordering information
The SN74LVTH16373 is a 16-bit transparent D-type latch with 3-state outputs designed for low-voltage (3.3-V)
operation, but with the capability to provide a TTL interface to a 5-V system environment. This device is
V
CC
particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the
Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the
D inputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
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Copyright 2004, Texas Instruments Incorporated
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ꢠ ꢤ ꢡ ꢠꢙ ꢚꢭ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢎ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢂ ꢊꢋ ꢌꢍ
ꢊꢎ ꢊꢋꢅ ꢏ ꢐ ꢆ ꢈ ꢉꢋ ꢐꢑ ꢆ ꢆꢒ ꢏꢁ ꢀꢍꢏꢒ ꢌꢁ ꢆ ꢓꢋꢆ ꢔ ꢍꢌ ꢄ ꢏꢆ ꢕꢇ
ꢖꢑ ꢆ ꢇ ꢊ ꢋꢀꢆꢏꢆ ꢌ ꢗꢘꢆ ꢍ ꢘꢆꢀ
SCBS778A − NOVEMBER 2003 − REVISED MARCH 2004
description/ordering information (continued)
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
When V
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup resistor;
CC
This device is fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
GQL OR ZQL PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1OE
1Q2
1Q4
1Q6
1Q8
2Q1
2Q3
2Q5
2Q7
2OE
NC
NC
NC
NC
1LE
1D2
1D4
1D6
1D8
2D1
2D3
2D5
2D7
2LE
A
B
C
D
E
F
1Q1
1Q3
1Q5
1Q7
2Q2
2Q4
2Q6
2Q8
NC
GND
GND
1D1
1D3
1D5
1D7
2D2
2D4
2D6
2D8
NC
V
CC
V
CC
GND
GND
G
H
J
GND
GND
G
H
J
V
CC
V
CC
GND
NC
GND
NC
K
K
NC − No internal connection
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
SSOP − DL
Tape and reel CLVTH16373IDLREP
LH16373EP
TSSOP − DGG Tape and reel CLVTH16373IDGGREP
LH16373EP
−40°C to 85°C
VFBGA − GQL
CLVTH16373IGQLREP
CLVTH16373IZQLREP
Tape and reel
LL373EP
VFBGA − ZQL
(Pb-free)
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢖ ꢑꢆ ꢇ ꢊ ꢋꢀꢆꢏꢆ ꢌ ꢗ ꢘꢆ ꢍ ꢘꢆꢀ
SCBS778A − NOVEMBER 2003 − REVISED MARCH 2004
FUNCTION TABLE
(each 8-bit section)
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
logic diagram (positive logic)
1
24
25
2OE
2LE
1OE
48
1LE
C1
1D
C1
2
13
2Q1
1Q1
47
36
2D1
1D1
1D
To Seven Other Channels
To Seven Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Current into any output in the low state, I
Current into any output in the high state, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA
O
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
GQL/ZQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51-7.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢂ ꢊꢋ ꢌꢍ
ꢊꢎ ꢊꢋꢅ ꢏ ꢐ ꢆ ꢈ ꢉꢋ ꢐꢑ ꢆ ꢆꢒ ꢏꢁ ꢀꢍꢏꢒ ꢌꢁ ꢆ ꢓꢋꢆ ꢔ ꢍꢌ ꢄ ꢏꢆ ꢕꢇ
ꢖꢑ ꢆ ꢇ ꢊ ꢋꢀꢆꢏꢆ ꢌ ꢗꢘꢆ ꢍ ꢘꢆꢀ
SCBS778A − NOVEMBER 2003 − REVISED MARCH 2004
recommended operating conditions (see Note 4)
MIN
2.7
2
MAX
UNIT
V
V
V
V
V
Supply voltage
3.6
CC
High-level input voltage
Low-level input voltage
Input voltage
V
IH
0.8
5.5
−32
64
V
IL
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
mA
mA
ns/V
µs/V
°C
OH
OL
∆t/∆v
∆t/∆V
Outputs enabled
10
200
−40
CC
T
A
Operating free-air temperature
85
NOTE 4: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇ ꢈꢉ ꢊꢂ ꢊꢋ ꢌꢍ
ꢊ ꢎꢊ ꢋꢅ ꢏꢐꢆ ꢈ ꢉ ꢋꢐꢑ ꢆ ꢆ ꢒꢏꢁꢀ ꢍꢏꢒꢌ ꢁꢆ ꢓꢋꢆ ꢔꢍ ꢌ ꢄꢏꢆꢕ ꢇ
ꢖ ꢑꢆ ꢇ ꢊ ꢋꢀꢆꢏꢆ ꢌ ꢗ ꢘꢆ ꢍ ꢘꢆꢀ
SCBS778A − NOVEMBER 2003 − REVISED MARCH 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
V
V
V
V
V
= 2.7 V,
I = −18 mA
−1.2
V
IK
CC
CC
CC
CC
I
= 2.7 V to 3.6 V,
= 2.7 V,
I
I
I
I
I
I
I
I
= −100 µA
= −8 mA
= −32 mA
= 100 µA
= 24 mA
= 16 mA
= 32 mA
= 64 mA
V
CC
−0.2
OH
OH
OH
OL
OL
OL
OL
OL
2.4
2
V
OH
V
V
= 3 V,
0.2
0.5
0.4
0.5
0.55
10
V
= 2.7 V
CC
CC
V
OL
V
= 3 V
V
V
= 0 or 3.6 V,
= 3.6 V,
V = 5.5 V
I
CC
Control
inputs
V = V
or GND
1
CC
I
CC
CC
I
I
µA
V = V
I
1
−5
V
V
= 3.6 V
= 0,
Data inputs
CC
V = 0
I
I
I
V or V = 0 to 4.5 V
100
µA
µA
off
CC
I
O
V = 0.8 V
I
75
V
CC
= 3 V
V = 2 V
I
−75
Data inputs
I(hold)
‡
V
CC
V
CC
V
CC
V
CC
= 3.6 V ,
V = 0 to 3.6 V
500
5
I
I
I
I
= 3.6 V,
= 3.6 V,
V
= 3 V
µA
µA
µA
OZH
O
O
V
= 0.5 V
−5
OZL
= 0 to 1.5 V, V = 0.5 V to 3 V, OE = don’t care
O
100
OZPU
V
= 1.5 V to 0, V = 0.5 V to 3 V, OE = don’t care
O
100
0.19
5
µA
I
CC
OZPD
Outputs high
Outputs low
I
V
= 3.6 V, I = 0, V = V
CC
or GND
mA
CC
§
CC
CC
O
I
Outputs disabled
0.19
0.2
V
= 3 V to 3.6 V, One input at V
CC
− 0.6 V, Other inputs at V
or GND
mA
pF
pF
∆I
CC
CC
C
C
V = 3 V or 0
I
3
9
i
V
O
= 3 V or 0
o
†
‡
§
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
or GND.
CC
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
V
= 3.3 V
CC
0.3 V
V
= 2.7 V
MAX
CC
UNIT
MIN MAX
MIN
3
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
3
1
1
ns
ns
ns
0.6
1.1
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢂ ꢊꢋ ꢌꢍ
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ꢖꢑ ꢆ ꢇ ꢊ ꢋꢀꢆꢏꢆ ꢌ ꢗꢘꢆ ꢍ ꢘꢆꢀ
SCBS778A − NOVEMBER 2003 − REVISED MARCH 2004
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
V
= 3.3 V
CC
0.3 V
V
= 2.7 V
CC
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
†
MIN TYP
MAX
3.8
3.6
4.3
4
MIN
MAX
4.2
4
t
t
t
t
t
t
t
t
1.5
1.5
2.1
2.1
1.5
1.5
2.4
2
2.7
2.5
3
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
D
Q
Q
Q
Q
ns
ns
ns
4.8
4
LE
2.9
2.8
2.8
3.5
3.2
4.3
4.3
5
5.1
4.7
5.4
4.8
OE
OE
ns
ns
4.7
t
0.5
sk(o)
†
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇ ꢈꢉ ꢊꢂ ꢊꢋ ꢌꢍ
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ꢖ ꢑꢆ ꢇ ꢊ ꢋꢀꢆꢏꢆ ꢌ ꢗ ꢘꢆ ꢍ ꢘꢆꢀ
SCBS778A − NOVEMBER 2003 − REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION
6 V
TEST
S1
S1
Open
500 Ω
From Output
Under Test
t
/t
PLH PHL
Open
6 V
GND
t
/t
PLZ PZL
C
= 50 pF
t
/t
GND
L
PHZ PZH
500 Ω
(see Note A)
2.7 V
0 V
Timing Input
Data Input
1.5 V
LOAD CIRCUIT
t
w
t
t
su
h
2.7 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
t
t
PHL
t
t
PLZ
PLH
PZL
Output
Waveform 1
S1 at 6 V
V
3 V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
+ 0.3 V
OL
V
OL
(see Note B)
V
OL
t
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
OH
V
− 0.3 V
OH
1.5 V
1.5 V
Output
≈0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
CLVTH16373IDGGREP
CLVTH16373IDLREP
CLVTH16373IZQLREP
Status (1)
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
48
48
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
ZQL
1000
Pb-Free
(RoHS)
SNAGCU
Level-1-260C-UNLIM
V62/04712-01XE
V62/04712-01YE
V62/04712-01ZA
ACTIVE
ACTIVE
ACTIVE
TSSOP
DGG
DL
48
48
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
GQL
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVTH16373-EP :
Catalog: SN74LVTH16373
Military: SN54LVTH16373
•
•
NOTE: Qualified Version Definitions:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
Catalog - TI's standard catalog product
Military - QML certified for Military and Defense Applications
•
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CLVTH16373IDGGREP TSSOP
CLVTH16373IDLREP SSOP
DGG
DL
48
48
56
2000
1000
1000
330.0
330.0
330.0
24.4
32.4
16.4
8.6
11.35 16.2
4.8 7.3
15.8
1.8
3.1
12.0
16.0
8.0
24.0
32.0
16.0
Q1
Q1
Q1
CLVTH16373IZQLREP BGA MI
ZQL
1.45
CROSTA
R JUNI
OR
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CLVTH16373IDGGREP
CLVTH16373IDLREP
TSSOP
SSOP
DGG
DL
48
48
56
2000
1000
1000
367.0
367.0
333.2
367.0
367.0
345.9
45.0
55.0
28.6
CLVTH16373IZQLREP BGA MICROSTAR
JUNIOR
ZQL
Pack Materials-Page 2
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