V62/04721-01XA [TI]
3.3-V ABT 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS; 具有三态输出的3.3V ABT 32位透明D型锁存器
| 型号： | V62/04721-01XA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V ABT 32-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS |
| 文件： | 总13页 (文件大小：387K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCBS794 − DECEMBER 2003
D
D
D
D
D
Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D
D
D
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
= 3.3 V, T = 25°C
CC A
I
and Power-Up 3-State Support Hot
off
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Insertion
Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
Enhanced Product-Change Notification
3.3-V V
)
†
CC
Qualification Pedigree
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Member of the Texas Instruments
Widebus+ Family
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
D
D
D
D
Supports Unregulated Battery Operation
Down To 2.7 V
Latch-Up Performance Exceeds 500 mA Per
JESD 17
†
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
GKE PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1Q2
1Q4
1Q6
1Q8
2Q2
2Q4
2Q6
2Q7
3Q2
3Q4
3Q6
3Q8
4Q2
4Q4
4Q6
4Q7
1Q1
1Q3
1Q5
1Q7
2Q1
2Q3
2Q5
2Q8
3Q1
3Q3
3Q5
3Q7
4Q1
4Q3
4Q5
4Q8
1OE
GND
1LE
GND
1D1
1D3
1D5
1D7
2D1
2D3
2D5
2D8
3D1
3D3
3D5
3D7
4D1
4D3
4D5
4D8
1D2
1D4
1D6
1D8
2D2
2D4
2D6
2D7
3D2
3D4
3D6
3D8
4D2
4D4
4D6
4D7
A
B
C
D
E
F
1V
CC
1V
CC
GND
GND
GND
GND
1V
CC
1V
CC
G
H
J
GND
2OE
3OE
GND
GND
2LE
G
H
J
3LE
K
L
GND
K
L
2V
CC
2V
CC
M
N
P
R
T
GND
GND
GND
GND
M
N
P
R
T
2V
CC
2V
CC
GND
4OE
GND
4LE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
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Copyright 2003, Texas Instruments Incorporated
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ꢟ ꢣ ꢠ ꢟꢘ ꢙꢬ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢍ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢈꢂ ꢈꢊ ꢋꢌ
ꢈꢍ ꢈꢊꢅ ꢎ ꢏ ꢆ ꢈ ꢉꢊ ꢏꢐ ꢆ ꢆꢑ ꢎꢁ ꢀꢌꢎꢑ ꢋꢁ ꢆ ꢒꢊꢆ ꢓ ꢌꢋ ꢄ ꢎꢆ ꢔꢇ
ꢕꢐ ꢆ ꢇ ꢈ ꢊꢀꢆꢎꢆ ꢋ ꢖꢗꢆ ꢌ ꢗꢆꢀ
SCBS794 − DECEMBER 2003
description/ordering information
The SN74LVTH32373 is a 32-bit transparent D-type latch designed for low-voltage (3.3-V) V
operation, but
CC
with the capability to provide a TTL interface to a 5-V system environment. This device is particularly suitable
for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
This device can be used as four 8-bit latches, two 16-bit latches, or one 32-bit latch. When the latch-enable (LE)
input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the
levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
When V
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup resistor;
CC
This device is fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
−40°C to 85°C LFBGA − GKE
Tape and reel
CLVTH32373IGKEREP
L373EP
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each 8-bit latch)
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
2
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ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇ ꢈꢉ ꢈꢂ ꢈꢊ ꢋꢌ
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ꢕ ꢐꢆ ꢇ ꢈ ꢊꢀꢆꢎꢆ ꢋ ꢖ ꢗꢆ ꢌ ꢗꢆꢀ
SCBS794 − DECEMBER 2003
logic diagram (positive logic)
A3
H3
1OE
2OE
2LE
A4
H4
E5
1LE
C1
C1
1D
A2
E2
1Q1
2Q1
A5
1D1
1D
2D1
To Seven Other Channels
To Seven Other Channels
J3
J4
T3
T4
3OE
3LE
4OE
4LE
C1
1D
C1
1D
J2
N2
3Q1
4Q1
J5
N5
3D1
4D1
To Seven Other Channels
To Seven Other Channels
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢈꢂ ꢈꢊ ꢋꢌ
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ꢕꢐ ꢆ ꢇ ꢈ ꢊꢀꢆꢎꢆ ꢋ ꢖꢗꢆ ꢌ ꢗꢆꢀ
SCBS794 − DECEMBER 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Current into any output in the low state, I
Current into any output in the high state, I (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
O
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Package thermal impedance, θ (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
JA
Storage temperature range, T (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction
of overall device life. See Figure 1 for additional information on thermal derating.
0.0001
125°C (16 kHours, 1.84 Years)
115°C (40 kHours, 4.57 Years)
0.00001
105°C (104 kHours, 11.94 Years)
100°C (172 kHours, 19.65 Years)
0.000001
1/TJ − Constant Device Junction Temperature
Figure 1. Estimated Wirebond Life
Based on Elevated-Temperature Kirkendall-Voiding Failure Mode
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢕ ꢐꢆ ꢇ ꢈ ꢊꢀꢆꢎꢆ ꢋ ꢖ ꢗꢆ ꢌ ꢗꢆꢀ
SCBS794 − DECEMBER 2003
recommended operating conditions (see Note 5)
MIN
2.7
2
MAX
UNIT
V
V
V
V
V
Supply voltage
3.6
CC
High-level input voltage
Low-level input voltage
Input voltage
V
IH
0.8
5.5
−32
64
V
IL
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
mA
mA
ns/V
µs/V
°C
OH
OL
∆t/∆v
∆t/∆V
Outputs enabled
10
200
−40
CC
T
A
Operating free-air temperature
85
NOTE 5: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢈꢂ ꢈꢊ ꢋꢌ
ꢈꢍ ꢈꢊꢅ ꢎ ꢏ ꢆ ꢈ ꢉꢊ ꢏꢐ ꢆ ꢆꢑ ꢎꢁ ꢀꢌꢎꢑ ꢋꢁ ꢆ ꢒꢊꢆ ꢓ ꢌꢋ ꢄ ꢎꢆ ꢔꢇ
ꢕꢐ ꢆ ꢇ ꢈ ꢊꢀꢆꢎꢆ ꢋ ꢖꢗꢆ ꢌ ꢗꢆꢀ
SCBS794 − DECEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
TYP
PARAMETER
TEST CONDITIONS
I = −18 mA
MIN
MAX
UNIT
V
IK
V
V
V
V
= 2.7 V,
−1.2
V
CC
CC
CC
CC
I
= 2.7 V to 3.6 V,
= 2.7 V,
I
I
I
I
I
I
I
I
= −100 µA
= −8 mA
= −32 mA
= 100 µA
= 24 mA
= 16 mA
= 32 mA
= 64 mA
V
−0.2
OH
OH
OH
OL
OL
OL
OL
OL
CC
2.4
2
V
OH
V
V
= 3 V,
0.2
0.5
0.4
0.5
0.55
10
V
= 2.7 V
CC
CC
V
OL
V
= 3 V
V
V
= 0 or 3.6 V,
= 3.6 V,
V = 5.5 V
I
CC
Control inputs
Data inputs
V = V
or GND
1
CC
I
CC
I
I
µA
V = V
1
I
CC
V
V
= 3.6 V
= 0,
CC
V = 0
I
−5
I
I
V or V = 0 to 4.5 V
100
µA
µA
off
CC
I
O
V = 0.8 V
I
75
V
CC
= 3 V
V = 2 V
I
−75
Data inputs
I(hold)
‡
V
CC
V
CC
V
CC
V
CC
= 3.6 V,
= 3.6 V,
= 3.6 V,
V = 0 to 3.6 V
500
5
I
I
I
I
V
= 3 V
µA
µA
µA
OZH
O
O
V
= 0.5 V
−5
OZL
= 0 to 1.5 V, V = 0.5 V to 3 V, OE = don’t care
O
100
OZPU
V
= 1.5 V to 0, V = 0.5 V to 3 V, OE = don’t care
O
100
0.38
10
µA
I
CC
OZPD
Outputs high
V
= 3.6 V, I = 0,
CC
O
Outputs low
I
mA
CC
V = V
or GND
I
CC
Outputs disabled
0.38
V
= 3 V to 3.6 V, One input at V − 0.6 V,
CC
CC
Other inputs at V
§
0.2
mA
∆I
CC
or GND
CC
C
C
V = 3 V or 0
3
9
pF
pF
i
I
V
O
= 3 V or 0
o
†
‡
§
All typical values are at V
CC
= 3.3 V, T = 25°C.
A
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V or GND.
CC
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 2)
V
= 3.3 V
CC
0.3 V
V
= 2.7 V
MAX
CC
UNIT
MIN MAX
MIN
3
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
3
1
1
ns
ns
ns
0.6
1.1
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇ ꢈꢉ ꢈꢂ ꢈꢊ ꢋꢌ
ꢈ ꢍꢈ ꢊꢅ ꢎꢏꢆ ꢈ ꢉ ꢊꢏꢐ ꢆ ꢆ ꢑꢎꢁꢀ ꢌꢎꢑꢋ ꢁꢆ ꢒꢊꢆ ꢓꢌ ꢋ ꢄꢎꢆꢔ ꢇ
ꢕ ꢐꢆ ꢇ ꢈ ꢊꢀꢆꢎꢆ ꢋ ꢖ ꢗꢆ ꢌ ꢗꢆꢀ
SCBS794 − DECEMBER 2003
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 2)
V
= 3.3 V
CC
0.3 V
V
= 2.7 V
CC
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
†
MIN TYP
MAX
3.8
3.6
4.3
4
MIN
MAX
4.2
4
t
t
t
t
t
t
t
t
1.5
1.5
2.1
2.1
1.5
1.5
2.4
2
2.7
2.5
3
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
D
Q
Q
Q
Q
ns
ns
ns
4.8
4
LE
2.9
2.8
2.8
3.5
3.2
4.3
4.3
5
5.1
4.7
5.4
4.8
OE
OE
ns
ns
4.7
t
0.5
sk(o)
†
All typical values are at V
CC
= 3.3 V, T = 25°C.
A
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢈꢂ ꢈꢊ ꢋꢌ
ꢈꢍ ꢈꢊꢅ ꢎ ꢏ ꢆ ꢈ ꢉꢊ ꢏꢐ ꢆ ꢆꢑ ꢎꢁ ꢀꢌꢎꢑ ꢋꢁ ꢆ ꢒꢊꢆ ꢓ ꢌꢋ ꢄ ꢎꢆ ꢔꢇ
ꢕꢐ ꢆ ꢇ ꢈ ꢊꢀꢆꢎꢆ ꢋ ꢖꢗꢆ ꢌ ꢗꢆꢀ
SCBS794 − DECEMBER 2003
PARAMETER MEASUREMENT INFORMATION
6 V
TEST
S1
S1
Open
500 Ω
From Output
Under Test
t
/t
PLH PHL
Open
6 V
GND
t
/t
PLZ PZL
C
= 50 pF
t
/t
GND
L
PHZ PZH
500 Ω
(see Note A)
2.7 V
0 V
Timing Input
Data Input
1.5 V
LOAD CIRCUIT
t
w
t
t
su
h
2.7 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
t
t
PHL
t
t
PLZ
PLH
PZL
Output
Waveform 1
S1 at 6 V
V
3 V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
+ 0.3 V
OL
V
OL
(see Note B)
V
OL
t
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
OH
V
− 0.3 V
OH
1.5 V
1.5 V
Output
≈0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
CLVTH32373IGKEREP
V62/04721-01XA
ACTIVE
ACTIVE
LFBGA
LFBGA
GKE
96
96
1000
1000
TBD
TBD
SNPB
SNPB
Level-3-220C-168 HR
Level-3-220C-168 HR
GKE
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVTH32373-EP :
Catalog: SN74LVTH32373
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CLVTH32373IGKEREP LFBGA
GKE
96
1000
330.0
24.4
5.7
13.7
2.0
8.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
LFBGA GKE 96
SPQ
Length (mm) Width (mm) Height (mm)
333.2 345.9 31.8
CLVTH32373IGKEREP
1000
Pack Materials-Page 2
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