V62/04724-01XE [TI]
16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS; 16位缓冲器/驱动器，具有三态输出
| 型号： | V62/04724-01XE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS |
| 文件： | 总10页 (文件大小：292K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVC16244A-EP
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS740A–DECEMBER 2003–REVISED JUNE 2005
FEATURES
DGG PACKAGE
(TOP VIEW)
•
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
1
48 2OE
47 1A1
1OE
1Y1
1Y2
GND
1Y3
1Y4
2
•
Enhanced Diminishing Manufacturing
Sources (DMS) Support
3
46
1A2
4
45 GND
44 1A3
43 1A4
•
•
•
Enhanced Product-Change Notification
5
(1)
Qualification Pedigree
6
Member of the Texas Instruments Widebus™
Family
7
42
41
40
39
V
CC
V
CC
8
2A1
2A2
GND
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
9
•
•
•
•
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 4.1 ns at 3.3 V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
38 2A3
37 2A4
36 3A1
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
35
34
33
32
31
30
29
28
27
26
25
3A2
GND
3A3
3A4
•
•
•
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Partial-Power-Down Mode
Operation
V
CC
V
CC
4A1
4A2
GND
4A3
4A4
3OE
4Y1
4Y2
GND
4Y3
4Y4
4OE
Supports Mixed-Mode Signal Operation On All
Ports (5-V Input/Output Voltage With 3.3-V
VCC
)
•
•
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
DESCRIPTION/ORDERING INFORMATION
This 16-bit buffer/driver is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC16244A is designed specifically to improve the performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented receivers and transmitters.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
–40°C to 85°C
TSSOP – DGG
Tape and reel
CLVC16244AIDGGREP
C16244AEP
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
On products compliant to MIL-PRF-38535, all parameters are
Instruments standard warranty. Production processing does not
tested unless otherwise noted. On all other products, production
necessarily include testing of all parameters.
processing does not necessarily include testing of all parameters.
SN74LVC16244A-EP
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS740A–DECEMBER 2003–REVISED JUNE 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and
symmetrical active-low output-enable (OE) inputs.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(EACH 4-BIT BUFFER)
INPUTS
OUTPUT
Y
OE
L
A
H
L
H
L
L
H
X
Z
LOGIC DIAGRAM (POSITIVE LOGIC)
1
25
1OE
1A1
1A2
1A3
1A4
3OE
47
46
2
3
5
6
36
35
33
32
13
14
16
17
1Y1
1Y2
1Y3
1Y4
3A1
3A2
3A3
3A4
3Y1
3Y2
3Y3
3Y4
44
43
48
41
40
24
30
29
2OE
2A1
2A2
2A3
2A4
4OE
4A1
4A2
4A3
4A4
8
9
19
20
22
23
2Y1
2Y2
2Y3
2Y4
4Y1
4Y2
4Y3
4Y4
38
37
11
12
27
26
2
SN74LVC16244A-EP
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS740A–DECEMBER 2003–REVISED JUNE 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
–0.5
MAX UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2)(3)
6.5
6.5
V
V
VO
VO
IIK
6.5
V
VCC + 0.5
–50
V
Input clamp current
VI < 0
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
–50
Continuous output current
Continuous current through each VCC or GND
Package thermal impedance(4)
Storage temperature range
±50
±100
θJA
70 °C/W
150 °C
Tstg
–65
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
MIN
MAX UNIT
Operating
1.65
3.6
V
VCC
Supply voltage
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
1.5
0.65 × VCC
VIH
High-level input voltage
1.7
2
V
0.35 × VCC
0.7
VIL
Low-level input voltage
V
0.8
5.5
VCC
5.5
–4
VI
Input voltage
0
0
0
V
V
High or low state
3-state
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
–8
IOH
High-level output current
Low-level output current
mA
mA
–12
–24
4
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
8
IOL
12
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
10
ns/V
°C
TA
–40
85
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
SN74LVC16244A-EP
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS740A–DECEMBER 2003–REVISED JUNE 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V
1.65 V
2.3 V
MIN TYP(1)
VCC – 0.2
MAX UNIT
IOH = –100 µA
IOH = –4 mA
IOH = –8 mA
1.2
1.7
2.2
2.4
2.2
VOH
V
2.7 V
IOH = –12 mA
3 V
IOH = –24 mA
IOL = 100 µA
3 V
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
IOL = 4 mA
0.45
VOL
IOL = 8 mA
0.7
0.4
0.55
±5
V
IOL = 12 mA
2.7 V
IOL = 24 mA
3 V
II
VI = 0 to 5.5 V
VI or VO = 5.5 V
VO = 0 to 5.5 V
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V(2)
3.6 V
µA
µA
µA
Ioff
IOZ
0
±10
±10
20
3.6 V
ICC
IO = 0
3.6 V
µA
20
∆ICC
Ci
One input at VCC – 0.6 V,
VI = VCC or GND
Other inputs at VCC or GND
2.7 V to 3.6 V
3.3 V
500
µA
pF
pF
5.5
6
Co
VO = VCC or GND
3.3 V
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) This applies in the disabled state only.
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.5
1.5
1.5
MAX
MIN
1
MAX
MIN
1
MAX
4.7
MIN
1.1
1
MAX
tpd
ten
A
Y
Y
Y
6.6
7.5
3.9
4.7
5.3
4.1
4.6
5.8
1
ns
ns
ns
ns
OE
OE
1
1
5.8
tdis
10.3
1
1
6.2
1.8
tsk(o)
Operating Characteristics
TA = 25°C
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TEST
CONDITIONS
PARAMETER
UNIT
TYP
33
2
TYP
35
3
TYP
39
4
Outputs enabled
Outputs disabled
Power dissipation capacitance
per buffer/driver
Cpd
f = 10 MHz
pF
4
SN74LVC16244A-EP
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS740A–DECEMBER 2003–REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
/t
S1
GND
t
t
Open
PLH PHL
C
L
t
/t
V
R
L
PLZ PZL
LOAD
GND
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
LOAD
C
L
R
L
V
∆
V
I
t /t
r f
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
V
V
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
/2
/2
2 × V
2 × V
6 V
6 V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
CC
CC
CC
V
CC
CC
CC
1.5 V
1.5 V
3.3 V ± 0.3 V
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
V
V
OH
V
V
/2
LOAD
V
V
V
M
M
Output
V
V
M
S1 at V
LOAD
V
OL
+ V
∆
OL
(see Note B)
OL
t
PHL
PLH
t
t
PHZ
PZH
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
- V
∆
V
M
OH
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
5
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
CLVC16244AIDGGREP
V62/04724-01XE
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
48
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
DGG
48
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC16244A-EP :
Catalog: SN74LVC16244A
Automotive: SN74LVC16244A-Q1
•
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Aug-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
CLVC16244AIDGGREP TSSOP
DGG
48
2000
330.0
24.4
8.6
15.8
1.8
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Aug-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP DGG 48
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 41.0
CLVC16244AIDGGREP
2000
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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