V62/06605-01XE [TI]
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS; 双上升沿触发D型触发器
| 型号： | V62/06605-01XE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS |
| 文件： | 总14页 (文件大小：506K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LV74A-EP
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
www.ti.com
SCLS696–JANUARY 2006
FEATURES
•
Controlled Baseline
•
•
Latch-Up Performance Exceeds 250 mA Per
JESD 17
– One Assembly/Test Site, One Fabrication
Site
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
•
•
Extended Temperature Performance of– 55°C
to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
– 1000-V Charged-Device Model (C101)
PW PACKAGE
(TOP VIEW)
•
•
•
•
•
Enhanced Product-Change Notification
(1)
Qualification Pedigree
2-V to 5.5-V VCC Operation
Max tpd of 13 ns at 5 V
1CLR
1D
V
CC
1
2
3
4
5
6
7
14
13
12
11
10
9
2CLR
2D
1CLK
1PRE
1Q
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
2CLK
2PRE
2Q
•
•
•
Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
1Q
8
GND
2Q
Supports Mixed-Mode Voltage Operation on
All Ports
Ioff Supports Partial-Power-Down Mode
Operation
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
DESCRIPTION/ORDERING INFORMATION
These dual positive-edge-triggered D-type flip-flops are designed for 2-V to 5.5-V VCC operation.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) inputs meeting the setup-time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the devices when they are powered down.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
LV74AEP
–55°C to 125°C
TSSOP – PW
Reel of 2000
SN74LV74AMPWREP
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains ADVANCE
Copyright © 2006, Texas Instruments Incorporated
INFORMATION on new products in the sampling or preproduction
phase of development. Characteristic data and other specifications
are subject to change without notice.
SN74LV74A-EP
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
www.ti.com
SCLS696–JANUARY 2006
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
L
CLR
H
CLK
X
D
X
X
X
H
L
Q
H
L
Q
L
H
L
X
H
H(1)
L
L
X
H(1)
H
H
↑
H
L
H
H
↑
L
H
H
H
L
X
Q0
Q 0
(1) This configuration is nonstable; that is, it does not persist when
PRE or CLR returns to its inactive (high) level.
LOGIC DIAGRAM, EACH FLIP-FLOP (POSITIVE LOGIC)
PRE
CLK
C
C
C
Q
TG
C
C
C
C
D
TG
TG
TG
Q
C
C
C
CLR
2
SN74LV74A-EP
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
www.ti.com
SCLS696–JANUARY 2006
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Output voltage range(2)(3)
7
7
7
V
V
VO
VO
IIK
V
–0.5 VCC + 0.5
V
Input clamp current
VI < 0
–20
–50
±25
±50
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through VCC or GND
Package thermal impedance(4)
Storage temperature range
VO = 0 to VCC
θJA
113 °C/W
150 °C
Tstg
–65
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 5.5 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
3
SN74LV74A-EP
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
www.ti.com
SCLS696–JANUARY 2006
Recommended Operating Conditions(1)
MIN
2
MAX
5.5
UNIT
VCC
Supply voltage
V
VCC = 2 V
1.5
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2 V
V
V
V
CC × 0.7
CC × 0.7
CC × 0.7
VIH
High-level input voltage
V
V
0.5
CC × 0.3
CC × 0.3
CC × 0.3
5.5
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
V
V
V
VIL
Low-level input voltage
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC
–50
–2
VCC = 2 V
µA
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2 V
IOH
High-level output current
Low-level output current
–6
mA
µA
–12
50
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
2
IOL
6
mA
12
200
100
20
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
TA
–55
125
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2 V to 5.5 V
2.3 V
MIN
VCC – 0.1
2
TYP
MAX UNIT
IOH = –50 µA
IOH = –2 mA
IOH = –6 mA
IOH = –12 mA
IOL = 50 µA
IOL = 2 mA
VOH
V
3 V
2.48
4.5 V
3.8
2 V to 5.5 V
2.3 V
0.1
0.4
V
VOL
IOL = 6 mA
3 V
0.44
IOL = 12 mA
4.5 V
0.55
II
VI = 5.5 V or GND
0 to 5.5 V
5.5 V
±1
20
5
µA
µA
µA
ICC
Ioff
VI = VCC or GND, IO = 0
VI or VO = 0 to 5.5 V
0
3.3 V
2
2
Ci
VI = VCC or GND
pF
5 V
4
SN74LV74A-EP
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
www.ti.com
SCLS696–JANUARY 2006
Timing Requirements
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
TA = 25°C
PARAMETER
MIN
MAX UNIT
MIN
8
MAX
PRE or CLR low
CLK
9
9
tw
Pulse duration
ns
8
Data
8
9
tsu
th
Setup time before CLK↑
ns
ns
PRE or CLR inactive
7
7
Hold time, data after CLK↑
0.5
0.5
Timing Requirements
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25°C
PARAMETER
MIN
MAX UNIT
MIN
6
MAX
PRE or CLR low
CLK
7
7
tw
Pulse duration
ns
6
Data
6
7
tsu
th
Setup time before CLK↑
ns
ns
PRE or CLR inactive
5
5
Hold time, data after CLK↑
1.45
2.15
Timing Requirements
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C
PARAMETER
MIN
MAX UNIT
MIN
5
MAX
PRE or CLR low
CLK
5
5
tw
Pulse duration
ns
5
Data
5
5
tsu
th
Setup time before CLK↑
ns
ns
PRE or CLR inactive
3
3
Hold time, data after CLK↑
1.45
2.15
Switching Characteristics
over recommended operating free-air temperature range,VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
TA = 25°C
TYP
70
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
MIN
MAX
UNIT
MHz
ns
MIN
MAX
fmax
tpd
CL = 50 pF
CL = 50 pF
30
25
1
PRE or CLR
CLK
13
17.4
20
20
23
Q or Q
14.2
1
5
SN74LV74A-EP
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
www.ti.com
SCLS696–JANUARY 2006
Switching Characteristics
over recommended operating free-air temperature range,VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25°C
TYP
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
MIN
MAX
UNIT
MHz
ns
MIN
MAX
fmax
tpd
CL = 50 pF
CL = 50 pF
50
90
45
1
PRE or CLR
CLK
9.2
15.8
15.4
18
18
Q or Q
10.2
1
Switching Characteristics
over recommended operating free-air temperature range,VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C
TYP
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
MIN
MAX
UNIT
MHz
ns
MIN
MAX
fmax
tpd
CL = 50 pF
CL = 50 pF
90
140
75
1
PRE or CLR
CLK
6.6
9.7
9.9
12
13
Q or Q
7.2
1
Noise Characteristics(1)
VCC = 3.3 V, CL = 50 pF, TA = 25°C
PARAMETER
Quiet output, maximum dynamic VOL
MIN TYP
MAX UNIT
VOL(P)
VOL(V)
VOH(V)
VIH(D)
VIL(D)
0.1
0.8
V
V
V
V
V
Quiet output, minimum dynamic VOL
Quiet output, minimum dynamic VOH
High-level dynamic input voltage
Low-level dynamic input voltage
0
3.2
–0.8
2.31
0.99
(1) Characteristics are for surface-mount packages only.
Operating Characteristics
TA = 25°C
PARAMETER
TEST CONDITIONS
CL = 50 pF, f = 10 MHz
VCC
3.3 V
5 V
TYP UNIT
21
pF
23
Cpd
Power dissipation capacitance
6
SN74LV74A-EP
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
www.ti.com
SCLS696–JANUARY 2006
PARAMETER MEASUREMENT INFORMATION
V
CC
S1
Open
R
L
= 1 kΩ
TEST
/t
S1
From Output
Under Test
Test
Point
From Output
Under Test
GND
t
t
Open
PLH PHL
C
L
C
L
t
/t
V
CC
PLZ PZL
(see Note A)
(see Note A)
/t
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
CC
Timing Input
0 V
t
w
t
h
t
su
V
CC
V
CC
50% V
50% V
CC
Input
Input
CC
50% V
50% V
CC
Data Input
0 V
CC
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
50% V
50% V
50% V
CC
CC
CC
CC
0 V
0 V
t
t
t
t
t
PLH
PHL
PZL
PLZ
Output
Waveform 1
≈V
V
CC
OH
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
V
+ 0.3 V
OL
S1 at V
CC
V
OL
V
OL
(see Note B)
t
PHL
PLH
t
t
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
OH
OL
Out-of-Phase
Output
− 0.3 V
OH
50% V
50% V
50% V
CC
CC
CC
V
≈0 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PHL
PHZ
are the same as t
PZH
en
are the same as t .
PLH pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuits and Voltage Waveforms
7
PACKAGE OPTION ADDENDUM
www.ti.com
9-May-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
SN74LV74AMPWREP
V62/06605-01XE
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
14
14
2000
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Add to cart
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Add to cart
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV74A-EP :
Catalog: SN74LV74A
•
Automotive: SN74LV74A-Q1
•
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-May-2012
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LV74AMPWREP
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 14
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
SN74LV74AMPWREP
2000
Pack Materials-Page 2
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