V62/06646-04ZE [TI]
HIGH-OUTPUT-DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN; 高输出驱动运算放大器，带有关断
| 型号： | V62/06646-04ZE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH-OUTPUT-DRIVE OPERATIONAL AMPLIFIERS WITH SHUTDOWN |
| 文件： | 总25页 (文件大小：884K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV4110-EP, TLV4111-EP
TLV4112-EP, TLV4113-EP
www.ti.com............................................................................................................................................................... SGLS314D–JUNE 2006–REVISED MAY 2008
HIGH-OUTPUT-DRIVE OPERATIONAL AMPLIFIERS
WITH SHUTDOWN
1
FEATURES
TLV4112
D OR DGN PACKAGE
(TOP VIEW)
23
•
Controlled Baseline
–
–
–
One Assembly Site
One Test Site
1OUT
1IN−
1IN+
GND
VDD
1
2
3
4
8
7
6
5
One Fabrication Site
2OUT
2IN−
2IN+
•
Extended Temperature Performance of
–55°C to 125°C
•
Enhanced Diminishing Manufacturing Sources
(DMS) Support
P0029-01
•
•
•
•
•
•
•
•
•
Enhanced Product-Change Notification
DESCRIPTION
(1)
Qualification Pedigree
The TLV411x single-supply operational amplifiers
provide output currents in excess of 300 mA at 5 V.
This enables standard pin-out amplifiers to be used
as high current buffers or in coil driver applications.
The TLV4110 and TLV4113 come with a shutdown
feature.
High Output Drive . . . >300 mA
Rail-To-Rail Output
Unity-Gain Bandwidth . . . 2.7 MHz
Slew Rate . . . 1.5 V/µs
Supply Current . . . 700 µA/Per Channel
Supply Voltage Range . . . 2.5 V to 6 V
Universal Op Amp EVM
The TLV411x is available in the ultra-small MSOP
PowerPAD™ package, which offers the exceptional
thermal impedance required for amplifiers delivering
high current levels.
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
All TLV411x devices are offered in SOIC (single and
dual) and MSOP PowerPAD (dual).
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
FAMILY PACKAGE TABLE
PACKAGE TYPES
MSOP SOIC
NUMBER OF
CHANNELS
DEVICE
SHUTDOWN
UNIVERSAL EVM BOARD
TLV4110
TLV4111
TLV4112
TLV4113
1
1
2
2
8
8
Yes
–
8
8
8
8
See the EVM Selection Guide (SLOU060)
–
10
14
Yes
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
PowerPAD is a trademark of Texas Instruments.
Parts, Microsim PSpice are trademarks of MicroSim Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2008, Texas Instruments Incorporated
TLV4110-EP, TLV4111-EP
TLV4112-EP, TLV4113-EP
SGLS314D–JUNE 2006–REVISED MAY 2008............................................................................................................................................................... www.ti.com
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
V
= 3 V
V
DD
= 3 V
DD
T
= 705C
A
T
A
= 255C
T
A
= 1255C
T
= 05C
A
T
A
= −405C
T
= 05C
T
A
= −405C
A
T
A
= 1255C
T
A
= 255C
T
A
= 705C
0
50
OH
100
150
200
250
300
0
50
100
150
200
250
300
I
− High-Level Output Current − mA
I
− Low-Level Output Current − mA
OL
G004
G005
TLV4110 AND TLV4111 AVAILABLE OPTIONS
TA
PACKAGED DEVICES
MSOP
SMALL OUTLINE (D)(1) (2)
SMALL OUTLINE
SYMBOL
(DGN)(1)
TLV4110MDREP(3)
TLV4111MDREP(3)
TLV4110MDGNREP(3)
TLV4111MDGNREP(3)
BTB
BTC
–55°C to 125°C
(1) The R designation indicates package is taped and reeled.
(2) In the SOIC package, the maximum RMS output power is thermally limited to 350 mW; 700 mW peaks can be driven, as long as the
RMS value is less than 350 mW.
(3) Product preview.
TLV4112 AND TLV4113 AVAILABLE OPTIONS
PACKAGED DEVICES
MSOP
TA
SMALL OUTLINE
(1) (2)
SMALL OUTLINE
(DGN)(1)
SMALL OUTLINE
(DGQ)(1)
(D)
SYMBOL
SYMBOL
TLV4112MDREP(3)
TLV4113MDREP(3)
TLV4112MDGNREP(3)
BTD
–
–
–
–55°C to 125°C
–
TLV4113MDGQREP
BTE
(1) The R designation indicates package is taped and reeled.
(2) In the SOIC package, the maximum RMS output power is thermally limited to 350 mW; 700 mW peaks can be driven, as long as the
RMS value is less than 350 mW.
(3) Product preview.
2
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Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TLV4110-EP, TLV4111-EP TLV4112-EP, TLV4113-EP
TLV4110-EP, TLV4111-EP
TLV4112-EP, TLV4113-EP
www.ti.com............................................................................................................................................................... SGLS314D–JUNE 2006–REVISED MAY 2008
TLV411X PACKAGE PINOUTS
TLV4110
D OR DGN PACKAGE
(TOP VIEW)
TLV4111
D OR DGN PACKAGE
(TOP VIEW)
TLV4112
D OR DGN PACKAGE
(TOP VIEW)
NC
IN−
IN+
SHDN
VDD
OUT
NC
NC
IN−
IN+
NC
1OUT
1IN−
1IN+
GND
VDD
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
VDD
OUT
NC
2OUT
2IN−
2IN+
GND
GND
TLV4113
TLV4113
D OR DGN PACKAGE
DGQ PACKAGE
(TOP VIEW)
(TOP VIEW)
1
1OUT
1IN−
1IN+
GND
1SHDN
VDD+
2OUT
2IN−
2IN+
2SHDN
10
1OUT
1IN−
1IN+
GND
NC
VDD
1
2
3
4
5
6
7
14
13
12
11
10
9
2
9
2OUT
2IN−
2IN+
NC
3
8
4
7
5
6
1SHDN
NC
2SHDN
NC
8
NC − No internal connection
P0029-02
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VDD
VID
VI
Supply voltage(2)
7 V
Differential input voltage
Input voltage range
Output current(3)
±VDD
±VDD
IO
800 mA
350 mA
110 mA
500 mA
155 mA
TJ ≤ 105°C
IO
Continuous RMS output current (each output of amplifier)
TJ ≤ 150°C
TJ ≤ 105°C
TJ ≤ 150°C
Peak output current (each output of
amplifier
IO
Continuous total power dissipation
Operating free-air temperature range
Maximum junction temperature
Storage temperature range
See Dissipation Rating Table
–55°C to 125°C
150°C
TA
TJ
Tstg
–65°C to 150°C
260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to GND.
(3) To prevent permanent damage, the die temperature must not exceed the maximum junction temperature.
Copyright © 2006–2008, Texas Instruments Incorporated
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3
Product Folder Link(s): TLV4110-EP, TLV4111-EP TLV4112-EP, TLV4113-EP
TLV4110-EP, TLV4111-EP
TLV4112-EP, TLV4113-EP
SGLS314D–JUNE 2006–REVISED MAY 2008............................................................................................................................................................... www.ti.com
100
10
1
120
125
130
135
140
Continous T − 5C
145
150
155
160
J
Figure 1. TLV4113MDGQ Wirebond Life
DISSIPATION RATING TABLE
θJC
(°C/W)
θJA
(°C/W)
T
A ≤ 25°C
TA = 25°C
POWER RATING
PACKAGE
POWER RATING
D (8)
D (14)
DGN (8)(1)
DGQ (10)(1)
38.3
176
122.3
52.7
52.3
710 mW
142 mW
26.9
4.7
1022 mW
2.37 W
204.4 mW
474.4 mW
478 mW
4.7
2.39 W
(1) See the Texas Instruments document, PowerPAD Thermally Enhanced Package Application Report (SLMA002), for more information on
the PowerPAD package. The thermal data was measured on a PCB layout, based on information in the section entitled Texas
Instruments Recommended Board for PowerPAD, on page 33 of SLMA002.
4
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Copyright © 2006–2008, Texas Instruments Incorporated
Product Folder Link(s): TLV4110-EP, TLV4111-EP TLV4112-EP, TLV4113-EP
TLV4110-EP, TLV4111-EP
TLV4112-EP, TLV4113-EP
www.ti.com............................................................................................................................................................... SGLS314D–JUNE 2006–REVISED MAY 2008
RECOMMENDED OPERATING CONDITIONS
MIN
2.5
0
MAX UNIT
VDD
VICR
TA
Supply voltage
6
VDD – 1.5
125
V
V
Common-mode input voltage range
Operating free-air temperature
–55
2.1
3.8
°C
VDD = 3 V
VDD = 5 V
VDD = 3 V
VDD = 5 V
V(on)
V(off)
V
V
Shutdown turnon/off voltage level(1)
0.9
1.65
(1) Relative to GND
ELECTRICAL CHARACTERISTICS
at recommended operating conditions, VDD = 3 V and 5 V (unless otherwise noted)
(1)
PARAMETER
DC PERFORMANCE
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
25°C
Full range
25°C
175
3500
µV
VIC = VDD/2, VO = VDD/2 , RL = 100 Ω,
RS = 50 Ω
VIO
Input offset voltage
4000
αVIO
CMRR
Offset voltage drift
3
63
68
84
µV/°C
VDD = 3 V, RS = 50 Ω, VIC = 0 to 2 V
VDD = 5 V, RS = 50 Ω, VIC = 0 to 4 V
25°C
Common-mode rejection ratio
dB
25°C
25°C
78
67
85
75
88
75
90
85
RL = 100 Ω
Full range
25°C
VDD = 3 V
100
94
RL = 10 kΩ
Full range
25°C
Large-signal differential voltage
amplification
AVD
dB
RL = 100 Ω
Full range
25°C
VDD = 5 V
110
RL = 10 kΩ
Full range
INPUT CHARACTERISTICS
25°C
Full range
25°C
0.3
0.3
25
pA
IIO
Input offset current
Input bias current
1000
50
pA
IIB
Full range
25°C
2000
ri(d)
CIC
Differential input resistance
1000
5
GΩ
Common-mode input capacitance
f = 100 Hz
25°C
pF
(1) Full range is –55°C to 125°C.
Copyright © 2006–2008, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Link(s): TLV4110-EP, TLV4111-EP TLV4112-EP, TLV4113-EP
TLV4110-EP, TLV4111-EP
TLV4112-EP, TLV4113-EP
SGLS314D–JUNE 2006–REVISED MAY 2008............................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
at specified free-air temperature, VDD = 3 V and 5 V (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP MAX
2.97
UNIT
OUTPUT CHARACTERISTICS
25°C
Full range
25°C
2.7
2.6
2.6
2.5
4.7
4.6
4.6
4.5
IOH = –10 mA
IOH = –100 mA
IOH = –10 mA
IOH = –100 mA
IOL = 10 mA
VDD = 3 V,
VIC = VDD/2
V
2.73
Full range
25°C
VOH
High-level output voltage
4.96
Full range
25°C
VDD = 5 V,
VIC = VDD/2
V
V
4.76
Full range
25°C
0.03
0.33
0.1
0.2
Full range
25°C
VDD = 3 V and 5 V,
VIC = VDD/2
VOL
Low-level output voltage
0.4
IOL = 100 mA
Full range
0.55
VDD = 3 V
VDD = 5 V
±220
±320
800
Measured at 0.5 V
from rail
IO
Output current
25°C
25°C
mA
mA
Sourcing
Sinking
IOS
Short-circuit output current
800
POWER SUPPLY
25°C
Full range
25°C
700 1000
1500
IDD
Supply current (per channel)
VO = VDD/2
µA
dB
dB
69
65
69
65
82
VDD = 2.7 to 3.3 V, No load
VIC = VDD/2 V
Full range
25°C
Power supply rejection ratio
PSRR
(ΔVDD / ΔVIO
)
79
VDD = 4.5 to 5.5 V, No load
VIC = VDD/2 V
Full range
(1) Full range is –55°C to 125°C.
6
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Product Folder Link(s): TLV4110-EP, TLV4111-EP TLV4112-EP, TLV4113-EP
TLV4110-EP, TLV4111-EP
TLV4112-EP, TLV4113-EP
www.ti.com............................................................................................................................................................... SGLS314D–JUNE 2006–REVISED MAY 2008
ELECTRICAL CHARACTERISTICS (continued)
at specified free-air temperature, VDD = 3 V and 5 V (unless otherwise noted)
(1)
PARAMETER
DYNAMIC PERFORMANCE
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
GBWP
Gain bandwidth product
RL = 100 Ω, CL = 10 pF
25°C
25°C
2.7
MHz
0.8
0.4
1
1.57
VDD = 3 V
Vo(pp) = 2.5 V,
RL = 100 Ω,
CL = 10 pF
Full range
25°C
SR
Slew rate at unity gain
V/µs
1.57
VDD = 5 V
Full range
25°C
0.5
φM
Phase margin
Gain margin
RL = 100 Ω, CL = 10 pF
RL = 100 Ω, CL = 10 pF
66
16
25°C
dB
µs
V(STEP)pp = 1 V,
AV = –1,
0.1%
0.7
ts
Settling time
25°C
25°C
CL = 10 pF,
RL = 100 Ω
0.01%
1.3
NOISE/DISTORTION PERFORMANCE
AV = 1
0.025
0.035
0.15
55
VO(pp) = VDD/2 V,
RL = 100 Ω,
f = 100 Hz
THD+N
Total harmonic distortion, plus noise
AV = 10
AV = 100
f = 100 Hz
f = 10 Hz
f = 1 Hz
Vn
In
Equivalent input noise voltage
Equivalent input noise current
25°C
25°C
nV/√Hz
fA/√Hz
10
0.31
SHUTDOWN CHARACTERISTICS
25°C
3.4
10
15
Supply current in shutdown mode (per
channel) (TLV4110, TLV4113)
IDD(SHDN)
SHDN = 0 V
µA
µs
Full range
t(ON)
t(Off)
Amplifier turnon time(2)
Amplifier turnoff time(2)
1
RL = 100 Ω
25°C
3.3
(1) Full range is –55°C to 125°C.
(2) Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the
supply current has reached half its final value.
Copyright © 2006–2008, Texas Instruments Incorporated
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Product Folder Link(s): TLV4110-EP, TLV4111-EP TLV4112-EP, TLV4113-EP
TLV4110-EP, TLV4111-EP
TLV4112-EP, TLV4113-EP
SGLS314D–JUNE 2006–REVISED MAY 2008............................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
Input offset voltage
vs Common-mode input voltage
vs Frequency
2, 3
4
CMRR
VOH
VOL
Zo
Common-mode rejection ratio
High-level output voltage
Low-level output voltage
Output impedance
vs High-level output current
vs Low-level output current
vs Frequency
5, 7
6, 8
9
IDD
Supply current
vs Supply voltage
vs Frequency
10
kSVR
AVD
Power supply voltage rejection ratio
Differential voltage amplification and phase
Gain-bandwidth product
11
vs Frequency
12
vs Supply voltage
vs Supply voltage
vs Temperature
13
14
SR
Vn
Slew rate
15
Total harmonic distortion+noise
Equivalent input voltage noise
Phase margin
vs Frequency
16
vs Frequency
17
vs Capacitive load
18
Voltage-follower signal pulse response
Inverting large-signal pulse response
Small-signal inverting pulse response
Crosstalk
19, 20
21
22
vs Frequency
23
Shutdown forward and reverse isolation
Shutdown supply current
24
vs Free-air temperature
25
Shutdown supply current/output voltage
26
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
6000
4000
2000
0
6000
4000
2000
0
120
110
100
90
V
T
A
= 3 V
V
T
A
= 5 V
V
= 3 V
DD
= 25°C
DD
= 25°C
DD
T = 25°C
A
80
70
−2000
−4000
−6000
−2000
−4000
−6000
60
50
40
100
1k
10k
100k
1M
10M
−0.2 0.4 1.0 1.6 2.2 2.8 3.4 4.0 4.6 5.2
−0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2
f − Frequency − Hz
V
ICR
− Common-Mode Input Voltage − V
V
ICR
− Common-Mode Input Voltage − V
G003
G002
G001
Figure 2.
Figure 3.
Figure 4.
8
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Product Folder Link(s): TLV4110-EP, TLV4111-EP TLV4112-EP, TLV4113-EP
TLV4110-EP, TLV4111-EP
TLV4112-EP, TLV4113-EP
www.ti.com............................................................................................................................................................... SGLS314D–JUNE 2006–REVISED MAY 2008
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
5.0
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4.0
V
= 3 V
V
DD
= 3 V
V
= 5 V
DD
DD
T
= 705C
A
T
A
= 255C
T
A
= 1255C
T
A
= 1255C
T
= 05C
A
T
A
= −405C
T
A
= −405C
T
A
= 05C
T
= 05C
T
A
= −405C
A
T
A
= 255C
T
A
= 1255C
T
A
= 255C
T
= 705C
A
T
A
= 705C
0
50
OH
100
150
200
250
300
0
50
100
150
200
250
300
0
50
100
150
200
250
300
I
− High-Level Output Current − mA
I
− Low-Level Output Current − mA
I
− High-Level Output Current − mA
OL
OH
G004
G005
G006
Figure 5.
Figure 6.
Figure 7.
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
OUTPUT IMPEDANCE
vs
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
FREQUENCY
100
10
1
1200
1000
800
600
400
200
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
V
= 5 V
V
T
A
= 3 V and 5 V
A = 1
V
DD
DD
= 25°C
T
= 1255C
A
V = V /2 V
I DD
T
A
= 705C
T
= 255C
= 05C
A
T
= 705C
A
T
T
= 05C
T = 255C
A
A
A
T
= −405C
A
T
A
= −405C
A = 100
T
A
= 1255C
A = 10
A = 1
1k
0.1
100
10k
100k
1M
10M
0
1
2
3
4
5
6
0
50
100
150
200
250
300
f − Frequency − Hz
V
DD
− Supply Voltage − V
I
− Low-Level Output Current − mA
OL
G008
G009
G007
Figure 8.
Figure 9.
Figure 10.
POWER-SUPPLY REJECTION
DIFFERENTIAL VOLTAGE
RATIO
vs
AMPLIFICATION AND PHASE
GAIN-BANDWIDTH PRODUCT
vs
vs
FREQUENCY
FREQUENCY
SUPPLY VOLTAGE
120
100
90
80
70
60
50
40
30
20
10
0
135
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
V
R
= 3 V and 5 V
= 1 kΩ
DD
100
80
F
R = 100 Ω
I
Phase
V = 0 V
I
90
45
0
T
A
= 25°C
60
40
Gain
20
0
V
R
C
= 3 V and 5 V
R
L
= 100 Ω
DD
= 100 kΩ
= 10 pF
= 25°C
F
L
C
L
= 10 pF
−20
f = 1 kHz
T
A
T
A
= 25°C
−40
100
−45
10M
A
V
= Open Loop
1k
10k
100k
1M
f − Frequency − Hz
100
1k
10k
100k
1M
10M
2.5
3.0
3.5
4.0
4.5
5.0
5.5
G011
f − Frequency − Hz
V
DD
− Supply Voltage − V
G010
G012
Figure 11.
Figure 12.
Figure 13.
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TOTAL HARMONIC
SLEW RATE
vs
SUPPLY VOLTAGE
SLEW RATE
vs
TEMPERATURE
DISTORTION+NOISE
vs
FREQUENCY
10
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
R
C
A
V
= 100 Ω
= 10 pF
= 1
L
L
V
R
= 5 V
DD
= 100 Ω
L
V
O(PP)
= V /2
DD
SR+
SR−
A
V
= 1, 10, and 100
SR+
1
SR−
A = 100
0.1
A = 10
A = 1
V
R
C
= 3 V and 5 V
DD
= 100 Ω
= 10 pF
= 1
L
L
A
V
0.01
10
100
1k
10k
100k
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
−40 −25 −10
5
20 35 50 65 80 95 110 125
f − Frequency − Hz
V
DD
− Supply Voltage − V
T
A
− Free-Air Temperature − °C
G015
G013
G014
Figure 14.
Figure 15.
Figure 16.
EQUIVALENT INPUT VOLTAGE
NOISE
vs
PHASE MARGIN
vs
CAPACITIVE LOAD
VOLTAGE-FOLLOWER
LARGE-SIGNAL PULSE RESPONSE
FREQUENCY
160
140
120
100
80
100
90
80
70
60
50
40
30
20
10
0
5
4
3
2
V
T
= 3 V and 5 V
DD
= 25°C
V
I
A
V
DD
= 3 V
R
= 100
L
R
L
= 600
R
= 20
V
DD
= 5 V
NULL
1
0
4
3
2
V
O
R
NULL
= 20
60
V
R
C
= 5 V
= 100 Ω
= 10 pF
= 25°C
= 1
DD
40
R
= 0
NULL
L
L
T
A
R
NULL
= 0
20
1
0
A
V
0
10
100
1k
10k
100k
−2
0
2
4
6
8
10
12
14
10
100
1k
10k
100k
f − Frequency − Hz
t − Time − µs
Capacitive Load − pF
G016
G018
G017
Figure 17.
Figure 18.
Figure 19.
VOLTAGE-FOLLOWER
SMALL-SIGNAL PULSE RESPONSE
INVERTING LARGE-SIGNAL
PULSE RESPONSE
SMALL-SIGNAL INVERTING
PULSE RESPONSE
2.60
2.55
2.50
2.45
3
2
2.58
2.54
2.50
2.46
2.42
2.54
2.50
V
I
V
I
1
V
R
C
= 5 V
= 100 Ω
= 50 pF
= 25°C
DD
0
L
L
V
R
C
= 5 V
DD
= 100 Ω
= 50 pF
= 25°C
−1
L
L
T
A
V
I
V = 2.5 V
I
−2
5
T
A
A
V
= −1
V = 2.5 V
I
V
O
A
V
= −1
2.55
2.50
2.45
2.40
4
V
R
C
T
= 5 V
DD
3
2
1
0
= 100 Ω
= 10 pF
= 25°C
V = 100 mV
= 1
L
L
V
O
A
2.46
2.42
I
V
O
A
V
−0.2 0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
−1
0
1
2
3
4
5
6
7
8
−0.2 0.2
0.6
1.0
1.4
1.8
2.2
2.6
3.0
t − Time − µs
t − Time − µs
t − Time − µs
G019
G020
G021
Figure 20.
Figure 21.
Figure 22.
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TLV4112-EP, TLV4113-EP
www.ti.com............................................................................................................................................................... SGLS314D–JUNE 2006–REVISED MAY 2008
CROSSTALK
vs
FREQUENCY
SHUTDOWN SUPPLY CURRENT
vs
SHUTDOWN FORWARD AND
REVERSE ISOLATION
FREE-AIR TEMPERATURE
0
−20
0
−20
16
14
12
10
8
V
R
= 3 V and 5 V
V
= 3 V and 5 V
V
V
= 3 V and 5 V
= V /2
DD
DD
= 100 Ω
DD
DD
R
C
T
= 100 Ω
= 50 pF
= 25°C
= 1
L
L
L
I
All Channels
No Load
A
−40
A
V
−40
−60
−60
−80
6
V
I
= 0.1 V
PP
−100
−120
−140
−160
−80
4
V
I
= 4 V
PP
2
−100
V
I
= 2.5 V
100
PP
0
V
I
= 2 V
10k
PP
−120
−2
10
100
1k
100k
10
1k
10k
100k
1M
10M
−40 −25 −10
5
20 35 50 65 80 95 110 125
f − Frequency − Hz
f − Frequency − Hz
T
A
− Free-Air Temperature − °C
G022
G023
G024
Figure 23.
Figure 24.
Figure 25.
SHUTDOWN SUPPLY CURRENT / OUTPUT VOLTAGE
4
3
2
1
SD
0
2
V
DD
= 3 V
R = 100 Ω
L
1.5
1
C
L
= 10 pF
T
A
= 25°C
V = V /2
I
DD
A
V
= 1
0.5
0
V
O
6
I
DD(SD)
4
2
0
−2
−20
0
20
40
60
80
100
120
t − Time − µs
G025
Figure 26.
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APPLICATION INFORMATION
SHUTDOWN FUNCTION
Two members of the TLV411x family (TLV4110/3) have a shutdown terminal for conserving battery life in
portable applications. When the shutdown terminal is tied low, the supply current is reduced to just nano amps
per channel, the amplifier is disabled, and the outputs are placed in a high-impedance mode. In order to save
power in shutdown mode, an external pullup resistor is required; therefore, to enable the amplifier, the shutdown
terminal must be pulled high. When the shutdown terminal is left floating, care should be taken to ensure that
parasitic leakage current at the shutdown terminal does not inadvertently place the operational amplifier into
shutdown.
DRIVING A CAPACITIVE LOAD
When the amplifier is configured in this manner, capacitive loading directly on the output decreases the device's
phase margin, leading to high-frequency ringing or oscillations. Therefore, for capacitive loads of greater than
1 nF, it is recommended that a resistor be placed in series ®NULL) with the output of the amplifier, as shown in
Figure 27. A maximum value of 20 Ω is recommended for most applications.
R
F
R
F
R
G
R
G
R
R
NULL
NULL
−
+
−
+
Input
Input
Output
LOAD
Output
Snubber
C
R
L
C
R
L
C
L
(a)
(b)
S0048-03
Figure 27. Driving a Capacitive Load
OFFSET VOLTAGE
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage.
R
F
I
IB−
R
G
+
−
+
V
I
V
O
R
S
I
IB+
R
R
F
F
V
+ V
1 ) ǒ Ǔ " I
R
1 ) ǒ Ǔ " I
R
ǒ Ǔ ǒ Ǔ
OO
IO
IB)
S
IB*
F
R
R
G
G
S0094-01
Figure 28. Output Offset Voltage Model
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TLV4110-EP, TLV4111-EP
TLV4112-EP, TLV4113-EP
www.ti.com............................................................................................................................................................... SGLS314D–JUNE 2006–REVISED MAY 2008
R
null
_
+
R
L
C
L
S0095-01
Figure 29.
GENERAL POWER DESIGN CONSIDERATIONS
When driving heavy loads at high junction temperatures there is an increased probability of electromigration
affecting the long-term reliability of ICs. Therefore, to avoid this issue:
•
The output current must be limited (at these high-junction temperatures).
OR
•
The junction temperature must be limited.
The maximum continuous output current at a die temperature 150°C will be 1/3 of the current at 105°C.
The junction temperature will be dependent on the ambient temperature around the IC, thermal impedance from
the die to the ambient and power dissipated within the IC.
TJ = TA + θJA × PDIS
Where:
PDIS is the IC power dissipation and is equal to the output current multiplied by the voltage dropped across
the output of the IC.
θJA is the thermal impedance between the junction and the ambient temperature of the IC.
TJ is the junction temperature.
TA is the ambient temperature.
Reducing one or more of these factors results in a reduced die temperature. The 8-pin SOIC (small outline
integrated circuit) has a thermal impedance from junction to ambient of 176°C/W. For this reason it is
recommended that the maximum power dissipation of the 8-pin SOIC package be limited to 350 mW, with peak
dissipation of 700 mW as long as the RMS value is less than 350 mW.
The use of the MSOP PowerPAD™ dramatically reduces the thermal impedance from junction to case. And, with
correct mounting, the reduced thermal impedance greatly increases the IC's permissible power dissipation and
output current handling capability. For example, the power dissipation of the PowerPAD™ is increased to above
1 W. Sinusoidal and pulse-width modulated output signals also increase the output current capability. The
equivalent dc current is proportional to the square-root of the duty cycle:
Ǹ
( )
duty cycle
I
+ I
DC(EQ)
Cont
(1)
CURRENT DUTY CYCLE
AT PEAK RATED CURRENT
EQUIVALENT DC CURRENT
AS A PERCENTAGE OF PEAK
100
70
100
84
50
71
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Note that, with an operational amplifier, a duty cycle of 70% often results in the op-amp sourcing current 70% of
the time and sinking current 30%; therefore, the equivalent dc current is still 0.84 times the continuous current
rating at a particular junction temperature.
GENERAL PowerPAD DESIGN CONSIDERATIONS
The TLV411x is available in a thermally-enhanced PowerPAD family of packages. These packages are
constructed using a downset lead frame upon which the die is mounted [see Figure 30(a) and Figure 30(b)]. This
arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see
Figure 30(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance
can be achieved by providing a good thermal path away from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat-dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with the previously awkward mechanical methods of heat sinking.
DIE
Thermal
Pad
Side View (a)
DIE
End View (b)
Bottom View (c)
M0031-01
Figure 30. Views of Thermally Enhanced DGN Package
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TLV4112-EP, TLV4113-EP
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Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the
recommended approach.
1. Prepare the PCB with a top-side etch pattern, as shown in Figure 31. There should be etch for the leads as
well as etch for the thermal pad.
2. Place five holes (dual) or nine holes (quad) in the area of the thermal pad. These holes should be 13 mils in
diameter. Keep them small so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the TLV411x IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal-resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In
this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the
holes under the TLV411x PowerPAD package should make their connection to the internal ground plane with
a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes (dual) or nine holes (quad) exposed. The bottom-side solder mask should cover the five or nine holes
of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the
reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the TLV411x IC is simply placed in position and run through the solder
reflow operation as any standard surface-mount component. This results in a part that is properly installed.
Thermal Pad Area
Single or Dual
68 mils × 70 mils) with 5 vias
(Via diameter = 13 mils
M0032−01
Figure 31. PowerPAD PCB Etch and Via Pattern
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SGLS314D–JUNE 2006–REVISED MAY 2008............................................................................................................................................................... www.ti.com
For a given θJA, the maximum power dissipation is shown in Figure 32 and is calculated by the following formula:
T
–T
MAX
A
P
+
ǒ Ǔ
D
q
JA
Where:
PD = Maximum power dissipation of TLV411x IC (watts)
TMAX = Absolute maximum junction temperature (150°C)
TA
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case
= Free-ambient air temperature (°C)
θCA = Thermal coefficient from case to ambient air (°C/W)
(2)
4.0
T = 150°C
J
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
DGN Package
Low-K Test PCB
= 52.7°C/W
θ
JA
SOIC Package
Low-K Test PCB
θ
= 176°C/W
JA
−55 −40 −25 −10
5
20 35 50 65 80 95 110 125
T
A
− Free-Air Temperature − °C
G026
NOTE: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 32. Maximum Power Dissipation vs Free-Air Temperature
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the device,
especially multi-amplifier devices. Because these devices have linear output stages (Class A-B), most of the heat
dissipation is at low output voltages with high output currents.
The other key factor when dealing with power dissipation is how the devices are mounted on the PCB. The
PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a
copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other
hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the
device, θJA decreases and the heat-dissipation capability increases. The currents and voltages shown in these
graphs are for the total package. For the dual or quad amplifier packages, the sum of the RMS output currents
and voltages should be used to choose the proper package.
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TLV4112-EP, TLV4113-EP
www.ti.com............................................................................................................................................................... SGLS314D–JUNE 2006–REVISED MAY 2008
MACROMODEL INFORMATION
Macromodel information provided was derived using Microsim Parts™, the model generation software used with
Microsim PSpice™ The Boyle macromodel (see Note 3) and subcircuit in Figure 33 are generated using the
TLV411x typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations
of the following key parameters can be generated to a tolerance of 20% (in most cases).
•
•
•
•
•
Common-mode rejection ratio
Phase margin
DC output resistance
AC output resistance
•
•
•
•
•
•
•
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
Short-circuit output current limit
Open-loop voltage amplification
Unity-gain frequency
NOTE 3: G.R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, "Macromodeling of Integrated Circuit Operational Amplifiers," IEEE Journal of Solid-State
Circuits, SC-9, 353 (1974).
3
99
V
DD
+
−
egnd
rd1
11
rd2
12
rss
ro2
css
fb
rp
c1
7
+
c2
vlim
1
2
+
−
r2
9
6
IN+
IN−
−
8
vc
D
S
D
S
+
vb
−
ga
G
G
ro1
gcm
ioff
53
OUT
dp
5
dlp
dln
91
90
92
10
−
+
−
+
−
iss
dc
vlp
hlim
vln
−
+
GND
+ 54
4
de
ve
* TLV4112_5V operational amplifier ”macromodel” subcircuit
iss
10
90
0
4
0
6
2
1
9
dc
13.800E−6
75E−9
* updated using Model Editor release 9.1 on 01/18/00 at 15:50
hlim
ioff
vlim 1K
dc
Model Editor is an OrCAD product.
*
j1
11
12
6
10 jx1
10 jx2
* connections: non−inverting input
J2
*
*
*
*
*
| inverting input
r2
100.00E3
5.9386E3
5.9386E3
10
| | positive power supply
rd1
3
11
12
5
| | | negative power supply
rd2
3
| | | | output
ro1
8
| | | | |
1 2 3 4 5
ro2
7
99
4
10
.subckt TLV4112_5V
*
rp
3
3.3333E3
14.493E6
dc 0
rss
10
9
99
0
c1
11
12
7
99
53
5
91
90
3
0
99
2.2439E−12
vb
c2
6
10.000E−12
vc
3
53
4
dc .86795
dc .86795
dc 0
dc 300
dc 300
css
dc
de
dlp
dln
dp
egnd
fb
10
5
454.55E−15
ve
54
7
dy
vlim
vlp
8
0
54
90
92
4
dy
91
0
dx
vln
92
dx
.model
.model
.model
.model
.ends
*$
dx
dy
jx1
jx2
D(Is=800.00E−18)
dx
D(Is=800.00E−18 Rs=1m Cjo=10p)
99
7
poly(2) (3,0) (4,0) 0 .5 .5
poly(5) vb vc ve vlp vln 0
NJF(Is=150.00E−12 Beta=2.0547E−3 +Vto=−1)
NJF(Is=150.00E−12 Beta=2.0547E−3 + Vto=−1)
+ 33.395E6 −1E3 1E3 33E6 −33E6
ga
gcm
6
0
0
6
11
10
12 168.39E−6
99 168.39E−12
S0096-01
Figure 33. Boyle Macromodel and Subcircuit
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Jan-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TLV4113MDGQREP
V62/06646-04ZE
ACTIVE
ACTIVE
MSOP-
PowerPAD
DGQ
DGQ
10
10
2500
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAGLevel-1-260C-UNLIM
MSOP-
PowerPAD
Green (RoHS
& no Sb/Br)
CU NIPDAUAGLevel-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV4113-EP :
Catalog: TLV4113
•
NOTE: Qualified Version Definitions:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jan-2012
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Mar-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV4113MDGQREP
MSOP-
Power
PAD
DGQ
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Mar-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
MSOP-PowerPAD DGQ 10
SPQ
Length (mm) Width (mm) Height (mm)
358.0 335.0 35.0
TLV4113MDGQREP
2500
Pack Materials-Page 2
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power.ti.com
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