V62/08628-01XE_技术文档

ADS6445-EP

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QUAD CHANNEL, 14 BIT, 125 MSPS ADC WITH SERIAL LVDS OUTPUTS

1

FEATURES

•

Supports Sine, LVCMOS, LVPECL, LVDS Clock

Inputs and Amplitude Down to 400 mV_PP

•

Controlled Baseline

Internal Reference with External Reference

Support

–

One Assembly

Test Site

No External Decoupling Required for

References

One Fabrication Site

•

–55°C to 125°C Operating Junction

Temperature Range

•

3.3-V Analog and Digital Supply

64-pin QFN Package (9 mm × 9 mm)

Pin Compatible 12-Bit Family (ADS642x)

Enhanced Diminishing Manufacturing Sources

(DMS) Support

Feature Compatible Dual Channel Family

(ADS624x, ADS644x)

•

Enhanced Product-Change Notification

(1)

Qualification Pedigree

Sample Rate: 125 MSPS

APPLICATIONS

14-Bit Resolution with No Missing Codes

Simultaneous Sample and Hold

•

Base-Station IF Receivers

Diversity Receivers

Medical Imaging

3.5-dB Coarse Gain and up to 6-dB

Programmable Fine Gain for SFDR/SNR

Trade-Off

Test Equipment

Table 1. ADS64XX Quad Channel Family⁽¹⁾

•

Serialized LVDS Outputs with Programmable

Internal Termination Option

125 MSPS 105 MSPS 80 MSPS 65 MSPS

(1) Component qualification in accordance with JEDEC and

industry standards to ensure reliable operation over an

extended temperature range. This includes, but is not limited

to, Highly Accelerated Stress Test (HAST) or biased 85/85,

temperature cycle, autoclave or unbiased HAST,

ADS644X

14 Bit

ADS6445

ADS6425

ADS6444

ADS6424

ADS6443 ADS6442

ADS6423 ADS6422

ADS642X

12 Bit

electromigration, bond intermetallic life, and mold compound

life. Such qualification testing should not be viewed as

justifying use of this component beyond specified

performance and environmental limits.

(1) Product Preview for ADS6444, ADS6443, ADS6442 and

ADS642X family

Table 2. Performance Summary

ADS6445

87

ADS6444

91

ADS6443

92

ADS6442

93

Fin = 10 MHz (0 dB gain)

Fin = 170 MHz (3.5 dB gain)

Fin = 10 MHz (0 dB gain)

Fin = 170 MHz (3.5 dB gain)

Power, per channel, mW

SFDR, dBc

79

83

84

73.4

68.3

420

73.4

69.3

340

74.2

69.4

300

74.3

70

SINAD, dBFS

265

DESCRIPTION/ORDERING INFORMATION

The ADS6445/ADS6444/ADS6443/ADS6442 (ADS644X) is a family of high performance 14 bit 125/105/80/65

MSPS quad channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in

a compact 64 pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device

includes 3.5 dB coarse gain option that can be used to improve SFDR performance with little degradation in

SNR. In addition to the coarse gain, fine gain options also exist, programmable in 1 dB steps up to 6 dB.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADS6445-EP

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The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it

possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1 Gbps easing

receiver design. The ADS644X also includes the traditional 1-wire interface that can be used at lower sampling

frequencies.

An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit

clock is used to serialize the 14 bit data from each channel. In addition to the serial data streams, the frame and

bit clocks also are transmitted as LVDS outputs.

The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and

internal termination options. These can be used to widen eye openings and improve signal integrity, easing

capture by the receiver.

The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.

The ADS644X has internal references, but also can support an external reference mode. The device is specified

over –55°C to 125°C operating junction temperature range.

2

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

BIT Clock

DCLKP

DCLKM

CLKP

CLKM

PLL

FRAME Clock

FCLKP

FCLKM

DA0_P

DA0_M

Digital

INA_P

INA_M

Encoder

and

Serializer

14 Bit

ADC

SHA

DA1_P

DA1_M

DB0_P

DB0_M

Digital

Encoder

and

INB_P

INB_M

14 Bit

ADC

DB1_P

DB1_M

Serializer

DC0_P

DC0_M

Digital

Encoder

and

INC_P

INC_M

14 Bit

ADC

DC1_P

DC1_M

Serializer

DD0_P

DD0_M

Digital

Encoder

and

IND_P

IND_M

14 Bit

ADC

DD1_P

DD1_M

Serializer

VCM

Reference

Parallel

Interface

Serial

Interface

ADS644x

B0199-03

PACKAGE/ORDERING INFORMATION⁽¹⁾

SPECIFIED

JUNCTION

TRANSPORT

MEDIA,

QUANTITY

PACKAGE

PRODUCT

PACKAGE-LEAD

ORDERING NUMBER

DESIGNATOR⁽²⁾TEMPERATURE MARKING

RANGE

ADS6445

QFN-64⁽³⁾

RGC

–55°C to 125°C

6445EP

ADS6445MRGCTEP

250, Tape/reel

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(3) For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θ_JA= 23.17 °C/W (0 LFM air flow), θ_JC

= 22.1 °C/W when used with 2 oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in. x 3 in. PCB.

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ABSOLUTE MAXIMUM RATINGS⁽¹⁾

VALUE

UNIT

V

AVDD

LVDD

Supply voltage range

–0.3 to 3.9

Supply voltage range

–0.3 to 3.9

V

Voltage between AGND and DGND

Voltage between AVDD to LVDD

Voltage applied to external pin, VCM

Voltage applied to analog input pins

Operating junction temperature range

Storage temperature range

–0.3 to 0.3

V

–0.3 to 3.3

V

–0.3 to 2.0

V

–0.3 V to minimum ( 3.6, AVDD + 0.3 V)

V

T_J

-55 to 125

–65 to 150

220

°C

T_stg

Lead temperature 1,6 mm (1/16") from the case for 10 seconds

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

NOM MAX UNIT

SUPPLIES

AVDD

LVDD

Analog supply voltage

LVDS Buffer supply voltage

3.0

3.3

3.6

V

ANALOG INPUTS

Differential input voltage range

2

V_pp

V

Input common-mode voltage

1.5±0.1

Voltage applied on VCM in external reference mode

1.45

1.50 1.55

V

CLOCK INPUT

Input clock sample rate, F_srated

Input clock amplitude differential (V_CLKP– V_CLKM

Input Clock duty cycle

ADS6445

5

125 MSPS

Sine wave, ac coupled

LVPECL, ac coupled

LVDS, ac coupled

LVCMOS, ac coupled

0.4

1.5

± 0.8

± 0.35

3.3

)

V_pp

35

50

65

%

DIGITAL OUTPUTS

Without internal termination

With internal termination

5

10

Maximum external load capacitance from each output pin

to DGND

C_LOAD

pF

R_LOAD

T_J

Differential load resistance (external) between the LVDS output pairs

Operating junction temperature

100

Ω

–55

125

°C

4

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ELECTRICAL CHARACTERISTICS

Typical values are at 25°C, min and max values are across the full junction temperature range T_J,MIN= –55°C to T_J,MAX

=

125°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1 dBFS differential analog input,

internal reference mode (unless otherwise noted).

ADS6445

UNIT

F_s= 125 MSPS

PARAMETER

MIN

TYP

MAX

RESOLUTION

14

Bits

ANALOG INPUT

Differential input voltage range

Differential input capacitance

Analog input bandwidth

2.0

7

V_PP

pF

500

MHz

µA

Analog input common mode current (per input pin of each

ADC)

155

REFERENCE VOLTAGES

VREFB

VREFT

ΔV_REF

VCM

Internal reference bottom voltage

1.0

2.0

1

V

Internal reference top voltage

Internal reference error (VREFT–VREFB)

Common mode output voltage

VCM output current capability

0.985

1.015

V

1.5

±4

V

mA

DC ACCURACY

No missing codes

Assured

E_O

Offset error, across devices and across channels within a

device

mV

–15

±2

15

Offset error temperature coefficient, across devices and

across channels within a device

0.05

mV/°C

There are two sources of gain error - internal reference inaccuracy and channel gain error

E_GREF

Gain error due to internal reference inaccuracy alone,

-0.75

0.1

0.75

% FS

(ΔV_REF/2.0) %

Reference gain error temperature coefficient

0.0125

±0.3

Δ%/°C

E_GCHAN

Gain error of channel alone, across devices and across

channels within a device

% FS

Channel gain error temperature coefficient, across devices

and across channels within a device

0.005

Δ%/°C

DNL

Differential nonlinearity, Fin = 50 MHz

Integral nonlinearity, Fin = 50 MHz

DC power supply rejection ratio

–0.99

-5

±0.6

±3

2.0

5

LSB

INL

PSRR

0.5

mV/V

POWER SUPPLY

I_CC

Total supply current

502

410

92

mA

W

I_AVDD

I_LVDD

Analog supply current

LVDS supply current

Total power

1.65

77

1.8

Power down (with input clock stopped)

150

mW

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ELECTRICAL CHARACTERISTICS

Typical values are at 25°C, min and max values are across the full junction temperature range T_J,MIN= –55°C to T_J,MAX

=

125°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1 dBFS differential analog input,

internal reference mode (unless otherwise noted).

ADS6445

F_s= 125 MSPS

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

DYNAMIC AC CHARACTERISTICS

Fin = 10 MHz

73.7

73.1

72.7

72.1

69.9

69.4

68.7

68.1

73.4

72.3

71.2

71.8

67.9

68.3

67.8

67.9

1.05

Fin = 50 MHz

Fin = 70 MHz

Fin = 100 MHz

68.5

SNR

dBFS

Signal to noise ratio

0 dB gain

Fin = 170 MHz

Fin = 230 MHz

3.5 dB Coarse gain

0 dB gain

3.5 dB Coarse gain

Fin = 10 MHz

Fin = 50 MHz

Fin = 70 MHz

Fin = 100 MHz

67.75

SINAD

Signal to noise and

distortion ratio

dBFS

LSB

0 dB gain

Fin = 170 MHz

3.5 dB Coarse gain

0 dB gain

Fin = 230 MHz

3.5 dB Coarse gain

RMS

Inputs tied to common-mode

Output noise

Fin = 10 MHz

Fin = 50 MHz

Fin = 70 MHz

Fin = 100 MHz

87

81

78

86

76

79

77

80

93

87

89

83

85

80

82

87

81

78

86

76

79

77

80

69

SFDR

Spurious free dynamic

range

dBc

0 dB gain

Fin = 170 MHz

Fin = 230 MHz

3.5 dB Coarse gain

0 dB gain

3.5 dB Coarse gain

Fin = 10 MHz

Fin = 50 MHz

Fin = 70 MHz

Fin = 100 MHz

HD2

Second harmonic

0 dB gain

Fin = 170 MHz

Fin = 230 MHz

3.5 dB Coarse gain

0 dB gain

3.5 dB Coarse gain

Fin = 10 MHz

Fin = 50 MHz

Fin = 70 MHz

Fin = 100 MHz

HD3

Third harmonic

0 dB gain

Fin = 170 MHz

Fin = 230 MHz

3.5 dB Coarse gain

0 dB gain

3.5 dB Coarse gain

6

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ELECTRICAL CHARACTERISTICS (continued)

Typical values are at 25°C, min and max values are across the full junction temperature range T_J,MIN= –55°C to T_J,MAX

=

125°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, –1 dBFS differential analog input,

internal reference mode (unless otherwise noted).

ADS6445

F_s= 125 MSPS

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

91

MAX

Fin = 10 MHz

Fin = 50 MHz

Fin = 100 MHz

Fin = 170 MHz

Fin = 230 MHz

Fin = 10 MHz

Fin = 50 MHz

Fin = 100 MHz

Fin = 170 MHz

Fin = 230 MHz

87

Worst harmonic (other

than HD2, HD3)

90

dBc

88

87

86

69

80

THD

84.5

73.5

74

dBc

Total harmonic distortion

ENOB

Effective number of bits

10.95

11.7

Fin = 50 MHz

Bits

F1= 46.09 MHz,

F2 = 50.09 MHz

88

86

90

IMD

2-Tone inter-

modulation distortion

dBFS

F1= 185.09 MHz,

F2 = 190.09 MHz

Near channel

Cross-talk signal

frequency = 10 MHz

Cross-talk

dBc

Far channel

103

Cross-talk signal

frequency = 10 MHz

Recovery to within 1% (of final value) for 6-dB overload

with sine wave input

1

Clock cycles

dBc

Input overload recovery

AC PSRR

35

Power supply rejection

ratio

< 100 MHz signal, 100 mV_PPon AVDD supply

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DIGITAL CHARACTERISTICS

The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic

level 0 or 1 AVDD = LVDD = 3.3 V, I_O= 3.5 mA, R_LOAD= 100 Ω⁽¹⁾

.

All LVDS specifications are characterized, but not tested at production.

ASD6445

TYP MAX

PARAMETER

DIGITAL INPUTS

TEST CONDITIONS

UNIT

MIN

High-level input voltage

Low-level input voltage

High-level input current

Low-level input current

Input capacitance

2.4

V

0.8

V

10

4

µA

pF

DIGITAL OUTPUTS

High-level output voltage

Low-level output voltage

Output differential voltage |V_OD

Output offset voltage V_OS

1375

1025

mV

pF

|

250 350

450

Common-mode voltage of OUTP and OUTM

1200

2

Output capacitance inside the device, from either output to

ground

Output capacitance

(1) I_Orefers to the LVDS buffer current setting, R_LOADis the external differential load resistance between the LVDS output pair.

8

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TIMING SPECIFICATIONS⁽¹⁾

Typical values are at 25°C, min and max values are across the full junction temperature range T_J,MIN= –55°C to T_J,MAX

=

125°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 V_PPclock amplitude, C_L= 5

pF ⁽²⁾, I_O= 3.5 mA, R_L= 100 Ω ⁽³⁾, no internal termination, unless otherwise noted.

ADS6445

F_s= 125 MSPS

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

t_J

Aperture jitter

Uncertainty in the sampling

instant

250

fs rms

INTERFACE: 2-wire, DDR bit clock, 14x serialization

From data cross-over to bit

clock cross-over

t_su

t_h

Data setup time^{(4) (5)(6)}

Data hold time^{(4) (5)(6)}

0.55

0.58

ns

From bit clock cross-over to

data cross-over

Input clock rising edge

cross-over to frame clock

rising edge cross-over

(6)

t_{pd_clk}

Clock propagation delay

Bit clock cycle-cycle jitter

4.4

ns

(5)

350

75

ps pp

Frame clock cycle-cycle jitter

(5)

The following specifications apply for 5 MSPS ≤ Fs ≤ 125 MSPS and all interface options.

Delay from input clock rising

t_A

Aperture delay

edge to the actual sampling

instant

2

±80

12

ns

ps

Channel-channel within same

device

Aperture delay variation

Time for a sample to

propagate to ADC outputs,

see Figure 1

(7)

ADC Latency

Clock cycles

Time to valid data after

coming out of global power

down

100

µs

Wake up time

Time to valid data after input

clock is re-started

100

200

µs

Time to valid data after

coming out of channel standby

Clock cycles

t_RISE

t_FALL

Data rise time

Data fall time

From –100 mV to +100 mV

From +100 mV to –100 mV

100

ps

Bit clock and frame clock rise

time

t_RISE

t_FALL

From –100 mV to +100 mV

From +100 mV to –100 mV

100

ps

Bit clock and frame clock fall

time

100

50%

LVDS Bit clock duty cycle

LVDS Frame clock duty

cycle

(1) Timing parameters are ensured by design and characterization and not tested in production.

(2) C_Lis the external single-ended load capacitance between each output pin and ground.

(3) I_orefers to the LVDS buffer current setting; R_Lis the external differential load resistance between the LVDS output pair.

(4) Timing parameters are measured at the end of a 2 inch PCB trace (100 Ω characteristic impedance) terminated by R_Land C_L.

(5) Setup and hold time specifications take into account the effect of jitter on the output data and clock.

(6) Refer to Output Timings in application section for timings at lower sampling frequencies and other interface options.

(7) Note that the total latency = ADC latency + internal serializer latency. The serializer latency depends on the interface option selected as

shown in Table 27.

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Sample

N+13

Sample

N+12

Sample

N+11

Sample

N

Input

Signal

t_A

CLKM

CLKP

Input

Clock

t_{PD_CLK}

Latency 12 Clocks

DCLKP

DCLKM

Bit

Clock

DOP

DOM

Output

Data

D13 D12 D11 D10

D6 D5 D4 D3 D2 D1 D0 D13 D12 D11 D10

D6 D5 D4 D3 D2 D1 D0

Sample N–1

Sample N

FCLKM

FCLKP

Frame

Clock

T0105-04

Figure 1. Latency

DCLKP

Bit Clock

DCLKM

t_su

t_h

t_su

t_h

Output Data

DOP, DOM

Dn+1

Dn

T0106-03

Figure 2. LVDS Timing

10

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DEVICE PROGRAMMING MODES

ADS644X offers flexibility with several programmable features that are easily configured.

The device can be configured independently using either parallel interface control or serial interface

programming.

In addition, the device supports a third configuration mode, where both the parallel interface and the serial control

registers are used. In this mode, the priority between the parallel and serial interfaces is determined by a priority

table (refer to Table 4). If this additional level of flexibility is not required, the user can select either the serial

interface programming or the parallel interface control.

USING PARALLEL INTERFACE CONTROL ONLY

To control the device using parallel interface, keep RESET tied to high (LVDD). Pins CFG1, CFG2, CFG3,

CFG4, PDN, SEN, SCLK, and SDATA are used to directly control certain functions of the ADC. After power-up,

the device is automatically configured as per the parallel pin voltage settings (refer to Table 5 to Table 8) and no

reset is required. In this mode, SEN, SCLK, and SDATA function as parallel interface control pins.

Frequently used functions are controlled in this mode—output data interface and format, power down modes,

coarse gain and internal/external reference. The parallel pins can be configured using a simple resistor string as

illustrated in Figure 3.

Table 3 has a description of the modes controlled by the parallel pins.

Table 3. Parallel Pin Definition

SEN

CONTROL FUNCTIONS

Coarse gain and internal/external reference.

SCLK, SDATA

PDN

Sync, deskew patterns and global power down.

Dedicated pin for global power down

CFG1

1-wire/2-wire and DDR/SDR bit clock

CFG2

14x/16x serialization and SDR bit clock capture edge

Reserved function. Tie CFG3 to Ground.

MSB/LSB first and data format.

CFG3

CFG4

USING SERIAL INTERFACE PROGRAMMING ONLY

In this mode, SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal

registers of ADC. The registers must first be reset to their default values either by applying a pulse on RESET

pin or by a high setting on the <RST> bit (in register ). After reset, the RESET pin must be kept low.

The serial interface section describes the register programming and register reset in more detail.

Because the parallel pins (CFG1-4 and PDN) are not used in this mode, they must be tied to ground. The

register override bit <OVRD> - D10 in register 0x0D has to be set high to disable the control of parallel interface

pins in this serial interface control ONLY mode.

USING BOTH THE SERIAL INTERFACE AND PARALLEL CONTROLS

For increased flexibility, a combination of serial interface registers and parallel pin controls (CFG1-4 and PDN)

also can be used to configure the device.

The parallel interface control pins CFG1 to CFG4 and PDN are available. After power-up, the device is

automatically configured as per the parallel pin voltage settings (refer to Table 5 through Table 11) and no reset

is required. A simple resistor string can be used as illustrated in Figure 3.

SEN, SDATA, and SCLK function as serial interface pins and are used to access the internal registers of ADC.

The registers must first be reset to their default values either by applying a pulse on RESET pin or by a high

setting on the <RST> bit (in register ). After reset, the RESET pin must be kept low.

The Serial Interface section describes the register programming and register reset in more detail.

Since some functions are controlled using both the parallel pins and serial registers, the priority between the two

is determined by a priority table (refer to Table 4).

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Table 4. Priority Between Parallel Pins and Serial Registers

FUNCTIONS SUPPORTED

PRIORITY

As described in Table 8

through Table 11

Register bits can control the modes only if the register bit <OVRD> is high. If <OVRD> bit

is low, then the control voltage on these parallel pins determines the function.

CFG1 to CFG4

Register bit <PDN GLOBAL> controls global power down only if PDN pin is low. If PDN is

high, device is in global power down.

PDN

SEN

Global power down

Coarse gain is controlled by register bit <COARSE GAIN> only if the <OVRD> bit is high.

Else, device has 0 dB coarse gain.

Serial interface enable

Internal/external reference setting is determined by register bit <REF>.

Register bits <PATTERNS> control the sync and deskew output patterns.

Power down is determined by bit <PDN GLOBAL>

Serial interface clock and

serial interface data pins

SCLK, SDATA

AVDD

(5/8) AVDD

3R

(5/8) AVDD

GND

AVDD

2R

3R

(3/8) AVDD

To Parallel Pin

GND

Figure 3. Simple Scheme to Configure Parallel Pins

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DESCRIPTION OF PARALLEL PINS

Table 5. SCLK, SDATA Control Pins

SCLK

SDATA

DESCRIPTION

LOW

NORMAL conversion.

SYNC – ADC outputs sync pattern on all channels. This pattern can be used by the receiver to align the

deserialized data to the frame boundary. See Capture Test Patterns for details.

LOW

HIGH

LOW

HIGH

POWER DOWN – Global power down, all channels of the ADC are powered down, including internal references,

PLL and output buffers.

DESKEW – ADC outputs deskew pattern on all channels. This pattern can be used by the receiver to ensure

deserializer uses the right clock edge. See Capture Test Patterns for details.

Table 6. SEN Control Pin

SEN

DESCRIPTION

0

External reference and 0 dB coarse gain (full-scale = 2 V_PP

External reference and 3.5 dB coarse gain (full-scale = 1.34 V_PP

Internal reference and 3.5 dB coarse gain (full-scale = 1.34 V_PP

Internal reference and 0 dB coarse gain (full-scale = 2 V_PP

)

(3/8)LVDD

(5/8)LVDD

LVDD

)

Independent of the programming mode used, after power-up the parallel pins PDN, CFG1 to CFG4 automatically

configure the device as per the voltage applied (refer to Table 7 to Table 11).

Table 7. PDN Control Pin

PDN

0

DESCRIPTION

Normal operation

AVDD

Power down global

Table 8. CFG1 Control Pin

CFG1

0

DESCRIPTION

DDR Bit clock and 1-wire interface

Not used

(3/8)LVDD

(5/8)LVDD

LVDD

SDR Bit clock and 2-wire interface

DDR Bit clock and 2-wire interface

Table 9. CFG2 Control Pin

CFG2

0

DESCRIPTION

14x Serialization and capture at falling edge of bit clock (only in 2-wire SDR bit clock mode)

16x Serialization and capture at falling edge of bit clock (only in 2-wire SDR bit clock mode)

16x Serialization and capture at rising edge of bit clock (only in 2-wire SDR bit clock mode)

14x Serialization and capture at rising edge of bit clock (only in 2-wire SDR bit clock mode)

(3/8)LVDD

(5/8)LVDD

LVDD

Table 10. CFG3 Control Pin

CFG3

RESERVED - TIE TO GROUND

Table 11. CFG4 Control Pin

CFG4

0

DESCRIPTION

MSB First and 2s complement

(3/8)LVDD

(5/8)LVDD

LVDD

MSB First and offset binary

LSB First and offset binary

LSB First and 2s complement

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SERIAL INTERFACE

The ADC has a serial interface formed by pins SEN (serial interface enable), SCLK (serial interface clock),

SDATA (serial interface data) and RESET. Serial shift of bits into the device is enabled when SEN is low. Serial

data SDATA is latched at every falling edge of SCLK when SEN is active (low). The serial data is loaded into the

register at every 16th SCLK falling edge when SEN is low. In case the word length exceeds a multiple of 16 bits,

the excess bits are ignored. Data can be loaded in multiple of 16 bit words within a single active SEN pulse. The

interface can work with SCLK frequency from 20 MHz down to very low speeds (few hertz) and even with

non-50% duty cycle SCLK.

The first 5 bits of the 16 bit word are the address of the register while the next 11 bits are the register data.

Register Reset

After power-up, the internal registers must be reset to their default values. This can be done in one of two ways:

1. Either by applying a high-going pulse on RESET (of width greater than 10 ns) OR

2. By applying software reset. Using the serial interface, set the <RST> bit in register 0x00 to high – this resets

the registers to their default values and then self-resets the <RST> bit to LOW.

When RESET pin is not used, it must be tied to LOW.

Register Address

Register Data

SDATA

A4

A3

A2

A1

A0 D10 D9

D8

D7

D6

D5

D4

D3

D2

t_(DH)

D1

D0

t_(SCLK)

t_(DSU)

SCLK

t_(SLOADH)

t_(SLOADS)

SEN

RESET

T0109-03

Figure 4. Serial Interface Timing

14

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SERIAL INTERFACE TIMING CHARACTERISTICS

Typical values at 25°C, min and max values across the full junction temperature range T_J,MIN= –55°C to T_J,MAX= 125°C,

AVDD = LVDD = 3.3 V, unless otherwise noted.

PARAMETER

SCLK Frequency, f_SCLK= 1/t_SCLK

MIN

TYP

MAX

UNIT

MHz

ns

f_SCLK

t_SLOADS

t_SLOADH

t_DSU

> DC

20

SEN to SCLK Setup time

25

SCLK to SEN Hold time

ns

SDATA Setup time

25

ns

t_DH

SDATA Hold time

25

ns

Time taken for register write to take effect after 16th SCLK falling edge

100

ns

RESET TIMING

Typical values at 25°C, min and max values across the full junction temperature range T_J,MIN= –55°C to T_J,MAX= 125°C,

AVDD = LVDD = 3.3 V, unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

Delay from power-up of AVDD and LVDD to RESET pulse

active

5

t₁

Power-on delay time

Reset pulse width

ms

t₂

Pulse width of active RESET signal

10

25

ns

t₃

Register write delay time Delay from RESET disable to SEN active

Power-up delay time Delay from power-up of AVDD and LVDD to output stable

t_PO

6.5

ms

Power Supply

AVDD, LVDD

t₁

RESET

t₂

t₃

SEN

T0108-03

Figure 5. Reset Timing

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SERIAL REGISTER MAP

Table 12. Summary of Functions Supported By Serial Interface

REGISTER

ADDRESS

REGISTER FUNCTIONS⁽¹⁾⁽²⁾

A4 - A0

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

<PDN

GLOBAL>

GLOBAL

POWER

DOWN

<REF>

INTERNAL

OR

POWER POWER POWER POWER

DOWN CH D DOWN CHC DOWN CH B DOWN CH A

<RST>

S/W RESET

00

0

EXTERNAL

INPUT CLOCK BUFFER GAIN CONTROL

04

0A

0

<DF>

DATA

FORMAT 2S

COMP OR

STRAIGHT

BINARY

TEST PATTERNS

0

CUSTOM PATTERN (LOWER 11 BITS)

0B

0C

FINE GAIN CONTROL (1 dB to 6 dB)

CUSTOM PATTERN (UPPER 3 BITS)

0

<COARSE

GAIN>

COURSE

GAIN

FALLING OR

RISING BIT

CLOCK

CAPTURE

EDGE

<OVRD>

OVERRIDE

BIT

BYTE-WISE

OR

BIT-WISE

14 BIT OR

16 BIT

SERIALIZE

DDR OR

SDR BIT

CLOCK

1-WIRE OR

2-WIRE

INTERFACE

MSB OR

LSB FIRST

0D

0

ENABLE

LVDS CURRENT SETTINGS

LVDS CURRENT DOUBLE

10

11

LVDS INTERNAL TERMINATION BIT AND WORD CLOCKS

WORD-WISE CONTROL

0

LVDS INTERNAL TERMINATION - DATA OUTPUTS

(1) The unused bits in each register (shown by blank cells in above table) must be programmed as 0.

(2) Multiple functions in a register can be programmed in a single write operation.

16

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DESCRIPTION OF SERIAL REGISTERS

Table 13. Serial Register A

REGISTER

ADDRESS

BITS

A4 - A0

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

<REF>

INTERNAL

OR

<PDN>

GLOBAL

POWER

DOWN

POWER POWER POWER POWER

DOWN CH D DOWN CHC DOWN CH B DOWN CH A

<RST>

S/W RESET

00

0

EXTERNAL

D0 - D4

Power down modes

D0

0

Normal operation

1

Global power down, including all channels ADCs, internal references, internal PLL and output

buffers

D1

0

CH A Powered up

CH A ADC Powered down

1

D2

0

CH B Powered up

CH B ADC Powered down

1

D3

0

CH C Powered up

CH C ADC Powered down

1

D4

0

CH D Powered up

CH D ADC Powered down

1

D5

0

<REF> Reference

Internal reference enabled

External reference enabled

1

D10

<RST>

1

Software reset applied – resets all internal registers and self-clears to 0

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Table 14. Serial Register B

REGISTER

ADDRESS

BITS

D5

A4 - A0

D10

D9

D8

D7

D6

D4

D3

D2

D1

D0

INPUT CLOCK BUFFER GAIN CONTROL

04

0

D6 - D2

11000

00000

01100

01010

01001

01000

<CLKIN GAIN> Input clock buffer gain control

Gain 0, minimum gain

Gain 1, default gain after reset

Gain 2

Gain 3

Gain 4

Gain 5, maximum gain

Table 15. Serial Register C

REGISTER

ADDRESS

BITS

A4 - A0

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

<DF>

DATA

DORMAT 2S

COMP OR

STRAIGHT

BINARY

TEST PATTERNS

00

0

D7 - D5

000

<PATTERNS> Capture test patterns

Normal ADC operation

Output all zeros

001

010

Output all ones

011

Output toggle pattern

Unused

100

101

Output custom pattern (contents of CUSTOM pattern registers 0x0B and 0x0C)

Output DESKEW pattern (serial stream of 1010..)

Output SYNC pattern

110

111

D9

0

<DF> Data format selection

2s Complement format

Straight binary format

1

18

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Table 16. Serial Register D

REGISTER

ADDRESS

BITS

A4 - A0

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

CUSTOM PATTERN (LOWER 11 BITS)

0B

D10 - D0

<CUSTOM A> Lower 11 bits of custom pattern <D10>…<D0>

Table 17. Serial Register E

REGISTER

ADDRESS

BITS

A4 - A0

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

FINE GAIN CONTROL (1 dB to 6 dB)

CUSTOM PATTERN (UPPER 3 BITS)

0C

0

D4 - D0

<CUSTOM B> Upper 3 bits of custom pattern <D13>…<D11>

<FINE GAIN> Fine gain control

D10-D8

000

0 dB Gain (full-scale range = 2.00 V_PP

1 dB Gain (full-scale range = 1.78 V_PP

2 dB Gain (full-scale range = 1.59 V_PP

3 dB Gain (full-scale range = 1.42 V_PP

4 dB Gain (full-scale range = 1.26 V_PP

5 dB Gain (full-scale range = 1.12 V_PP

6 dB Gain (full-scale range = 1.00 V_PP

)

001

010

011

100

101

110

Table 18. Serial Register F

REGISTER

ADDRESS

BITS

A4 - A0

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

<COARSE

GAIN>

COURSE

GAIN

FALLING OR

RISING BIT

CLOCK

CAPTURE

EDGE

<OVRD>

OVER-RIDE

BITE

BYTE-WISE

OR

BIT-WISE

14 BIT OR

16 BIT

SERIALIZE

DDR OR

SDR BIT

CLOCK

1-WIRE OR

2- WIRE

INTERFACE

MSB OR

LSB FIRST

0D

0

ENABLE

D0

0

Interface selection

1-Wire interface

2-Wire interface

1

D1

0

Bit clock selection (only in 2-wire interface)

DDR Bit clock

1

SDR Bit clock

D2

0

Serialization factor selection

14X Serialization

1

16X Serialization

D4

0

Bit clock capture edge (only when SDR bit clock is selected, D1 = 1)

Capture data with falling edge of bit clock

1

Capture data with rising edge of bit clock

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D5

0

<COARSE GAIN>Coarse gain control

0 dB Coarse gain (full-scale range = 2.0 V_PP

)

1

3.5 dB Coarse gain (full-scale range = 1.34 V_PP)

D6

0

MSB or LSB First selection

MSB First

1

LSB First

D7

0

Byte/bit wise outputs (only when 2-wire is selected)

Byte wise

Bit wise

1

D10

<OVRD> Over-ride bit. All the functions in register 0x0D also can be controlled using the

parallel control pins. By setting bit <OVRD> = 1, the contents of register 0x0D will over-ride

the settings of the parallel pins.

0

1

Disable over-ride

Enable over-ride

Table 19. Serial Register G

REGISTER

ADDRESS

BITS

A4 - A0

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

LVDS CURRENT SETTINGS

LVDS CURRENT DOUBLE

10

LVDS INTERNAL TERMINATION BIT AND WORD CLOCKS

D0

0

<CURR DOUBLE> LVDS current double for data outputs

Nominal LVDS current, as set by <D5…D2>

Double the nominal value

1

D1

0

<CURR DOUBLE> LVDS current double for bit and word clock outputs

Nominal LVDS current, as set by <D5…D2>

Double the nominal value

1

D3-D2

00

<LVDS CURR> LVDS current setting for data outputs

3.5 mA

4 mA

01

10

2.5 mA

3 mA

11

D5-D4

00

<LVDS CURR> LVDS current setting for bit and word clock outputs

3.5 mA

4 mA

01

10

2.5 mA

3 mA

11

D10-D6

00000

00001

<TERM CLK> LVDS internal termination for bit and word clock outputs

No internal termination

166 Ω

20

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00010

00100

01000

10000

200 Ω

250 Ω

333 Ω

500 Ω

Any combination of above bits also can be programmed, resulting in a parallel combination of

the selected values. For example, 00101 is the parallel combination of 166||250 = 100 Ω

00101

100 Ω

Table 20. Serial Register H

REGISTER

ADDRESS

BITS

A4 - A0

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

LVDS INTERNAL TERMINATION - DATA OUTPUTS

11

WORD-WISE CONTROL

0

D4-D0

00000

00001

00010

00100

01000

10000

<TERM DATA> LVDS internal termination for data outputs

No internal termination

166 Ω

200 Ω

250 Ω

333 Ω

500 Ω

Any combination of above bits can also be programmed, resulting in a parallel combination

of the selected values. For example, 00101 is the parallel combination of 166||250 = 100 Ω

00101

100 Ω

D10-D9

00

Only when 2-wire interface is selected

Byte-wise or bit-wise output, 1x frame clock

Word-wise output enabled, 0.5x frame clock

Do not use

11

01,10

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PIN CONFIGURATION (2-WIRE INTERFACE)

ADS644x

RGC PACKAGE

(TOP VIEW)

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

DA1_P

DA1_M

DA0_P

DA0_M

CAP

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

DD0_M

DD0_P

DD1_M

DD1_P

SCLK

2

3

4

5

RESET

LVDD

6

SDATA

SEN

7

AGND

AVDD

AGND

INA_M

INA_P

AGND

INB_M

INB_P

AGND

8

PDN

PAD

9

AVDD

AGND

IND_M

IND_P

AGND

INC_M

INC_P

AGND

10

11

12

13

14

15

16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

P0056-04

PIN ASSIGNMENTS (2-WIRE INTERFACE)

PINS

I/O

NO. OF PINS

DESCRIPTION

NAME

NO.

SUPPLY AND GROUND PINS

9, 17, 19,

AVDD

6

Analog power supply

Analog ground

27, 32, 40

8, 10, 13,

16, 18, 23,

26, 31, 33,

AGND

11

36, 39

LVDD

7, 49, 64

54, 59

3

2

Digital power supply

Digital ground

LGND

INPUT PINS

22

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PIN ASSIGNMENTS (2-WIRE INTERFACE) (continued)

PINS

I/O

NO. OF PINS

DESCRIPTION

NAME

NO.

CLKP,

CLKM

24, 25

I

2

Differential input clock pair

INA_P,

INA_M

Differential input signal pair, channel A. If unused, the pins should be tied

to VCM. Do not float.

12, 11

15, 14

34, 35

INB_P,

INB_M

Differential input signal pair, channel B. If unused, the pins should be tied

to VCM. Do not float.

INC_P,

INC_M

Differential input signal pair, channel C If unused, the pins should be tied

to VCM. Do not float.

IND_P,

IND_M

Differential input signal pair, channel D. If unused, the pins should be tied

to VCM. Do not float.

37, 38

5

2

1

CAP

Connect 2-nF capacitor from pin to ground

This pin functions as serial interface clock input when RESET is low.

When RESET is high, it controls DESKEW, SYNC and global POWER

DOWN modes (along with SDATA). Refer to Table 5 for description.

This pin has an internal pull-down resistor.

SCLK

44

43

42

I

1

This pin functions as serial interface data input when RESET is low.

When RESET is high, it controls DESKEW, SYNC and global POWER

DOWN modes (along with SCLK). Refer to Table 5 for description.

This pin has an internal pull-down resistor.

SDATA

SEN

This pin functions as serial interface enable input when RESET is low.

When RESET is high, it controls coarse gain and internal/external

reference modes. Refer to Table 6 for description.

This pin has an internal pull-up resistor.

Serial interface reset input.

When using the serial interface

mode, the user MUST initialize

internal registers through

hardware RESET by applying a

high-going pulse on this pin or by

using software reset option.

Refer to the Seri1al Interface

section. In parallel interface

mode, tie RESET permanently

high. (SCLK, SDATA and SEN

function as parallel control pins in

this mode).

RESET

6

I

The pin has an internal pull-down

resistor to ground.

PDN

41

30

I

1

Global power down control pin.

Parallel input pin. It controls 1-wire or 2-wire interface and DDR or SDR

bit clock selection. Refer to Table 8 for description.

CFG1

1

Tie to AVDD for 2-wire interface with DDR bit clock.

Parallel input pin. It controls 14x or 16x serialization and SDR bit clock

capture edge. Refer to Table 9 for description.

CFG2

29

I

1

For 14x serialization with DDR bit clock, tie to ground or AVDD.

CFG3

CFG4

28

21

I

1

RESERVED pin - Tie to ground.

Parallel input pin. It controls data format and MSB or LSB first modes.

Refer to Table 11 for description.

Internal reference mode – common-mode voltage output

External reference mode – reference input. The voltage forced on this

pin sets the internal reference.

VCM

22

I/O

1

OUTPUT PINS

DA0_P,D

A0_M

3, 4

1, 2

O

2

Channel A differential LVDS data output pair, wire 0

Channel A differential LVDS data output pair, wire 1

DA1_P,D

A1_M

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PIN ASSIGNMENTS (2-WIRE INTERFACE) (continued)

PINS

I/O

NO. OF PINS

DESCRIPTION

NAME

NO.

DB0_P,D

B0_M

62, 63

O

2

Channel B differential LVDS data output pair, wire 0

Channel B differential LVDS data output pair, wire 1

Channel C differential LVDS data output pair, wire 0

Channel C differential LVDS data output pair, wire 1

Channel D differential LVDS data output pair, wire 0

Channel D differential LVDS data output pair, wire 1

Differential bit clock output pair

DB1_P,D

B1_M

60, 61

52, 53

50, 51

47, 48

45, 46

57, 58

DC0_P,D

C0_M

DC1_P,D

C1_M

DD0_P,D

D0_M

DD1_P,D

D1_M

DCLKP,

DCLKM

FCLKP,F

CLKM

55, 56

20

2

1

Differential frame clock output pair

Do Not Connect

NC

Connect to ground plane using multiple vias. Refer to Board Design

Considerations section.

PAD

0

24

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PIN CONFIGURATION (1-WIRE INTERFACE)

ADS644x

RGC PACKAGE

(TOP VIEW)

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

UNUSED

CAP

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

UNUSED

SCLK

2

3

4

5

RESET

LVDD

6

SDATA

SEN

7

AGND

8

PDN

PAD

AVDD

9

AVDD

AGND

10

11

12

13

14

15

16

AGND

IND_M

IND_P

AGND

INC_M

INC_P

AGND

INA_M

INA_P

AGND

INB_M

INB_P

AGND

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

P0056-05

PIN ASSIGNMENTS (1-WIRE INTERFACE)

PINS

NO. OF

PINS

I/O

DESCRIPTION

NAME

NO.

SUPPLY AND GROUND PINS

9, 17, 19, 27,

AVDD

32, 40

6

Analog power supply

Analog ground

8, 10, 13, 16,

18, 23, 26, 31,

33, 36, 39

AGND

11

LVDD

7, 49, 64

54, 59

3

2

Digital power supply

Digital ground

LGND

INPUT PINS

CLKP, CLKM

24, 25

I

2

Differential input clock pair

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PIN ASSIGNMENTS (1-WIRE INTERFACE) (continued)

PINS

NO. OF

PINS

I/O

DESCRIPTION

NAME

NO.

Differential input signal pair, channel A. If unused, the pins should be tied to VCM. Do

not float.

INA_P, INA_M

12, 11

I

2

Differential input signal pair, channel B. If unused, the pins should be tied to VCM. Do

not float.

INB_P, INB_M

INC_P, INC_M

15, 14

34, 35

Differential input signal pair, channel C. If unused, the pins should be tied to VCM. Do

not float.

Differential input signal pair, channel D. If unused, the pins should be tied to VCM. Do

not float.

IND_P, IND_M

CAP

37, 38

5

2

1

Connect 2 nF capacitance from pin to ground

This pin functions as serial interface clock input when RESET is low.

When RESET is high, it controls DESKEW, SYNC and global POWER DOWN

modes (along with SDATA). Refer to Table 5 for description.

This pin has an internal pull-down resistor.

SCLK

SDATA

SEN

44

43

42

I

1

This pin functions as serial interface data input when RESET is low.

When RESET is high, it controls DESKEW, SYNC and global POWER DOWN

modes (along with SCLK). Refer to Table 5 for description.

This pin has an internal pull-down resistor.

This pin functions as serial interface enable input when RESET is low.

When RESET is high, it controls coarse gain and internal/external reference modes.

Refer to Table 6 for description.

This pin has an internal pull-up resistor.

Serial interface reset input.

When using the serial interface mode, the user MUST initialize internal registers

through hardware RESET by applying a high-going pulse on this pin or by using

software reset option. Refer to the Serial Interface section. In parallel interface mode,

tie RESET permanently high. (SCLK, SDATA and SEN function as parallel control

pins in this mode).

RESET

6

I

1

The pin has an internal pull-down resistor to ground.

Global power down control pin.

PDN

41

30

I

1

Parallel input pin. It controls 1-wire or 2-wire interface and DDR or SDR bit clock

selection. Refer to Table 8 for description.

CFG1

Tie to ground for 1-wire interface with DDR bit clock.

Parallel input pin. It controls 14x or 16x serialization and SDR bit clock capture edge.

Refer to Table 9 for description.

CFG2

29

I

1

For 14x serialization with DDR bit clock, tie to ground or AVDD.

CFG3

CFG4

28

21

I

1

RESERVED pin - Tie to ground.

Parallel input pin. It controls data format and MSB or LSB first modes. Refer to

Table 11 for description.

Internal reference mode – common-mode voltage output

External reference mode – reference input. The voltage forced on this pin sets the

internal reference.

VCM

22

I/O

1

OUTPUT PINS

DA_P,DA_M

DB_P,DB_M

DC_P,DC_M

DD_P,DD_M

62, 63

60, 61

52, 53

50, 51

57, 58

55, 56

1–4, 45–48

20

O

2

8

1

Channel A differential LVDS data output pair

Channel B differential LVDS data output pair

Channel C differential LVDS data output pair

Channel D differential LVDS data output pair

Differential bit clock output pair

DCLKP,DCLKM

FCLKP,FCLKM

UNUSED

Differential frame clock output pair

These pins are unused in the 1-wire interface. Do not connect

Do not connect

NC

Connect to ground plane using multiple vias. Refer to Board Design Considerations in

the application section.

PAD

0

1

26

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TYPICAL CHARACTERISTICS

All plots are at 25°C, AVDD = LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 V_PPdifferential

clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain (unless

otherwise noted)

ADS6445 (F_srated= 125 MSPS)

FFT for 10 MHz INPUT SIGNAL

FFT for 100 MHz INPUT SIGNAL

0

−20

0

−20

SFDR = 88 dBc

SINAD = 74 dBFS

SNR = 74.3 dBFS

THD = 87.6 dBc

SFDR = 86 dBc

SINAD = 72.63 dBFS

SNR = 72.76 dBFS

THD = 85 dBc

−40

−60

−80

−100

−120

−140

−160

−100

−120

−140

−160

0

10

20

30

40

50

60

0

10

20

30

40

50

60

f − Frequency − MHz

G001

G002

Figure 6.

Figure 7.

FFT for 230 MHz INPUT SIGNAL

INTERMODULATION DISTORTION (IMD) vs FREQUENCY

0

−20

0

SFDR = 77.9 dBc

f

1 = 185.1 MHz, –7 dBFS

2 = 190.1 MHz, –7 dBFS

2-Tone IMD = –86 dBFS

SFDR = –95 dBFS

IN

SINAD = 68 dBFS

SNR = 69.2 dBFS

THD = 75.3 dBc

IN

−20

−40

−60

−80

−100

−120

−140

−160

−100

−120

−140

−160

10

20

30

40

50

60

0

10

20

30

40

50

60

f − Frequency − MHz

G003

G004

Figure 8.

Figure 9.

SFDR vs INPUT FREQUENCY

SNR vs INPUT FREQUENCY

92

90

88

86

84

82

80

78

76

74

75

74

73

72

71

70

69

68

67

Gain = 3.5 dB

Gain = 0 dB

Gain = 3.5 dB

Gain = 0 dB

50

100

150

200

250

0

50

100

150

200

250

f

IN

− Input Frequency − MHz

f

IN

− Input Frequency − MHz

G005

G006

Figure 10.

Figure 11.

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ADS6445 (F_srated= 125 MSPS) (continued)

SFDR vs INPUT FREQUENCY ACROSS GAINS

SINAD vs INPUT FREQUENCY ACROSS GAINS

92

90

88

86

84

82

80

78

76

74

75

74

73

72

71

70

69

68

67

66

65

Input adjusted to get −1dBFS input

6 dB

0 dB

3.5 dB

2 dB

1 dB

4 dB

5 dB

3 dB

2 dB

4 dB

5 dB

6 dB

0 dB

1 dB

10 30 50 70 90 110 130 150 170 190 210 230

20

40

60

80 100 120 140 160 180 200 220

f

IN

− Input Frequency − MHz

f

IN

− Input Frequency − MHz

G007

G008

Figure 12.

Figure 13.

PERFORMANCE vs AVDD

PERFORMANCE vs LVDD

98

94

90

86

82

78

75

74

73

72

71

70

88

86

84

82

80

78

76

74

72

78

77

76

75

74

73

72

71

70

f

= 50.1 MHz

f

= 50.1 MHz

IN

SFDR

AV = 3.3 V

DD

LV = 3.3 V

DD

SNR

SFDR

3.0

3.1

3.2

3.3

3.4

3.5

3.6

3.0

3.1

3.2

3.3

3.4

3.5

3.6

LV − Supply Voltage − V

DD

AV − Supply Voltage − V

DD

G010

G009

Figure 14.

Figure 15.

PERFORMANCE vs TEMPERATURE

PERFORMANCE vs INPUT AMPLITUDE

86

84

82

80

78

76

74

77

76

75

74

73

72

71

110

100

90

78

77

76

75

74

73

72

71

70

SFDR (dBFS)

SFDR

80

SNR (dBFS)

70

SNR

60

50

SFDR (dBc)

40

f

IN

= 50.1 MHz

f

IN

= 20 MHz

−10 0

30

−60

−50

−40

−30

−20

−40

−20

0

20

40

60

80

Input Amplitude − dBFS

T − Temperature − °C

G012

G011

Figure 16.

Figure 17.

28

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ADS6445 (F_srated= 125 MSPS) (continued)

PERFORMANCE vs CLOCK AMPLITUDE (differential)

PERFORMANCE vs CLOCK DUTY CYCLE

90

89

88

87

86

85

84

78

77

76

75

74

73

72

86

84

82

80

78

76

74

72

77

f

IN

= 50.1 MHz

SFDR

76

75

74

73

72

71

70

SFDR

SNR

f

IN

= 20.1 MHz

0.5

1.0

1.5

2.0

2.5

3.0

35

40

45

50

55

60

65

Input Clock Amplitude − V

Input Clock Duty Cycle − %

PP

G013

G014

Figure 18.

Figure 19.

OUTPUT NOISE HISTOGRAM WITH

INPUTS TIED TO COMMON-MODE

POWER DISSIPATION vs SAMPLING FREQUENCY

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

40

RMS (LSB) = 1.064

35

30

25

20

15

10

5

AVDD

LVDD

0

8187 8188 8189 8190 8191 8192 8193 8194 8195 8196

0

25

50

75

100

125

f

S

− Sampling Frequency − MSPS

G015

Output Code

G016

Figure 20.

Figure 21.

PERFORMANCE IN EXTERNAL REFERENCE MODE

CMRR vs FREQUENCY

94

92

90

88

86

84

78

0

f

= 50.1 MHz

IN

−10

−20

−30

−40

−50

−60

−70

−80

−90

−100

External Reference Mode

76

74

72

70

68

SNR

SFDR

0

50

100

150

200

250

300

1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70

f − Frequency − MHz

V

VCM

− VCM Voltage − V

G018

G017

Figure 22.

Figure 23.

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ADS6444 (F_srated= 105 MSPS)

FFT for 10 MHz INPUT SIGNAL

FFT for 70 MHz INPUT SIGNAL

0

−20

0

−20

SFDR = 91.2 dBc

SFDR = 81.2 dBc

SINAD = 73.9 dBFS

SNR = 74.1 dBFS

THD = 89.7 dBc

SINAD = 71.6 dBFS

SNR = 72.6 dBFS

THD = 79.9 dBc

−40

−60

−80

−100

−120

−140

−160

−100

−120

−140

−160

0

10

20

30

40

50

0

10

20

30

40

50

f − Frequency − MHz

G019

G020

Figure 24.

Figure 25.

FFT for 230 MHz INPUT SIGNAL

INTERMODULATION DISTORTION (IMD) vs FREQUENCY

0

−20

0

SFDR = 81 dBc

SINAD = 68.6 dBFS

SNR = 69 dBFS

THD = 79 dBc

f

1 = 185.1 MHz, –7 dBFS

2 = 190.1 MHz, –7 dBFS

IN

−20

−40

2-Tone IMD = –88 dBFS

SFDR = –89 dBFS

−40

−60

−80

−100

−120

−140

−160

−100

−120

−140

−160

10

20

30

40

50

0

10

20

30

40

50

f − Frequency − MHz

G021

G022

Figure 26.

Figure 27.

SFDR vs INPUT FREQUENCY

SNR vs INPUT FREQUENCY

92

90

88

86

84

82

80

78

76

75

74

73

72

71

70

69

68

67

66

Gain = 3.5 dB

Gain = 0 dB

Gain = 3.5 dB

Gain = 0 dB

50

100

150

200

250

0

50

100

150

200

250

f

IN

− Input Frequency − MHz

f

IN

− Input Frequency − MHz

G023

G024

Figure 28.

Figure 29.

30

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ADS6444 (F_srated= 105 MSPS) (continued)

SFDR vs INPUT FREQUENCY ACROSS GAINS

SINAD vs INPUT FREQUENCY ACROSS GAINS

92

90

88

86

84

82

80

78

76

74

75

74

73

72

71

70

69

68

67

66

65

Input adjusted to get −1dBFS input

0 dB

3.5 dB

4 dB

5 dB

1 dB

2 dB

3 dB

6 dB

2 dB

1 dB

0 dB

4 dB

5 dB

6 dB

10 30 50 70 90 110 130 150 170 190 210 230

20

40

60

80 100 120 140 160 180 200 220

f

IN

− Input Frequency − MHz

f

IN

− Input Frequency − MHz

G025

G026

Figure 30.

Figure 31.

PERFORMANCE vs AVDD

PERFORMANCE vs LVDD

98

94

90

86

82

78

75

74

73

72

71

70

88

86

84

82

80

78

76

74

72

78

f

= 70.1 MHz

f

= 70.1 MHz

IN

77

76

75

74

73

72

71

70

AV = 3.3 V

DD

LV = 3.3 V

DD

SFDR

SNR

SFDR

SNR

3.0

3.1

3.2

3.3

3.4

3.5

3.6

3.0

3.1

3.2

3.3

3.4

3.5

3.6

LV − Supply Voltage − V

DD

AV − Supply Voltage − V

DD

G028

G027

Figure 32.

Figure 33.

PERFORMANCE vs TEMPERATURE

PERFORMANCE vs INPUT AMPLITUDE

86

84

82

80

78

76

74

77

76

75

74

73

72

71

110

100

90

85

80

75

70

65

60

55

50

SFDR (dBFS)

SFDR

SNR

80

SNR (dBFS)

70

60

50

SFDR (dBc)

40

f

IN

= 70.1 MHz

f

IN

= 20 MHz

−10 0

30

−60

−40

−20

0

20

40

60

80

−50

−40

−30

−20

T − Temperature − °C

Input Amplitude − dBFS

G029

G030

Figure 34.

Figure 35.

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ADS6444 (F_srated= 105 MSPS) (continued)

PERFORMANCE vs CLOCK AMPLITUDE (differential)

PERFORMANCE vs CLOCK DUTY CYCLE

92

90

88

86

84

82

80

78

76

93

91

89

87

85

83

76

75

74

73

72

71

f

IN

= 70.1 MHz

f

IN

= 20.1 MHz

SFDR

75

74

73

72

71

70

69

68

SNR

SFDR

2.0

35

40

45

50

55

60

65

0.5

1.0

1.5

2.5

3.0

Input Clock Duty Cycle − %

Input Clock Amplitude − V

PP

G032

G031

Figure 36.

Figure 37.

OUTPUT NOISE HISTOGRAM WITH

INPUTS TIED TO COMMON-MODE

POWER DISSIPATION vs SAMPLING FREQUENCY

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

40

RMS (LSB) = 1.054

35

30

25

20

15

10

5

AVDD

LVDD

0

8179 8180 8181 8182 8183 8184 8185 8186 8187 8188

0

20

40

60

80

100

f

S

− Sampling Frequency − MSPS

G033

Output Code

G034

Figure 38.

Figure 39.

PERFORMANCE IN EXTERNAL REFERENCE MODE

CMRR vs FREQUENCY

85

84

83

82

81

80

76

0

f

= 70.1 MHz

IN

−10

−20

−30

−40

−50

−60

−70

−80

−90

−100

External Reference Mode

74

72

70

68

66

SNR

SFDR

1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70

0

50

100

150

200

250

300

f − Frequency − MHz

V

VCM

− VCM Voltage − V

G018

G035

Figure 40.

Figure 41.

32

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ADS6443 (F_srated= 80 MSPS)

FFT for 10 MHz INPUT SIGNAL

FFT for 70 MHz INPUT SIGNAL

0

−20

0

−20

SFDR = 91 dBc

SFDR = 85.7 dBc

SINAD = 74.2 dBFS

SNR = 74.4 dBFS

THD = 88.5 dBc

SINAD = 73 dBFS

SNR = 73.5 dBFS

THD = 83.9 dBc

−40

−60

−80

−100

−120

−140

−160

−100

−120

−140

−160

0

10

20

30

40

0

10

20

30

40

f − Frequency − MHz

G037

G038

Figure 42.

Figure 43.

FFT for 230 MHz INPUT SIGNAL

INTERMODULATION DISTORTION (IMD) vs FREQUENCY

0

−20

0

SFDR = 82 dBc

f

1 = 185.1 MHz, –7 dBFS

2 = 190.1 MHz, –7 dBFS

2-Tone IMD = –93 dBFS

SFDR = –98 dBFS

IN

SINAD = 69.4 dBFS

SNR = 69.7 dBFS

THD = 83.4 dBc

IN

−20

−40

−60

−80

−100

−120

−140

−160

−100

−120

−140

−160

10

20

30

40

0

10

20

30

40

f − Frequency − MHz

G039

G040

Figure 44.

Figure 45.

SFDR vs INPUT FREQUENCY

SNR vs INPUT FREQUENCY

96

94

92

90

88

86

84

82

80

78

76

75

74

73

72

71

70

69

68

67

66

Gain = 0 dB

Gain = 3.5 dB

Gain = 0 dB

50

100

150

200

250

0

50

100

150

200

250

f

IN

− Input Frequency − MHz

f

IN

− Input Frequency − MHz

G041

G042

Figure 46.

Figure 47.

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ADS6443 (F_srated= 80 MSPS) (continued)

SFDR vs INPUT FREQUENCY ACROSS GAINS

SINAD vs INPUT FREQUENCY ACROSS GAINS

94

92

90

88

86

84

82

80

78

76

75

74

73

72

71

70

69

68

67

66

65

Input adjusted to get −1dBFS input

4 dB

2 dB

1 dB

5 dB

3 dB

3.5 dB

0 dB

6 dB

2 dB

1 dB

0 dB

4 dB

5 dB

6 dB

10 30 50 70 90 110 130 150 170 190 210 230

20

40

60

80 100 120 140 160 180 200 220

f

IN

− Input Frequency − MHz

f

IN

− Input Frequency − MHz

G043

G044

Figure 48.

Figure 49.

PERFORMANCE vs AVDD

PERFORMANCE vs LVDD

92

91

90

89

88

87

86

76

75

74

73

72

71

70

94

92

90

88

86

84

82

78

77

76

75

74

73

72

f

= 50.1 MHz

f

= 50.1 MHz

IN

AV = 3.3 V

DD

LV = 3.3 V

DD

SNR

SFDR

SNR

3.0

3.1

3.2

3.3

3.4

3.5

3.6

3.0

3.1

3.2

3.3

3.4

3.5

3.6

LV − Supply Voltage − V

DD

AV − Supply Voltage − V

DD

G046

G045

Figure 50.

Figure 51.

PERFORMANCE vs TEMPERATURE

PERFORMANCE vs INPUT AMPLITUDE

92

90

88

86

84

82

78

77

76

75

74

73

110

100

90

85

80

75

70

65

60

55

50

f

IN

= 50.1 MHz

SFDR (dBFS)

SFDR

SNR

80

SNR (dBFS)

70

60

50

SFDR (dBc)

40

f

IN

= 20 MHz

−10 0

30

−60

−50

−40

−30

−20

−40

−20

0

20

40

60

80

Input Amplitude − dBFS

T − Temperature − °C

G048

G047

Figure 52.

Figure 53.

34

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ADS6443 (F_srated= 80 MSPS) (continued)

PERFORMANCE vs CLOCK AMPLITUDE (differential)

PERFORMANCE vs CLOCK DUTY CYCLE

92

90

88

86

84

82

80

78

76

78

76

75

74

73

72

71

92

90

88

86

84

82

f

IN

= 50.1 MHz

77

76

75

74

73

72

71

70

SFDR

SNR

f

IN

= 20.1 MHz

0.5

1.0

1.5

2.0

2.5

3.0

35

40

45

50

55

60

65

Input Clock Amplitude − V

Input Clock Duty Cycle − %

PP

G049

G050

Figure 54.

Figure 55.

OUTPUT NOISE HISTOGRAM WITH

INPUTS TIED TO COMMON-MODE

POWER DISSIPATION vs SAMPLING FREQUENCY

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

40

RMS (LSB) = 1.016

35

30

25

20

15

10

5

AVDD

LVDD

0

8180 8181 8182 8183 8184 8185 8186 8187 8188 8189

0

20

40

60

80

f

S

− Sampling Frequency − MSPS

G051

Output Code

G052

Figure 56.

Figure 57.

PERFORMANCE IN EXTERNAL REFERENCE MODE

CMRR vs FREQUENCY

96

94

92

90

88

86

76

0

f

= 50.1 MHz

IN

−10

−20

−30

−40

−50

−60

−70

−80

−90

−100

External Reference Mode

74

72

70

68

66

SNR

SFDR

1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70

0

50

100

150

200

250

300

f − Frequency − MHz

V

VCM

− VCM Voltage − V

G018

G053

Figure 58.

Figure 59.

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ADS6442 (F_srated= 65 MSPS)

FFT for 10 MHz INPUT SIGNAL

FFT for 50 MHz INPUT SIGNAL

0

−20

0

−20

SFDR = 92.4 dBc

SFDR = 88.8 dBc

SINAD = 74.3 dBFS

SNR = 74.5 dBFS

THD = 90 dBc

SINAD = 73.6 dBFS

SNR = 73.9 dBFS

THD = 86.6 dBc

−40

−60

−80

−100

−120

−140

−160

−100

−120

−140

−160

0

10

20

30

0

10

20

30

f − Frequency − MHz

G055

G056

Figure 60.

Figure 61.

FFT for 230 MHz INPUT SIGNAL

INTERMODULATION DISTORTION (IMD) vs FREQUENCY

0

−20

0

SFDR = 82.1 dBc

f

1 = 185.1 MHz, –7 dBFS

2 = 190.1 MHz, –7 dBFS

2-Tone IMD = –96 dBFS

SFDR = –86 dBFS

IN

SINAD = 69.3 dBFS

SNR = 69.7 dBFS

THD = 81.2 dBc

IN

−20

−40

−60

−80

−100

−120

−140

−160

−100

−120

−140

−160

10

20

30

0

10

20

30

f − Frequency − MHz

G057

G058

Figure 62.

Figure 63.

SFDR vs INPUT FREQUENCY

SNR vs INPUT FREQUENCY

96

94

92

90

88

86

84

82

80

78

76

75

74

73

72

71

70

69

68

67

Gain = 0 dB

Gain = 3.5 dB

Gain = 0 dB

50

100

150

200

250

0

50

100

150

200

250

f

IN

− Input Frequency − MHz

f

IN

− Input Frequency − MHz

G059

G060

Figure 64.

Figure 65.

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ADS6442 (F_srated= 65 MSPS) (continued)

SFDR vs INPUT FREQUENCY ACROSS GAINS

SINAD vs INPUT FREQUENCY ACROSS GAINS

96

94

92

90

88

86

84

82

80

78

76

75

74

73

72

71

70

69

68

67

66

65

Input adjusted to get −1dBFS input

5 dB

3.5 dB

1 dB

2 dB

3 dB

4 dB

3 dB

0 dB

6 dB

1 dB

4 dB

2 dB

5 dB

6 dB

0 dB

10 30 50 70 90 110 130 150 170 190 210 230

20

40

60

80 100 120 140 160 180 200 220

f

IN

− Input Frequency − MHz

f

IN

− Input Frequency − MHz

G061

G062

Figure 66.

Figure 67.

PERFORMANCE vs AVDD

PERFORMANCE vs LVDD

92

91

90

89

88

87

86

76

75

74

73

72

71

70

94

92

90

88

86

84

82

78

77

76

75

74

73

72

f

= 50.1 MHz

f

= 50.1 MHz

IN

AV = 3.3 V

DD

LV = 3.3 V

DD

SNR

SFDR

SNR

3.0

3.1

3.2

3.3

3.4

3.5

3.6

3.0

3.1

3.2

3.3

3.4

3.5

3.6

LV − Supply Voltage − V

DD

AV − Supply Voltage − V

DD

G064

G063

Figure 68.

Figure 69.

PERFORMANCE vs TEMPERATURE

PERFORMANCE vs INPUT AMPLITUDE

96

94

92

90

88

86

84

79

78

77

76

75

74

73

110

100

90

85

80

75

70

65

60

55

50

SFDR

SFDR (dBFS)

80

SNR (dBFS)

70

60

SNR

50

SFDR (dBc)

40

f

IN

= 50.1 MHz

f

IN

= 20 MHz

−10 0

30

−60

−40

−20

0

20

40

60

80

−50

−40

−30

−20

T − Temperature − °C

Input Amplitude − dBFS

G065

G066

Figure 70.

Figure 71.

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ADS6442 (F_srated= 65 MSPS) (continued)

PERFORMANCE vs CLOCK AMPLITUDE (differential)

PERFORMANCE vs CLOCK DUTY CYCLE

96

94

92

90

88

86

84

82

80

95

93

91

89

87

85

76

75

74

73

72

71

f

IN

= 50.1 MHz

79

78

77

76

75

74

73

72

SFDR

SNR

f

IN

= 20.1 MHz

35

40

45

50

55

60

65

0.5

1.0

1.5

2.0

2.5

3.0

Input Clock Duty Cycle − %

Input Clock Amplitude − V

PP

G068

G067

Figure 72.

Figure 73.

OUTPUT NOISE HISTOGRAM WITH

INPUTS TIED TO COMMON-MODE

POWER DISSIPATION vs SAMPLING FREQUENCY

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

40

RMS (LSB) = 1.027

35

30

25

20

15

10

5

AVDD

LVDD

0

8189 8190 8191 8192 8193 8194 8195 8196 8197

0

10

20

30

40

50

60

f

S

− Sampling Frequency − MSPS

G069

Output Code

G070

Figure 74.

Figure 75.

PERFORMANCE IN EXTERNAL REFERENCE MODE

CMRR vs FREQUENCY

96

94

92

90

88

86

76

0

f

= 50.1 MHz

IN

−10

−20

−30

−40

−50

−60

−70

−80

−90

−100

External Reference Mode

74

72

70

68

66

SNR

SFDR

0

50

100

150

200

250

300

1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70

f − Frequency − MHz

V

VCM

− VCM Voltage − V

G018

G071

Figure 76.

Figure 77.

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Contour Plots across Input and Sampling Frequencies

125

65

92

89

86

80

83

120

110

100

90

86

80

83

74

89

68

71

77

83

86

80

83

86

80

74

68

71

77

89

70

80

65

60

83

50

89

68

71

77

40

74

350

86

80

83

150

65

500

30

10

50

100

200

250

300

400

450

f_IN- Input Frequency - MHz

75 80

65

70

85

90

SFDR - dBc

M0049-13

Figure 78. SFDR Contour (no gain)

125

120

85

79

91

88

76

70

82

110

100

90

91

88

73

88

79

85

94

82

76

82

88

80

70

91

67

73

70

79

85

60

88

76

50

70

82

40

91

65

79

250

73

85

150

76

300

30

10

50

100

200

350

400

450

500

f_IN- Input Frequency - MHz

80

70

75

85

90

SFDR - dBc

M0049-14

Figure 79. SFDR Contour (3.5 dB coarse gain)

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Contour Plots across Input and Sampling Frequencies (continued)

125

68

64

120

110

100

90

67

65

72

66

73

74

70

69

71

66

64

65

67

68

80

71

69

72

70

73

74

60

66

65

64

50

67

66

40

69

68

72

70

73

71

64

74

65

70

63

62

30

10

50

100

150

200

250

300

350

400

450

500

75

f_IN- Input Frequency - MHz

60

65

SNR - dBFS

M0048-13

Figure 80. SNR Contour (no gain)

125

120

110

100

90

67

66

72

65

68

69

71

70

67

71

68

80

65

72

70

69

66

64

70

60

50

71

67

72

69

40

65

64

66

63

68

70

62

63

61

30

10

50

100

150

200

250

300

350

400

450

500

f_IN- Input Frequency - MHz

60

62

64

66

68

70

72

SNR - dBFS

M0048-14

Figure 81. SNR Contour (3.5 dB coarse gain)

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APPLICATION INFORMATION

THEORY OF OPERATION

The ADS6445/ADS6444/ADS6443/ADS6442 (ADS644X) is a family of quad channel, 14 bit pipeline ADC based

on switched capacitor architecture in CMOS technology.

The conversion is initiated simultaneously by all the four channels at the rising edge of the external input clock.

After the input signals are captured by the sample and hold circuit of each channel, the samples are sequentially

converted by a series of low resolution stages. The stage outputs are combined in a digital correction logic block

to form the final 14 bit word with a latency of 12 clock cycles. The 14 bit word of each channel is serialized and

output as LVDS levels. In addition to the data streams, a bit clock and frame clock also are output. The frame

clock is aligned with the 14 bit word boundary.

ANALOG INPUT

The analog input consists of a switched-capacitor based differential sample and hold architecture, shown in

Figure 82. This differential topology results in very good AC performance even for high input frequencies. The

INP and INM pins have to be externally biased around a common-mode voltage of 1.5 V, available on VCM pin

13. For a full-scale differential input, each input pin INP, INM has to swing symmetrically between VCM + 0.5 V

and VCM – 0.5 V, resulting in a 2 V_PPdifferential input swing. The maximum swing is determined by the internal

reference voltages REFP (2.0 V nominal) and REFM (1.0 V, nominal). The sampling circuit has a 3 dB bandwidth

that extends up to 500 MHz (see Figure 83, shown by the transfer function from the analog input pins to the

voltage across the sampling capacitors, TF_ADC).

Sampling

Switch

Sampling

Capacitor

L_pkg

3 nH

RCR Filter

25 W

INP

R_on

C_par2

1 pF

C_bond

2 pF

C_samp

15 W

50 W

4.0 pF

R_esr

200 W

3.2 pF

C_par1

0.8 pF

R_on

10 W

C_samp

L_pkg

3 nH

50 W

R_on

4.0 pF

25 W

15 W

INM

C_par2

1 pF

C_bond

2 pF

Sampling

Capacitor

R_esr

200 W

Sampling

Switch

S0237-01

Figure 82. Input Sampling Circuit

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1

0

−1

−2

−3

−4

−5

−6

0

100

200

300

400

500

600

700

f

IN

− Input Frequency − MHz

G073

Figure 83. Analog Input Bandwidth (represented by magnitude of TF_ADC, see Figure 85 )

Drive Circuit Requirements

For optimum performance, the analog inputs must be driven differentially. This improves the common-mode

noise immunity and even order harmonic rejection.

A 5 Ω resistor in series with each input pin is recommended to damp out ringing caused by the package

parasitics. It is also necessary to present low impedance (< 50 Ω) for the common mode switching currents. For

example, this is achieved by using two resistors from each input terminated to the common mode voltage (VCM).

In addition to the above, the drive circuit may have to be designed to provide a low insertion loss over the

desired frequency range and matched impedance to the source. While doing this, the ADC input impedance has

to be taken into account. Figure 84 shows that the impedance (Zin, looking into the ADC input pins) decreases at

high input frequencies. The Smith chart shows that the input impedance is capacitive and can be approximated

by a series R-C up to 500 MHz.

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F1

Freq = 50 MHz

S(1, 1) = 0.967 / –13.241

Impedance = 62.211 – j421.739

1000

F1

900

Frequency = 50 MHz

Mag(Zin1) = 426.302

800

700

600

500

400

300

200

100

0

F2

Frequency = 400 MHz

Mag(Zin1) = 65.193

F1

F2

F1

F2

0

50

100

150

200

250

300

350

400

450

500

f_I-- Input Frequency -- MHz

Frequency (100 kHz to 500 MHz)

F2

Freq = 400 MHz

S(1, 1) = 0.273 / –59.329

Impedance = 58.132 – j29.510

M0087-01

Figure 84. ADC Input Impedance, Zin

Using RF-Transformers Based Drive Circuits

Figure 85 shows a configuration using a single 1:1 turns ratio transformer (for example, Coilcraft WBC1-1) that

can be used for low input frequencies up to 100 MHz.

The single-ended signal is fed to the primary winding of the RF transformer. The transformer is terminated on the

secondary side. Putting the termination on the secondary side helps to shield the kickbacks caused by the

sampling circuit from the RF transformer’s leakage inductances. The termination is accomplished by two resistors

connected in series, with the center point connected to the 1.5 V common mode (VCM pin). The value of the

termination resistors (connected to common mode) has to be low (< 100 Ω) to provide a low-impedance path for

the ADC common-mode switching current.

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TF_ADC

ADS6xxx

0.1 mF

5 W

INP

25 W

0.1 mF

25 W

INM

5 W

1:1

VCM

S0256-01

Figure 85. Single Transformer Drive Circuit

At high input frequencies, the mismatch in the transformer parasitic capacitance (between the windings) results

in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps

minimize this mismatch, and good performance is obtained for high frequency input signals. Figure 86 shows an

example using two transformers (like Coilcraft WBC1-1). An additional termination resistor pair (enclosed within

the shaded box in Figure 86) may be required between the two transformers to improve the balance between the

P and M sides. The center point of this termination must be connected to ground.

ADS6xxx

0.1 µF

5 Ω

INP

50 Ω

0.1 µF

50 Ω

INM

5 Ω

1:1

VCM

S0164-04

Figure 86. Two Transformer Drive Circuit

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Using Differential Amplifier Drive Circuits

Figure 87 shows a drive circuit using a differential amplifier (TI's THS4509) to convert a single-ended input to

differential output that can be interfaced to the ADC input pins. In addition to the single-ended to differential

conversion, the amplifier also provides gain (10 dB in Figure 87). As shown in the figure, R_FILhelps to isolate the

amplifier output from the switching inputs of the ADC. Together with C_FIL, it also forms a low-pass filter that

bandlimits the noise (and signal) at the ADC input. As the amplifier outputs are ac-coupled, the common-mode

voltage of the ADC input spins is set using two resistors connected to VCM.

The amplifier outputs also can be dc-coupled. Using the output common-mode control of the THS4509, the ADC

input pins can be biased to 1.5 V. In this case, use +4 V and -1 V supplies for the THS4509 to ensure that it's

output common-mode voltage (1.5 V) is at mid-supply.

R_F

+V_S

0.1 mF

R_FIL

500 W

5 W

0.1 mF 10 mF

0.1 mF

INP

R_S

R_G

C_FIL

200 W

0.1 mF

R_T

CM THS4509

R_G

200 W

5 W

C_FIL

R_FIL

INM

0.1 mF

500 W

R_S|| R_T

VCM ADS6xxx

0.1 mF

–V_S

0.1 mF 10 mF

0.1 mF

R_F

S0259-01

Figure 87. Drive Circuit Using THS4509

Refer to the EVM User Guide (SLAU196) for more information.

INPUT COMMON MODE

To ensure a low-noise common-mode reference, the VCM pin is filtered with a 0.1 µF low-inductance capacitor

connected to ground. The VCM pin is designed to directly drive the ADC inputs. The input stage of the ADC

sinks a common-mode current in the order of 155 µA at 125 MSPS (per input pin). Equation 1 describes the

dependency of the common-mode current and the sampling frequency.

155 mAxFs

125 MSPS

(1)

This equation helps to design the output capability and impedance of the CM driving circuit accordingly.

REFERENCE

The ADS644X has built-in internal references REFP and REFM, requiring no external components. Design

schemes are used to linearize the converter load seen by the references; this and the on-chip integration of the

requisite reference capacitors eliminates the need for external decoupling. The full-scale input range of the

converter can be controlled in the external reference mode as explained below. The internal or external reference

modes can be selected by programming the register bit <REF> (refer to Table 13).

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INTREF

Internal

VCM

Reference

1 kW

INTREF

4 kW

EXTREF

REFM

REFP

ADS6xxx

S0165-04

Figure 88. Reference Section

Internal Reference

When the device is in internal reference mode, the REFP and REFM voltages are generated internally.

Common-mode voltage (1.5 V nominal) is output on VCM pin, which can be used to externally bias the analog

input pins.

External Reference

When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on the

VCM pin is buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The differential

input

voltage

corresponding

to

full-scale

is

given

by

Equation

2.

Full−scale differential input pp + (Voltage forced on VCM) 1.33

(2)

In this mode, the range of voltage applied on VCM should be 1.45 V to 1.55 V. The 1.5-V common-mode voltage

to bias the input pins has to be generated externally.

COARSE GAIN AND PROGRAMMABLE FINE GAIN

ADS644X includes gain settings that can be used to get improved SFDR performance (compared to 0 dB gain

mode). The gain settings are 3.5 dB coarse gain and programmable fine gain from 0 dB to 6 dB. For each gain

setting, the analog input full-scale range scales proportionally, as listed in Table 21.

The coarse gain is a fixed setting of 3.5 dB and is designed to improve SFDR with little degradation in SNR (as

seen in Figure 10 and Figure 11). The fine gain is programmable in 1 dB steps from 0 to 6 dB. With fine gain

also, SFDR improvement is achieved, but at the expense of SNR (there is about 1 dB SNR degradation for every

1 dB of fine gain).

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So, the fine gain can be used to trade-off between SFDR and SNR. The coarse gain makes it possible to get

best SFDR but without losing SNR significantly. At high input frequencies, the gains are especially useful as the

SFDR improvement is significant with marginal degradation in SINAD.

The gains can be programmed using the register bits <COARSE GAIN> (refer to Table 18) and <FINE GAIN>

(refer to Table 17). Note that the default gain after reset is 0 dB.

Table 21. Full-Scale Range Across Gains

GAIN, dB

TYPE

FULL-SCALE, V_PP

0

3.5

1

Default (after reset)

Coarse setting (fixed)

2

1.34

1.78

1.59

1.42

1.26

1.12

1.00

2

3

Fine setting (programmable)

4

5

6

CLOCK INPUT

The ADS644X clock inputs can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS),

with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to

VCM using internal 5 kΩ resistors as shown in Figure 89. This allows using transformer-coupled drive circuits for

sine wave clock or ac-coupling for LVPECL, LVDS clock sources (see Figure 90 and Figure 92).

VCM

5 kW

CLKP

CLKM

ADS6xxx

S0166-04

Figure 89. Internal Clock Buffer

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0.1 mF

CLKP

Differential Sine-Wave

or PECL or LVDS Clock Input

0.1 mF

CLKM

ADS6xxx

S0167-05

Figure 90. Differential Clock Driving Circuit

Figure 91 shows a typical scheme using PECL clock drive from a CDCM7005 clock driver. SNR performance

with this scheme is comparable with that of a low jitter sine wave clock source.

V_CC

Reference Clock

REF_IN

Y0

CLKP

CLKM

V_CC

Y0B

CDCM7005

ADS6xxx

VCXO

OUTP

VCXO_INP

VCXO_INM

OUTM

CTRL

S0238-02

Figure 91. PECL Clock Drive Using CDCM7005

Single-ended CMOS clock can be ac coupled to the CLKP input, with CLKM (pin) connected to ground with a

0.1-µF capacitor, as shown in Figure 92.

0.1 mF

CMOS Clock Input

CLKP

0.1 mF

CLKM

ADS6xxx

S0168-07

Figure 92. Single-Ended Clock Driving Circuit

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For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode

noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Bandpass

filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a

non-50% duty cycle clock input.

CLOCK BUFFER GAIN

When using a sinusoidal clock input, the noise contributed by clock jitter improves as the clock amplitude is

increased. Hence, it is recommended to use large clock amplitude. As shown by Figure 18, use clock amplitude

greater than 1 V_PPto avoid performance degradation.

In addition, the clock buffer has programmable gain to amplify the input clock to support very low clock

amplitude. The gain can be set by programming the register bits <CLKIN GAIN> (refer to Table 14) and

increases monotonically from Gain 0 to Gain 4 settings. Table 22 lists the minimum clock amplitude supported for

each gain setting.

Table 22. Minimum Clock Amplitude across gains

MINIMUM CLOCK AMPLITUDE SUPPORTED

CLOCK BUFFER GAIN

mV_PPdifferential

Gain 0 (minimum gain)

Gain 1 (default gain)

Gain 2

800

400

300

200

150

Gain 3

Gain 4 (highest gain)

POWER DOWN MODES

The ADS644X has three power-down modes – global power down, channel standby and input clock stop.

Global Power Down

This is a global power-down mode in which almost the entire chip is powered down, including the four ADCs,

internal references, PLL and LVDS buffers. As a result, the total power dissipation falls to about 77 mW typical

(with input clock running). This mode can be initiated by setting the register bit <PDN GLOBAL> (refer to

Table 13). The output data and clock buffers are in high-impedance state.

The wake-up time from this mode to data becoming valid in normal mode is 100 µs.

Channel Standby

In this mode, only the ADC of each channel is powered down and this helps to get very fast wake-up times. Each

of the four ADCs can be powered down independently using the register bits <PDN CH> (refer to Table 13). The

output LVDS buffers remain powered up.

The wake-up time from this mode to data becoming valid in normal mode is 200 clock cycles.

Input Clock Stop

The converter enters this mode:

•

If the input clock frequency falls below 1 MSPS or

If the input clock amplitude is less than 400 mV_PP, differential with default clock buffer gain setting) at any

sampling frequency.

All ADCs and LVDS buffers are powered down and the power dissipation is about 235 mW. The wake-up time

from this mode to data becoming valid in normal mode is 100 µs.

Table 23. Power-Down Mode Summary

AVDD POWER

(mW)

LVDD POWER

(mW)

POWER-DOWN MODE

WAKE-UP TIME

In power-up

1360

297

–

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Table 23. Power-Down Mode Summary (continued)

AVDD POWER

(mW)

LVDD POWER

(mW)

POWER-DOWN MODE

WAKE-UP TIME

Global power down

1 Channel in standby

2 Channels in standby

3 Channels in standby

4 Channels in standby

Input clock stop

65

12

100 µs

(1)

1115

297

200 Clocks

100 µs

(1)

825

297

(1)

532

297

(1)

245

297

200

35

(1) Sampling frequency = 125 MSPS.

POWER SUPPLY SEQUENCING

During power-up, the AVDD and LVDD supplies can come up in any sequence. The two supplies are separated

inside the device. Externally, they can be driven from separate supplies or from a single supply.

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DIGITAL OUTPUT INTERFACE

The ADS644X offers several flexible output options making it easy to interface to an ASIC or an FPGA. Each of

these options can be easily programmed using either parallel pins or the serial interface.

The output interface options are:

• 1-Wire, 1× frame clock, 14× and 16× serialization with DDR bit clock

• 2-Wire, 1× frame clock, 16× serialization, with DDR and SDR bit clock, byte wise/bit wise/word wise

• 2-Wire, 1× frame clock, 14× serialization, with SDR bit clock, byte wise/bit wise/word wise

• 2-Wire, (0.5 x) frame clock, 14× serialization, with DDR bit clock, byte wise/bit wise/word wise

The maximum sampling frequency, bit clock frequency and output data rate will vary depending on the interface

options selected (refer to Table 12).

Table 24. Maximum Recommended Sampling Frequency for Different Output Interface Options

MAXIMUM

RECOMMENDED

SAMPLING

FREQUENCY,

MSPS

BIT CLOCK

FREQUENCY,

MHZ

FRAME CLOCK

FREQUENCY, MHZ

SERIAL DATA RATE,

Mbps

INTERFACE OPTIONS

14× Serialization

65

455

520

65

910

1040

875

DDR Bit

clock

1-Wire

2-Wire

16× Serialization

14× Serialization

16× Serialization

14× Serialization

16× Serialization

125

65

437.5

500

62.5

125

65

DDR Bit

clock

1000

910

455

SDR Bit

clock

65

520

65

1040

Each interface option is described in detail in the following sections.

1-WIRE INTERFACE - 14× AND 16× SERIALIZATION WITH DDR BIT CLOCK

Here the device outputs the data of each ADC serially on a single LVDS pair (1 wire). The data is available at the

rising and falling edges of the bit clock (DDR bit clock). The ADC outputs a new word at the rising edge of every

frame clock, starting with the MSB. Optionally, it can also be programmed to output the LSB first. The data rate is

14 × sample frequency (14× serialization) and 16 × sample frequency (16× serialization).

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Input Clock,

CLKP/M

Freq = Fs

Frame Clock,

FCLKP

Freq = 1 × Fs

Bit Clock – DDR,

DCLKP/M

Freq = 7 × Fs

Output Data

DA, DB, DC, DD

Data Rate = 14 × Fs

D13 D12 D11 D10

D9

D8

D7

D6

D5

(D0) (D1) (D2) (D3) (D4) (D5) (D6) (D7) (D8) (D9)

D4

D13 D12

(D0) (D1)

D3

D2

D1

(D10) (D11) (D12) (D13)

D0

Bit Clock – DDR,

DCLKP/M

Freq = 8 × Fs

Output Data

DA, DB, DC, DD

Data Rate = 16 × Fs

0

D13 D12 D11 D10 D9

D8

D7

D6

(D0) (D1) (D2) (D3) (D4) (D5) (D6) (D7) (D8) (D9)

D1

(0)

D0

(0) (D0) (D1)

0

D5

D4

D3

(D10) (D11) (D12) (D13)

D2

Sample N

Sample N + 1

Data Bit in MSB First Mode

D13

(D2)

Data Bit in LSB First Mode

⁽¹⁾In 16 Bit serialization, two zero bits are padded to the 14 bit ADC data on the MSB side.

T0225-02

Figure 93. 1-Wire Interface

2-WIRE INTERFACE - 16× SERIALIZATION WITH DDR/SDR BIT CLOCK

The 2-wire interface is recommended for sampling frequencies above 65 MSPS. In 16× serialization, two zero

bits are padded to the 14 bit ADC data on the MSB side and the combined 16 bit data is serialized and output

over two LVDS pairs. The data rate is 8 × Sample frequency since 8 bits are sent on each wire every clock cycle.

The data is available along with DDR bit clock or optionally with SDR bit clock. Each ADC sample is sent over

the 2 wires as byte-wise or bit-wise or word-wise.

Using the 16× serialization makes it possible to upgrade to a 16-bit ADC in the future seamlessly, without

requiring any modification to the receiver capture logic design.

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Input Clock,

CLKP/M

Freq = Fs

Frame Clock,

FCLKP/M

Freq = 1 ´ Fs

Bit Clock – SDR,

DCLKP/M

Freq = 8 ´ Fs

Bit Clock – DDR,

DCLKP/M

Freq = 4 ´ Fs

Output Data

DA0, DB0, DC0, DD0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

(D0) (D1) (D2) (D3) (D4) (D5) (D6) (D7) (D0) (D1) (D2) (D3) (D4) (D5) (D6) (D7)

D4

D3

D2

D1

D0

Output Data

DA1, DB1, DC1, DD1

0

(D8) (D9)

0

D9

(0)

D8

(0)

0 0

(D8) (D9)

D9

(0)

D8

(0)

D13 D12 D11 D10

(D10) (D11) (D12) (D13)

D13 D12 D11 D10

(D10) (D11) (D12) (D13)

Data Rate = 8 ´ Fs

Output Data

DA0, DB0, DC0, DD0

0

(D0) (D2) (D4) (D6) (D8)

D12 D10

D8

D6

D0

(0)

0

(D0) (D2) (D4) (D6) (D8)

D12 D10

D8

D6

D4 D2

(D10) (D12)

D4 D2

(D10) (D12)

D0

(0)

Output Data

DA1, DB1, DC1, DD1

0

(D1) (D3) (D5) (D7) (D9)

D13 D11

D9

D7

D1

(0)

0

D13 D11

(D1) (D3) (D5) (D7) (D9)

D9

D7

D1

(0)

D5 D3

(D11) (D13)

D5 D3

(D11) (D13)

Output Data

DA0, DB0, DC0, DD0

0

D13 D12 D11 D10

D9

D8

D7

(D0) (D1) (D2) (D3) (D4) (D5) (D6) (D7) (D8) (D9)

D6

D1

(0)

D0

(0)

D5

D4

D3

(D10) (D11) (D12) (D13)

D2

Output Data

DA1, DB1, DC1, DD1

0

D13 D12 D11 D10

D9

D8

D7

(D0) (D1) (D2) (D3) (D4) (D5) (D6) (D7) (D8) (D9)

D6

D1

(0)

D0

(0)

D5

D4

D3

(D10) (D11) (D12) (D13)

D2

White Cells – Sample N

Data Bit in MSB First Mode

Data Bit in LSB First Mode

D13

(D3)

Grey Cells – Sample N + 1

T0226-02

Figure 94. 2-Wire Interface 16× Serialization

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2-WIRE INTERFACE - 14× SERIALIZATION

The 14 bit ADC data is serialized and output over two LVDS pairs. A frame clock at 1× sample frequency is also

available with an SDR bit clock. With DDR bit clock option, the frame clock frequency is 0.5× sample frequency.

The output data rate will be 7 × sample frequency as 7 data bits are output every clock cycle on each wire. Each

ADC sample is sent over the 2 wires as byte-wise or bit-wise or word-wise.

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Input Clock,

CLK

Freq = Fs

Frame Clock,

FCLK

Freq = 1 ´ Fs

Bit Clock – SDR,

DCLK

Freq = 7 ´ Fs

Output Data

DA0, DB0, DC0, DD0

D6

D5

D4

D3

D2

D1

D0

D6

D5

D4

D3

(D0) (D1) (D2) (D3) (D4) (D5) (D6) (D0) (D1) (D2) (D3) (D4) (D5) (D6) (D0) (D1)

D2

D1

D0

D6

D5

Output Data

DA1, DB1, DC1, DD1

D13 D12 D11

(D7) (D8) (D9)

D13 D12 D11

(D7) (D8) (D9)

D8

(0)

D7

(0)

D13 D12

(D7) (D8)

D10

D9

D8

D7

(D10) (D11) (D12) (D13)

D10 D9

(D10) (D11)

Data Rate = 7 ´ Fs

Output Data

DA0, DB0, DC0, DD0

D12 D10

(D0) (D2) (D4) (D6) (D8)

D8

D6

D4

D12 D10

D8

(D0) (D2) (D4) (D6) (D8)

D6

D4

D12 D10

(D0) (D2)

D2 D0

(D10) (D12)

D2 D0

(D10) (D12)

Output Data

DA1, DB1, DC1, DD1

D13 D11

(D1) (D3) (D5) (D7) (D9)

D9

D7

D5

D13 D11

D9

(D1) (D3) (D5) (D7) (D9)

D7

D5

D13 D11

(D1) (D3)

D3 D1

(D11) (D13)

D3 D1

(D11) (D13)

Output Data

DA0, DB0, DC0, DD0

D13 D12 D11 D10

D9

D8

D7

D6

D5

(D0) (D1) (D2) (D3) (D4) (D5) (D6) (D7) (D8) (D9)

D4

D13 D12

(D0) (D1)

D3

D2

D1

(D10) (D11) (D12) (D13)

D0

Output Data

DA1, DB1, DC1, DD1

D13 D12 D11 D10

D9

D8

D7

D6

D5

(D0) (D1) (D2) (D3) (D4) (D5) (D6) (D7) (D8) (D9)

D4

D13 D12

(D0) (D1)

D3

D2

D1

(D10) (D11) (D12) (D13)

D0

White Cells – Sample N

Data Bit in MSB First Mode

Data Bit in LSB First Mode

D6

(D0)

Grey Cells – Sample N + 1

T0227-02

Figure 95. 2-Wire Interface 14× Serialization - SDR Bit Clock

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Input Clock,

CLK

Freq = Fs

Frame Clock,

FCLK

Freq = 0.5 ´ Fs

Bit Clock – DDR,

DCLK

Freq = 3.5 ´ Fs

Output Data

DA0, DB0, DC0, DD0

D6

D5

D4

D3

D2

D1

D0

D6

D5

D4

D3

(D0) (D1) (D2) (D3) (D4) (D5) (D6) (D0) (D1) (D2) (D3) (D4) (D5) (D6) (D0) (D1)

D2

D1

D0

D6

D5

Output Data

DA1, DB1, DC1, DD1

D13 D12 D11

(D7) (D8) (D9)

D8

(0)

D7

(0)

D13 D12 D11

(D7) (D8) (D9)

D8

(0)

D7

(0)

D13 D12

(D7) (D8)

D10 D9

(D10) (D11)

D10 D9

(D10) (D11)

Data Rate = 7 ´ Fs

Output Data

DA0, DB0, DC0, DD0

D12 D10

(D0) (D2) (D4) (D6) (D8)

D8

D6

D4

D0

(0)

D12 D10

D8

(D0) (D2) (D4) (D6) (D8)

D6

D4

D12 D10

(D0) (D2)

D2

(D10)

D2 D0

(D10) (D12)

Output Data

DA1, DB1, DC1, DD1

D13 D11

(D1) (D3) (D5) (D7) (D9)

D9

D7

D5

D1

(0)

D13 D11

D9

(D1) (D3) (D5) (D7) (D9)

D7

D5

D13 D11

(D1) (D3)

D3

(D11)

D3 D1

(D11) (D13)

Output Data

DA0, DB0, DC0, DD0

D13 D12 D11 D10

D9

D8

D7

D6

D5

(D0) (D1) (D2) (D3) (D4) (D5) (D6) (D7) (D8) (D9)

D4

0 0

(D0) (D1)

D3

D2

D1

(D10) (D11) (D12) (D13)

D0

Output Data

DA1, DB1, DC1, DD1

D13 D12 D11 D10

D9

D8

D7

D6

D5

(D0) (D1) (D2) (D3) (D4) (D5) (D6) (D7) (D8) (D9)

D4

D13 D12

(D0) (D1)

D3

D2

D1

(D10) (D11) (D12) (D13)

D0

White Cells – Sample N

Data Bit in MSB First Mode

Data Bit in LSB First Mode

D6

(D0)

Grey Cells – Sample N + 1

T0228-02

Figure 96. 2-Wire interface 14× Serialization - DDR Bit Clock

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OUTPUT BIT ORDER

In the 2-wire interface, three types of bit order are supported - byte-wise, bit-wise and word-wise.

Byte-wise: Each 14 bit sample is split across the 2 wires. Wires DA0, DB0, DC0, and DD0 carry the 7 LSB bits

D6 - D0 and wires DA1, DB1, DC1, and DD1 carry the 7 MSB bits.

Bit-wise: Each 14 bit sample is split across the 2 wires. Wires DA0, DB0, DC0 and DD0 carry the 7 even bits

(D0, D2, D4...) and wires DA1, DB1, DC1 and DD1 carry the 7 odd bits (D1, D3, D5...).

Word-wise: In this case, all 14 bits of a sample are sent over a single wire. Successive samples are sent over

the 2 wires. For example sample N is sent on wires DA0, DB0, DC0 and DD0, while sample N+1 is sent over

wires DA1, DB1, DC1 and DD1. The frame clock frequency is 0.5x sampling frequency, with the rising edge

aligned with the start of each word.

MSB/LSB FIRST

By default after reset, the 14 bit ADC data is output serially with the MSB first (D13, D12, D11,...D1, D0). The

data can be output LSB first also by programming the register bit <MSB_LSB_First>. In the 2-wire mode, the bit

order in each wire is flipped in the LSB first mode.

OUTPUT DATA FORMATS

Two output data formats are supported – 2s complement (default after reset) and offset binary. They can be

selected using the serial interface register bit <DF>. In the event of an input voltage overdrive, the digital outputs

go to the appropriate full-scale level. For a positive overdrive, the output code is 0x3FFF in offset binary output

format, and 0x1FFF in 2s complement output format. For a negative input overdrive, the output code is 0x0000 in

offset binary output format and 0x2000 in 2s complement output format.

LVDS CURRENT CONTROL

The default LVDS buffer current is 3.5 mA. With an external 100 Ω termination resistance, this develops ±350

mV logic levels at the receiver. The LVDS buffer currents also can be programmed to 2.5 mA, 3.0 mA, and 4.5

mA using the register bits <LVDS CURR>. In addition, there exists a current double mode, where the LVDS

nominal current is doubled (register bits <CURR DOUBLE>, refer to Table 19).

LVDS INTERNAL TERMINATION

An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially

terminated inside the device. Five termination resistances are available – 166, 200, 250, 333, and 500 Ω

(nominal with ±20% variation). Any combination of these terminations can be programmed; the effective

termination is the parallel combination of the selected resistances. The terminations can be programmed

separately for the clock and data buffers (bits <TERM CLK> and <TERM DATA>, refer to Table 20).

The internal termination helps to absorb any reflections from the receiver end, improving the signal integrity. This

makes it possible to drive up to 10 pF of load capacitance, compared to only 5 pF without the internal

termination. Figure 97 and Figure 98 show the eye diagram with 5 pF and 10 pF load capacitors (connected from

each output pin to ground).

With 100 Ω internal and 100 Ω external termination, the voltage swing at the receiver end will be halved

(compared to no internal termination). The voltage swing can be restored by using the LVDS current double

mode (bits <CURR DOUBLE>, refer to Table 19).

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C001

Figure 97. LVDS Data Eye Diagram With 5 pF Load Capacitance (No Internal Termination)

C002

Figure 98. LVDS Data Eye Diagram With 10 pF Load Capacitance (100 Ω Internal Termination)

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CAPTURE TEST PATTERNS

ADS644X outputs the bit clock (DCLK), positioned nearly at the center of the data transitions. It is recommended

to route the bit clock, frame clock and output data lines with minimum relative skew on the PCB. This ensures

sufficient setup/hold times for a reliable capture by the receiver.

The DESKEW is a 1010... or 0101... pattern output on the serial data lines that can be used to verify if the

receiver capture clock edge is positioned correctly. This may be useful in case there is some skew between

DCLK and serial data inside the receiver. Once deserialized, it is required to ensure that the parallel data is

aligned to the frame boundary. The SYNC test pattern can be used for this. For example, in the 1-wire interface,

the SYNC pattern is 7 '1's followed by 7 '0's (from MSB to LSB). This information can be used by the receiver

logic to shift the deserialized data until it matches the SYNC pattern.

In addition to DESKEW and SYNC, the ADS644X includes other test patterns to verify correctness of the capture

by the receiver such as all zeros, all ones and toggle. These patterns are output on all four channel data lines

simultaneously. Some patterns like custom and sync are affected by the type of interface selected, serialization

and bit order.

Table 25. Test Patterns

PATTERN

All zeros

All ones

DESCRIPTION

Outputs logic low.

Outputs logic high.

Outputs toggle pattern - <D13 – D0> alternates between 10101010101010 and

01010101010101 every clock cycle.

Toggle

Outputs a 14 bit custom pattern. The 14 bit custom pattern can be specified into two

serial interface registers. In the 2-wire interface, each code is sent over the 2 wires

depending on the serialization and bit order.

Custom

Sync

Outputs a sync pattern.

Outputs deskew pattern. Either <D13 – D0> = 10101010101010 or <D11 – D0> =

01010101010101 every clock cycle.

Deskew

Table 26. SYNC Pattern

INTERFACE

OPTION

SERIALIZATION

SYNC PATTERN ON EACH WIRE

14 X

16 X

14 X

16 X

MSB-11111110000000-LSB

MSB-111111111000000000-LSB

MSB-1111000-LSB

1-Wire

2-Wire

MSB-11110000-LSB

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OUTPUT TIMINGS AT LOWER SAMPLING FREQUENCIES

Setup, hold, and other timing parameters are specified across sampling frequencies and for each type of output

interface in the following tables.

Table 28 to Table 31: Typical values are at 25°C, min and max values are across the full temperature range T_MIN

= –40°C to T_MAX= 85°C, AVDD = LVDD = 3.3 V, C_L= 5 pF, I_O= 3.5 mA, R_L= 100 Ω, no internal termination,

unless otherwise noted.

Timing parameters are ensured by design and characterization and not tested in production.

Ts = 1/ Sampling frequency = 1/Fs

Table 27. Clock Propagation Delay for Different Interface Options

(1)

SERIALIZER LATENCY

INTERFACE

SERIALIZATION

CLOCK PROPAGATION DELAY, t_{pd_clk}

clock cycles

14x

16x

t_{pd_clk}= 0.428 x T_s+ t_delay

t_{pd_clk}= 0.375 x T_s+ t_delay

1-Wire with DDR bit clock

0

2

(when t_{pd_clk}≥ T_s)

2-Wire with DDR bit clock

2-Wire with SDR bit clock

2-Wire with DDR bit clock

2-Wire with SDR bit clock

t_{pd_clk}= 0.857 x T_s+ t_delay

t_{pd_clk}= 0.428 x T_s+ t_delay

t_{pd_clk}= 0.75 x T_s+ t_delay

t_{pd_clk}= 0.375 x T_s+ t_delay

14x

16x

1

(when t_{pd_clk}< T_s)

0

1

(when t_{pd_clk}≥ T_s)

0

(when t_{pd_clk}< T_s)

0

(1) Note that the total latency = ADC latency + internal serializer latency. The ADC latency is 12 clock cycles.

Table 28. Timing for 1-Wire Interface

DATA SETUP TIME, t_su

ns

DATA HOLD TIME, t_h

ns

t_delay

ns

SAMPLING

SERIALIZATION FREQUENCY

MSPS

MIN

TYP

0.5

MAX

MIN

0.4

0.7

1.6

3.2

TYP

0.6

0.9

1.9

3.6

MAX

MIN

3

TYP

MAX

65

0.3

0.65

1.3

F

_s≥ 40 MSPS

40

0.85

1.65

3.5

4

5

6

14×

20

F_s< 40 MSPS

10

65

3.2

3

4.5

0.22

0.42

0.35

0.55

F

_s≥ 40 MSPS

3

4

5

6

16×

F_s< 40 MSPS

4.5

Table 29. Timing for 2-Wire Interface, DDR Bit Clock

DATA SETUP TIME, t_su

ns

DATA HOLD TIME, t_h

ns

t_delay

ns

SAMPLING

FREQUENCY

MSPS

SERIALIZATION

MIN

TYP

0.65

0.75

0.85

1.1

MAX

MIN

0.5

0.6

0.7

0.8

1.5

TYP

0.7

0.8

0.9

1.1

1.9

MAX

MIN

3.4

TYP

MAX

5.4

105

92

80

65

40

0.45

0.55

0.65

0.8

F

_s≥ 45 MSPS

4.4

14×

F_s< 45 MSPS

1.4

1.7

3.7

5.2

6.7

105

92

80

65

40

0.35

0.45

0.55

0.6

0.55

0.65

0.75

0.9

0.4

0.5

0.6

0.7

1.3

0.6

0.7

0.8

1

F

_s≥ 45 MSPS

3.4

3.7

4.4

5.4

6.7

16×

F_s< 45 MSPS

1.1

1.4

1.7

5.2

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Table 30. Timing for 2-Wire Interface, SDR Bit Clock

DATA SETUP TIME, t_su

ns

DATA HOLD TIME, t_h

ns

t_delay

ns

SAMPLING

FREQUENCY

MSPS

SERIALIZATION

MIN

TYP

1

MAX

MIN

1

TYP

1.2

1.8

3.5

6.9

MAX

MIN

3.4

TYP

_s≥ 40 MSPS

4.4

MAX

5.4

65

40

20

10

0.8

1.5

3.4

6.9

F

1.7

3.6

7.2

1.6

3.3

6.6

14×

F_s< 40 MSPS

3.7

5.2

6.7

65

40

20

10

0.65

1.3

2.8

6.0

0.85

1.5

3.0

6.3

0.8

1.4

2.8

5.8

1.0

1.6

3.0

6.1

F

_s≥ 40 MSPS

3.4

3.7

4.4

5.4

6.7

16×

F_s< 40 MSPS

5.2

Table 31. Output Jitter (applies to all interface options)

BIT CLOCK JITTER, CYCLE-CYCLE

ps, peak-peak

FRAME CLOCK JITTER, CYCLE-CYCLE

ps, peak-peak

SAMPLING FREQUENCY

MSPS

MIN

TYP

MAX

MIN

TYP

MAX

≥ 65

350

75

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BOARD DESIGN CONSIDERATIONS

Grounding

A single ground plane is sufficient to give optimum performance, provided the analog, digital, and clock sections

of the board are cleanly partitioned. Refer to the EVM User Guide (SLAU196) for board layout schemes.

Supply Decoupling

As the ADS644X already includes internal decoupling, minimal external decoupling can be used without loss in

performance. Note that the decoupling capacitors can help to filter external power supply noise, so the optimum

number of decoupling capacitors would depend on actual application.

It is recommended to use separate supplies for the analog and digital supply pins to isolate digital switching

noise from sensitive analog circuitry. In case only a single 3.3 V supply is available, it should be routed first to

AVDD. It can then be tapped and isolated with a ferrite bead (or inductor) with decoupling capacitor, before being

routed to LVDD.

Exposed Thermal Pad

It is necessary to solder the exposed pad at the bottom of the package to a ground plane for best thermal

performance. For detailed information, see application notes QFN Layout Guidelines(SLOA122A) and QFN/SON

PCB Attachment (SLUA271A).

62

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ADS6445-EP

www.ti.com ............................................................................................................................................................................................ SLAS573–FEBRUARY 2008

DEFINITION OF SPECIFICATIONS

Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with

respect to the low frequency value.

Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at

which the sampling occurs. This delay will be different across channels. The maximum variation is specified as

aperture delay variation (channel-channel).

Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay.

Clock Pulse Width/Duty Cycle – The duty cycle of a clock signal is the ratio of the time the clock signal remains

at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a

percentage. A perfect differential sine-wave clock results in a 50% duty cycle.

Maximum Conversion Rate – The maximum sampling rate at which certified operation is given. All parametric

testing is performed at this sampling rate unless otherwise noted.

Minimum Conversion Rate – The minimum sampling rate at which the ADC functions.

Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly

1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs.

Integral Nonlinearity (INL) – The INL is the deviation of the ADC's transfer function from a best fit line

determined by a least squares curve fit of that transfer function, measured in units of LSBs.

Gain Error – The gain error is the deviation of the ADC's actual input full-scale range from its ideal value. The

gain error is given as a percentage of the ideal input full-scale range. The gain error does not include the error

caused by the internal reference deviation from ideal value. This is specified separately as internal reference

error. The maximum variation of the gain error across devices and across channels within a device is specified

separately.

Offset Error – The offset error is the difference, given in number of LSBs, between the ADC's actual average

idle channel output code and the ideal average idle channel output code. This quantity is often mapped into mV.

Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies the

change per degree Celsius of the parameter from T_MINto T_MAX. It is calculated by dividing the maximum deviation

of the parameter across the T_MINto T_MAXrange by the difference T_MAX–T_MIN

.

Signal-to-Noise Ratio(SNR) is the ratio of the power of the fundamental (PS) to the noise floor power (PN),

excluding the power at DC and the first nine harmonics.

P

S

SNR + 10Log10

P

N

(3)

SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the

reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s

full-scale range.

Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (P_S) to the power

of all the other spectral components including noise (P_N) and distortion (P_D), but excluding dc.

P_S

PN ) PD

SINAD + 10Log10

(4)

SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the

reference, or dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter's

full-scale range.

Effective Number of Bits (ENOB) – The ENOB is a measure of a converter’s performance as compared to the

theoretical limit based on quantization noise.

SINAD * 1.76

ENOB +

6.02

(5)

Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (P_S) to the power of the

first nine harmonics (PD).

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P_S

PD

THD + 10Log10

(6)

THD is typically given in units of dBc (dB to carrier).

Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other

spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).

Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f1

and f2) to the power of the worst spectral component at either frequency 2f1 – f2 or 2f2 – f1. IMD3 is either given

in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB

to full scale) when the power of the fundamental is extrapolated to the converter’s full-scale range.

DC Power Supply Rejection Ratio (DC PSRR) – The DC PSSR is the ratio of the change in offset error to a

change in analog supply voltage. The DC PSRR is typically given in units of mV/V.

AC Power Supply Rejection Ratio (AC PSRR) – AC PSRR is the measure of rejection of variations in the

supply voltage by the ADC. If ΔVsup is the change in supply voltage and ΔVout is the resultant change of the

ADC output code (referred to the input), then

DVout

DVsup

PSRR + 20Log10

, expressed in dBc

(7)

Voltage Overload Recovery – The number of clock cycles taken to recover to less than 1% error after an

overload on the analog inputs. This is tested by separately applying a sine wave signal with 6-dB positive and

negative overload. The deviation of the first few samples after the overload (from their expected values) is noted.

Common Mode Rejection Ratio (CMRR) – CMRR is the measure of rejection of variation in the analog input

common-mode by the ADC. If ΔVcm_in is the change in the common-mode voltage of the input pins and ΔVout

is the resultant change of the ADC output code (referred to the input), then

DVout

DVcm_in

CMRR + 20Log10

, expressed in dBc

(8)

Cross-Talk (only for multi-channel ADC)– This is a measure of the internal coupling of a signal from adjacent

channel into the channel of interest. It is specified separately for coupling from the immediate neighboring

channel (near-channel) and for coupling from channel across the package (far-channel). It is usually measured

by applying a full-scale signal in the adjacent channel. Cross-talk is the ratio of the power of the coupling signal

(as measured at the output of the channel of interest) to the power of the signal applied at the adjacent channel

input. It is typically expressed in dBc.

64

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PACKAGE OPTION ADDENDUM

www.ti.com

18-Sep-2008

PACKAGING INFORMATION

Orderable Device

ADS6445MRGCTEP

V62/08628-01XE

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

VQFN

RGC

64

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

VQFN

RGC

64

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF ADS6445-EP :

Catalog: ADS6445

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) W1 (mm)

(mm) (mm) Quadrant

ADS6445MRGCTEP

VQFN

RGC

64

250

330.0

16.4

9.3

1.5

12.0

16.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2008

*All dimensions are nominal

Device

Package Type Package Drawing Pins

VQFN RGC 64

SPQ

Length (mm) Width (mm) Height (mm)

333.2 345.9 28.6

ADS6445MRGCTEP

250

Pack Materials-Page 2

IMPORTANT NOTICE

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型号：	V62/08628-01XE
厂家：	TEXAS INSTRUMENTS
描述：	四通道、14 位、125MSPS 模数转换器 (ADC) - 增强型产品 \| RGC \| 64 \| -55 to 125 转换器模数转换器
文件：	总71页 (文件大小：3143K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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