V62/10606-01XE [TI]
1-Mbps QUAD DIGITAL ISOLATORS; 1 Mbps的4通道数字隔离器
| 型号： | V62/10606-01XE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1-Mbps QUAD DIGITAL ISOLATORS |
| 文件： | 总17页 (文件大小：450K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO7241A-EP
www.ti.com
SLLSE18 –JANUARY 2010
1-Mbps QUAD DIGITAL ISOLATORS
Check for Samples: ISO7241A-EP
1
FEATURES
•
4000-Vpeak Isolation, 560-Vpeak VIORM
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
–
UL 1577 , IEC 60747-5-2 (VDE 0884, Rev 2),
IEC 61010-1, IEC 60950-1 and CSA
Approved
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C)
Temperature Range(1)
•
•
•
4-kV ESD Protection
Operates With 3.3-V or 5-V Supplies
Typical 25-Year Life at Rated Working Voltage
(See Application Note (SLLA197 ) and
Figure 10)
•
•
•
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
•
High Electromagnetic Immunity
(See Application Report (SLLA181))
ISO7241A
(TOP VIEW)
APPLICATIONS
V
V
CC2
1
2
3
4
5
6
7
8
16
15
CC1
GND1
•
•
•
•
Industrial Fieldbus
GND2
Computer Peripheral Interface
Servo Control Interface
Data Acquisition
IN
IN
IN
14
13
12
11
10
9
OUT
A
A
B
C
OUT
B
OUT
C
OUT
EN
IN
D
D
EN
2
1
GND1
GND2
(1) Additional temperature ranges available - contact factory
DESCRIPTION
See the Product Notification section. The ISO7241A is a quad-channel digital isolator with multiple channel
configurations and output enable functions. This device has logic input and output buffers separated by TI’s
silicon dioxide (SiO2) isolation barrier. Used in conjunction with isolated power supplies, this device blocks high
voltage, isolate grounds, and prevent noise currents from entering the local ground and interfering with or
damaging sensitive circuitry.
The ISO7241A has three channels the same direction and one channel in opposition.
This device has TTL input thresholds and a noise-filter at the input that prevents transient pulses from being
passed to the output of the device.
A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh
pulse is not received, the input is assumed to be unpowered or not being actively driven, and the failsafe circuit
drives the output to a logic high state. (See ISO7240CF (SLLS869) or contact TI for a logic low failsafe option).
The ISO7241A may be powered from either 3.3-V or 5-V supplies on either side in any 3.3-V / 3.3-V, 5-V / 5-V,
5-V / 3.3-V, or 3.3-V / 5-V combination. Note that the signal input pins are 5-V tolerant regardless of the voltage
supply level being used.
This device is characterized for operation over the ambient temperature range of –55°C to 125°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ISO7241A-EP
SLLSE18 –JANUARY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FUNCTION DIAGRAM
Galvanic Isolation
Barrier
DC Channel
Filter
OSC
+
PWM
Pulse Width
Demodulation
Vref
Carrier Detect
EN
Data MUX
AC Detect
Input
+
Filter
Vref
IN
OUT
Output Buffer
AC Channel
Table 1. Device Function Table(1)
INPUT
(IN)
OUTPUT ENABLE
OUTPUT
(OUT)
INPUT VCC
OUTPUT VCC
(EN)
H or Open
H or Open
L
H
L
H
L
PU
PU
X
Z
H
H
Z
Open
X
H or Open
H or Open
L
PD
PD
PU
PU
X
(1) PU = Powered Up; PD = Powered Down ; X = Irrelevant; H = High Level; L = Low Level
Table 2. ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
–55°C to 125°C
DW
Reel
ISO7241AMDWREP
ISO7241AM
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
2
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SLLSE18 –JANUARY 2010
ABSOLUTE MAXIMUM RATINGS(1)
VALUE
–0.5 to 6
–0.5 to 6
±15
UNIT
V
VCC Supply voltage(2), VCC1, VCC2
VI
IO
Voltage at IN, OUT, EN
Output current
V
mA
Human Body Model
Electrostatic Field-Induced-Charged Device
JEDEC Standard 22, Test Method A114-C.01
JEDEC Standard 22, Test Method C101
ANSI/ESDS5.2-1996
±4
kV
ESD
TJ
All pins
±1
discharge
Model
Machine Model
±200
170
V
Maximum junction temperature
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal and are peak voltage values.
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX UNIT
VCC Supply voltage(1), VCC1, VCC2
3.15
5.5
4
V
mA
mA
μs
IOH
IOL
tui
High-level output current
Low-level output current
Input pulse width
–4
1
1/tui Signaling rate
0
1000
VCC
0.8
kbps
V
VIH
VIL
TJ
High-level input voltage (IN) (EN on all devices)
2
Low-level input voltage (IN) (EN on all devices)
Junction temperature
0
V
150
°C
H
External magnetic field-strength immunity per IEC 61000-4-8 and IEC 61000-4-9
certification
A/m
1000
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
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ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 5-V(1) OPERATION
, over recommended operating conditions (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN TYP MAX
UNIT
Quiescent
1 Mbps
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
ICC1
6.5
11
mA
mA
Quiescent
1 Mbps
13
13
20
20
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
ICC2
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
EN at 0 V, Single channel
IOH = –4 mA, See Figure 1
IOH = –20 μA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 μA, See Figure 1
0
μA
VCC – 0.8
VCC – 0.1
VOH
High-level output voltage
V
0.4
0.1
VOL
Low-level output voltage
V
VI(HYS) Input voltage hysteresis
150
mV
μA
IIH
High-level input current
10
IN from 0 V to VCC
IIL
Low-level input current
–10
25
CI
Input capacitance to ground
Common-mode transient immunity
IN at VCC, VI = 0.4 sin (4E6πt)
2
pF
CMTI
VI = VCC or 0 V, See Figure 4
50
kV/μs
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
See Figure 1
MIN
TYP
MAX
95
UNIT
ns
tPLH, tPHL
PWD
tsk(o)
tr
Propagation delay
Pulse-width distortion(1) |tPHL – tPLH
40
|
10
(2)
Channel-to-channel output skew
2
ns
Output signal rise time
Output signal fall time
2
2
See Figure 1
ns
tf
tPHZ
tPZH
tPLZ
tPZL
tfs
Propagation delay, high-level-to-high-impedance output
Propagation delay, high-impedance-to-high-level output
Propagation delay, low-level-to-high-impedance output
Propagation delay, high-impedance-to-low-level output
Failsafe output delay time from input power loss
15
15
15
15
12
20
20
20
20
See Figure 2
See Figure 3
ns
μs
(1) Also referred to as pulse skew.
(2) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
4
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SLLSE18 –JANUARY 2010
ELECTRICAL CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN
TYP
MAX UNIT
Quiescent
1 Mbps
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
ICC1
6.5
11
mA
mA
Quiescent
1 Mbps
8
8
13
13
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
ICC2
ELECTRICAL CHARACTERISTICS
IOFF
VOH
Sleep mode output current
High-level output voltage
EN at 0 V, Single channel
0
μA
IOH = –4 mA, See Figure 1
IOH = –20 μA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 μA, See Figure 1
(5-V side)
VCC – 0.8
VCC – 0.1
V
0.4
0.1
VOL
Low-level output voltage
V
VI(HYS) Input voltage hysteresis
150
mV
μA
IIH
High-level input current
Low-level input current
Input capacitance to ground
10
IN from 0 V to VCC
IIL
–10
25
CI
IN at VCC, VI = 0.4 sin (4E6πt)
2
pF
CMTI
Common-mode transient immunity VI = VCC or 0 V, See Figure 4
50
kV/μs
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
SWITCHING CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
40
MAX
UNIT
ns
tPLH, tPHL Propagation delay
100
11
3
See Figure 1
PWD
tsk(o)
tr
Pulse-width distortion(1) |tPHL – tPLH
|
(2)
Channel-to-channel output skew
ns
Output signal rise time
Output signal fall time
2
2
See Figure 1
ns
tf
tPHZ
tPZH
tPLZ
tPZL
tfs
Propagation delay, high-level-to-high-impedance output
Propagation delay, high-impedance-to-high-level output
Propagation delay, low-level-to-high-impedance output
Propagation delay, high-impedance-to-low-level output
Failsafe output delay time from input power loss
15
15
15
15
18
20
20
20
20
See Figure 2
See Figure 3
ns
μs
(1) Also known as pulse skew
(2) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
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ELECTRICAL CHARACTERISTICS: VCC1 at 3.3-V, VCC2 at 5-V(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN TYP MAX UNIT
Quiescent
1 Mbps
4
4
7
7
ICC1
VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V
VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V
mA
mA
Quiescent
1 Mbps
13
13
20
20
ICC2
ELECTRICAL CHARACTERISTICS
IOFF
VOH
Sleep mode output current EN at VCC, Single channel
0
μA
High-level output voltage
IOH = –4 mA, See Figure 1
IOH = –20 μA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 μA, See Figure 1
(5-V side)
VCC – 0.8
VCC – 0.1
V
0.4
0.1
VOL
Low-level output voltage
V
VI(HYS)
IIH
Input voltage hysteresis
High-level input current
Low-level input current
150
mV
μA
10
IN from 0 V to VCC
IIL
–10
25
CI
Input capacitance to
ground
IN at VCC, VI = 0.4 sin (4E6πt)
2
pF
Common-mode transient
immunity
VI = VCC or 0 V, See Figure 4
CMTI
50
kV/μs
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
SWITCHING CHARACTERISTICS: VCC1 at 3.3-V and VCC2 at 5-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
See Figure 1
MIN
TYP MAX
UNIT
ns
tPLH, tPHL
PWD
tsk(o)
tr
Propagation delay
Pulse-width distortion(1) |tPHL – tPLH
40
100
|
11
(2)
Channel-to-channel output skew
2.5
ns
Output signal rise time
Output signal fall time
2
2
See Figure 1
ns
tf
tPHZ
tPZH
tPLZ
tPZL
tfs
Propagation delay, high-level-to-high-impedance output
Propagation delay, high-impedance-to-high-level output
Propagation delay, low-level-to-high-impedance output
Propagation delay, high-impedance-to-low-level output
Failsafe output delay time from input power loss
15
15
15
15
12
20
20
20
20
See Figure 2
See Figure 3
ns
μs
(1) Also known as pulse skew
(2) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
6
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ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
SUPPLY CURRENT
TEST CONDITIONS
MIN TYP MAX UNIT
Quiescent
1 Mbps
4
4
8
8
7
7
VI = VCC or 0 V, all channels, no load, EN1 at 3 V,
EN2 at 3 V
ICC1
mA
mA
Quiescent
1 Mbps
13
13
VI = VCC or 0 V, all channels, no load, EN1 at 3 V,
EN2 at 3 V
ICC2
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
EN at 0 V, single channel
IOH = –4 mA, See Figure 1
IOH = –20 μA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 μA, See Figure 1
0
μA
VCC – 0.4
VCC – 0.1
VOH
High-level output voltage
V
0.4
0.1
VOL
Low-level output voltage
V
VI(HYS) Input voltage hysteresis
150
mV
μA
IIH
High-level input current
10
IN from 0 V or VCC
IIL
Low-level input current
–10
25
CI
Input capacitance to ground
Common-mode transient immunity
IN at VCC, VI = 0.4 sin (4E6πt)
2
pF
CMTI
VI = VCC or 0 V, See Figure 4
50
kV/μs
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
Propagation delay
TEST CONDITIONS
MIN
TYP MAX
UNIT
tPLH, tPHL
PWD
tsk(o)
tr
45
110
See Figure 1
ns
(1)
Pulse-width distortion |tPHL – tPLH
Channel-to-channel output skew
Output signal rise time
|
12
(2)
3.5
2
2
ns
See Figure 1
tf
Output signal fall time
tPHZ
tPZH
tPLZ
tPZL
tfs
Propagation delay, high-level-to-high-impedance output
Propagation delay, high-impedance-to-high-level output
Propagation delay, low-level-to-high-impedance output
Propagation delay, high-impedance-to-low-level output
Failsafe output delay time from input power loss
15
15
15
15
18
20
20
20
20
See Figure 2
See Figure 3
ns
μs
(1) Also referred to as pulse skew.
(2) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
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PARAMETER MEASUREMENT INFORMATION
V
1
CC
V
V
1/2
V
1/2
I
CC
CC
IN
OUT
0 V
t
t
PHL
PLH
Input
Generator
V
C
V
V
O
50 W
OH
OL
L
NOTE B
I
90%
10%
V
O
50%
50%
NOTE A
V
t
t
f
r
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms
Vcc
Vcc
RL = 1 kW 1ꢀ
Vcc/2
50ꢀ
Vcc/2
V
I
IN
0 V
Vcc
0.5 V
OUT
VO
tPZL
0V
tPLZ
EN
CL
V
O
NOTE
B
Input
VOL
VI
Generator
50 W
NOTE A
Vcc
V
O
IN
Vcc/2
Vcc/2
OUT
V
3V
I
0 V
VOH
t
PZH
EN
CL
RL = 1 kW 1ꢀ
50ꢀ
0.5 V
NOTE
B
V
Input
O
0 V
VI
Generator
tPHZ
50 W
NOTE A
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 2. Enable/Disable Propagation Delay Time Test Circuit and Waveform
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PARAMETER MEASUREMENT INFORMATION (continued)
V
I
V
1
V
1
CC
CC
2.7 V
V
I
0 V
or
OUT
0 V
V
IN
V
O
t
V
1
fs
CC
OH
C
L
V
50%
O
NOTE B
fs low
V
OL
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
Figure 3. Failsafe Delay Time Test Circuit and Voltage Waveforms
V
1
V
2
CC
CC
C = 0.1 mF 1ꢀ
C = 0.1 mF 1ꢀ
Pass-fail criteria:
Output must
remain stable
OUT
IN
S1
NOTE B
V
or V
OL
OH
GND1
GND2
V
CM
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
Figure 4. Common-Mode Transient Immunity Test Circuit and Voltage Waveform
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DEVICE INFORMATION
PACKAGE CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
L(I01) Minimum air gap (Clearance)
Shortest terminal-to-terminal distance through air
8.34
mm
L(I02) Minimum external tracking (Creepage) Shortest terminal-to-terminal distance across the
package surface
8.1
mm
mm
Minimum Internal Gap (Internal
Distance through the insulation
Clearance)
0.008
Input to output, VIO = 500 V, all pins on each side of the
barrier tied together creating a two-terminal device
RIO
Isolation resistance
>1012
Ω
CIO
CI
Barrier capacitance Input to output
Input capacitance to ground
VI = 0.4 sin (4E6πt)
2
2
pF
pF
VI = 0.4 sin (4E6πt)
DEVICE I/O SCHEMATICS
Enable
Output
Input
VCC
VCC
VCC
VCC
VCC
VCC
VCC
1 MW
1 MW
500 W
8 W
500 W
IN
EN
OUT
13 W
REGULATORY INFORMATION
VDE
CSA
UL
Certified according to IEC
60747-5-2
Approved under CSA Component Acceptance
Notice
Recognized under 1577 Component Recognition
Program(1)
File Number: 40016131
File Number: 1698195
File Number: E181974
(1) Production tested ≥ 3000 Vrms for 1 second in accordance with UL 1577.
THERMAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
Junction-to-air
TEST CONDITIONS
Low-K Thermal Resistance(1)
MIN
TYP MAX UNIT
168
°C/W
96.1
θJA
High-K Thermal Resistance
θJB
θJC
Junction-to-Board Thermal Resistance
Junction-to-Case Thermal Resistance
61
48
°C/W
°C/W
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 50% duty cycle square wave
PD
Device Power Dissipation
220
mW
(1) Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages.
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TYPICAL CHARACTERISTIC CURVES
INPUT VOLTAGE THRESHOLD
VCC1 FAILSAFE THRESHOLD
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1.4
1.35
1.3
3
2.9
2.8
VCC at 5 V or 3.3 V,
5 V Vth+
Load = 15 pF,
Air Flow at 7/cf/m,
Low-K Board
3.3 V Vth+
2.7
2.6
2.5
2.4
2.3
Vfs+
1.25
1.2
Air Flow at 7 cf/m,
Low_K Board
Vfs-
1.15
1.1
5 V Vth-
2.2
1.05
1
3.3 V Vth-
2.1
2
-40 -25
-10
5
20
35
50
65
80
95
110 125
-40
-25
-10
5
20
35
50
65
80
95
110 125
TA - Free-Air Temperature - °C
TA - Free-Air Temperature - °C
Figure 5.
Figure 6.
HIGH-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
50
45
50
40
30
20
Load = 15 pF,
TA = 25°C
Load = 15 pF,
TA = 25°C
VCC = 5 V
40
35
VCC = 3.3 V
VCC = 3.3 V
30
25
20
VCC = 5 V
15
10
10
0
5
0
1
0
2
3
4
5
0
4
6
2
VO - Output Voltage - V
VO - Output Voltage - V
Figure 7.
Figure 8.
Copyright © 2010, Texas Instruments Incorporated
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Product Folder Link(s): ISO7241A-EP
ISO7241A-EP
SLLSE18 –JANUARY 2010
www.ti.com
APPLICATION INFORMATION
2 mm
2 mm
max. from
V
V
max. from
CC1
CC2
V
CC1
V
CC2
0.1 mF
0.1 mF
1
2
16
15
GND1
GND2
IN
A
14
13
12
11
10
9
3
4
5
6
7
8
OUT
OUT
OUT
A
B
C
IN
B
IN
C
D
OUT
IN
D
EN1
EN2
GND2
GND1
ISO7241A
Figure 9. Typical Application Circuit
LIFE EXPECTANCY vs. WORKING VOLTAGE
100
V
at 560-V
IORM
28 Years
10
0
120
250
500
750
1000
880
WORKING VOLTAGE (VIORM) -- V
Figure 10. Time-Dependant Dielectric Breakdown Testing Results
12
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): ISO7241A-EP
ISO7241A-EP
www.ti.com
SLLSE18 –JANUARY 2010
PRODUCT NOTIFICATION
An ISO7241A anomaly occurs when a negative-going pulse below the specified 1-μs minimum bit width is input
to the device. The output locks in a logic-low condition until the next rising edge occurs after a 1-μs period.
Positive noise edges in pulses of less than the minimum specified 1 μs have no effect on the device, and are
properly filtered.
To prevent noise from interfering with ISO7241A performance, it is recommended that an appropriately sized
capacitor be placed on each input of the device
Figure 11. ISO7241A Anomaly
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Product Folder Link(s): ISO7241A-EP
PACKAGE OPTION ADDENDUM
www.ti.com
20-Feb-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
ISO7241AMDWREP
ISO7241AMDWREPG4
V62/10606-01XE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
DW
DW
DW
16
16
16
2000
2000
2000
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ISO7241A-EP :
Catalog: ISO7241A
•
NOTE: Qualified Version Definitions:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Feb-2012
Catalog - TI's standard catalog product
•
Addendum-Page 2
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