V62/13611-01XE [TI]
增强型产品单路差分比较器 | DBV | 5 | -55 to 125;
| 型号： | V62/13611-01XE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 增强型产品单路差分比较器 | DBV | 5 | -55 to 125 比较器 |
| 文件： | 总10页 (文件大小：507K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TL331-EP
www.ti.com.cn
ZHCSB62 –JUNE 2013
单路差分比较器
查询样品: TL331-EP
1
特性
•
•
•
单电源或双电源
支持国防、航空航天、和医疗应用
宽电源电压范围：2V 至 36V
•
•
•
•
•
•
•
受控基线
独立于电源电压的低电源电流漏极：0.4mA（典型
值）
一个组装和测试场所
一个制造场所
•
•
•
•
•
•
低输入偏置电流：25nA（典型值）
低输入偏移电压：2mV（典型值）
共模输入电压范围包括接地
支持军用（-55°C 至 125°C）温度范围
延长的产品生命周期
延长的产品变更通知
差分输入电压范围等于最大额定电源电压：±36V
低输出饱和电压
产品可追溯性
DBV PACKAGE
(TOP VIEW)
输出与 TTL，MOS 和 CMOS 兼容
1
2
3
5
4
IN−
VCC−/GND
IN+
VCC
OUT
说明/订购信息
这个器件包含一个单电压比较器，此比较器被设计成在宽范围电压上由一个单电源供电运行。 如果两个电源之间的
电压差在 2V 和 36V 之间且 VCC比输入共模电压的正值至少高 1.5V，也可使用双电源供电运行。 电流漏极与电源
电压无关。 为了实现线与关系，用户可将输出连接至另外一个集电极开路输出。
ORDERING INFORMATION(1)
ORDERABLE PART
NUMBER
TOP-SIDE
MARKING
TA
VIO(MAX) at 25°C
PACKAGE
VID NUMBER
Reel of 3000
Reel of 250
TL331MDBVREP
TL331MDBVTEP
–55°C to 125°C
5 mV
SOT-23 (DBV)
TEPU
V62/13611-01XE
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
English Data Sheet: SLVSBU6
TL331-EP
ZHCSB62 –JUNE 2013
www.ti.com.cn
LOGIC DIAGRAM
SCHEMATIC
IN+
IN−
OUT
V
CC
80-µA
Current Regulator
80 µA
10 µA
60 µA
10 µA
COMPONENT COUNT
Epi-FET
1
Diodes
2
Resistors
Transistors
1
20
IN+
IN−
OUT
GND
Note: Current values shown are nominal.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VCC
VID
VI
Supply voltage(2)
36 V
±36 V
Differential input voltage(3)
Input voltage range (either input)
Output voltage
–0.3 V to 36 V
36 V
VO
IO
Output current
20 mA
Duration of output short-circuit to ground(4)
Operating virtual junction temperature
Storage temperature range
Unlimited
150°C
TJ
Tstg
–65°C to 150°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to the network ground.
(3) Differential voltages are at IN+ with respect to IN–.
(4) Short circuits from outputs to VCC can cause excessive heating and eventual destruction.
2
Copyright © 2013, Texas Instruments Incorporated
TL331-EP
www.ti.com.cn
ZHCSB62 –JUNE 2013
THERMAL INFORMATION
TL331-EP
DBV
5 PINS
299
THERMAL METRIC(1)
UNITS
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
θJCtop
θJB
65.4
97.1
°C/W
ψJT
0.8
ψJB
95.5
θJCbot
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
ELECTRICAL CHARACTERISTICS
at specified free-air temperature, VCC = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS(1)
TA
MIN
TYP
MAX UNIT
25°C
2
5
VCC = 5 V to 30 V, VO = 1.4 V,
VIC = VIC(min)
VIO
IIO
IIB
Input offset voltage
mV
9
–55°C to 125°C
25°C
5
50
nA
Input offset current
Input bias current
VO = 1.4 V
VO = 1.4 V
–55°C to 125°C
25°C
250
–25
–250
nA
–55°C to 125°C
–400
0 to
VCC – 1.5
25°C
–55°C to 125°C
25°C
Common-mode input voltage
range(2)
VICR
V
0 to
VCC – 2
Large-signal differential-voltage
amplification
VCC = 15 V, VO = 1.4 V to 11.4 V,
AVD
IOH
50
200
0.1
V/mV
RL ≥ 15 kΩ to VCC
VOH = 5 V, VID = 1 V
VOH = 30 V, VID = 1 V
25°C
–55°C to 125°C
25°C
50
1
nA
High-level output current
Low-level output voltage
μA
150
0.4
400
700
VOL
IOL = 4 mA, VID = –1 V
mV
–55°C to 125°C
25°C
IOL
ICC
Low-level output current
Supply current
VOL = 1.5 V, VID = –1 V
6
mA
mA
RL = ∞, VCC = 5 V
25°C
0.7
(1) All characteristics are measured with zero common-mode input voltage, unless otherwise specified.
(2) The voltage at either input or common-mode should not be allowed to go negative by more than 0.3 V. The upper end of the common-
mode voltage range is VCC+ – 1.5 V, but either or both inputs can go to 30 V without damage.
Copyright © 2013, Texas Instruments Incorporated
3
TL331-EP
ZHCSB62 –JUNE 2013
www.ti.com.cn
SWITCHING CHARACTERISTICS
VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TYP
1.3
UNIT
100-mV input step with 5-mV overdrive
TTL-level input step
Response time RL connected to 5 V through 5.1 kΩ, CL = 15 pF(1) (2)
μs
0.3
(1) CL includes probe and jig capacitance.
(2) The response time specified is the interval between the input step function and the instant when the output crosses 1.4 V.
4
Copyright © 2013, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TL331MDBVTEP
V62/13611-01XE
ACTIVE
ACTIVE
SOT-23
SOT-23
DBV
DBV
5
5
250
250
RoHS & Green
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
-55 to 125
TEPU
TEPU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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