V62/16623-01XE [TI]
具有分离输出和有源保护功能的 5.7kVrms、2.5A/5A 增强型单通道隔离式栅极驱动器 | DW | 16 | -55 to 125;型号: | V62/16623-01XE |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有分离输出和有源保护功能的 5.7kVrms、2.5A/5A 增强型单通道隔离式栅极驱动器 | DW | 16 | -55 to 125 栅极驱动 双极性晶体管 光电二极管 接口集成电路 驱动器 |
文件: | 总45页 (文件大小:1966K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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ISO5852S-EP
ZHCSFX1 –DECEMBER 2016
ISO5852S-EP 具有分离输出和有源安全保护功能的
高 CMTI 2.5A 和 5A 增强型隔离式 IGBT、MOSFET 栅极 驱动器
1 特性
3 说明
1
•
在 VCM = 1500V 时,共模瞬态抗扰度 (CMTI) 的最
小值为 100kV/μs
ISO5852S-EP 器件是一款用于 IGBT 和 MOSFET 的
5.7 kVRMS 增强型隔离栅极驱动器,具有分离输出
(OUTH 和 OUTL)以及 2.5A 的拉电流能力和 5A 的
灌电流能力。输入端由 2.25V 至 5.5V 的单电源供电运
行。输出端允许的电源范围为 15V 至 30V。两个互补
CMOS 输入控制栅极驱动器的输出状态。76ns 的短暂
传播时间保证了对于输出级的精确控制。
•
•
分离输出,可提供 2.5A 峰值拉电流和
5A 峰值灌电流
短暂传播延迟:76ns(典型值),
110ns(最大值)
•
•
•
•
2A 有源米勒钳位
输出短路钳位
内置的去饱和 (DESAT) 故障检测功能可识别 IGBT 何
时处于过流状态。检测到 DESAT 时,静音逻辑会立即
阻断隔离器输出,并启动软关断过程以禁用 OUTH 引
脚并将 OUTL 引脚拉至低电平持续 2μs。当 OUTL 引
脚达到 2V 时(相对于最大负电源电势 VEE2),栅极
驱动器会被“硬”拉至 VEE2 电势,从而立即将 IGBT 关
断。
短路期间的软关断 (STO)
在检测到去饱和故障时通过 FLT 发出故障报警并通
过 RST 复位
•
•
具有就绪 (RDY) 引脚指示的输入和输出欠压锁定
(UVLO)
有源输出下拉特性,在低电源或输入悬空的情况下
默认输出低电平
•
•
•
•
•
•
•
2.25V 至 5.5V 输入电源电压
当发生去饱和故障时,器件会通过隔离隔栅发送故障信
号,以将输入端的 FLT 输出拉为低电平并阻断隔离器
的输入。静音逻辑在软关断期间激活。FLT 的输出状
态将被锁存,并只能在 RDY 引脚变为高电平后通过
RST 输入上的低电平有效脉冲复位。
15V 至 30V 输出驱动器电源电压
互补金属氧化物半导体 (CMOS) 兼容输入
抑制短于 20ns 的输入脉冲和瞬态噪声
工作环境温度范围:-55°C 至 +125°C
浪涌抗扰度为 12800 VPK(根据 IEC 61000-4-5)
安全相关认证:
器件信息(1)
器件型号
封装
封装尺寸(标称值)
–
符合 DIN V VDE V 0884-10 (VDE V 0884-
10):2006-12 标准的 8000 VPK VIOTM 和 2121
ISO5852S-EP
SOIC (16)
10.30mm x 7.50mm
VPK VIORM 增强型隔离
(1) 要了解所有可用封装,请参见数据表末尾的可订购产品附录。
–
–
符合 UL 1577 标准且长达 1 分钟的 5700 VRMS
隔离
功能框图
VCC1
VCC2
CSA 组件接受通知 5A,IEC 60950-1、IEC
60601-1 和 IEC 61010-1 终端设备标准
VCC1
UVLO1
UVLO2
500 µA
DESAT
GND2
INœ
–
–
符合 GB4943.1-2011 的 CQC 认证
Mute
9 V
已通过 UL、VDE、CQC、TUV 认证并规划进
行 CSA 认证
IN+
VCC2
VCC1
RDY
Gate Drive
and
OUTH
OUTL
Ready
2 应用
Encoder
Logic
STO
•
隔离式绝缘栅双极型晶体管 (IGBT) 和金属氧化物
半导体场效应晶体管 (MOSFET) 驱动器
VCC1
FLT
Decoder
Q
Q
S
R
2 V
Fault
CLAMP
VCC1
–
–
–
–
–
工业电机控制驱动器
RST
工业用电源
GND1
VEE2
太阳能逆变器
Copyright © 2016, Texas Instruments Incorporated
混合动力汽车 (HEV) 和电动车 (EV) 电源模块
感应加热
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSEW1
ISO5852S-EP
ZHCSFX1 –DECEMBER 2016
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性.......................................................................... 1
9
Detailed Description ............................................ 23
9.1 Overview ................................................................. 23
9.2 Functional Block Diagram ....................................... 23
9.3 Feature Description................................................. 24
9.4 Device Functional Modes........................................ 25
应用.......................................................................... 1
说明.......................................................................... 1
修订历史................................................................... 2
说明 (续).............................................................. 3
Pin Configuration and Function........................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 6
7.5 Power Ratings........................................................... 6
7.6 Insulation Specifications............................................ 7
7.7 Safety Limiting Values .............................................. 8
7.8 Safety-Related Certifications..................................... 8
7.9 Electrical Characteristics........................................... 9
7.10 Switching Characteristics...................................... 10
7.11 Insulation Characteristics Curves ......................... 11
7.12 Typical Characteristics.......................................... 12
Parameter Measurement Information ................ 19
10 Application and Implementation........................ 26
10.1 Application Information.......................................... 26
10.2 Typical Applications .............................................. 26
11 Power Supply Recommendations ..................... 36
12 Layout................................................................... 36
12.1 Layout Guidelines ................................................. 36
12.2 PCB Material......................................................... 36
12.3 Layout Example .................................................... 36
13 器件和文档支持 ..................................................... 37
13.1 文档支持................................................................ 37
13.2 接收文档更新通知 ................................................. 37
13.3 社区资源................................................................ 37
13.4 商标....................................................................... 37
13.5 静电放电警告......................................................... 37
13.6 Glossary................................................................ 37
14 机械、封装和可订购信息....................................... 37
8
4 修订历史
注:之前版本的页码可能与当前版本有所不同。
日期
修订版本
注释
2016 年 12 月
*
最初发布。
2
版权 © 2016, Texas Instruments Incorporated
ISO5852S-EP
www.ti.com.cn
ZHCSFX1 –DECEMBER 2016
5 说明 (续)
如果在由双极输出电源供电的正常运行期间关断 IGBT,输出电压会被硬钳位为 VEE2。如果输出电源为单极,那么
可采用有源米勒钳位,这种钳位会在一条低阻抗路径上灌入米勒电流,从而防止 IGBT 在高电压瞬态状态下发生动
态导通。
栅极驱动器是否准备就绪待运行由两个欠压锁定电路控制,这两个电路会监视输入端和输出端的电源。如果任意一
端电源不足,RDY 输出会变为低电平,否则该输出为高电平。
ISO5852S-EP 器件采用 16 引脚小外形尺寸集成电路 (SOIC) 封装。此器件的额定工作环境温度范围为 -55°C 至
+125°C。
Copyright © 2016, Texas Instruments Incorporated
3
ISO5852S-EP
ZHCSFX1 –DECEMBER 2016
www.ti.com.cn
6 Pin Configuration and Function
DW Package
16-Pin SOIC
Top View
VEE2
DESAT
GND2
OUTH
VCC2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND1
VCC1
RST
FLT
RDY
INœ
OUTL
CLAMP
VEE2
IN+
GND1
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
CLAMP
DESAT
FLT
NO.
7
O
I
Miller clamp output
2
Desaturation voltage input
13
9
O
Fault output, active-low during DESAT condition
GND1
—
Input ground
16
3
GND2
IN+
—
I
Gate drive common. Connect to IGBT emitter.
Non-inverting gate drive voltage control input
Inverting gate drive voltage control input
Positive gate drive voltage output
10
11
4
IN–
I
OUTH
OUTL
RDY
RST
O
O
O
I
6
Negative gate drive voltage output
12
14
15
5
Power-good output, active high when both supplies are good.
Reset input, apply a low pulse to reset fault latch.
Positive input supply (2.25-V to 5.5-V)
VCC1
VCC2
—
—
Most positive output supply potential.
1
VEE2
—
Output negative supply. Connect to GND2 for unipolar supply application.
8
4
Copyright © 2016, Texas Instruments Incorporated
ISO5852S-EP
www.ti.com.cn
ZHCSFX1 –DECEMBER 2016
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
GND1 – 0.3
–0.3
MAX
UNIT
V
VCC1
Supply-voltage input side
6
35
VCC2
Positive supply-voltage output side
Negative supply-voltage output side
Total-supply output voltage
(VCC2 – GND2)
(VEE2 – GND2)
V
VEE2
–17.5
0.3
V
V(SUP2)
V(OUTH)
V(OUTL)
(VCC2 - VEE2
)
–0.3
35
V
Positive gate-driver output voltage
Negative gate-driver output voltage
VEE2 – 0.3
VEE2 – 0.3
VCC2 + 0.3
VCC2 + 0.3
V
V
Maximum pulse width = 10 μs, Maximum
duty cycle = 0.2%)
I(OUTH)
I(OUTL)
Gate-driver high output current
Gate-driver low output current
2.7
5.5
A
A
Maximum pulse width = 10 μs, Maximum
duty cycle = 0.2%)
V(LIP)
I(LOP)
Voltage at IN+, IN–,FLT, RDY, RST
Output current of FLT, RDY
GND1 – 0.3
VCC1 + 0.3
10
V
mA
V
V(DESAT) Voltage at DESAT
V(CLAMP) Clamp voltage
GND2 – 0.3
VEE2 – 0.3
–55
VCC2 + 0.3
VCC2 + 0.3
150
V
TJ
Junction temperature
Storage temperature
°C
°C
TSTG
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±4000
±1500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
V
VCC1
VCC2
V(EE2)
V(SUP2)
V(IH)
V(IL)
tUI
Supply-voltage input side
2.25
5.5
Positive supply-voltage output side (VCC2 – GND2)
Negative supply-voltage output side (VEE2 – GND2)
15
30
V
–15
0
30
V
Total supply-voltage output side (VCC2 – VEE2
High-level input voltage (IN+, IN–, RST)
Low-level input voltage (IN+, IN–, RST)
)
15
V
0.7 × VCC1
VCC1
V
0
40
0.3 × VCC1
V
Pulse width at IN+, IN– for full output (CLOAD = 1 nF)
Pulse width at RST for resetting fault latch
Ambient temperature
ns
ns
°C
tRST
800
–55
TA
125
Copyright © 2016, Texas Instruments Incorporated
5
ISO5852S-EP
ZHCSFX1 –DECEMBER 2016
www.ti.com.cn
7.4 Thermal Information
ISO5852S-EP
DW (SOIC)
16 PINS
99.6
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
48.5
56.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
29.2
ψJB
56.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Ratings
Full-chip power dissipation is derated 10.04 mW/°C beyond 25°C ambient temperature. At 125°C ambient temperature, a
maximum of 251 mW total power dissipation is allowed. Power dissipation can be optimized depending on ambient
temperature and board design, while ensuring that the junction temperature does not exceed 150°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1255
175
UNIT
mW
mW
mW
PD
Maximum power dissipation (both sides)
Maximum input power dissipation
Maximum output power dissipation
VCC1 = 5.5-V, VCC2 = 30-V, TA = 25°C
VCC1 = 5.5-V, VCC2 = 30-V, TA = 25°C
VCC1 = 5.5-V, VCC2 = 30-V, TA = 25°C
PD(I)
PD(O)
1080
6
Copyright © 2016, Texas Instruments Incorporated
ISO5852S-EP
www.ti.com.cn
ZHCSFX1 –DECEMBER 2016
7.6 Insulation Specifications
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
CLR
CPG
DTI
External clearance(1)
External creepage(1)
Shortest terminal-to-terminal distance through air
8
8
mm
mm
µm
V
Shortest terminal-to-terminal distance across the
package surface
Distance through the insulation
Comparative tracking index
Material group
Minimum internal gap (internal clearance)
21
600
DIN EN 60112 (VDE 0303-11); IEC 60112; Material
Group I according to IEC 60664-1; UL 746A
CTI
I
Rated mains voltage ≤ 600 VRMS
Rated mains voltage ≤ 1000 VRMS
I-IV
I-III
Overvoltage Category
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12(2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar)
2121
1500
2121
8000
VPK
VRMS
VDC
AC voltage (sine wave) Time dependent dielectric
breakdown (TDDB) test, see Figure 1
VIOWM
Maximum isolation working voltage
DC voltage
VTEST = VIOTM; t = 60 s (qualification); t = 1 s (100%
production)
VIOTM
VIOSM
Maximum transient isolation voltage
Maximum surge isolation voltage(3)
VPK
Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
8000
VPK
Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
≤5
Vpd(m) = 1.2 × VIORM = 2545 VPK
tm = 10 s
,
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
≤5
≤5
qpd
Apparent charge(4)
Vpd(m) = 1.6 × VIORM = 3394 VPK
tm = 10 s
,
pC
Method b1: At routine test (100% production) and
preconditioning (type test)
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.875× VIORM = 3977 VPK
tm = 10 s
,
CIO
RIO
Barrier capacitance, input to output(5)
Isolation resistance, input to output(5)
Pollution degree
VIO = 0.4 sin (2πft), f = 1 MHz
VIO = 500 V, TA = 25°C
1
pF
> 1012
> 1011
> 109
2
VIO = 500 V, 100°C ≤ TA ≤ 125°C
VIO = 500 V at TS = 150°C
Ω
UL 1577
VTEST = VISO = 5700 VRMS, t = 60 s (qualification);
VTEST = 1.2 × VISO = 6840 VRMS, t = 1 s (100%
production)
VISO
Withstand isolation voltage
5700
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall
be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device.
Copyright © 2016, Texas Instruments Incorporated
7
ISO5852S-EP
ZHCSFX1 –DECEMBER 2016
www.ti.com.cn
7.7 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RθJA = 99.6°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C,
456
see Figure 2
θJA = 99.6°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C,
see Figure 2
θJA = 99.6°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C,
see Figure 2
θJA = 99.6°C/W, VI = 15 V, TJ = 150°C, TA = 25°C,
see Figure 2
θJA = 99.6°C/W, VI = 30 V, TJ = 150°C, TA = 25°C,
see Figure 2
R
346
228
84
Safety input, output, or supply
current
R
IS
mA
R
R
42
Safety input, output, or total
power
PS
TS
RθJA = 99.6°C/W, TJ = 150°C, TA = 25°C, see Figure 3
255(1)
150
mW
°C
Safety temperature
(1) Input, output, or the sum of input and output power should not exceed this value.
The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that
of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended
maximum input voltage times the current. The junction temperature is then the ambient temperature plus the
power times the junction-to-air thermal resistance.
7.8 Safety-Related Certifications
VDE
CSA
UL
CQC
TUV
Certified according to DIN V Plan to certify under CSA
Recognized under UL 1577 Certified according to
Certified according to
EN 61010-1:2010 (3rd Ed) and
EN 60950-
1:2006/A11:2009/A1:2010/
A12:2011/A2:2013
VDE V 0884-10
Component Acceptance
Component Recognition
GB4943.1-2011
(VDE V 0884-10):2006-12
and DIN EN 61010-1 (VDE
0411-1):2011-07
Notice 5A, IEC 60950-1, and Program
IEC 60601-1
Reinforced Insulation
Isolation Rating of 5700
Single Protection, 5700
VRMS
Reinforced Insulation,
Altitude ≤ 5000m, Tropical
climate, 400 VRMS maximum working voltage of 600 VRMS
working voltage
5700 VRMS Reinforced insulation per
EN 61010-1:2010 (3rd Ed) up to
(1)
Maximum Transient isolation VRMS
voltage, 8000 VPK
Maximum surge isolation
voltage, 8000 VPK
;
;
Reinforced insulation per
CSA 60950-1- 07+A1+A2
and IEC 60950-1 (2nd Ed.),
800 VRMS max working
voltage (pollution degree 2,
material group I) ;
5700 VRMS Reinforced insulation per
EN 60950-
1:2006/A11:2009/A1:2010/
A12:2011/A2:2013 up to working
voltage of 800 VRMS
,
Maximum repetitive peak
isolation voltage, 2121 VPK
2 MOPP (Means of Patient
Protection) per CSA 60601-
1:14 and IEC 60601-1 Ed.
3.1, 250 VRMS (354 VPK
)
max working voltage
Certification completed
Certificate number:
40040142
Certificate planned
Certification completed
File number: E181974
Certification completed
Certificate number:
CQC16001141761
Certification completed
Client ID number: 77311
(1) Production tested ≥ 6840 VRMS for 1 second in accordance with UL 1577.
8
Copyright © 2016, Texas Instruments Incorporated
ISO5852S-EP
www.ti.com.cn
ZHCSFX1 –DECEMBER 2016
7.9 Electrical Characteristics
Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, VCC1 = 5 V, VCC2
GND2 = 15 V, GND2 – VEE2 = 8 V
–
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE SUPPLY
Positive-going UVLO1 threshold-voltage
input side
VIT+(UVLO1)
VIT-(UVLO1)
VHYS(UVLO1)
VIT+(UVLO2)
VIT–(UVLO2)
VHYS(UVLO2)
2.25
V
V
V
V
V
V
Negative-going UVLO1 threshold-voltage
input side
1.7
UVLO1 Hysteresis voltage (VIT+ – VIT–
input side
)
0.2
12
11
1
Positive-going UVLO2 threshold-voltage
output side
13
Negative-going UVLO2 threshold-voltage
output side
9.5
UVLO2 hysteresis voltage (VIT+ – VIT–
output side
)
IQ1
Input-supply quiescent current
Output-supply quiescent current
2.8
3.6
4.5
6
mA
mA
IQ2
LOGIC I/O
Positive-going input-threshold voltage (IN+,
IN–, RST)
VIT+(IN,RST)
VIT–(IN,RST)
0.7 × VCC1
V
V
Negative-going input-threshold voltage
(IN+, IN–, RST)
0.3 × VCC1
VHYS(IN,RST)
Input hysteresis voltage (IN+, IN–, RST)
High-level input leakage at (IN+)(1)
Low-level input leakage at (IN–, RST)(2)
Pullup current of FLT, RDY
0.15 × VCC1
100
V
IIH
IN+ = VCC1
µA
µA
µA
V
IIL
IN– = GND1, RST = GND1
V(RDY) = GND1, V(FLT) = GND1
I(FLT) = 5 mA
-100
IPU
V(OL)
100
Low-level output voltage at FLT, RDY
0.2
2
GATE DRIVER STAGE
V(OUTPD) Active output pulldown voltage
VOUTH
I(OUTH/L) = 200 mA, VCC2 = open
I(OUTH) = –20 mA
V
V
High-level output voltage
Low-level output voltage
VCC2 – 0.5
VCC2 – 0.24
VEE2 + 13
VOUTL
I(OUTL) = 20 mA
VEE2 + 50
mV
IN+ = high, IN– = low,
V(OUTH) = VCC2 - 15 V
I(OUTH)
I(OUTL)
I(OLF)
High-level output peak current
Low-level output peak current
1.5
3.4
2.5
5
A
A
IN+ = low, IN– = high,
V(OUTL) = VEE2 + 15 V
Low-level output current during fault
condition
130
mA
ACTIVE MILLER CLAMP
V(CLP) Low-level clamp voltage
I(CLP)
I(CLP) = 20 mA
VEE2 + 0.015
VEE2 + 0.08
V
A
V
Low-level clamp current
Clamp threshold voltage
V(CLAMP) = VEE2 + 2.5 V
1.6
1.6
2.5
2.1
3.3
2.5
V(CLTH)
SHORT CIRCUIT CLAMPING
Clamping voltage
V(CLP-OUTH)
IN+ = high, IN– = low, tCLP = 10 µs,
I(OUTH) = 500 mA
1.1
1.3
1.3
0.7
0.7
1.3
1.5
V
V
V
V
V
(VOUTH – VCC2
)
Clamping voltage
(VOUTL – VCC2
IN+ = high, IN– = low, tCLP = 10 µs,
I(OUTL) = 500 mA
V(CLP-OUTL)
V(CLP-CLP)
V(CLP-CLAMP)
)
Clamping voltage
(VCLP – VCC2
IN+ = high, IN– = low, tCLP = 10 µs,
I(CLP) = 500 mA
)
IN+ = High, IN– = Low, I(CLP) = 20
mA
Clamping voltage at CLAMP
Clamping voltage at OUTL
1.1
1.1
IN+ = High, IN– = Low, I(OUTL) = 20
mA
V(CLP-OUTL)
(VCLP – VCC2
)
DESAT PROTECTION
I(CHG)
Blanking-capacitor charge current
Blanking-capacitor discharge current
V(DESAT) – GND2 = 2 V
V(DESAT) – GND2 = 6 V
0.42
9
0.5
14
0.58
mA
mA
I(DCHG)
(1) IIH for IN–, RST pin is zero as they are pulled high internally.
(2) IIL for IN+ is zero as it is pulled low internally.
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Electrical Characteristics (continued)
Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, VCC1 = 5 V, VCC2
GND2 = 15 V, GND2 – VEE2 = 8 V
–
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DESAT threshold voltage with respect to
GND2
V(DSTH)
V(DSL)
8.3
9
9.5
V
DESAT voltage with respect to GND2,
when OUTH or OUTL is driven low
0.4
1
V
7.10 Switching Characteristics
Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25°C, VCC1 = 5 V, VCC2
GND2 = 15 V, GND2 – VEE2 = 8 V
–
PARAMETER
TEST CONDITIONS
CLOAD = 1 nF
MIN
12
TYP
18
MAX UNIT
tr
Output-signal rise time at OUTH
Output-signal fall time at OUTL
Propagation Delay
35
37
ns
ns
ns
ns
ns
ns
ns
μs
ns
μs
ns
ns
tf
CLOAD = 1 nF
CLOAD = 1 nF
CLOAD = 1 nF
CLOAD = 1 nF
CLOAD = 1 nF
12
20
tPLH, tPHL
tsk-p
76
110
20
Pulse skew |tPHL – tPLH
|
See Figure 44, Figure 45,
and Figure 46
tsk-pp
Part-to-part skew
30(1)
tGF (IN,/RST)
tDS (90%)
tDS (10%)
tDS (GF)
tDS (FLT)
tLEB
Glitch filter on IN+, IN–, RST
20
30
553
2
40
DESAT sense to 90% VOUTH/L delay CLOAD = 10 nF
DESAT sense to 10% VOUTH/L delay CLOAD = 10 nF
760
3.5
DESAT-glitch filter delay
CLOAD = 1 nF
See Figure 46
330
DESAT sense to FLT-low delay
Leading-edge blanking time
Glitch filter on RST for resetting FLT
1.4
480
800
See Figure 44 and Figure 45
310
300
400
tGF(RSTFLT)
VI = VCC1 / 2 + 0.4 × sin (2πft), f = 1 MHz,
VCC1 = 5 V
CI
Input capacitance(2)
2
pF
CMTI
Common-mode transient immunity
VCM = 1500 V, see Figure 47
100
120
kV/μs
(1) Measured at same supply voltage and temperature condition.
(2) Measured from input pin to ground.
10
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7.11 Insulation Characteristics Curves
500
450
400
350
300
250
200
150
100
50
1.E+11
Safety Margin Zone: 1800 VRMS, 254 Years
Operating Zone: 1500 VRMS, 135 Years
TDDB Line (<1 PPM Fail Rate)
87.5%
VCC1 = 2.75 V
VCC1 = 3.6 V
VCC1 = 5.5 V
VCC2 = 15 V
VCC2 = 30 V
1.E+10
1.E+9
1.E+8
1.E+7
1.E+6
1.E+5
1.E+4
1.E+3
20%
1.E+2
0
0
50
100
150
200
1.E+1
Ambient Temperature (èC)
500 1500 2500 3500 4500 5500 6500 7500 8500 9500
Stress Voltage (VRMS
)
TA up to 150°C
Stress-voltage frequency = 60 Hz
Figure 1. Isolation Capacitor Lifetime Projection for Basic
Insulation
Figure 2. Thermal Derating Curve for Safety Limiting
Current per VDE
1400
1200
1000
800
600
400
200
0
Power
0
50
100
Ambient Temperature (èC)
150
200
Figure 3. Thermal Derating Curve for Safety Limiting Power per VDE
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7.12 Typical Characteristics
0
-0.5
-1
0
-0.5
-1
TA = -40èC
TA = 25èC
TA = 125èC
-1.5
-2
-1.5
-2
-2.5
-2.5
-3
-3
VCC2 - VOUT = 2.5 V
VCC2 - VOUT = 5 V
VCC2 - VOUT = 10 V
VCC2 - VOUT = 15 V
VCC2 - VOUT = 20 V
-3.5
-4
-3.5
-4
-40 -25 -10
5
20 35 50 65 80 95 110 125
0
5
10
15
20
25
30
Ambient Temperature (èC)
VCC2 - VOUTH/L Voltage (V)
D001
D003
Figure 4. Output High Drive Current vs Temperature
Figure 5. Output High Drive Current vs Output Voltage
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
VOUT - VEE2 = 2.5 V
VOUT - VEE2 = 5 V
VOUT - VEE2 = 10 V
VOUT - VEE2 = 15 V
VOUT - VEE2 = 20 V
TA = -40èC
TA = 25èC
TA = 125èC
-40 -25 -10
5
20 35 50 65 80 95 110 125
0
5
10
15
20
25
30
Ambient Temperature (èC)
VOUTH/L - VEE2 Voltage (V)
D002
D004
Figure 6. Output Low Drive Current vs Temperature
Figure 7. Output Low Drive Current vs Output Voltage
9.2
9.1
9
8.9
8.8
8.7
8.6
8.5
15 V Unipolar
30 V Unipolar
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (èC)
50 ns / Div
D005
CL = 1 nF
RGH = 0 Ω
RGL = 0 Ω
Unipolar: VCC2 – VEE2 = VCC2 – GND2
VCC2 – VEE2 = VCC2 – GND2 = 20 V
Figure 9. Output Transient Waveform
Figure 8. DESAT Threshold Voltage vs Temperature
12
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Typical Characteristics (continued)
2 ms / Div
500 ns / Div
CL = 10 nF
RGH = 0 Ω
RGL = 0 Ω
CL = 100 nF
RGH = 0 Ω
RGL = 0 Ω
VCC2 – VEE2 = VCC2 – GND2 = 20 V
VCC2 – VEE2 = VCC2 – GND2 = 20 V
Figure 10. Output Transient Waveform
Figure 11. Output Transient Waveform
50 ns / Div
500 ns / Div
CL = 1 nF
RGH = 10 Ω
RGL = 5 Ω
CL = 10 nF
RGH = 10 Ω
RGL = 5 Ω
VCC2 – VEE2 = VCC2 – GND2 = 20 V
VCC2 – VEE2 = VCC2 – GND2 = 20 V
Figure 12. Output Transient Waveform
Figure 13. Output Transient Waveform
OUT
DESAT
FLT
RDY
1 µs/Div
2 ms / Div
CL = 10 nF
RGH = 0 Ω
RGL = 0 Ω
CL = 100 nF
RGH = 10 Ω
RGL = 5 Ω
VCC2 – VEE2 = VCC2 – GND2 = 15 V
DESAT = 220 pF
VCC2 – VEE2 = VCC2 – GND2 = 20 V
Figure 15. Output Transient Waveform DESAT, RDY, and
FLT
Figure 14. Output Transient Waveform
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Typical Characteristics (continued)
OUT
OUT
DESAT
/FLT
DESAT
/FLT
RDY
RDY
2 ms / Div
1 ms / Div
CL = 10 nF
RGH = 0 Ω
RGL = 0 Ω
CL = 10 nF
RGH = 0 Ω
RGL = 0 Ω
VCC2 – VEE2 = VCC2 – GND2 = 15 V
DESAT = 220 pF
VCC2 – VEE2 = VCC2 – GND2 = 30 V
DESAT = 220 pF
Figure 16. Output Transient Waveform DESAT, RDY, and
FLT
Figure 17. Output Transient Waveform DESAT, RDY, and
FLT
3.4
3.2
3
OUT
DESAT
/FLT
2.8
2.6
2.4
2.2
2
RDY
VCC1 = 3 V
VCC1 = 3.3 V
VCC1 = 5 V
VCC1 = 5.5 V
2 ms / Div
-55
-35
-15
5
25
45
65
85
105 125
CL = 10 nF
RGH = 0 Ω
RGL = 0 Ω
Ambient Temperature (èC)
D006
VCC2 – VEE2 = VCC2 – GND2 = 30 V
DESAT = 220 pF
IN+ = High
IN– = Low
Figure 18. Output Transient Waveform DESAT, RDY, and
FLT
Figure 19. ICC1 Supply Current vs Temperature
2
1.9
1.8
1.7
1.6
1.5
1.4
3
2.5
2
1.5
1
1.3
VCC1 = 3 V
VCC1 = 3.3 V
1.2
0.5
0
VCC1 = 5 V
VCC1 = 5.5 V
VCC1 = 3 V
VCC1 = 5.5 V
1.1
1
-55
-35
-15
5
25
45
65
85
105 125
0
50
100
150
200
250
300
Ambient Temperature (èC)
Input Frequency - (kHz)
D007
D008
IN+ = Low
IN– = Low
Figure 20. ICC1 Supply Current vs Temperature
Figure 21. >ICC1 Supply Current vs Input Frequency
14
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Typical Characteristics (continued)
5
5.5
5
4.5
4
4.5
4
3.5
3
3.5
3
VCC2 = 15 V
VCC2 = 20 V
VCC2 = 30 V
VCC2 = 15 V
VCC2 = 20 V
VCC2 = 30 V
2.5
2.5
2
2
-55
-35
-15
5
25
45
65
85
105 125
0
50
100
150
200
250
300
Ambient Temperature (èC)
Input Frequency - (kHz)
D010
D009
Input frequency = 1 kHz
No CL
Figure 22. ICC2 Supply Current vs Temperature
Figure 23. ICC2 Supply Current vs Input Frequency
100
90
80
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
tpLH at VCC2 = 15 V
tpHL at VCC2 = 15 V
tpLH at VCC2 = 30 V
tpHL at VCC2 = 30 V
VCC2 = 15 V
VCC2 = 30 V
-55
-35
-15
5
25
45
65
85
105 125
0
10
20
30
40
50
60
70
80
90 100
Ambient Temperature (èC)
Load Capacitance (nF)
D012
D011
CL = 1 nF
VCC1 = 5 V
RGH = 0 Ω
RGL = 0 Ω
RGH = 10 Ω
RGL = 5 Ω, 20 kHz
Figure 25. Propagation Delay vs Temperature
Figure 24. ICC2 Supply Current vs Load Capacitance
100
90
80
70
60
50
40
30
20
10
0
1200
1000
800
600
400
200
0
tpLH at VCC2 = 15 V
tpLH at VCC2 = 30 V
tpHL at VCC2 = 15 V
tpHL at VCC2 = 30 V
tpLH at VCC1 = 3.3 V
tpHL at VCC1 = 3.3 V
tpLH at VCC1 = 5 V
tpHL at VCC1 = 5 V
-55
-35
-15
5
25
45
65
85
105 125
0
10
20
30
40
50
60
70
80
90 100
Ambient Temperature (èC)
Ambient Temperature (èC)
D013
D014
CL = 1 nF
VCC2 = 15 V
RGH = 0 Ω
RGL = 0 Ω
RGH = 10 Ω
RGL = 5 Ω
VCC1 = 5 V
Figure 26. Propagation Delay vs Temperature
Figure 27. Propagation Delay vs Load Capacitance
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Typical Characteristics (continued)
1000
600
500
400
300
200
100
0
VCC2 = 15 V
VCC2 = 30 V
VCC2 = 15 V
VCC2 = 30 V
900
800
700
600
500
400
300
200
100
0
0
10
20
30
40
50
60
70
80
90 100
0
10
20
30
40
50
60
70
80
90 100
Load Capacitance (nF)
Load Capacitance (nF)
D015
D016
RGH = 0 Ω
RGL = 0 Ω
VCC1 = 5 V
RGH = 0 Ω
RGL = 0 Ω
VCC1 = 5 V
Figure 28. tr Rise Time vs Load Capacitance
Figure 29. tf Fall Time vs Load Capacitance
6000
5000
4000
3000
2000
1000
0
2000
1800
1600
1400
1200
1000
800
VCC2 = 15 V
VCC2 = 30 V
VCC2 = 15 V
VCC2 = 30 V
600
400
200
0
0
10
20
30
40
50
60
70
80
90 100
0
10
20
30
40
50
60
70
80
90 100
Load Capacitance (nF)
Load Capacitance (nF)
D017
D018
RGH = 10 Ω
RGL = 5 Ω
VCC1 = 5 V
RGH = 10 Ω
RGL = 5 Ω
VCC1 = 5 V
Figure 30. tr Rise Time vs Load Capacitance
Figure 31. tf Fall Time vs Load Capacitance
500
480
460
440
420
400
380
360
340
320
300
4
3.5
3
VCC2 = 15 V
VCC2 = 30 V
2.5
2
VCC2 = 15 V
VCC2 = 30 V
1.5
-55
-35
-15
5
25
45
65
85
105 125
1
-55
Ambient Temperature (èC)
-35
-15
5
25
45
65
85
105 125
D019
Ambient Temperature (èC)
D020
CL = 10 nF
RGH = 0 Ω
RGL = 0 Ω
Figure 33. DESAT Sense to VOUT 10% Delay vs Temperature
Figure 32. Leading Edge Blanking Time With Temperature
16
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Typical Characteristics (continued)
610
1.25
1.2
VCC2 = 15 V
VCC2 = 30 V
VCC2 = 15 V
VCC2 = 30 V
590
570
550
530
510
490
470
450
1.15
1.1
1.05
-55
-35
-15
5
25
45
65
85
105 125
-55
-35
-15
5
25
45
65
85
105 125
Ambient Temperature (èC)
D021
Ambient Temperature (èC)
D022
CL = 10 nF
RGH = 0 Ω
RGL = 0 Ω
Figure 34. DESAT Sense to VOUT 90% Delay vs Temperature
Figure 35. DESAT Sence to Fault Low Delay vs Temperature
120
5
4.8
4.6
4.4
4.2
4
100
80
60
40
3.8
3.6
VCC1 = 3 V
VCC1 = 3.3 V
VCC1 = 5 V
20
VCC1 = 5.5 V
VCC1 = 5 V, VCC2 = 15 V
3.4
-40 -25 -10
0
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (èC)
Ambient Temperature (èC)
D024
D023
Figure 36. Fault and RDY Low to RDY High Delay vs
Temperature
Figure 37. Reset to Fault Delay Across Temperature
2
1.8
1.6
1.4
1.2
1
5
4.5
4
3.5
3
2.5
2
0.8
0.6
0.4
0.2
0
1.5
1
V(CLAMP) = 2 V
V(CLAMP) = 4 V
V(CLAMP) = 6 V
I(OUTH/L) = 100 mA
I(OUTH/L) = 200 mA
0.5
0
-55
-35
-15
5
25
45
65
85
105 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Ambient Temperature (èC)
Ambient Temperature (èC)
D026
D025
Figure 39. Active Pulldown Voltage vs Temperature
Figure 38. Miller Clamp Current vs Temperature
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Typical Characteristics (continued)
1500
1350
1200
1050
900
1400
1200
1000
800
600
400
200
0
20 mA at VCC2 = 15 V
20 mA at VCC2 = 30 V
250 mA at VCC2 = 15 V
250 mA at VCC2 = 30 V
500 mA at VCC2 = 15 V
500 mA at VCC2 = 30 V
750
600
450
300
20 mA at VCC2 = 15 V
20 mA at VCC2 = 30 V
250 mA at VCC2 = 15 V
250 mA at VCC2 = 30 V
500 mA at VCC2 = 15 V
500 mA at VCC2 = 30 V
150
0
-55
-35
-15
5
25
45
65
85
105 125
-55
-35
-15
5
25
45
65
85
105 125
Ambient Temperature (èC)
Ambient Temperature (èC)
D029
D027
Figure 40. Short-Circuit Clamp Voltage on Clamp Across
Temperature
Figure 41. Short-Circuit Clamp Voltage on OUTH Across
Temperature
1500
-400
1350
1200
1050
900
750
600
450
300
150
0
-420
-440
-460
-480
-500
-520
-540
-560
-580
-600
20 mA at VCC2 = 15 V
20 mA at VCC2 = 30 V
250 mA at VCC2 = 15 V
250 mA at VCC2 = 30 V
500 mA at VCC2 = 15 V
500 mA at VCC2 = 30 V
VDESAT = 6 V
85 105 125
-55
-35
-15
5
25
45
65
85
105 125
-55
-35
-15
5
25
45
65
Ambient Temperature (èC)
D028
Ambient Temperature (èC)
D030
VCC2 = 15 V
DESAT = 6 V
Figure 42. Short-Circuit Clamp Voltage on OUTL Across
Temperature
Figure 43. Blanking Capacitor Charging Current vs
Temperature
18
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ZHCSFX1 –DECEMBER 2016
8 Parameter Measurement Information
INœ
0 V
50 %
50 %
IN+
tr
tf
90%
50%
10%
OUTH/L
tPLH
tPHL
Figure 44. OUTH and OUTL Propagation Delay, Non-Inverting Configuration
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Parameter Measurement Information (continued)
INœ
50 %
50 %
IN+
VCC1
tr
tf
90%
50%
10%
OUTH/L
tPLH
tPHL
Figure 45. OUTH and OUTL Propagation Delay, Inverting Configuration
20
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ZHCSFX1 –DECEMBER 2016
Parameter Measurement Information (continued)
Inputs
Inputs
blocked
released
The inputs are muted for 5 µs by internal circuit after
DESAT is detected. RDY is also low until the mute time.
FLT can be reset, only if RDY goes high.
IN+
(INœ = GND1)
90%
VOUTH/L
tDS(90%)
10%
tDS(10%)
VDSTH
tLEB
DESAT
FLT
tDS(FLT)
RDY
RST
tMute
RST-rising edge
turns FLT high
tRST
Figure 46. DESAT, OUTH/L, FLT, RST Delay
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Parameter Measurement Information (continued)
5
15
VCC2
VCC1
15V
0.1µF
1µF
2.25 V- 5.5 V
3
9 ,16
14
GND1
GND2
VEE2
1,8
6
RST
IN+
+
S1
-
10
OUTL
+
Pass œ Fail Criterion :
OUT must remain stable
11
CL
1nF
IN -
13
12
2
-
FLT
DESAT
7
4
CLAMP
OUTH
RDY
Copyright © 2016, Texas Instruments
Incorporated
-
+
VCM
Figure 47. Common-Mode Transient Immunity Test Circuit
22
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ZHCSFX1 –DECEMBER 2016
9 Detailed Description
9.1 Overview
The ISO5852S-EP device is an isolated gate driver for IGBTs and MOSFETs. Input CMOS logic and output
power stage are separated by a Silicon dioxide (SiO2) capacitive isolation.
The IO circuitry on the input side interfaces with a micro controller and consists of gate drive control and RESET
(RST) inputs, READY (RDY) and FAULT (FLT) alarm outputs. The power stage consists of power transistors to
supply 2.5-A pullup and 5-A pulldown currents to drive the capacitive load of the external power transistors, as
well as DESAT detection circuitry to monitor IGBT collector-emitter overvoltage under short circuit events. The
capacitive isolation core consists of transmit circuitry to couple signals across the capacitive isolation barrier, and
receive circuitry to convert the resulting low-swing signals into CMOS levels. The ISO5852S-EP device also
contains undervoltage lockout circuitry to prevent insufficient gate drive to the external IGBT, and active output
pulldown feature which ensures that the gate-driver output is held low, if the output supply voltage is absent. The
ISO5852S-EP device also has an active Miller clamp which can be used to prevent parasitic turnon of the
external power transistor, due to Miller effect, for unipolar supply operation.
9.2 Functional Block Diagram
VCC2
VCC1
VCC1
UVLO1
UVLO2
500 µA
DESAT
GND2
INœ
Mute
9 V
IN+
VCC2
VCC1
RDY
Gate Drive
and
OUTH
OUTL
Ready
Encoder
Logic
STO
VCC1
FLT
Decoder
Q
Q
S
R
2 V
Fault
CLAMP
VCC1
RST
GND1
VEE2
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
23
ISO5852S-EP
ZHCSFX1 –DECEMBER 2016
www.ti.com.cn
9.3 Feature Description
9.3.1 Supply and Active Miller clamp
The ISO5852S-EP device supports both bipolar and unipolar power supply with active Miller clamp.
For operation with bipolar supplies, the IGBT is turned off with a negative voltage on its gate with respect to its
emitter. This prevents the IGBT from unintentionally turning on because of current induced from its collector to its
gate due to Miller effect. In this condition it is not necessary to connect CLAMP output of the gate driver to the
IGBT gate. Typical values of VCC2 and VEE2 for bipolar operation are 15-V and -8-V with respect to GND2.
For operation with unipolar supply, typically, VCC2 is connected to 15-V with respect to GND2, and VEE2 is
connected to GND2. In this use case, the IGBT can turn on due to additional charge from IGBT Miller
capacitance caused by a high voltage slew rate transition on the IGBT collector. To prevent IGBT to turn on, the
CLAMP pin is connected to IGBT gate and Miller current is sinked through a low impedance CLAMP transistor.
Miller CLAMP is designed for Miller current up to 2-A. When the IGBT is turned-off and the gate voltage
transitions below 2-V the CLAMP current output is activated.
9.3.2 Active Output Pulldown
The Active output pulldown feature ensures that the IGBT gate OUTH/L is clamped to VEE2 to ensure safe IGBT
off-state, when the output side is not connected to the power supply.
9.3.3 Undervoltage Lockout (UVLO) With Ready (RDY) Pin Indication Output
Undervoltage Lockout (UVLO) ensures correct switching of IGBT. The IGBT is turned-off, if the supply VCC1
drops below VIT-(UVLO1), irrespective of IN+, IN– and RST input till VCC1 goes above VIT+(UVLO1)
.
In similar manner, the IGBT is turned-off, if the supply VCC2 drops below VIT-(UVLO2), irrespective of IN+, IN– and
RST input till VCC2 goes above VIT+(UVLO2)
.
Ready (RDY) pin indicates status of input and output side Undervoltage Lockout (UVLO) internal protection
feature. If either side of device have insufficient supply (VCC1 or VCC2), the RDY pin output goes low; otherwise,
RDY pin output is high. RDY pin also serves as an indication to the micro-controller that the device is ready for
operation.
9.3.4 Soft Turnoff, Fault (FLT) and Reset (RST)
During IGBT overcurrent condition, a mute logic initiates a soft-turn-off procedure which disables, OUTH, and
pulls OUTL to low over a time span of 2 μs. When desaturation is active, a fault signal is sent across the isolation
barrier pulling the FLT output at the input side low and blocking the isolator input. mute logic is activated through
the soft-turn-off period. The FLT output condition is latched and can be reset only after RDY goes high, through a
active-low pulse at the RST input. RST has an internal filter to reject noise and glitches. By asserting RST for at-
least the specified minimum duration (800 ns), device input logic can be enabled or disabled.
9.3.5 Short Circuit Clamp
Under short circuit events it is possible that currents are induced back into the gate-driver OUTH/L and CLAMP
pins due to parasitic Miller capacitance between the IGBT collector and gate terminals. Internal protection diodes
on OUTH/L and CLAMP help to sink these currents while clamping the voltages on these pins to values slightly
higher than the output side supply.
24
Copyright © 2016, Texas Instruments Incorporated
ISO5852S-EP
www.ti.com.cn
ZHCSFX1 –DECEMBER 2016
9.4 Device Functional Modes
In ISO5852S-EP OUTH/L to follow IN+ in normal functional mode, FLT pin must be in the high state. Table 1 lists
the device functions.
Table 1. Function Table(1)
VCC1
PU
PD
PU
PU
PU
PU
PU
VCC2
PD
IN+
X
IN–
X
RST
X
RDY
Low
Low
High
Low
High
High
High
OUTH/L
Low
PU
X
X
X
Low
PU
X
X
Low
X
Low
Open
PU
X
X
Low
Low
X
X
X
Low
PU
High
Low
X
Low
PU
High
High
High
(1) PU: Power Up (VCC1 ≥ 2.25 V, VCC2 ≥ 13 V), PD: Power Down (VCC1 ≤ 1.7 V, VCC2 ≤ 9.5 V), X: Irrelevant
Copyright © 2016, Texas Instruments Incorporated
25
ISO5852S-EP
ZHCSFX1 –DECEMBER 2016
www.ti.com.cn
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The ISO5852S-EP device is an isolated gate driver for power semiconductor devices such as IGBTs and
MOSFETs. It is intended for use in applications such as motor control, industrial inverters and switched mode
power supplies. In these applications, sophisticated PWM control signals are required to turn the power devices
on and off, which at the system level eventually may determine, for example, the speed, position, and torque of
the motor or the output voltage, frequency and phase of the inverter. These control signals are usually the
outputs of a microcontroller, and are at low voltage levels such as 2.5 V, 3.3 V or 5 V. The gate controls required
by the MOSFETs and IGBTs, however, are in the range of 30-V (using unipolar output supply) to 15-V (using
bipolar output supply), and require high-current capability to drive the large capacitive loads offered by those
power transistors. The gate drive must also be applied with reference to the emitter of the IGBT (source for
MOSFET), and by construction, the emitter node in a gate-drive system swings between 0 to the DC-bus voltage,
which can be several 100s of volts in magnitude.
The ISO5852S-EP device is therefore used to level shift the incoming 2.5-V, 3.3-V, and 5-V control signals from
the microcontroller to the 30-V (using unipolar output supply) to 15-V (using bipolar output supply) drive required
by the power transistors while ensuring high-voltage isolation between the driver side and the microcontroller
side.
10.2 Typical Applications
Figure 48 shows the typical application of a three-phase inverter using six ISO5852S-EP isolated gate drivers.
Three-phase inverters are used for variable-frequency drives to control the operating speed of AC motors and for
high-power applications such as high-voltage DC (HVDC) power transmission.
The basic three-phase inverter consists of three single-phase inverter switches each comprising two ISO5852S-
EP devices that are connected to one of the three load terminals. The operation of the three switches is
coordinated so that one switch operates at each 60 degree point of the fundamental output waveform, therefore
creating a six-step line-to-line output waveform. In this type of applications, carrier-based PWM techniques are
applied to retain waveform envelope and cancel harmonics.
26
Copyright © 2016, Texas Instruments Incorporated
ISO5852S-EP
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ZHCSFX1 –DECEMBER 2016
Typical Applications (continued)
ISO
ISO
ISO
ISO
5852S
5852S
5852S
5852S
1
2
3
4
5
6
PWM
µC
3-Phase
Input
M
FAULT
ISO
ISO
5852S
5852S
Figure 48. Typical Motor-Drive Application
10.2.1 Design Requirements
Unlike optocoupler-based gate drivers which required external current drivers and biasing circuitry to provide the
input control signals, the input control to the ISO5852S-EP device is CMOS and can be directly driven by the
microcontroller. Other design requirements include decoupling capacitors on the input and output supplies, a
pullup resistor on the common-drain FLT output signal, and a high-voltage protection diode between the IGBT
collector and the DESAT input. Additional details are explained in the subsequent sections. Table 2 lists the
allowed range for input and output supply voltage, and the typical current output available from the gate-driver.
Table 2. Design Parameters
PARAMETER
Input supply voltage
VALUE
2.25 V to 5.5 V
15 V to 30 V
15 V to 30 V
0 V to 15 V
2.5 A
Unipolar output-supply voltage (VCC2 – GND2 = VCC2 – VEE2
)
Bipolar output-supply voltage (VCC2 – VEE2
)
Bipolar output-supply voltage (GND2 – VEE2
Output current
)
10.2.2 Detailed Design Procedure
10.2.2.1 Recommended ISO5852S-EP Application Circuit
The ISO5852S-EP device has both, inverting and noninverting gate-control inputs, an active-low reset input, and
an open-drain fault output suitable for wired-OR applications. The recommended application circuit in Figure 49
shows a typical gate-driver implementation with unipolar output supply. Figure 50 shows a typical gate-driver
implementation with bipolar output supply using the ISO5852S-EP device.
Copyright © 2016, Texas Instruments Incorporated
27
ISO5852S-EP
ZHCSFX1 –DECEMBER 2016
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A 0.1-μF bypass capacitor, recommended at the VCC1 input supply pin, and 1-μF bypass capacitor,
recommended at the VCC2 output supply pin, provide the large transient currents required during a switching
transition to ensure reliable operation. The 220-pF blanking capacitor disables DESAT detection during the off-to-
on transition of the power device. The DESAT diode (DDST) and the 1-kΩ series resistor on the DESAT pin are
external protection components. The RG gate resistor limits the gate-charge current and indirectly controls the
rise and fall times of the IGBT collector voltage. The open-drain FLT output and RDY output have a passive 10-
kΩ pullup resistor. In this application, the IGBT gate driver is disabled when a fault is detected and does not
resume switching until the microcontroller applies a reset signal.
10R
10R
ISO5852S
ISO5852S
15
5
15
5
VCC1
GND1
IN+
VCC2
GND2
VEE2
VCC1
GND1
IN+
VCC2
GND2
VEE2
+
+
+
+
2.25 to
5 V
2.25 to
5 V
15 V
15 V
15 V
0.1 µF
0.1 µF
0.1 µF
0.1 µF
œ
œ
œ
œ
3
3
9
16
9
16
+
0.1 µF
œ
10
10
1
8
1
8
+
+
DDST
DDST
1 kꢀ
1 kꢀ
10 kꢀ
10 kꢀ
10 kꢀ
10 kꢀ
11
12
13
14
2
7
6
4
11
12
13
14
2
7
6
4
œ
œ
INœ
DESAT
CLAMP
OUTL
INœ
DESAT
CLAMP
OUTL
RDY
FLT
RST
RDY
FLT
RST
RGL
RGH
RGL
RGH
OUTH
OUTH
220 pF
220 pF
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
Figure 49. Unipolar Output Supply
10.2.2.2 FLT and RDY Pin Circuitry
Figure 50. Bipolar Output Supply
A is 50-kΩ pullup resistor exists internally on FLT and RDY pins. The FLT and RDY pins are an open-drain
output. A 10-kΩ pullup resistor can be used to make it faster rise and to provide logic high when FLT and RDY is
inactive, as shown in Figure 51.
Fast common-mode transients can inject noise and glitches on FLT and RDY pins because of parasitic coupling.
The injection of noise and glitches is dependent on board layout. If required, additional capacitance (100 pF to
300 pF) can be included on the FLT and RDY pins.
10R
ISO5852S
15
VCC1
+
2.25 to 5 V
0.1 µF
œ
9
GND1
16
10 kꢀ
10 kꢀ
12
13
14
RDY
FLT
µC
RST
10
11
IN+
INœ
Copyright © 2016, Texas Instruments Incorporated
Figure 51. FLT and RDY Pin Circuitry for High CMTI
28
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ISO5852S-EP
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ZHCSFX1 –DECEMBER 2016
10.2.2.3 Driving the Control Inputs
The amount of common-mode transient immunity (CMTI) can be curtailed by the capacitive coupling from the
high-voltage output circuit to the low-voltage input side of the ISO5852S-EP device. For maximum CMTI
performance, the digital control inputs, IN+ and IN–, must be actively driven by standard CMOS, push-pull drive
circuits. This type of low-impedance signal source provides active drive signals that prevent unwanted switching
of the ISO5852S-EP output under extreme common-mode transient conditions. Passive drive circuits, such as
open-drain configurations using pullup resistors, must be avoided. A 20-ns glitch filter exists that can filter a glitch
up to 20 ns on IN+ or IN–.
10.2.2.4 Local Shutdown and Reset
In applications with local shutdown and reset, the FLT output of each gate driver is polled separately, and the
individual reset lines are independently asserted low to reset the motor controller after a fault condition.
10R
10R
ISO 5852S - EP
VCC1
ISO 5852S - EP
VCC1
15
15
0.1 µF
0.1 µF
2.25 V - 5.5 V
2.25 V - 5.5 V
9, 16
9, 16
GND1
GND1
10 kꢀ
10 kꢀ
10 kꢀ
10 kꢀ
12
13
12
13
RDY
FLT
RDY
FLT
µC
µC
14
10
14
10
RST
IN+
RST
IN+
11
11
INœ
INœ
Copyright © 2016, Texas Instruments Incorporated
Figure 52. Local Shutdown and Reset for Noninverting (left) and Inverting Input Configuration (right)
Copyright © 2016, Texas Instruments Incorporated
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ISO5852S-EP
ZHCSFX1 –DECEMBER 2016
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10.2.2.5 Global-Shutdown and Reset
When configured for inverting operation, the ISO5852S-EP device can be configured to shutdown automatically
in the event of a fault condition by tying the FLT output to IN+. For high reliability drives, the open drain FLT
outputs of multiple ISO5852S-EP devices can be wired together forming a single, common fault bus for
interfacing directly to the microcontroller. When any of the six gate drivers of a three-phase inverter detects a
fault, the active-low FLT output disables all six gate drivers simultaneously.
10R
ISO5852S
15
VCC1
+
2.25 to 5 V
0.1 µF
œ
9
GND1
16
10 kꢀ
10 kꢀ
12
13
14
RDY
FLT
µC
RST
10
11
IN+
INœ
To other
RST pins
To other
FLT pins
Copyright © 2016, Texas Instruments Incorporated
Figure 53. Global Shutdown With Inverting Input Configuration
30
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ISO5852S-EP
www.ti.com.cn
ZHCSFX1 –DECEMBER 2016
10.2.2.6 Auto-Reset
In this case, the gate control signal at IN+ is also applied to the RST input to reset the fault latch every switching
cycle. Incorrect RST makes output go low. A fault condition, however, the gate driver remains in the latched fault
state until the gate control signal changes to the gate-low state and resets the fault latch.
If the gate control signal is a continuous PWM signal, the fault latch is always reset before IN+ goes high again.
This configuration protects the IGBT on a cycle-by-cycle basis and automatically resets before the next on cycle.
10R
10R
ISO 5852S - EP
VCC1
ISO 5852S - EP
VCC1
15
15
2.25 V- 5.5 V
0.1 µF
0.1 µF
2.25 V- 5.5 V
9, 16
9, 16
GND1
GND1
10k
10k
10k
10k
12
13
12
13
RDY
FLT
RDY
FLT
µC
µC
14
10
14
10
RST
IN +
IN -
RST
IN +
IN -
11
11
Copyright © 2016, Texas Instruments Incorporated
Figure 54. Auto Reset for Noninverting and Inverting Input Configuration
Copyright © 2016, Texas Instruments Incorporated
31
ISO5852S-EP
ZHCSFX1 –DECEMBER 2016
www.ti.com.cn
10.2.2.7 DESAT Pin Protection
Switching inductive loads causes large, instantaneous forward-voltage transients across the freewheeling diodes
of the IGBTs. These transients result in large negative-voltage spikes on the DESAT pin which draw substantial
current out of the device. To limit this current below damaging levels, a 100-Ω to 1-kΩ resistor is connected in
series with the DESAT diode.
Further protection is possible through an optional Schottky diode, whose low-forward voltage assures clamping of
the DESAT input to GND2 potential at low-voltage levels.
ISO5852S
5
3
VCC2
GND2
VEE2
+
15 V
15 V
1 µF
œ
+
0.1 µF
œ
1
8
DDST
RS
2
7
6
DESAT
CLAMP
OUTL
œ
RGL
RGH
VFW-Inst
4
+
OUTH
VFW
220 pF
Copyright © 2016, Texas Instruments Incorporated
Figure 55. DESAT Pin Protection With Series Resistor and Schottky Diode
32
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ISO5852S-EP
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ZHCSFX1 –DECEMBER 2016
10.2.2.8 DESAT Diode and DESAT Threshold
The function of the DESAT diode is to conduct forward current, allowing sensing of the saturated collector-to-
emitter voltage of the IGBT, V(DESAT), (when the IGBT is on), and to block high voltages (when the IGBT is off).
During the short transition time when the IGBT is switching, a commonly high dVCE/dt voltage ramp rate occurs
across the IGBT. This ramp rate results in a charging current I(CHARGE) = C(D-DESAT) × dVCE/dt, charging the
blanking capacitor. C(D-DESAT) is the diode capacitance at DESAT.
To minimize this current and avoid false DESAT triggering, fast switching diodes with low capacitance are
recommended. As the diode capacitance builds a voltage divider with the blanking capacitor, large collector
voltage transients appear at DESAT attenuated by the ratio of 1+ C(BLANK) / C(D-DESAT)
.
Because the sum of the DESAT diode forward-voltage and the IGBT collector-emitter voltage make up the
voltage at the DESAT-pin, VF + VCE = V(DESAT), the VCE level, which triggers a fault condition, can be modified by
adding multiple DESAT diodes in series: VCE-FAULT(TH) = 9 V – n × VF (where n is the number of DESAT diodes).
When using two diodes instead of one, diodes with half the required maximum reverse-voltage rating can be
selected.
10.2.2.9 Determining the Maximum Available, Dynamic Output Power, POD-max
The ISO5852S-EP maximum-allowed total power consumption of PD = 251 mW consists of the total input power,
PID, the total output power, POD, and the output power under load, POL
:
PD = PID + POD + POL
(1)
(2)
(3)
(4)
With:
PID = VCC1-max × ICC1-max = 5.5 V × 4.5 mA = 24.75 mW
and:
POD = (VCC2 – VEE2) × ICC2-max = (15 V – [–8 V]) × 6 mA = 138 mW
then:
POL = PD – PID – POD = 251 mW – 24.75 mW – 138 mW = 88.25 mW
In comparison to POL, the actual dynamic output power under worst case condition, POL-WC, depends on a variety
of parameters:
æ
ç
è
ö
÷
ø
ron-max
roff-max
POL-WC = 0.5 ´ f
´ QG
´
V
- VEE2
´
+
(
)
INP
CC2
ron-max + RG
roff-max + RG
where
•
•
•
•
•
•
•
fINP = signal frequency at the control input IN+
QG = power device gate charge
VCC2 = positive output supply with respect to GND2
VEE2 = negative output supply with respect to GND2
ron-max = worst case output resistance in the on-state: 4 Ω
roff-max = worst case output resistance in the off-state: 2.5 Ω
RG = gate resistor
(5)
When RG is determined, Equation 5 is to be used to verify whether POL-WC < POL. Figure 56 shows a simplified
output stage model for calculating POL-WC
.
Copyright © 2016, Texas Instruments Incorporated
33
ISO5852S-EP
ZHCSFX1 –DECEMBER 2016
www.ti.com.cn
ISO5852S
VCC2
+
œ
Ron-max
15 V
RG
OUTH/L
QG
Roff-max
+
8 V
œ
VEE2
Copyright © 2016, Texas Instruments Incorporated
Figure 56. Simplified Output Model for Calculating POL-WC
10.2.2.10 Example
This examples considers an IGBT drive with the following parameters:
•
•
•
•
•
ION-PK = 2 A
QG = 650 nC
fINP = 20 kHz
VCC2 = 15 V
VEE2 = –8 V
Applying the value of the gate resistor RG = 10 Ω.
Then, calculating the worst-case output-power consumption as a function of RG, using Equation 5 ron-max = worst
case output resistance in the on-state: 4 Ω, roff-max = worst case output resistance in the off-state: 2.5 Ω, RG
=
gate resistor yields
4 Ω
2.5 Ω
æ
ö
POL-WC = 0.5´20 kHz´650 nC´ 15 V -( -8 V) ´
+
4 Ω + 10 Ω 2.5 Ω + 10 Ω
= 72.61 mW
(
)
ç
è
÷
ø
(6)
Because POL-WC = 72.61 mW is less than the calculated maximum of POL = 88.25 mW, the resistor value of RG =
10 Ω is suitable for this application.
34
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ISO5852S-EP
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ZHCSFX1 –DECEMBER 2016
10.2.2.11 Higher Output Current Using an External Current Buffer
To increase the IGBT gate drive current, a non-inverting current buffer (such as the npn/pnp buffer shown in
Figure 57) can be used. Inverting types are not compatible with the desaturation fault protection circuitry and
must be avoided. The MJD44H11/MJD45H11 pair is appropriate for currents up to 8 A, the D44VH10/ D45VH10
pair for up to 15 A maximum.
ISO5852S
5
3
VCC2
GND2
VEE2
+
15 V
15 V
1 µF
œ
+
0.1 µF
œ
1
8
DDST
1 kꢀ
2
7
6
DESAT
CLAMP
OUTL
RG
10 ꢀ
10 ꢀ
4
OUTH
220 pF
Copyright © 2016, Texas Instruments Incorporated
Figure 57. Current Buffer for Increased Drive Current
10.2.3 Application Curves
5 µs/Div
5 µs/Div
CL = 1 nF
VCC2 – GND2 = 15 V
(VCC2 – VEE2 = 23 V)
RGH = 10 Ω
RGL = 10 Ω
CL = 1 nF
RGH = 10 Ω
RGL = 10 Ω
GND2 - VEE2 = 8 V
VCC2 – VEE2 = VCC2 - GND2 = 20 V
Figure 58. Normal Operation - Bipolar Supply
Figure 59. Normal Operation - Unipolar Supply
Copyright © 2016, Texas Instruments Incorporated
35
ISO5852S-EP
ZHCSFX1 –DECEMBER 2016
www.ti.com.cn
11 Power Supply Recommendations
To help ensure reliable operation at all data rates and supply voltages, a 0.1-μF bypass capacitor is
recommended at the VCC1 input supply pin and a 1-μF bypass capacitor is recommended at the VCC2output
supply pin. The capacitors should be placed as close to the supply pins as possible. The recommended
placement of the capacitors is 2 mm (maximum) from the input and output power supply pins (VCC1 and VCC2).
12 Layout
12.1 Layout Guidelines
minimum of four layers is required to accomplish a low EMI PCB design (see Figure 60). Layer stacking should
be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency
signal layer.
•
Routing the high-current or sensitive traces on the top layer avoids the use of vias (and the introduction of
their inductances) and allows for clean interconnects between the gate driver and the microcontroller and
power transistors. Gate driver control input, Gate driver output OUTH/L and DESAT should be routed in the
top layer.
•
•
Placing a solid ground plane next to the sensitive signal layer provides an excellent low-inductance path for
the return current flow. On the driver side, use GND2 as the ground plane.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/inch2. On the gate-driver VEE2 and VCC2 can be used as power planes. They can share
the same layer on the PCB as long as they are not connected together.
•
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
For more detailed layout recommendations, including placement of capacitors, impact of vias, reference planes,
routing, and other details, see the Digital Isolator Design Guide (SLLA284).
12.2 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and
stiffness, and the self-extinguishing flammability-characteristics.
12.3 Layout Example
High-speed traces
10 mils
Ground plane
Yeep this
FR-4
0 ~ 4.5
space free
from planes,
traces, pads,
and vias
40 mils
10 mils
r
Power plane
Low-speed traces
Figure 60. Recommended Layer Stack
36
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ISO5852S-EP
www.ti.com.cn
ZHCSFX1 –DECEMBER 2016
13 器件和文档支持
13.1 文档支持
13.1.1 相关文档ꢀ
相关文档如下:
•
•
•
数字隔离器设计指南
《ISO5852S 评估模块 (EVM) 用户指南》
隔离相关术语
13.2 接收文档更新通知
要接收文档更新通知,请访问 www.ti.com.cn 您器件对应的产品文件夹。点击右上角的提醒我 (Alert me) 注册后,
即可每周定期收到已更改的产品信息。有关更改的详细信息,请查阅已修订文档的修订历史记录。
13.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本,请查阅左侧的导航栏。
版权 © 2016, Texas Instruments Incorporated
37
重要声明
德州仪器 (TI) 公司有权按照最新发布的 JESD46 对其半导体产品和服务进行纠正、增强、改进和其他修改,并不再按最新发布的 JESD48 提
供任何产品和服务。买方在下订单前应获取最新的相关信息,并验证这些信息是否完整且是最新的。
TI 公布的半导体产品销售条款 (http://www.ti.com/sc/docs/stdterms.htm) 适用于 TI 已认证和批准上市的已封装集成电路产品的销售。另有其
他条款可能适用于其他类型 TI 产品及服务的使用或销售。
复制 TI 数据表上 TI 信息的重要部分时,不得变更该等信息,且必须随附所有相关保证、条件、限制和通知,否则不得复制。TI 对该等复制文
件不承担任何责任。第三方信息可能受到其它限制条件的制约。在转售 TI 产品或服务时,如果存在对产品或服务参数的虚假陈述,则会失去
相关 TI 产品或服务的明示或暗示保证,且构成不公平的、欺诈性商业行为。TI 对此类虚假陈述不承担任何责任。
买方和在系统中整合 TI 产品的其他开发人员(总称“设计人员”)理解并同意,设计人员在设计应用时应自行实施独立的分析、评价和判断,且
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人员就自己设计的 应用声明,其具备制订和实施下列保障措施所需的一切必要专业知识,能够 (1) 预见故障的危险后果,(2) 监视故障及其后
果,以及 (3) 降低可能导致危险的故障几率并采取适当措施。设计人员同意,在使用或分发包含 TI 产品的任何 应用前, 将彻底测试该等 应用
和 该等应用中所用 TI 产品的 功能。
TI 提供技术、应用或其他设计建议、质量特点、可靠性数据或其他服务或信息,包括但不限于与评估模块有关的参考设计和材料(总称“TI 资
源”),旨在帮助设计人员开发整合了 TI 产品的 应用, 如果设计人员(个人,或如果是代表公司,则为设计人员的公司)以任何方式下载、
访问或使用任何特定的 TI 资源,即表示其同意仅为该等目标,按照本通知的条款使用任何特定 TI 资源。
TI 所提供的 TI 资源,并未扩大或以其他方式修改 TI 对 TI 产品的公开适用的质保及质保免责声明;也未导致 TI 承担任何额外的义务或责任。
TI 有权对其 TI 资源进行纠正、增强、改进和其他修改。除特定 TI 资源的公开文档中明确列出的测试外,TI 未进行任何其他测试。
设计人员只有在开发包含该等 TI 资源所列 TI 产品的 应用时, 才被授权使用、复制和修改任何相关单项 TI 资源。但并未依据禁止反言原则或
其他法理授予您任何TI知识产权的任何其他明示或默示的许可,也未授予您 TI 或第三方的任何技术或知识产权的许可,该等产权包括但不限
于任何专利权、版权、屏蔽作品权或与使用TI产品或服务的任何整合、机器制作、流程相关的其他知识产权。涉及或参考了第三方产品或服务
的信息不构成使用此类产品或服务的许可或与其相关的保证或认可。使用 TI 资源可能需要您向第三方获得对该等第三方专利或其他知识产权
的许可。
TI 资源系“按原样”提供。TI 兹免除对资源及其使用作出所有其他明确或默认的保证或陈述,包括但不限于对准确性或完整性、产权保证、无屡
发故障保证,以及适销性、适合特定用途和不侵犯任何第三方知识产权的任何默认保证。TI 不负责任何申索,包括但不限于因组合产品所致或
与之有关的申索,也不为或对设计人员进行辩护或赔偿,即使该等产品组合已列于 TI 资源或其他地方。对因 TI 资源或其使用引起或与之有关
的任何实际的、直接的、特殊的、附带的、间接的、惩罚性的、偶发的、从属或惩戒性损害赔偿,不管 TI 是否获悉可能会产生上述损害赔
偿,TI 概不负责。
除 TI 已明确指出特定产品已达到特定行业标准(例如 ISO/TS 16949 和 ISO 26262)的要求外,TI 不对未达到任何该等行业标准要求而承担
任何责任。
如果 TI 明确宣称产品有助于功能安全或符合行业功能安全标准,则该等产品旨在帮助客户设计和创作自己的 符合 相关功能安全标准和要求的
应用。在应用内使用产品的行为本身不会 配有 任何安全特性。设计人员必须确保遵守适用于其应用的相关安全要求和 标准。设计人员不可将
任何 TI 产品用于关乎性命的医疗设备,除非已由各方获得授权的管理人员签署专门的合同对此类应用专门作出规定。关乎性命的医疗设备是
指出现故障会导致严重身体伤害或死亡的医疗设备(例如生命保障设备、心脏起搏器、心脏除颤器、人工心脏泵、神经刺激器以及植入设
备)。此类设备包括但不限于,美国食品药品监督管理局认定为 III 类设备的设备,以及在美国以外的其他国家或地区认定为同等类别设备的
所有医疗设备。
TI 可能明确指定某些产品具备某些特定资格(例如 Q100、军用级或增强型产品)。设计人员同意,其具备一切必要专业知识,可以为自己的
应用选择适合的 产品, 并且正确选择产品的风险由设计人员承担。设计人员单方面负责遵守与该等选择有关的所有法律或监管要求。
设计人员同意向 TI 及其代表全额赔偿因其不遵守本通知条款和条件而引起的任何损害、费用、损失和/或责任。IMPORTANT NOTICE
邮寄地址:上海市浦东新区世纪大道 1568 号中建大厦 32 楼,邮政编码:200122
Copyright © 2017 德州仪器半导体技术(上海)有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO5852SMDWREP
V62/16623-01XE
ACTIVE
ACTIVE
SOIC
SOIC
DW
DW
16
16
2000 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-55 to 125
-55 to 125
ISO5852SM
ISO5852SM
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
DW 16
7.5 x 10.3, 1.27 mm pitch
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016B
SOIC - 2.65 mm max height
S
C
A
L
E
1
.
5
0
0
SOIC
C
10.63
9.97
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
14X 1.27
16
1
2X
10.5
10.1
NOTE 3
8.89
8
9
0.51
0.31
16X
7.6
7.4
B
2.65 MAX
0.25
C A
B
NOTE 4
0.33
0.10
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 - 8
1.27
0.40
DETAIL A
TYPICAL
(1.4)
4221009/B 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (2)
1
16X (1.65)
SEE
DETAILS
SEE
DETAILS
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
R0.05 TYP
9
9
8
8
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
LAND PATTERN EXAMPLE
SCALE:4X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221009/B 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016B
SOIC - 2.65 mm max height
SOIC
SYMM
SYMM
16X (1.65)
16X (2)
1
1
16
16
16X (0.6)
16X (0.6)
SYMM
SYMM
14X (1.27)
14X (1.27)
8
9
8
9
R0.05 TYP
R0.05 TYP
(9.75)
(9.3)
HV / ISOLATION OPTION
8.1 mm CLEARANCE/CREEPAGE
IPC-7351 NOMINAL
7.3 mm CLEARANCE/CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4221009/B 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资
源,不保证其中不含任何瑕疵,且不做任何明示或暗示的担保,包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任:(1) 针对您的应用选择合适的TI 产品;(2) 设计、
验证并测试您的应用;(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更,恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源,也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等,TI对此概不负责,并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址:上海市浦东新区世纪大道 1568 号中建大厦 32 楼,邮政编码:200122
Copyright © 2020 德州仪器半导体技术(上海)有限公司
相关型号:
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