V62/19608-01XE_技术文档

TSB82AF15-EP

ZHCSS38 –JULY 2020

TSB82AF15-EP 基于PCI Express 的IEEE 1394b OHCI 主机控制器

1 特性

2 应用

• 基于PCI Express^™的1394b 开放式主机控制器接

口(OHCI) 链路层控制器

• 航空电子设备和国防

• 工厂自动化与控制

• 医疗

– TQFP 封装简化了电路板布线和电路板检查

– 独立链路层控制器可以灵活连接到1394b s400

或1394b s800 物理层控制器

3 说明

德州仪器 (TI) TSB82AF15-EP 是一款单功能 PCI

Express^™(PCIe) 至 PCI 本地总线转换桥接器，其中

PCI 总线接口在内部连接至 1394b 开放式主机控制器/

链路层控制器。正确配置 TSB82AF15-EP 后，该解决

方案可提供完整的PCIe 至1394 链路层控制器。

• 完全符合1394 OHCI 规范修订版1.1 和修订版1.2

草案

• 符合PCI Express^™(PCIe) 基础规范修订版1.1。

请参阅节11.1

• 完全支持IEEE 标准P1394b-2002、IEEE 标准

1394-1995 和IEEE 标准1394a-2000 的规定

• EEPROM 配置支持加载1394 结构的全局唯一ID

• 采用100MHz 差分PCI Express^™通用参考时钟

• 支持D1、D2、D3_hot

• 当PCI Express^™链路上的数据包活动处于空闲状

态（使用L0s 和L1 状态）时，活动状态链路电源

管理功能可实现省电

TSB82AF15-EP 可随时在每个方向上同时支持多达 4

个已发布写入事务、4 个未发布事务和 4 个待处理完成

事务。每个已发布写入数据队列和完成数据队列可存储

多达 8K 字节的数据。未发布数据队列可存储多达 128

字节的数据。

• 八个3.3V 多功能通用I/O (GPIO) 端子

• 支持国防、航空航天和医疗应用：

– 受控基线

器件信息⁽¹⁾

封装尺寸（标称值）

器件型号

封装

14.00mm ×

14.00mm

TSB82AF15-EP

100 引脚PZT

– 一个组装/测试厂和一个制造厂

– 延长产品生命周期和产品变更通知

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

PCI Express

Transmitter

PCI Express

Receiver

Power

Mgmt

GPIO

Configuration and

Memory Register

Serial

EEPROM

Clock

Generator

Reset

Controller

PCI Bus Interface

1394b OHCI

简化版方框图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SCPS271

TSB82AF15-EP

ZHCSS38 –JULY 2020

www.ti.com.cn

Table of Contents

10.3 Feature Description.................................................18

10.4 Device Functional Modes........................................30

10.5 Programming.......................................................... 32

10.6 Register Maps.........................................................33

11 Application and Implementation.............................. 166

11.1 Known exceptions to functional specification

(errata).......................................................................166

11.2 Application Information..........................................167

12 Power Supply Recommendations............................169

13 Layout.........................................................................170

13.1 Layout Guidelines................................................. 170

14 Device and Documentation Support........................171

14.1 Device Support..................................................... 171

14.2 Documentation Support........................................ 171

14.3 Receiving Notification of Documentation Updates171

14.4 支持资源................................................................171

14.5 Trademarks...........................................................171

14.6 静电放电警告........................................................ 172

14.7 术语表................................................................... 172

15 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

Pin Functions.................................................................... 3

6 Specifications.................................................................. 8

6.1 Absolute Maximum Ratings ....................................... 8

6.2 ESD Ratings .............................................................. 8

6.3 Recommended Operating Conditions ........................8

6.4 Thermal Information ...................................................8

6.5 PCIe Differential Transmitter Output Ranges .............9

6.6 PCIe Differential Receiver Input Ranges ..................11

6.7 PCIe Differential Reference Clock Input Ranges .....13

6.8 Electrical Characteristics Over Recommended

Operating Conditions (3.3-V I/O) ................................13

6.9 Switching Characteristics .........................................13

7 Operating Life Deration.................................................14

8 Typical Characteristics................................................. 15

9 Parameter Measurement Information..........................16

10 Detailed Description....................................................17

10.1 Overview.................................................................17

10.2 Functional Block Diagram.......................................17

Information.................................................................. 173

15.1 Mechanical Data................................................... 174

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

DATE

REVISION

NOTES

September 2020

*

Initial release.

2

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English Data Sheet: SCPS271

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5 Pin Configuration and Functions

The TSB82AF15-EP is packaged in a 100-pin PZT package.

REFCLK+

REFCLK-

VSSA

VDD_33

LPS

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

VSS

2

PERST

GRST

3

4

VDD_33

RSVD_VSS

RSVD

5

PINT

LINKON

LREQ

VSS

6

7

8

VSS

9

RSVD

PCLK

VDD_15

LCLK

VDD_33

CTL0

CTL1

VSS

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

RSVD

RSVD_VSS

VDD_15

REFCLK_SEL

SDA

SCL

VSS

D0

CLKREQ

RSVD

D1

D2

VDD_33

RSVD

VDD_15

D3

RSVD

D4

RSVD

D5

VDD_15

RSVD

VSS

D6

RSVD

Not to scale

图5-1. PZT Package 100-Pin QFP Top View

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

Reference clock positive. REFCLK+ and REFCLK- comprise the differential input pair for the

100-MHz system reference clock.

REFCLK+

1

DI

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Product Folder Links: TSB82AF15-EP

English Data Sheet: SCPS271

TSB82AF15-EP

ZHCSS38 –JULY 2020

www.ti.com.cn

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

Reference clock negative. REFCLK+ and REFCLK- comprise the differential input pair for the

100-MHz system reference clock.

REFCLK-

2

DI

VSSA

3

4

P

Analog ground.

VDD_33

3.3-V digital I/O power. Filter from VDDA_33 supply.

Link power status. This terminal must be connected to the LPS input terminal of the

connected PHY.

LPS

5

6

O

I

PHY interrupt. The connected PHY uses this signal to transfer status and interrupt information

serially to the LLC. This terminal must be connected to the PINT output of the connected PHY.

PINT

Link-on notification. LINKON is an input to the LLC from the connected PHY that is used to

provide notification that a link-on packet has been received or an event, such as a port

connection, has occurred. This I/O only has meaning when LPS is disabled. This includes the

D0 (uninitialized), D2, and D3 power states. If LINKON becomes active in the D0

(uninitialized), D2, or D3 power state, the TSB82AF15-EP device sets bit 15 (PME_STS) in

the power-management control and status register in the PCI configuration space at offset

48h. This terminal must be connected to the LKON output terminal of the connected PHY.

LINKON

LREQ

7

8

I/O

O

LLC request. The LLC uses this output to initiate a service request to the connected PHY. This

terminal must be connected to the LREQ input of the connected PHY.

VSS

9

P

I

Digital ground.

PCLK

10

11

12

13

PHY clock. This terminal must be connected to the PCLK output of the connected PHY.

1.5-V digital core power for the link. Filter from VDDA_15 supply.

LLC clock. This terminal must be connected to the LCLK input terminal of the connected PHY.

3.3-V digital I/O power. Filter from VDDA_33 supply.

VDD_15

LCLK

P

O

P

VDD_33

Control. CTL[1:0] are bidirectional control bus signals that are used to indicate the phase of

operation of the PHY link interface. Upon a reset of the interface, this bus is driven by the

PHY. When driven by the PHY, information on CTL[1:0] is synchronous to PCLK. When driven

by the link, information on CTL[1:0] is synchronous to LCLK. If not implemented, these

terminals should be left unconnected.

CTL0

14

I/O

Control. CTL[1:0] are bidirectional control bus signals that are used to indicate the phase of

operation of the PHY link interface. Upon a reset of the interface, this bus is driven by the

PHY. When driven by the PHY, information on CTL[1:0] is synchronous to PCLK. When driven

by the link, information on CTL[1:0] is synchronous to LCLK. If not implemented, these

terminals should be left unconnected.

CTL1

VSS

D0

15

16

17

I/O

P

Digital ground.

Data. D[7:0] comprise a bidirectional data bus that is used to carry 1394 packet data, packet

speed, and grant type information between the PHY and the link. Upon a reset of the

interface, this bus is driven by the PHY. When driven by the PHY, information on D[7:0] is

synchronous to PCLK. When driven by the link, information on D[7:0] is synchronous to LCLK.

If not implemented, these terminals should be left unconnected.

I/O

D1

18

19

20

21

22

23

24

25

26

27

I/O

P

D1

D2

VDD_15

D3

1.5-V digital core power for the link. Filter from VDDA_15 supply.

I/O

P

D3

D4

D5

VSS

D6

Digital ground.

I/O

P

D6

D7

VDD_33

3.3-V digital I/O power. Filter from VDDA_33 supply.

General-purpose I/O 0. This terminal functions as a GPIO controlled by bit 0 (GPIO0_DIR) in

the GPIO control register (See 节10.6.1.60). Note: This terminal has an internal active pullup

resistor.

GPIO0

28

I/O

4

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English Data Sheet: SCPS271

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ZHCSS38 –JULY 2020

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TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

General-purpose I/O 1. This terminal functions as a GPIO controlled by bit 1 (GPIO1_DIR) in

the GPIO control register (See 节10.6.1.60). Note: This terminal has an internal active pullup

resistor.

GPIO1

29

I/O

General-purpose I/O 2. This terminal functions as a GPIO controlled by bit 2 (GPIO2_DIR) in

the GPIO control register (See 节10.6.1.60). Note: This terminal has an internal active pullup

resistor.

GPIO2

VSS

30

31

32

I/O

P

Digital ground.

General-purpose I/O 3. This terminal functions as a GPIO controlled by bit 3 (GPIO3_DIR) in

the GPIO control register (See 节10.6.1.60). Note: This terminal has an internal active pullup

resistor.

GPIO3

I/O

General-purpose I/O 4. This terminal functions as a GPIO controlled by bit 4 (GPIO4_DIR) in

the GPIO control register (See 节10.6.1.60). Note: This terminal has an internal active pullup

resistor.

GPIO4

GPIO5

33

34

I/O

General-purpose I/O 5. This terminal functions as a GPIO controlled by bit 5 (GPIO5_DIR) in

the GPIO control register (See 节10.6.1.60). Note: This terminal has an internal active pullup

resistor.

General-purpose I/O 6. This terminal functions as a GPIO controlled by bit 6 (GPIO6_DIR) in

the GPIO control register (See 节10.6.1.60). Note: This terminal has an internal active pullup

resistor.

GPIO6

35

36

37

38

39

I/O

P

VDD_15

GPIO7

1.5-V digital core power for the link. Filter from VDDA_15 supply.

General-purpose I/O 7. This terminal functions as a GPIO controlled by bit 7 (GPIO7_DIR) in

the GPIO control register (See 节10.6.1.60). Note: This terminal has an internal active pullup

resistor.

I/O

P

VDD_15

OHCI_PME#

1.5-V digital core power for the link. Filter from VDDA_15 supply.

OHCI power-management event. This is an optional signal that can be used by a device to

request a change in the device or system power state. This signal must be enabled by

software.

O

VSS

40

41

P

Digital ground.

Cycle out. This terminal provides an 8-kHz cycle timer synchronization signal. If not

implemented, this terminal should be left unconnected.

CYCLEOUT

O

RSVD_VSS

RSVD

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

I

Reserved pin, connect to VSS.

O

P

Reserved pin, leave unconnected.

3.3-V digital I/O power. Filter from VDDA_33 supply.

Reserved pin, leave unconnected.

Digital ground.

VDD_33

RSVD

O

P

RSVD

VSS

RSVD

O

P

Reserved pin, leave unconnected.

1.5-V digital core power for the link. Filter from VDDA_15 supply.

Reserved pin, leave unconnected.

3.3-V digital I/O power. Filter from VDDA_33 supply.

Reserved pin, leave unconnected.

RSVD

VDD_15

RSVD

O

P

RSVD

VDD_33

RSVD

O

Clock request. This terminal is used to support the clock request protocol. Note: CLKREQ is

an open-drain output buffer. An external pullup resistor is required, even if CLKREQ

functionality is unused.

CLKREQ

59

O

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English Data Sheet: SCPS271

TSB82AF15-EP

ZHCSS38 –JULY 2020

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NAME

TYPE⁽¹⁾

DESCRIPTION

NO.

VSS

60

P

Digital ground.

Serial-bus clock. This signal is used as a serial bus clock when a pullup is detected on SDA or

when the SBDETECT bit is set in the serial bus control and status register. Note: This terminal

has an internal active pullup resistor.

SCL

61

62

63

I/O

I

Serial-bus data. This signal is used as serial bus data when a pullup is detected on SDA or

when the SBDETECT bit is set in the serial bus control and status register. Note: In serial-bus

mode, an external pullup resistor is required to prevent the SDA signal from floating.

SDA

Reference clock select. This terminal selects the reference clock input. 0 = 100-MHz

differential common reference clock used. REFCLK_SEL must be driven logic low to enable

100Mhz differential clock. 125Mhz single ended clocking is not supported.

REFCLK_SEL

VDD_15

RSVD_VSS

RSVD

64

65

66

67

68

69

70

71

72

P

I

1.5-V digital core power for the link. Filter from VDDA_15 supply.

Reserved Pin, connect to VSS.

O

P

O

I

Reserved pin, leave unconnected.

Digital ground.

RSVD

VSS

RSVD

Reserved pin, leave unconnected.

Reserved Pin, connect to VSS.

RSVD_VSS

VDD_33

I

Reserved Pin, connect to VSS.

P

3.3-V digital I/O power. Filter from VDDA_33 supply.

Global power reset. This reset brings all of the TSB82AF15-EP internal link registers to their

default states. This should be a one-time power-on reset. This terminal has hysteresis and an

integrated pullup resistor.

GRST

73

I

PCI Express reset. PERST identifies when the system power is stable and generates an

internal power-on reset. Note: The PERST input buffer has hysteresis.

PERST

74

75

76

I

VSS

P

Digital ground.

Internal 1.5-V main power output for external bypass capacitor filtering. Caution: Do not use

this terminal to supply external power to other devices.

VDD_15_COMB

Internal 3.3-V IO power output for external bypass capacitor filtering. Caution: Do not use this

terminal to supply external power to other devices.

VDD_33_COMBIO

77

P

VSSA

78

79

P

Analog ground.

REF0_PCIE

I/O

External reference resistor + and –terminals for setting TX driver current. An external

resistance of 14.532kΩis connected between REF0_PCIE and REF1_PCIE terminals. To

eliminate the need for a custom resistor, two series resistors are recommended: a 14.3kΩ,

1% resistor and a 232Ω, 1% resistor.

REF1_PCIE

80

I/O

VSS

81

82

83

84

P

Digital ground.

This terminal is connected to VSS through a 10kΩpulldown resistor. The TSB82AF15-EP

does not support auxiliary power.

VDD_33_AUX

VDDA_33

3.3-V digital I/O power for the link. Filter from VDD_33 supply.

Internal 3.3-V main power output for external bypass capacitor filtering. Caution: Do not use

this terminal to supply external power to other devices.

VDD_33_COMB

VDDA_15

VSSA_PCIE

85

86

87

P

1.5-V analog power for the link. Filter from VDD_15 supply.

Analog ground for PCIe function.

High-speed transmit pair. TXP and TXN comprise the differential transmit pair for the single

PCIe lane.

TXP

TXN

88

89

DO

High-speed transmit pair. TXP and TXN comprise the differential transmit pair for the single

PCIe lane

VSSA_PCIE

VDD_15

90

91

92

P

Analog ground for PCIe function.

1.5-V digital core power for the link. Filter from VDDA_15 supply.

Digital ground for PCIe function.

VSS_PCIE

6

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TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

93

VDDA_15

VSSA

P

1.5-V analog power for the link. Filter from VDD_15 supply.

Analog ground.

94

VDDA_15

VSSA_PCIE

95

1.5-V analog power for the link. Filter from VDD_15 supply.

Analog ground for PCIe function.

96

High-speed receive pair. RXP and RXN comprise the differential receive pair for the single

PCIe lane.

RXP

RXN

97

98

DI

High-speed receive pair. RXP and RXN comprise the differential receive pair for the single

PCIe lane.

VSSA_PCIE

VDDA_33

99

P

Analog ground for PCIe function.

100

3.3-V digital I/O power for the link. Filter from VDD_33 supply.

(1)

•

Pin Type Legend:

– DI: Differential Input

– DO: Differential Output

– I: Input pin

– O: Output pin

– I/O: Pin can be Input or Output depending on configuration

– P: Power Supply or Ground

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English Data Sheet: SCPS271

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6 Specifications

6.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted)

MIN

–0.5

–0.6

–0.5

MAX

UNIT

V

V_{SUP_33}

V_{SUP_15}

Supply voltage range V_{DD_33}, V_{DDA_33}, V_{DD_33_COMB}

Supply voltage range V_{DD_15}, V_{DDA_15}, V_{DD_15_COMB}

PCIe (RX)

4.2

2.1

V

1.2

V_I

Input voltage range

PCIe REFCLK

1.2

V_{SUP_33}+ 0.5

V_{SUP_15}+ 0.5

V_{SUP_33}+ 0.5

20

V

Miscellaneous 3.3-V I/O

PCIe (TX)

V_O

Output voltage range

V

Miscellaneous 3.3-V I/O

Input clamp current (V_I< 0 or V_I> VDD)⁽¹⁾

Output clamp current (V_O< 0 or V_O> VDD)⁽²⁾

Absolute maximum junction temperature

Storage temperature range

mA

°C

20

T_J

150

T_stg

150

°C

–65

(1) Applies for external input and bidirectional buffers. V_I< 0 or V_I> V_{SUP_33}

(2) Applies for external output and bidirectional buffers. V_O< 0 or V_O> V_{SUP_33}

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±1000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

OPERATION

MIN

1.4

3

NOM

1.5

3.3

25

MAX

1.6

UNIT

V

V_{SUP_15}

V_{SUP_33}

T_A

Supply voltage

1.5 V

3.3 V

Supply voltage (I/O)

3.6

V

Operating Temperature (free-air)

Junction temperature

-40

110

125

°C

T_J

25

6.4 Thermal Information

TQFP (PZT)

100 PINS

46.5

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

°C/W

7.0

Junction-to-board thermal resistance

25.1

Junction-to-top characterization parameter

Junction-to-board characterization parameter

0.2

24.6

ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

English Data Sheet: SCPS271

8

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6.5 PCIe Differential Transmitter Output Ranges

TXP and TXN. At T_J= –40°C to 125°C, unless otherwise noted.

PARAMETER

MIN NOM

MAX UNIT

COMMENTS

Each UI is 400 ps 300 ppm. UI does not

account for SSC dictated variations.⁽¹⁾

UI

Unit interval

399.88

0.8

400 400.12

ps

V

Differential peak-to-peak

output voltage

(2)

V_TX-DIFFp-p

1.2

4.0

V_TX-DIFFp-p= 2*|V_TXP- V_TXN|

This is the ratio of the V_TX-DIFFp-pof the

second and following bits after a transition

divided by the V_TX-DIFFp-pof the first bit after a

transition. ⁽²⁾

Deemphasized

differential output voltage

(ratio)

V_TX-DE-RATIO

3.0

3.5

dB

UI

The maximum transmitter jitter can be

derived as T_{TXMAX- JITTER}= 1 –T_TX-EYE= 0.3

UI.^{(2) (3)}

TTX-EYE

Minimum TX eye width

0.75

Jitter is defined as the measurement variation

of the crossing points (V_TX-DIFFp-p= 0 V) in

relation to recovered TX UI. A recovered TX

UI is calculated over 3500 consecutive UIs of

sample data. Jitter is measured using all

edges of the 250 consecutive UIs in the

center of the 3500 UIs used for calculating

the TX UI.⁽²⁾

Maximum time between

jitter median and

maximum deviation from

the median

T_{TX-EYE-MEDIAN-to-MAX-JITTER}

0.15

UI

T_TX-RISE

T_TX-FALL

P/N TX output rise/fall

time

(2) (3)

0.125

RMS ac peak common-

mode output voltage

V_TX-CM-ACp= RMS(|V_TXP + V_TXN|/2 - V_TX-CM-

_DC) V_TX-CM-DC= DC(avg) of |V_TXP+ V_TXN|/2⁽²⁾

V_TX-CM-ACp

20 mV

Absolute delta of dc

common-mode voltage

during L0 and electrical

idle

|V_TX-CM-DC- V_{TX-CM-Idle-DC}| 100 mV V_TX-CM-DC

= DC_(avg)of |V_TXP+ V_TXN|/2 [during L0]

V_{TX-CM-Idle-DC}= DC_(avg)of |V_TXP+ V_TXN|/2

(during electrical idle)⁽²⁾

V_{TX-CM-DC-ACTIVE-IDLE-DELTA}

100 mV

Absolute delta of dc

common-mode voltage

between P and N

|V_TXP-CM-DC- V_TXN-CM-DC| ≤25 mV when

V_{TX-CM-DC-LINE-DELTA}

25 mV

20 mV

600 mV

V_TXP-CM-DC= DC_(avg)of |V_TXP

|

(2)

V_TXN-CM-DC= DC_(avg)of |V_TXN

|

Electrical idle differential

peak output voltage

V_{TX-IDLE-DIFFp}= |V_TXP-Idle- V_TXN-Idle| ≤20

V_{TX-IDLE-DIFFp}

mV⁽²⁾

Amount of voltage

change allowed during

receiver detection

The total amount of voltage change that a

transmitter can apply to sense whether a low

impedance receiver is present

V_{TX-RCV-DETECT}

TX dc common-mode

voltage

The allowed dc common-mode voltage under

any condition

V_TX-DC-CM

I_TX-SHORT

0

3.6

V

TX short-circuit current

limit

The total current the transmitter can provide

when shorted to its ground

90 mA

Minimum time a transmitter must be in

electrical Idle. Utilized by the receiver to start

looking for an electrical idle exit after

successfully receiving an electrical idle

ordered set.

Minimum time spent in

electrical idle

T_TX-IDLE-MIN

50

UI

After sending an electrical idle ordered set,

the transmitter must meet all electrical idle

specifications within this time. This is

considered a debounce time for the

transmitter to meet electrical idle after

transitioning from L0.

Maximum time to

transition to a valid

electrical idle after

sending an electrical idle

ordered set

T_{TX-IDLE-SET-to-IDLE}

20

UI

Maximum time to

transition to valid TX

specifications after

leaving an electrical idle

condition

Maximum time to meet all TX specifications

when transitioning from electrical idle to

sending differential data. This is considered a

debounce time for the TX to meet all TX

specifications after leaving electrical idle.

T_{TX-IDLE-to-DIFF-DATA}

UI

RL_TX-DIFF

Differential return loss

10

dB

Measured over 50 MHz to 1.25 GHz⁽⁴⁾

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TXP and TXN. At T_J= –40°C to 125°C, unless otherwise noted.

PARAMETER

MIN NOM

MAX UNIT

COMMENTS

Common-mode return

loss

RL_TX-CM

Z_TX-DIFF-DC

Z_TX-DC

6

80

40

75

dB

Measured over 50 MHz to 1.25 GHz⁽⁴⁾

DC differential TX

impedance

100

120

200

TX dc differential mode low impedance

Ω

Transmitter dc

impedance

Required TXP as well as TXN dc impedance

during all states

All transmitters are ac coupled and are

required on the PWB.

C_TX

AC coupling capacitor

nF

(1) No test load is necessarily associated with this value.

(2) Specified at the measurement point into a timing and voltage compliance test load and measured over any 250 consecutive TX UIs.

(3) A T_TX-EYE= 0.75 UI provides for a total sum of deterministic and random jitter budget of T_{TX-JITTER-MAX}= 0.25 UI for the transmitter

collected over any 250 consecutive TX UIs. The T_{TX-EYE-MEDIAN-to-MAX-JITTER}specification ensures a jitter distribution in which the

median and the maximum deviation from the median is less than half of the total TX jitter budget collected over any 250 consecutive

TX UIs. It must be noted that the median is not the same as the mean. The jitter median describes the point in time where the number

of jitter points on either side is approximately equal as opposed to the averaged time value.

(4) The transmitter input impedance results in a differential return loss greater than or equal to 10 dB and a common-mode return loss

greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid

input levels. The reference impedance for return loss measurements is 50 to ground for both the P and N lines. Note that the series

capacitors C_TXis optional for the return loss measurement.

English Data Sheet: SCPS271

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6.6 PCIe Differential Receiver Input Ranges

RXP and RXN. At T_J= –40°C to 125°C, unless otherwise noted.

PARAMETER

MIN NOM

MAX UNIT

COMMENTS

Each UI is 400 ps 300 ppm. UI does not

account for SSC dictated variations⁽¹⁾

UI

Unit interval

399.88

0.175

400 400.12 ps

Differential input peak-to-

peak voltage

V_RX-DIFFp-p

1.200

V

V_RX-DIFFp-p= 2*|V_RXP- V_RXN, |⁽²⁾

The maximum interconnect media and

transmitter jitter that can be tolerated by the

receiver is derived as T_{RX-MAX-JITTER}= 1 -

T_RX-EYE= 0.6 UI^{(2) (3)}

Minimum receiver eye

width

T_RX-EYE

0.4

UI

Jitter is defined as the measurement

variation of the crossing points (V_RX-DIFFp-p

= 0 V) in relation to recovered TX UI. A

recovered TX UI is calculated over 3500

consecutive UIs of sample data. Jitter is

measured using all edges of the 250

consecutive UIs in the center of the 3500

UIs used for calculating the TX UI.^{(2) (3)}

Maximum time between

jitter median and maximum

deviation from median

T_{RX-EYE-MEDIAN-to-MAX-JITTER}

0.3 UI

V_RX-CM-ACp= RMS(|V_RXP+ V_RXN|/2 - V_RX-

AC peak common-mode

input voltage

V_RX-CM-ACp

RL_RX-DIFF

RL_RX-CM

150 mV

)

CM-DC

V_RX-CM-DC= DC_(avg)of |V_RXP+ V_RXN|/2⁽²⁾

Measured over 50 MHz to 1.25 GHz with

the P and N lines biased at +300 mV and -

300 mV, respectively⁽⁴⁾

Differential return loss

10

6

dB

Measured over 50 MHz to 1.25 GHz with

the P and N lines biased at +300 mV and

300 mV, respectively⁽⁴⁾

Common-mode return loss

DC differential input

impedance

Z_RX-DIFF-DC

Z_RX-DC

80

40

100

50

120

RX dc differential mode impedance⁽⁴⁾

Ω

Required RXP as well as RXN dc

impedance (50 Ω 20% tolerance)^{(2) (5)}

DC input impedance

60

Ω

Required RXP as well as RXN dc

impedance when the receiver terminations

do not have power⁽⁶⁾

Powered down dc input

impedance

Z_{RX-HIGH-IMP-D}

200

65

kΩ

V_{RX-IDLE-DET-DIFFp-p}= 2*|V_RXP- V_RXN

measured at the receiver package

terminals

|

Electrical idle detect

threshold

V_{RX-IDLE-DET-DIFFp-p}

175 mV

10 ms

An unexpected electrical idle

(V_RX-DIFFp-p< V_{RX-IDLE-DET-DIFFp-p}) must be

recognized no longer than

T_{RX-IDLE-DET-DIFF-ENTER-TIME}to signal an

unexpected idle condition.

Unexpected electrical idle

enter detect threshold

integration time

T_{RX-IDLE-DET-DIFF-ENTER-TIME}

(1) No test load is necessarily associated with this value.

(2) Specified at the measurement point and measured over any 250 consecutive UIs. A test load must be used as the RX device when

taking measurements. If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500

consecutive UI is used as a reference for the eye diagram.

(3) A T_RX-EYE= 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and interconnect

collected any 250 consecutive UIs. The T_{RX-EYE-MEDIAN-to-MAX-JITTER}specification ensures a jitter distribution in which the median and

the maximum deviation from the median is less than half of the total UI jitter budget collected over any 250 consecutive TX UIs. It must

be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points

on either side is approximately equal as opposed to the averaged time value. If the clocks to the RX and TX are not derived from the

same reference clock, the TX UI recovered from 3500 consecutive UIs must be used as the reference for the eye diagram.

(4) The receiver input impedance results in a differential return loss greater than or equal to 15 dB with the P line biased to 300 mV and

the N line biased to 300 mV and a common-mode return loss greater than or equal to 6 dB (no bias required) over a frequency range

of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference impedance for return loss

measurements for is 50Ω to ground for both the P and N line (i.e., as measured by a vector network analyzer with 50Ω probes). The

series capacitors CTX is optional for the return loss measurement.

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(5) Impedance during all link training status state machine (LTSSM) states. When transitioning from a PCIe reset to the detect state (the

initial state of the LTSSM) there is a 5-ms transition time before receiver termination values must be met on the unconfigured lane of a

port.

(6) The RX dc common-mode impedance that exists when no power is present or PCIe reset is asserted. This helps ensure that the

receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at 300 mV above

the RX ground.

English Data Sheet: SCPS271

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6.7 PCIe Differential Reference Clock Input Ranges

REFCLK+ and REFCLK–. At T_J= –40°C to 125°C, unless otherwise noted.

PARAMETER

MIN

0.175

40%

NOM

MAX UNIT

COMMENTS

The input frequency is 100 MHz + 300 ppm

and 2800 ppm including SSC-dictated

variations.

f_IN-DIFF

Differential input frequency

100

MHz

Differential input peak-to-peak

voltage

V_RX-DIFFp-p

1.200

V

V_RX-DIFFp-p= 2*|V_REFCLK+V_REFCLK–|

V_RX-CM-ACp= RMS(|V_REFCLK++ V_REFCLK–|/2

V_RX-CM-DC) V_RX-CM-DC= DC_(avg)of

|V_REFCLK++ V_REFCLK–|/2

AC peak common-mode input

voltage

V_RX-CM-ACp

140

mV

Duty cycle

Z_RX-DIFF-DC

60%

Differential waveform input duty cycle

REFCLK dc differential mode impedance

DC differential input impedance

20

kΩ

6.8 Electrical Characteristics Over Recommended Operating Conditions (3.3-V I/O)

All signals (I) Input, (O) Output, (I/O) pins excluding the differential Inputs (DI), Differential Outputs (DO) pins. At T_J= –40°C

to 125°C, unless otherwise noted.

PARAMETER

High-level input voltage⁽¹⁾

Low-level input voltage⁽¹⁾

Input voltage

OPERATION

V_{SUP_33}

TEST CONDITIONS

MIN

MAX

V_{SUP_33}

UNIT

V

V_IH

V_IL

V_I

0.7 V_{SUP_33}

V_{SUP_33}

0

0.28 V_{SUP_33}

V_{SUP_33}

V

V_O

t_T

Output voltage⁽²⁾

V_{SUP_33}

V

Input transition time (t_riseand t_fall

)

25

ns

V

V_hys

V_OH

V_OL

I_OZ

Input hysteresis⁽³⁾

0.3 V_{SUP_33}

High-level output voltage

Low-level output voltage

V_{SUP_33}

I_OH= 4 mA

0.8 V_{SUP_33}

V

I_OL= 4 mA

0.22 V_{SUP_33}

±20

V

High-impedance, output current⁽²⁾

V_I= 0 to V_{SUP_33}

μA

High-impedance, output current with internal

pullup or pulldown resistor⁽⁴⁾

I_OZP

I_I

V_{SUP_33}

V_I= 0 to V_{SUP_33}

±150

±1

μA

Input current⁽⁵⁾

(1) Applies to external inputs and bidirectional buffers

(2) Applies to external outputs and bidirectional buffers

(3) Applies to PERST and GRST

(4) Applies to GRST (pullup resistor) and most GPIOs (pullup resistor)

(5) Applies to external input buffers

6.9 Switching Characteristics

At T_J= –40°C to 125°C, unless otherwise noted.

PARAMETER

TEST CONDITION

MIN

TYP MAX UNIT

t_su

t_h

2.5

0

ns

Setup time, CTL0, CTL1, D1–D7, PINT/LREQ to PCLK/LCLK

Hold time, CTL0, CTL1, D1–D7, PINT/LREQ after PCLK/LCLK

Delay time, PCLK/LCLK to CTL0, CTL1, D1–D7, PINT/LREQ

Delay from rising edge of PCLK to LCLK

50% to 50%, See 图9-1

50% to 50%, See 图9-2

50% to 50%

t_d

0.5

7

4

ns

t_pl

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7 Operating Life Deration

The information in the section below is provided solely for your convenience and does not extend or modify the

warranty provided under TI’s standard terms and conditions for TI semiconductor products.

500000

Electromigration Fail Mode

Wirebond Voiding Fail Mode

400000

300000

200000

100000

70000

60000

50000

40000

30000

20000

85

90

95

100

105

110

115

120

125

Continuous Junction Temperature - T_J(°C)

TSB8

A. Silicon operating life design goal is 100000 power-on hours (POH) at 105°C junction temperature (does not include package

interconnect life).

B. The predicted operating lifetime versus junction temperature is based on reliability modeling using electromigration as the dominant

failure mechanism affecting device wear out for the specific device process and design characteristics.

图7-1. TSB82AF15-EP Operating Life Derating Chart

English Data Sheet: SCPS271

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8 Typical Characteristics

PCIe 1.1 TX Jitter setup

RFSource

2.5GHz

0dBm

Agilent Infinium

DCA 86100A

Pulse Generator

Ch2

Trig Out

Ch 1

Ch 2

Ch 3

Ch 4

Ext Trig

Ch 1

Trig

2.5GHz

Trigger

input

Div25 Clk board

Pulse Generator

Ch2

Trig Out

Ch 1

Ext Trig

图8-1. TSB82AF15-EP Eye Diagram

TXP

TXN

PCIe

Adapter

Board

PCIe Compliance Board

Refclk+

+

-

+

-

Refclk-

图8-2. TSB82AF15-EP Reference Jitter Setup

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9 Parameter Measurement Information

xCLK

t

su

t

h

Dx, CTLx, LREQ

图9-1. Dx, CTLx, LREQ Input Setup and Hold Time Waveforms

xCLK

t

d

Dx, CTLx

图9-2. Dx and CTLx Output Delay Relative to xCLK Waveforms

English Data Sheet: SCPS271

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10 Detailed Description

10.1 Overview

The PCIe interface supports a ×1 link operating at full 250 MB/s packet throughput in each direction

simultaneously. Also, the bridge supports the advanced error reporting capability including ECRC as defined in

the PCI Express Base Specification, Revision 1.1. Supplemental firmware or software is required to fully utilize

both of these features.

Robust pipeline architecture is implemented to minimize system latency. If parity errors are detected, packet

poisoning is supported for both upstream and downstream operations.

PCIe power management (PM) features include active-state link PM, PME mechanisms, and all conventional

PCI D states. If the active-state link PM is enabled, the link automatically saves power when idle using the L0s

and L1 states. PM active-state NAK, PM PME, and PME-to-ACK messages are supported. The bridge is

compliant with the latest PCI Bus Power Management Specification and provides several low-power modes,

which enable the host power system to further reduce power consumption

Eight general-purpose inputs and outputs (GPIOs), configured through accesses to the PCIe configuration

space, allow for further system control and customization.

Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies. The device provides

physical write posting and a highly tuned physical data path for SBP-2 performance. The device is capable of

transferring data between the PCIe bus and the 1394 bus at 100M bit/s, 200M bit/s, 400M bit/s, and 800M bit/s.

As required by the 1394 Open Host Controller Interface (OHCI) Specification, internal control registers are

memory mapped and nonprefetchable. This configuration header is accessed through configuration cycles

specified by PCIe, and it provides plug-and-play (PnP) compatibility.

10.2 Functional Block Diagram

This section provides a high-level overview of all significant device features. 图 10-1 shows a simplified block

diagram of the basic architecture of the PCIe to PCI bridge with 1394b OHCI. The top of the diagram is the PCIe

interface, and the 1394b OHCI link is located at the bottom of the diagram.

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PCI Express

Transmitter

PCI Express

Receiver

Power

Mgmt

GPIO

Configuration and

Memory Register

Serial

EEPROM

Clock

Generator

Reset

Controller

PCI Bus Interface

1394b OHCI

图10-1. TSB82AF15-EP Block Diagram

10.3 Feature Description

10.3.1 Power-Up/Power-Down Sequencing

The bridge contains both 1.5-V and 3.3-V power terminals. The following power-up and power-down sequences

describe how power is applied to these terminals.

In addition, the bridge has three resets: PERST, GRST, and an internal power-on reset. These resets are

described in 节 10.3.2. The following power-up and power-down sequences describe how PERST is applied to

the bridge.

The application of the PCIe reference clock (REFCLK) is important to the power-up/-down sequence and is

included in the following power-up and power-down descriptions.

10.3.1.1 Power-Up Sequence

1. Assert GRST and PERST to the device.

2. Apply 1.5-V and 3.3-V voltages. The order of the 1.5-V or 3.3-V supplies coming up is not important, as long

as the supplies never exceed more than 2.6V from each other.

3. Apply a stable PCIe reference clock.

4. To meet PCIe specification requirements, PERST cannot be deasserted until the following two delay

requirements are satisfied:

• Wait a minimum of 100 μs after applying a stable PCIe reference clock. The 100 μs limit satisfies the

requirement for stable device clocks by the deassertion of PERST.

• Wait a minimum of 100 ms after applying power. The 100 ms limit satisfies the requirement for stable

power by the deassertion of PERST.

See the power-up sequencing diagram in 图10-2.

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VDD_15 and

VDDA_15

VDD_33 and

VDDA_33

REFCLK

PERST

GRST

100 ms

图10-2. Power-Up Sequence

10.3.1.2 Power-Down Sequence

1. Assert PERST to the device.

2. Remove the reference clock.

3. Remove 3.3-V and 1.5-V voltages. The order of the 1.5-V or 3.3-V supplies going down is not important, as

long as the supplies never exceed more than 2.6 V from each other.

See the power-down sequencing diagram in 图10-3

VDD_15 and

VDDA_15

VDD_33 and

VDDA_33

REFCLK

PERST

图10-3. Power-Down Sequence

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10.3.2 TSB82AF15-EP Reset Features

There are five TSB82AF15-EP reset options that include internally-generated power-on reset, resets generated

by asserting input terminals, and software-initiated resets that are controlled by sending a PCIe hot reset or

setting a configuration register bit. 表 10-1 identifies these reset sources and describes how the TSB82AF15-EP

responds to each reset.

表10-1. TSB82AF15-EP Reset Options

RESET OPTION

TSB82AF15-EP FEATURE

RESET RESPONSE

TSB82AF15-EP During a power-on cycle, the TSB82AF15-EP asserts an

When the internal power-on reset is asserted, all control

internally-

internal reset and monitors V_{DD_15_COMB}. When this supply registers, state machines, sticky register bits, and power

generated

power-on reset

reaches 90% of the nominal input voltage specification,

power is considered stable. After stable power, the

TSB82AF15-EP monitors the PCIe reference clock

(REFCLK) and waits 10 μs after active clocks are detected.

Then, internal power-on reset is deasserted.

management state machines are initialized to their default

state.

In addition, the TSB82AF15-EP asserts the internal PCI

bus reset.

Global reset

input ( GRST, )

When GRST is asserted low, an internal power-on reset

occurs. This reset is asynchronous.

When GRST is asserted low, all control registers, state

machines, sticky register bits, and power management

state machines are initialized to their default state. When

the rising edge of GRST occurs, the bridge samples the

state of all static control inputs and latches the information

internally. If an external serial EEPROM is detected, then a

download cycle is initiated. Also, the process to configure

and initialize the PCI Express link is started. The bridge

starts link training within 80 ms after GRST is deasserted.

PCIe reset input This TSB82AF15-EP input terminal is used by an upstream When PERST is asserted low, all control register bits that

( PERST, )

PCIe device to generate a PCIe reset and to signal a system are not sticky are reset. Within the configuration register

power good condition.

maps, the sticky bits are indicated by the symbol. Also, all

state machines that are not associated with sticky

functionality are reset.

When PERST is asserted low, the TSB82AF15-EP

generates an internal PCIe reset as defined in the PCI

Express Specification.

When PERST transitions from low to high, a system power In addition, the TSB82AF15-EP asserts the internal PCI

good condition is assumed by the TSB82AF15-EP.

bus reset.

Note: The system must assert PERST before power is

removed, before REFCLK is removed or before REFCLK

becomes unstable.

When the rising edge of PERST occurs, the TSB82AF15-

EP samples the state of all static control inputs and latches

the information internally. If an external serial EEPROM is

detected, a download cycle is initiated. Also, the process

to configure and initialize the PCIe link is started. The

TSB82AF15-EP starts link training within 80 ms after

PERST is deasserted.

PCIe training

The TSB82AF15-EP responds to a training control hot reset In the DL_DOWN state, all remaining configuration register

control hot reset received on the PCIe interface. After a training control hot

reset, the PCIe interface enters the DL_DOWN state.

bits and state machines are reset. All remaining bits

exclude sticky bits and EEPROM loadable bits. All

remaining state machines exclude sticky functionality and

EEPROM functionality.

Within the configuration register maps, the sticky bits are

reset by a global reset ( GRST) or the internally-generated

power-on reset and EEPROM loadable bits are rest by a

PCIe reset ( PERST), GRST, or internally generated

power-on reset.

In addition, the TSB82AF15-EP asserts the internal PCI

bus reset.

PCI bus reset

System software has the ability to assert and deassert the

PCI bus reset on the secondary PCI bus interface.

When bit 6 (SRST) in the TSB82AF15-EP control register

at offset 3Eh (see 节10.6.1.30) is asserted, the

TSB82AF15-EP asserts the internal PCI bus reset. A 0b in

the SRST bit deasserts the PCI bus reset.

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10.3.3 PCI Express (PCIe) Interface

10.3.3.1 External Reference Clock

The TSB82AF15-EP requires an external reference clock for the PCI-Express interface. This section provides

information concerning the requirements for this reference clock. The TSB82AF15-EP is designed to meet all

stated specifications when the reference clock input is within all PCI Express operating parameters. This

includes both standard clock oscillator sources or spread spectrum clock oscillator sources.

The TSB82AF15-EP supports the 100-MHz common differential reference clock. The 125-Mhz single ended

option is not supported.

A single clock source with multiple differential clock outputs is connected to all PCI Express devices in the

system. The differential connection between the clock source and each PCI Express device is point-to-point.

This system implementation is referred to as a common clock design.

The TSB82AF15-EP is optimized for this type of system clock design. The REFCLK+ and REFCLK– pins

provide differential reference clock inputs to the TSB82AF15-EP. The circuit board routing rules associated with

the 100-MHz differential reference clock are the same as the 2.5-Gb/s TX and RX link routing rules itemized in

2.5-Gb/s Transmit and Receive Links. The only difference is that the differential reference clock does not require

series capacitors. The requirement is a DC connection from the clock driver output to the TSB82AF15-EP

receiver input.

Terminating the differential clock signal is circuit board design specific. But, the TSB82AF15-EP design does not

have internal 100Ωdifferential or 50Ωto ground termination resistors. Both REFCLK inputs are high impedance

inputs with approximately 20kΩto ground.

10.3.3.2 Beacon and Wake

Since the 1394b OHCI function in the TSB82AF15-EP does not support PME from D3cold, it is not necessary for

the PCIe to PCI bridge portion of the design to support beacon generation or WAKE signaling. As a result, the

TSB82AF15-EP does not implement VAUX power support.

10.3.3.3 Initial Flow Control Credits

The bridge flow control credits are initialized using the rules defined in the PCI Express Base Specification. 表

10-2 identifies the initial flow control credit advertisement for the bridge.

表10-2. Initial Flow Control Credit Advertisements

CREDIT TYPE

INITIAL ADVERTISEMENT

Posted request headers (PH)

Posted request data (PD)

Nonposted header (NPH)

Nonposted data (NPD)

8

128

4

Completion header (CPLH)

Completion data (CPLD)

0 (infinite)

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10.3.3.4 PCIe Message Transactions

PCIe messages are both initiated and received by the bridge. 表 10-3 outlines message support within the

bridge.

表10-3. Messages Supported by Bridge

MESSAGE

SUPPORTED

BRIDGE ACTION

Transmitted upstream

Received and processed

Transmitted upstream

Received and processed

Transmitted upstream

Received and processed

Discarded

Assert_INTx

Yes

Deassert_INTx

PM_Active_State_Nak

PM_PME

Yes

PME_Turn_Off

PME_TO_Ack

ERR_COR

Yes

ERR_NONFATAL

ERR_FATAL

Yes

Set_Slot_Power_Limit

Unlock

Yes

No

Hot plug messages

No

Discarded

Advanced switching messages

Vendor defined type 0

No

Discarded

No

Unsupported request

Discarded

Vendor defined type 1

No

All supported message transactions are processed per the PCI Express Base Specification.

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10.3.4 PCI Interrupt Conversion to PCIe Messages

The bridge converts interrupts from the PCI bus sideband interrupt signals to PCIe interrupt messages. Since the

1394a OHCI only generates INTA interrupts, only PCIe INTA messages are generated by the bridge.

PCIe Assert_INTA messages are generated when the 1394a OHCI signals an INTA interrupt. The requester ID

portion of the Assert_INTA message uses the value stored in the primary bus number register (see 节10.6.1.12)

as the bus number, 0 as the device number, and 0 as the function number. The tag field for each Assert_INTA

message is 00h.

PCIe Deassert_INTA messages are generated when the 1394a OHCI deasserts the INTA interrupt. The

requester ID portion of the Deassert_INTA message uses the value stored in the primary bus number register as

the bus number, 0 as the device number, and 0 as the function number. The Tag field for each Deassert_INTA

message is 00h.

图10-4 and 图10-5 show the format for both the assert and deassert INTA messages.

+0

+1

+2

+3

7

6

5

1

4

1

3

0

2

Type

1

0

7

6

0

5

TC

0

4

0

3

2

1

0

7

T

D

6

E

P

5

4

0

3

2

1

0

7

0

6

0

5

4

3

0

2

0

1

0

Fmt

Attr

Length

Byte 0>

Byte 4>

R

Reserved

R

0

1

0

Code

Reserved ID

Tag

0

Byte 8>

Byte 12>

Reserved

图10-4. PCIe Assert_INTA Message

+0

+1

+2

+3

7

6

0

5

4

1

3

0

2

Type

1

0

7

6

0

5

TC

0

4

0

3

2

1

0

7

T

D

6

E

P

5

4

0

3

2

1

0

7

0

6

0

5

4

3

0

2

0

1

0

Fmt

Attr

Length

Byte 0>

Byte 4>

R

Reserved

R

1

0

1

0

Code

Reserved ID

Tag

0

Byte 8>

Byte 12>

Reserved

图10-5. PCIe Deassert_INTX Message

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10.3.5 Two-Wire Serial-Bus Interface

The bridge provides a two-wire serial-bus interface to load subsystem identification information and specific

register defaults from an external EEPROM. The serial-bus interface signals are SCL and SDA.

10.3.5.1 Serial-Bus Interface Implementation

To enable the serial-bus interface, a pullup resistor must be implemented on the SDA signal. At the rising edge

of PERST or GRST, whichever occurs later in time, the SDA terminal is checked for a pullup resistor. If one is

detected, bit 3 (SBDETECT) in the serial-bus control and status register (see 节 10.6.1.59) is set. Software may

disable the serial-bus interface at any time by writing a 0b to the SBDETECT bit. If no external EEPROM is

required, the serial-bus interface is permanently disabled by attaching a pulldown resistor to the SDA signal.

The bridge implements a two-terminal serial interface with one clock signal (SCL) and one data signal (SDA).

The SCL signal is a unidirectional output from the bridge and the SDA signal is bidirectional. Both are open-drain

signals and require pullup resistors. The bridge is a bus master device and drives SCL at approximately 60 kHz

during data transfers and places SCL in a high-impedance state (0 frequency) during bus idle states. The serial

EEPROM is a bus slave device and must acknowledge a slave address equal to A0h. 图 10-6 shows an

example application implementing the two-wire serial bus.

VDD_33

Serial

EEPROM

TSB82AF15

A0

SCL

SDA

A1 SCL

A2 SDA

图10-6. Serial EEPROM Application

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10.3.5.2 Serial-Bus Interface Protocol

All data transfers are initiated by the serial-bus master. The beginning of a data transfer is indicated by a start

condition, which is signaled when the SDA line transitions to the low state while SCL is in the high state (see 图

10-7). The end of a requested data transfer is indicated by a stop condition, which is signaled by a low-to-high

transition of SDA while SCL is in the high state (see 图 10-7). Data on SDA must remain stable during the high

state of the SCL signal, as changes on the SDA signal during the high state of SCL are interpreted as control

signals, that is, a start or stop condition.

SDA

SCL

Start

Condition

Stop

Condition

Change of

Data Allowed

Data Line Stable,

Data Valid

图10-7. Serial-Bus Start/Stop Conditions and Bit Transfers

Data is transferred serially in 8-bit bytes. During a data transfer operation, the exact number of bytes that are

transmitted is unlimited. However, each byte must be followed by an acknowledge bit to continue the data

transfer operation. An acknowledge (ACK) is indicated by the data byte receiver pulling the SDA signal low, so

that it remains low during the high state of the SCL signal. 图10-8 shows the acknowledge protocol.

SCL From

Master

1

2

3

7

8

9

SDA Output

By Transmitter

SDA Output

By Receiver

图10-8. Serial-Bus Protocol Acknowledge

The bridge performs three basic serial-bus operations: single-byte reads, single-byte writes, and multibyte reads.

The single-byte operations occur under software control. The multibyte read operations are performed by the

serial EEPROM initialization circuitry immediately after a PCIe reset (see 节 10.3.5.3, Serial-Bus EEPROM

Application, for details on how the bridge automatically loads the subsystem identification and other register

defaults from the serial-bus EEPROM.

图 10-9 shows a single-byte write. The bridge issues a start condition and sends the 7-bit slave device address,

and the R/W command bit is equal to 0b. A 0b in the R/W command bit indicates that the data transfer is a write.

The slave device acknowledges if it recognizes the slave address. If no acknowledgment is received by the

bridge, bit 1 (SB_ERR) is set in the serial-bus control and status register (PCI offset B3h, see 节 10.6.1.59).

Next, the EEPROM word address is sent by the bridge, and another slave acknowledgment is expected. Then

the bridge delivers the data-byte most significant bit (MSB) first and expects a final acknowledgment before

issuing the stop condition.

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Data Byte

b7 b6 b5 b4 b3 b2 b1 b0

Slave Address

b6 b5 b4 b3 b2 b1 b0

Word Address

S

0

A

b7 b6 b5 b4 b3 b2 b1 b0

A

P

R/W

A = Slave Acknowledgement

S/P = Start/Stop Condition

图10-9. Serial-Bus Protocol Byte Write

图10-10 shows a single-byte read. The bridge issues a start condition and sends the 7-bit slave device address,

and the R/ W command bit is equal to 0b (write). The slave device acknowledges if it recognizes the slave

address. Next, the EEPROM word address is sent by the bridge, and another slave acknowledgment is

expected. Then, the bridge issues a restart condition followed by the 7-bit slave address, and the R/ W

command bit is equal to 1b (read). Once again, the slave device responds with an acknowledge. Next, the slave

device sends the 8-bit data byte, MSB first. Since this is a 1-byte read, the bridge responds with no acknowledge

(logic high) indicating the last data byte. Finally, the bridge issues a stop condition.

Slave Address

b2 b1 b0

Word Address

Slave Address

S

b6 b5 b4 b3

0

A

S

b6 b5 b4 b3 b2 b1 b0

1

A

b7 b6 b5 b4 b3 b2 b1 b0

A

Start

Restart

R/W

Data Byte

b7 b6 b5 b4 b3 b2 b1 b0

M

P

Stop

A = Slave Acknowledgement

M = Master Acknowledgement

S/P = Start/Stop Condition

图10-10. Serial-Bus Protocol Byte Read

图 10-11 shows the serial interface protocol during a multibyte serial EEPROM download. The serial-bus

protocol starts exactly the same as a 1-byte read. The only difference is that multiple data bytes are transferred.

The number of transferred data bytes is controlled by the bridge master. After each data byte, the bridge master

issues acknowledge (logic low) if more data bytes are requested. The transfer ends after a bridge master no

acknowledge (logic high) followed by a stop condition.

Slave Address

Word Address

Slave Address

S

1

0

1

0

A

0

A

S

1

0

1

0

1

A

Start

R/W

Restart

R/W

Data Byte 0

A = Slave Acknowledgement

Data Byte 1

Data Byte 2

Data Byte 3

S/P = Start/Stop Condition

M

P

M = Master Acknowledgement

图10-11. Serial-Bus Protocol Multibyte Read

Bit 7 (PROT_SEL) in the serial-bus control and status register changes the serial-bus protocol. Each of the three

previous serial-bus protocol figures show the PROT_SEL bit default (logic low). When this control bit is asserted,

the word address and corresponding acknowledge are removed from the serial-bus protocol. This feature allows

the system designer a second serial-bus protocol option when selecting external EEPROM devices.

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10.3.5.3 Serial-Bus EEPROM Application

The registers and corresponding bits that are loaded through the EEPROM are provided in 表10-4.

表10-4. EEPROM Register Loading Map

SERIAL EEPROM

BYTE DESCRIPTION

WORD ADDRESS

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

PCIe to PCI bridge function indicator (00h)

Number of bytes to download (1Eh)s

PCI 84h, subsystem vendor ID, byte 0

PCI 85h, subsystem vendor ID, byte 1

PCI 86h, subsystem ID, byte 0s

PCI 87h, subsystem ID, byte 1s

PCI D4h, general control, byte 0

PCI D5h, general control, byte 1

PCI D6h, general control, byte 2

PCI D7h, general control, byte 3

TI Proprietary register load 00h (PCI D8h)

TI Proprietary register load 00h (PCI D9h)

Reserved —no bits loaded 00h (PCI DAh)

PCI DCh, arbiter control

PCI DDh, arbiter request mask

PCI C0h, TL control and diagnostic register, byte 0

PCI C0h, TL control and diagnostic register, byte 1

PCI C0h, TL control and diagnostic register, byte 2

PCI C0h, TL control and diagnostic register, byte 3

PCI C4h, DLL control and diagnostic register, byte 0

PCI C5h, DLL control and diagnostic register, byte 1

PCI C6h, DLL control and diagnostic register, byte 2

PCI C7h, DLL control and diagnostic register, byte 3

PCI C8h, PHY control and diagnostic register, byte 0

PCI C9h, PHY control and diagnostic register, byte 1

PCI CAh, PHY control and diagnostic register, byte 2

PCI CBh, PHY control and diagnostic register, byte 3

Reserved —no bits loaded 00h (PCI CEh)

Reserved —no bits loaded 00h (PCI CFh)

TI proprietary register load 00h (PCI E0h)

TI proprietary register load 00h (PCI E2h)

TI proprietary register load 00h (PCI E3h)

1394 OHCI function indicator (01h)

Number of bytes (18h)

PCI 3Fh, maximum latency, bits 7-4

PCI 3Eh, minimum grant, bits 3-0

PCI 2Ch, subsystem vendor ID, byte 0

PCI 2Dh, subsystem vendor ID, byte 1

PCI 2Eh, subsystem ID, byte 0

PCI 2Fh, subsystem ID, byte 1

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表10-4. EEPROM Register Loading Map (continued)

SERIAL EEPROM

WORD ADDRESS

BYTE DESCRIPTION

[7]

[6]

[5:3]

RSVD

[2]

Link_Enh

[1]

Link_Enh enab_accel

[0]

RSVD

Link_Enh enab_unfair

HC Control

Program Phy

Enable

27h

28h

Mini-ROM address, this byte indicates the MINI ROM offset into the EEPROM

00h = No MINI ROM

01h to FFh = MINI ROM offset

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

OHCI 24h, GUIDHi, byte 0

OHCI 25h, GUIDHi, byte 1

OHCI 26h, GUIDHi, byte 2

OHCI 27h, GUIDHi, byte 3

OHCI 28h, GUIDLo, byte 0

OHCI 29h, GUIDLo, byte 1

OHCI 2Ah, GUIDLo, byte 2

OHCI 2Bh, GUIDLo, byte 3

Reserved —no bits loaded

PCI F5h, Link_Enh, byte 1, bits 7, 6, 5, 4

PCI F0h, PCI miscellaneous, byte 0, bits 7, 4, 2, 1, 0

PCI F1h, PCI miscellaneous, byte 1, bits 1, 0

Reserved —no bits loaded

Reserved multifunction select register

End-of-list indicator (80h)

This format must be explicitly followed for the bridge to correctly load initialization values from a serial EEPROM.

All byte locations must be considered when programming the EEPROM.

The serial EEPROM is addressed by the bridge at slave address 1010 000b. This slave address is internally

hardwired and cannot be changed by the system designer. Therefore, all three hardware address bits for the

EEPROM are tied to V_SSto achieve this address. The serial EEPROM in the sample application circuit (图 10-6)

assumes the 1010b high-address nibble. The lower three address bits are terminal inputs to the chip, and the

sample application shows these terminal inputs tied to V_SS

.

During an EEPROM download operation, bit 4 (ROMBUSY) in the serial-bus control and status register is

asserted. After the download is finished, bit 0 (ROM_ERR) in the serial-bus control and status register may be

monitored to verify a successful download.

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10.3.5.4 Accessing Serial-Bus Devices Through Software

The bridge provides a programming mechanism to control serial-bus devices through system software. The

programming is accomplished through a doubleword of PCI configuration space at offset B0h. 表 10-5 lists the

registers that program a serial-bus device through software.

表10-5. Registers Used To Program Serial-Bus Devices

PCI OFFSET

REGISTER NAME

DESCRIPTION

B0h

Serial-bus data

(see 节10.6.1.56)

Contains the data byte to send on write commands or the received data byte on read

commands.

B1h

Serial-bus word address

(see 节10.6.1.57)

The content of this register is sent as the word address on byte writes or reads. This register is

not used in the quick command protocol. Bit 7 (PROT_SEL) in the serial-bus control and status

register (offset B3h, see 节10.6.1.59) is set to 1b to enable the slave address to be sent.

B2h

B3h

Serial-bus slave address

(see 节10.6.1.58)

Write transactions to this register initiate a serial-bus transaction. The slave device address

and the R/ W command selector are programmed through this register.

Serial-bus control and

status (see 节10.6.1.59)

Serial interface enable, busy, and error status are communicated through this register. In

addition, the protocol-select bit (PROT_SEL) and serial-bus test bit (SBTEST) are programmed

through this register.

To access the serial EEPROM through the software interface, the following steps are performed:

1. The control and status byte is read to verify the EEPROM interface is enabled (SBDETECT asserted) and

not busy (REQBUSY and ROMBUSY deasserted).

2. The serial-bus word address is loaded. If the access is a write, the data byte is also loaded.

3. The serial-bus slave address and R/ W command selector byte is written.

4. REQBUSY is monitored until this bit is deasserted.

5. SB_ERR is checked to verify that the serial-bus operation completed without error. If the operation is a read,

the serial-bus data byte is now valid.

10.3.6 General-Purpose I/O (GPIO) Interface

Up to eight GPIO terminals are provided for system customization. These GPIO terminals are 3.3-V tolerant.

The exact number of GPIO terminals varies based on implementing the clock-run, power-override, and serial

EEPROM interface features. These features share four of the eight GPIO terminals. When any of the three

shared functions are enabled, the associated GPIO terminal is disabled.

All eight GPIO terminals are individually configurable as either inputs or outputs by writing the corresponding bit

in the GPIO control register at offset B4h. A GPIO data register at offset B6h exists to either read the logic state

of each GPIO input or to set the logic state of each GPIO output. The power-up default state for the GPIO control

register is input mode.

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10.4 Device Functional Modes

10.4.1 Advanced Error Reporting Registers

In the extended PCIe configuration space, the bridge supports the advanced error reporting capabilities

structure. For the PCIe interface, both correctable and uncorrectable error statuses are provided. For the PCI

bus interface, secondary uncorrectable error status is provided. All uncorrectable status bits have corresponding

mask and severity control bits. For correctable status bits, only mask bits are provided.

Both the primary and secondary interfaces include first error pointer and header log registers. When the first

error is detected, the corresponding bit position within the uncorrectable status register is loaded into the first

error pointer register. Likewise, the header information associated with the first failing transaction is loaded into

the header log. To reset this first error control logic, the corresponding status bit in the uncorrectable status

register is cleared by a writeback of 1b.

For systems that require high data reliability, ECRC is fully supported on the PCIe interface. The primary-side

advanced error capabilities and control register has both ECRC generation and checking enable control bits.

When the checking bit is asserted, all received TLPs are checked for a valid ECRC field. If the generation bit is

asserted, all transmitted TLPs contain a valid ECRC field.

10.4.2 Data Error Forwarding Capability

The bridge supports the transfer of data errors in both directions.

If a downstream PCIe transaction with a data payload is received that targets the internal PCI bus and the EP bit

is set indicating poisoned data, the bridge must ensure that this information is transferred to the PCI bus. To do

this, the bridge forces a parity error on each PCI bus data phase by inverting the parity bit calculated for each

double word of data.

If the bridge is the target of a PCI transaction that is forwarded to the PCIe interface and a data parity error is

detected, this information is passed to the PCIe interface. To do this, the bridge sets the EP bit in the upstream

PCIe header.

10.4.3 Set Slot Power Limit Functionality

The PCI Express Specification provides a method for devices to limit internal functionality and save power based

on the value programmed into the captured slot power limit scale (CSPLS) and capture slot power limit value

(CSPLV) fields of the PCIe device capabilities register at offset 94h (see 节 10.6.1.50, Device Capabilities

Register, for details). The bridge writes these fields when a set slot power limit message is received on the PCIe

interface.

After the deassertion of PERST, the TSB82AF15-EP compares the information within the CSPLS and CSPLV

fields of the device capabilities register to the minimum power scale (MIN_POWER_SCALE) and minimum

power value (MIN_POWER_VALUE) fields in the general control register at offset D4h (see 节 10.6.1.66,

General Control Register, for details). If the CSPLS and CSPLV fields are less than the MIN_POWER_SCALE

and MIN_POWER_VALUE fields, respectively, the bridge takes the appropriate action that is defined below.

The power usage action is programmable within the bridge. The general control register includes a 3-bit

POWER_OVRD field. This field is programmable to the following two options:

• Ignore slot power limit fields.

• Respond with unsupported request to all transactions except type 0/1 configuration transactions, and set slot

power limit messages.

10.4.4 PCIe and PCI Bus Power Management

The bridge supports both software-directed power management and active-state power management through

standard PCI configuration space. Software-directed registers are located in the power management capabilities

structure located at offset 50h. Active-state power management control registers are located in the PCIe

capabilities structure located at offset 90h.

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During software-directed power-management state changes, the bridge initiates link state transitions to L1 or

L2/L3 after a configuration write transaction places the device in a low-power state. The power-management

state machine is also responsible for gating internal clocks based on the power state. 表 10-6 identifies the

relationship between the D-states and bridge clock operation.

表10-6. Clocking In Low Power States

CLOCK SOURCE

D0/L0

D1/L1

D2/L1

On

D3/L2/L3

On/Off

Off

PCIe reference clock input (REFCLK)

Internal PCI bus clock to bridge function

Internal PCI bus clock to 1394b OHCI function

On

Off

On

On/Off

The link power management (LPM) state machine manages active-state power by monitoring the PCIe

transaction activity. If no transactions are pending and the transmitter has been idle for at least the minimum time

required by the PCI Express Specification, the LPM state machine transitions the link to either the L0s or L1

state. By reading the bridges L0s and L1 exit latency in the link capabilities register, the system software may

make an informed decision relating to system performance versus power savings. The ASLPMC field in the link

control register provides an L0s-only option, L1-only option, or both L0s and L1 options.

Finally, the bridge generates the PM_Active_State_Nak Message if a PM_Active_State_Request_L1 DLLP is

received on the PCIe interface and the link cannot be transitioned to L1.

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10.5 Programming

10.5.1 1394b OHCI Controller Functionality

10.5.1.1 1394b OHCI Power Management

The 1394b OHCI controller complies with the PCI Bus Power Management Interface Specification. The controller

supports the D0 (uninitialized), D0 (active), D1, D2, and D3 power states as defined by the power-management

definition in the 1394 Open Host Controller Interface Specification, Appendix A4.

表10-7 identifies the supported power-management registers within the 1394 OHCI configuration register map.

表10-7. 1394b OHCI Configuration Register Map

REGISTER NAME

OFFSET

Power management capabilities

Next item pointer

Capability ID

44h

PM data Power management control/status register bridge support extensions Power management control/status (CSR)

48h

10.5.1.2 1394b OHCI and V_AUX

The 1394b OHCI function within the TSB82AF15-EP is not powered by V_AUX. Therefore, during the D3_cold

power-management state, V_AUXis not supplied to the 1394b OHCI function.

This implies that the 1394b OHCI function does not implement sticky bits must be initialized after a D3_coldpower-

management state. An external serial EEPROM interface is available to initialize critical configuration register

bits. The EEPROM download is triggered by the deassertion of the PERST input. Otherwise, the BIOS must

initialize the 1394b OHCI function.

10.5.1.3 1394b OHCI and Reset Options

The 1394b OHCI function is completely reset by the internal power-on reset feature, GRST input, or PERST

input. This includes all EEPROM loadable bits, power-management functions, and all remaining configuration

register bits and logic.

A PCIe training control hot reset or the PCI bus configuration register reset bit (SRST) excludes the EEPROM

loadable bits, power-management functions, and 1394 PHY. All remaining configuration registers and logic are

reset.

If the OHCI controller is in the power-management D2 or D3 state, or if the OHCI configuration register reset bit

(SoftReset) is set, the OHCI controller DMA logic and link logic is reset.

Finally, if the OHCI configuration register PHY reset bit (ISBR) is set, the 1394 PHY logic is reset.

10.5.1.4 1394b OHCI PCI Bus Master

As a bus master, the 1394 OHCI function supports the memory commands specified in 表 10-8. The commands

include memory read, memory read line, memory read multiple, memory write, and memory write and invalidate.

The read command usage for read transactions of greater than two data phases are determined by the selection

in bits 9:8 (MR_ENHANCE field) of the PCI miscellaneous configuration register at offset F0h (see 节10.6.4.21).

For read transactions of one or two data phases, a memory read command is used.

The write command usage is determined by the MWI_ENB bit 4 of the command configuration register at offset

04h (see 节 10.6.1.3). If bit 4 is asserted and a memory write starts on a cache boundary with a length greater

than one cache line, memory write and invalidate commands are used. Otherwise, memory write commands are

used.

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表10-8. 1394 OHCI Memory Command Options

COMMAND C/

BE3C/ BE0

PCI

OHCI MASTER FUNCTION

Memory read

Memory write

0110

DMA read from memory

DMA write to memory

DMA read from memory

DMA write to memory

0111

Memory read multiple

Memory read line

1100

1110

Memory write and invalidate

1111

10.5.1.5 1394b OHCI Subsystem Identification

The subsystem identification register at offset 2Ch is used for system and option card identification purposes.

This register can be initialized from the serial EEPROM or programmed via the subsystem access register at

offset F8h in the 1394a OHCI PCI configuration space (see 节10.6.4.23).

Write access to the subsystem access register updates the subsystem identification registers identically to

OHCI-Lynx^™integrated circuits. The contents of the subsystem access register are aliased to the subsystem

vendor ID and subsystem ID registers at PCI offsets 2Ch and 2Eh, respectively. The subsystem ID value written

to this register may also be read back from this register.

10.5.1.6 1394b OHCI PME Support

Since the 1394b OHCI controller is not connected to VAUX, PME generation is disabled for D3cold power-

management states.

10.6 Register Maps

10.6.1 Classic PCI Configuration Space

The programming model of the TSB82AF15-EP PCIe to PCI bridge is compliant to the classic PCI-to-PCI bridge

programming model. The PCI configuration map uses the type 1 PCI bridge header.

Sticky bits are reset by a global reset ( GRST) or the internally-generated power-on reset. EEPROM loadable

bits are reset by a PCIe reset ( PERST), GRST, or the internally-generated power-on reset. The remaining

register bits are reset by a PCIe hot reset, PERST, GRST, or the internally-generated power-on reset.

• The following section defines the configuration space for the bridge. For each register bit, the software

access method is identified in an access column. The legend for this access column includes the following

entries:

– R: Read access by software

– U: Updates by the bridge internal hardware

– W: Write access by software

– C: Clear an asserted bit with a write back of 1b by software. Write of zero to the field has no effect.

– S: The field may be set by a write of one. Write of zero to the field has no effect.

– NA: Not accessible or not applicable

表10-9. Classic PCI Configuration Register Map

REGISTER NAME

OFFSET

000h

Device ID

Status

Vendor ID

Command

004h

Class code

Header type

Device contol base address

Scratchpad RAM base address

Subordinate bus number Secondary bus number

Revision ID

008h

BIST

Primary latency timer

Cache line size

00Ch

010h

014h

Secondary latency timer

Primary bus number

I/O base

018h

Secondary status

I/O limit

01Ch

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表10-9. Classic PCI Configuration Register Map (continued)

REGISTER NAME

OFFSET

020h

Memory limit

Memory base

Prefetchable memory limit

I/O limit upper 16 bits

Bridge control

Prefetchable memory base

024h

Prefetchable base upper 32 bits

Prefetchable limit upper 32 bits

028h

02Ch

I/O base upper 16 bits

030h

Reserved

Capabilities pointer

034h

Reserved

038h

Interrupt pin

Interrupt line

03Ch

040h-04Ch

050h

Power management capabilities

Power management bridge

support extention

Next item pointer

PM apability ID

Power management data

Power management control/status

054h

Reserved

058h-05Ch

060h

MSI message control

Next item pointer

MSI capability ID

MSI message lower address

MSI message upper address

064h

068h

Reserved

MSI message data

06Ch

Reserved

070h-07Ch

080h

Reserved

Next item pointer

SSID/SSVID capability ID

Subsystem ID⁽¹⁾

Subsystem vendor ID⁽¹⁾

084h

Reserved

Device capabilities

Link capabilities

Reserved

088h-08Ch

090h

PCI Express capabilities register

Device status

Next item pointer

PCI Express capability ID

094h

Device control

098h

09Ch

Link status

Link control

0A0h

0A4h-0ACh

Serial-bus control and

Serial-bus slave address⁽¹⁾

GPIO data⁽¹⁾

Serial-bus word address⁽¹⁾

Serial-bus data⁽¹⁾

0B0h

status⁽¹⁾

GPIO control⁽¹⁾

0B4h

0B8h-0BCh

0C0h

Reserved

Control and diagnostic register 0⁽¹⁾

Control and diagnostic register 1⁽¹⁾

Control and diagnostic register 2⁽¹⁾

Reserved

0C4h

0C8h

0CCh

Subsystem access⁽¹⁾

0D0h

General control⁽¹⁾

0D4h

Reserved

TI proprietary⁽¹⁾

Arbiter time-out status

TI proprietary⁽¹⁾

Reserved

TI proprietary⁽¹⁾

Arbiter control⁽¹⁾

TI proprietary⁽¹⁾

0D8h

Arbiter request mask⁽¹⁾

0DCh

Reserved

0E0h

TI proprietary

0E4h

Reserved

0E8h-0FCh

10.6.1.1 Vendor ID Register

This 16-bit read-only register contains the value 104Ch, which is the vendor ID assigned to TI.,

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PCI register offset:

00h

Register type:

Default value:

Read-only

104Ch

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

1

0

10.6.1.2 Device ID Register

This 16-bit read-only register contains the value 823Eh, which is the device ID assigned by TI for the bridge.,

PCI register offset:

Register type:

02h

Read only

823Eh

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

10.6.1.3 Command Register

The command register controls how the bridge behaves on the PCIe interface. See 表 10-10 for a complete

description of the register contents.

PCI register offset:

Register type:

04h

Read only, Read/Write

0000h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

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表10-10. Command Register Description

BIT

15:11

10

FIELD NAME

ACCESS

DESCRIPTION

RSVD

R

Reserved. Returns 00000b when read.

INT_DISABLE

INTx disable. This bit enables device specific interrupts. Since the bridge does not

generate any internal interrupts, this bit is read-only 0b.

9

8

FBB_ENB

R

Fast back-to-back enable. The bridge does not generate fast back-to-back transactions;

therefore, this bit returns 0b when read.

SERR_ENB

RW

SERR enable. When this bit is set, the bridge can signal fatal and nonfatal errors on the

PCIe interface on behalf of SERR assertions detected on the PCI bus.

0 = Disable the reporting of nonfatal errors and fatal errors (default)

1 = Enable the reporting of nonfatal errors and fatal errors

7

6

STEP_ENB

PERR_ENB

R

Address/data stepping control. The bridge does not support address/data stepping, and

this bit is hardwired to 0b.

RW

Controls the setting of bit 8 (DATAPAR) in the status register (offset 06h, see 节10.6.1.4)

in response to a received poisoned TLP from PCIe. A received poisoned TLP is forwarded

with bad parity to conventional PCI, regardless of the setting of this bit.

0 = Disables the setting of the master data parity error bit (default)

1 = Enables the setting of the master data parity error bit

5

4

VGA_ENB

MWI_ENB

R

VGA palette snoop enable. The bridge does not support VGA palette snooping; therefore,

this bit returns 0b when read.

RW

Memory write and invalidate enable. When this bit is set, the bridge translates PCIe

memory write requests into memory write and invalidate transactions on the PCI interface.

0 = Disable the promotion to memory write and invalidate (default)

1 = Enable the promotion to memory write and invalidate

3

2

SPECIAL

R

Special cycle enable. The bridge does not respond to special cycle transactions; therefore,

this bit returns 0b when read.

MASTER_ENB

RW

Bus master enable. When this bit is set, the bridge is enabled to initiate transactions on the

PCIe interface.

0 = PCIe interface cannot initiate transactions. The bridge must disable the response

to memory and I/O transactions on the PCI interface (default).

1 = PCIe interface can initiate transactions. The bridge can forward memory and I/O

transactions from PCI secondary interface to the PCIe interface.

1

0

MEMORY_ENB

RW

Memory space enable. Setting this bit enables the bridge to respond to memory

transactions on the PCIe interface.

0 = PCIe receiver cannot process downstream memory transactions and must respond

with an unsupported request (default)

1 = PCIe receiver can process downstream memory transactions. The bridge can

forward memory transactions to the PCI interface.

IO_ENB

I/O space enable. Setting this bit enables the bridge to respond to I/O transactions on the

PCIe interface.

0 = PCIe receiver cannot process downstream I/O transactions and must respond with

an unsupported request (default)

1 = PCIe receiver can process downstream I/O transactions. The bridge can forward

I/O transactions to the PCI interface.

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10.6.1.4 Status Register

The status register provides information about the PCIe interface to the system. See 表 10-11 for a complete

description of the register contents.

PCI register offset:

Register type:

06h

Read only, Read/Clear

0010h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

表10-11. Status Register Description

BIT

FIELD NAME

PAR_ERR

ACCESS

DESCRIPTION

15

RCU

Detected parity error. This bit is set when the PCIe interface receives a poisoned TLP. This

bit is set regardless of the state of bit 6 (PERR_ENB) in the command register (offset 04h,

see 节10.6.1.3).

0 = No parity error detected

1 = Parity error detected

14

SYS_ERR

RCU

Signaled system error. This bit is set when the bridge sends an ERR_FATAL or

ERR_NONFATAL message and bit 8 (SERR_ENB) in the command register (offset 04h,

see 节10.6.1.3) is set.

0 = No error signaled

1 = ERR_FATAL or ERR_NONFATAL signaled

13

12

11

MABORT

RCU

RCUT

Received master abort. This bit is set when the PCIe interface of the bridge receives a

completion-with-unsupported-request status.

0 = Unsupported request not received on the PCIe interface

1 = Unsupported request received on the PCIe interface

TABORT_REC

TABORT_SIG

Received target abort. This bit is set when the PCIe interface of the bridge receives a

completion-with-completer-abort status.

0 = Completer abort not received on the PCIe interface

1 = Completer abort received on the PCIe interface

Signaled target abort. This bit is set when the PCIe interface completes a request with

completer abort status.

0 = Completer abort not signaled on the PCIe interface

1 = Completer abort signaled on the PCIe interface

10:9

8

PCI_SPEED

DATAPAR

R

DEVSEL timing. These bits are read-only 00b, because they do not apply to PCIe.

RCU

Master data parity error. This bit is set if bit 6 (PERR_ENB) in the command register (offset

04h, see 节10.6.1.3) is set and the bridge receives a completion with data marked as

poisoned on the PCIe interface or poisons a write request received on the PCIe interface.

0 = No uncorrectable data error detected on the primary interface

1 = Uncorrectable data error detected on the primary interface

7

FBB_CAP

R

Fast back-to-back capable. This bit does not have a meaningful context for a PCIe device

and is hardwired to 0b.

6

5

RSVD

R

Reserved. Returns 0b when read.

66MHZ

66-MHz capable. This bit does not have a meaningful context for a PCIe device and is

hardwired to 0b.

4

3

CAPLIST

INT_STATUS

RSVD

R

Capabilities list. This bit returns 1b when read, indicating that the bridge supports

additional PCI capabilities.

Interrupt status. This bit reflects the interrupt status of the function. This bit is read-only 0b

since the bridge does not generate any interrupts internally.

2:0

Reserved. Returns 000b when read.

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10.6.1.5 Class Code and Revision ID Register

This read-only register categorizes the base class, subclass, and programming interface of the bridge. The base

class is 06h, identifying the device as a bridge. The subclass is 04h, identifying the function as a PCI to PCI

bridge, and the programming interface is 00h. Furthermore, the TI device revision is indicated in the lower byte

(00h). See 表10-12 for a complete description of the register contents.

PCI register offset:

Register type:

08h

Read only

0604 0001h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

1

0

1

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

表10-12. Class Code and Revision ID Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:24 BASECLASS

23:16 SUBCLASS

15:8 PGMIF

R

Base class. This field returns 06h when read, which classifies the function as a bridge device.

Subclass. This field returns 04h when read, which classifies the function as a PCI to PCI bridge.

Programming interface. This field returns 00h when read.

7:0

CHIPREV

Silicon revision. This field returns the silicon revision of the function.

10.6.1.6 Cache Line Size Register

If the EN_CACHE_LINE_CHECK bit in the TL control and diagnostic register is 0, Cheetah- Express shall use

side-band signals from the 1394b OHCI core to determine how much data to fetch when handling delayed read

transactions. In this case, the cache line size register will have no effect on the design and will essentially be a

read/write scratchpad register. If the EN_CACHE_LINE_CHECK bit is 1, the cache line size register is used by

the bridge to determine how much data to prefetch when handling delayed read transactions. In this case, the

value in this register must be programmed to a power of 2, and any value greater than 32 DWORDs will be

treated as 32 DWORDs.

PCI register offset:

Register type:

0Ch

Read/Write

00h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

10.6.1.7 Primary Latency Timer Register

This read-only register has no meaningful context for a PCIe device and returns 00h when read.

PCI register offset:

Register type:

0Dh

Read only

00h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

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10.6.1.8 Header Type Register

This read-only register indicates that this function has a type 1 PCI header. Bit 7 of this register is 0b, indicating

that the bridge is a single-function device.

PCI register offset:

Register type:

0Eh

Read only

01h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

1

10.6.1.9 BIST Register

Since the bridge does not support a built-in self test (BIST), this read-only register returns the value of 00h when

read.

PCI register offset:

Register type:

0Fh

Read only

00h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

10.6.1.10 Device Control Base Address Register

This read/write register programs the memory base address that accesses the device control registers. See 表

10-13 for a complete description of the register contents.

PCI register offset:

Register type:

10h

Read only, Read/Write

0000 0000h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-13. Device Control Base Address Register Description

BIT

FIELD NAME

ADDRESS

ACCESS

DESCRIPTION

31:12

R or RW Memory address. The memory address field for TSB82AF15-EP uses 20 read/write bits

indicating that 4096 bytes of memory space are required. While less than this is actually

used, typical systems will allocate this space on a 4K boundary. If the BAR0_EN bit (bit 5 at

C8h) is 0, these bits are read only and return zeros when read. If the BAR0_EN bit is 1, these

bits are read/write.

11:4

3

RSVD

R

Reserved. These bits are read only and return 00h when read.

PRE_FETCH

MEM_TYPE

Prefetchable. This bit is read-only 0b indicating that this memory window is not prefetchable.

2:1

Memory type. This field is read-only 00b indicating that this window can be located anywhere

in the 32-bit address space.

0

MEM_IND

R

Memory space indicator. This field returns 0b indicating that memory space is used.

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10.6.1.11 Scratchpad RAM Base Address

This register is used to program the memory address used to access the embedded scratchpad RAM.

PCI register offset:

Register type:

14h

Read only, Read/Write

0000 0000h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-14. Device Control Base Address Register Description

BIT

FIELD NAME

ADDRESS

ACCESS

DESCRIPTION

31:12

R or RW Memory address. The memory address field for TSB82AF15-EP uses 20 read/write bits

indicating that 4096 bytes of memory space are required. If the BAR1_EN bit (bit 6 at C8h) is

0, these bits are read only and return zeros when read. If the BAR1_EN bit is 1, these bits are

read/write.

11:4

3

RSVD

R

Reserved. These bits are read only and return 00h when read.

PRE_FETCH

MEM_TYPE

Prefetchable. This bit is read-only 0b indicating that this memory window is not prefetchable.

2:1

Memory type. This field is read-only 00b indicating that this window can be located anywhere

in the 32-bit address space.

0

MEM_IND

R

Memory space indicator. This field returns 0b indicating that memory space is used.

10.6.1.12 Primary Bus Number Register

This read/write register specifies the bus number of the PCI bus segment that the PCIe interface is connected to.

PCI register offset:

Register type:

18h

Read/Write

00h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

10.6.1.13 Secondary Bus Number Register

This read/write register specifies the bus number of the PCI bus segment that the PCI interface is connected to.

The bridge uses this register to determine how to respond to a type 1 configuration transaction.

PCI register offset:

Register type:

19h

Read/Write

00h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

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10.6.1.14 Subordinate Bus Number Register

This read/write register specifies the bus number of the highest-number PCI bus segment that is downstream of

the bridge. Since the PCI bus is internal and only connects to the 1394a OHCI, this register must always be

equal to the secondary bus number register (offset 19h, see 节 10.6.1.13). The bridge uses this register to

determine how to respond to a type 1 configuration transaction.

PCI register offset:

Register type:

1Ah

Read/Write

00h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

10.6.1.15 Secondary Latency Timer Register

This read/write register specifies the secondary bus latency timer for the bridge, in units of PCI clock cycles.

PCI register offset:

Register type:

1Bh

Read/Write

00h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

10.6.1.16 I/O Base Register

This read/write register specifies the lower limit of the I/O addresses that the bridge forwards downstream. See

表10-15 for a complete description of the register contents.

PCI register offset:

Register type:

1Ch

Read only, Read/Write

01h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

1

表10-15. I/O Base Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

7:4

R

IOBASE

3:0

IOTYPE

I/O type. This field is read-only 1h indicating that the bridge supports 32-bit I/O addressing.

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10.6.1.17 I/O Limit Register

This read/write register specifies the upper limit of the I/O addresses that the bridge forwards downstream. See

表10-16 for a complete description of the register contents.

PCI register offset:

Register type:

1Dh

Read only, Read/Write

01h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

1

表10-16. I/O Limit Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

7:4

IOLIMIT

RW

I/O limit. Defines the top address of the I/O address range that determines when to forward I/O

transactions from one interface to the other. These bits correspond to address bits [15:12] in the

I/O address. The lower 12 bits are assumed to be FFFh. The 16 bits corresponding to address bits

[31:16] of the I/O address are defined in the I/O limit upper 16 bits register (offset 32h, see 节

10.6.1.26).

3:0

IOTYPE

R

I/O type. This field is read-only 1h indicating that the bridge supports 32-bit I/O addressing.

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10.6.1.18 Secondary Status Register

The secondary status register provides information about the PCI bus interface. See 表 10-17 for a complete

description of the register contents.

PCI register offset:

Register type:

1Eh

Read only, Read/Clear

02X0h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

x

0

表10-17. Secondary Status Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15 PAR_ERR

RCU

Detected parity error. This bit reports the detection of an uncorrectable address, attribute, or data

error by the bridge on its internal PCI bus secondary interface. This bit must be set when any of the

following three conditions are true:

The bridge detects an uncorrectable address or attribute error as a potential target.

The bridge detects an uncorrectable data error when it is the target of a write transaction.

The bridge detects an uncorrectable data error when it is the master of a read transaction

(immediate read data).

The bit is set irrespective of the state of bit 0 (PERR_EN) in the bridge control register at offset 3Eh

(see 节10.6.1.30).

0 = Uncorrectable address, attribute, or data error not detected on secondary interface

1 = Uncorrectable address, attribute, or data error detected on secondary interface

Received system error. This bit is set when the bridge detects an SERR assertion.

14 SYS_ERR

13 MABORT

RCU

0 = No error asserted on the PCI interface

1 = SERR asserted on the PCI interface

Received master abort. This bit is set when the PCI interface of the bridge reports the detection of a

master abort termination by the bridge when it is the master of a transaction on its secondary

interface.

0 = Master abort not received on the PCI interface

1 = Master abort received on the PCI interface

12 TABORT_REC

11 TABORT_SIG

RCU

Received target abort. This bit is set when the PCI interface of the bridge receives a target abort.

0 = Target abort not received on the PCI interface

1 = Target abort received on the PCI interface

Signaled target abort. This bit reports the signaling of a target abort termination by the bridge when it

responds as the target of a transaction on its secondary interface.

0 = Target abort not signaled on the PCI interface

1 = Target abort signaled on the PCI interface

10:9 PCI_SPEED

R

DEVSEL timing. These bits are 01b indicating that this is a medium-speed decoding device.

8

DATAPAR

RCU

Master data parity error. This bit is set if the bridge is the bus master of the transaction on the PCI

bus, bit 0 (PERR_EN) in the bridge control register (offset 3Eh see 节10.6.1.30) is set, and the

bridge either asserts PERR on a read transaction or detects PERR asserted on a write transaction.

0 = No data parity error detected on the PCI interface

1 = Data parity error detected on the PCI interface

7

FBB_CAP

R

Fast back-to-back capable. This bit returns a 1b when read indicating that the secondary PCI

interface of bridge supports fast back-to-back transactions.

6

5

RSVD

R

Reserved. Returns 0b when read.

66MHZ

66-MHz capable. The bridge operates at a PCI bus CLK frequency of 66 MHz; therefore, this bit

always returns a 1b.

4:0 RSVD

R

Reserved. Returns 00000b when read.

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10.6.1.19 Memory Base Register

This read/write register specifies the lower limit of the memory addresses that the bridge forwards downstream.

See 表10-18 for a complete description of the register contents.

PCI register offset:

Register type:

20h

Read only, Read/Write

0000h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-18. Memory Base Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:4 MEMBASE

RW

Memory base. Defines the lowest address of the memory address range that determines when to

forward memory transactions from one interface to the other. These bits correspond to address

bits [31:20] in the memory address. The lower 20 bits are assumed to be 00000h.

3:0

RSVD

R

Reserved. Returns 0h when read.

10.6.1.20 Memory Limit Register

This read/write register specifies the upper limit of the memory addresses that the bridge forwards downstream.

See 表10-19 for a complete description of the register contents.

PCI register offset:

Register type:

22h

Read only, Read/Write

0000h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-19. Memory Limit Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:4 MEMLIMIT

RW

Memory limit. Defines the highest address of the memory address range that determines when to

forward memory transactions from one interface to the other. These bits correspond to address

bits [31:20] in the memory address. The lower 20 bits are assumed to be FFFFFh.

3:0

RSVD

R

Reserved. Returns 0h when read.

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10.6.1.21 Prefetchable Memory Base Register

This read/write register specifies the lower limit of the prefetchable memory addresses that the bridge forwards

downstream. See 表10-20 for a complete description of the register contents.

PCI register offset:

Register type:

24h

Read only, Read/Write

0001h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

表10-20. Prefetchable Memory Base Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:4 PREBASE

RW

Prefetchable memory base. Defines the lowest address of the prefetchable memory address

range that determines when to forward memory transactions from one interface to the other.

These bits correspond to address bits [31:20] in the memory address. The lower 20 bits are

assumed to be 00000h. The prefetchable base upper 32 bits register (offset 28h, see 节

10.6.1.23) specifies the bit [63:32] of the 64-bit prefetchable memory address.

3:0

64BIT

R

64-bit memory indicator. These read-only bits indicate that 64-bit addressing is supported for this

memory window.

10.6.1.22 Prefetchable Memory Limit Register

This read/write register specifies the upper limit of the prefetchable memory addresses that the bridge forwards

downstream. See 表10-21 for a complete description of the register contents.

PCI register offset:

Register type:

26h

Read only, Read/Write

0001h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

表10-21. Prefetchable Memory Limit Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:4 PRELIMIT

RW

Prefetchable memory limit. Defines the highest address of the prefetchable memory address

range that determines when to forward memory transactions from one interface to the other.

These bits correspond to address bits [31:20] in the memory address. The lower 20 bits are

assumed to be FFFFFh. The prefetchable limit upper 32 bits register (offset 2Ch, see 节

10.6.1.24) specifies the bit [63:32] of the 64-bit prefetchable memory address.

3:0

64BIT

R

64-bit memory indicator. These read-only bits indicate that 64-bit addressing is supported for this

memory window.

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10.6.1.23 Prefetchable Base Upper 32 Bits Register

This read/write register specifies the upper 32 bits of the prefetchable memory base register. See 表 10-22 for a

complete description of the register contents.

PCI register offset:

Register type:

28h

Read/Write

0000 0000h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-22. Prefetchable Base Upper 32 Bits Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:0 PREBASE

RW

Prefetchable memory base upper 32 bits. Defines the upper 32 bits of the lowest address of the

prefetchable memory address range that determines when to forward memory transactions

downstream.

10.6.1.24 Prefetchable Limit Upper 32 Bits Register

This read/write register specifies the upper 32 bits of the prefetchable memory limit register. See 表 10-23 for a

complete description of the register contents.

PCI register offset:

Register type:

2Ch

Read/Write

0000 0000h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-23. Prefetchable Limit Upper 32 Bits Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:0 PRELIMIT

RW

Prefetchable memory limit upper 32 bits. Defines the upper 32 bits of the highest address of the

prefetchable memory address range that determines when to forward memory transactions

downstream.

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10.6.1.25 I/O Base Upper 16 Bits Register

This read/write register specifies the upper 16 bits of the I/O base register. See 表 10-24 for a complete

description of the register contents.

PCI register offset:

Register type:

30h

Read/Write

0000h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-24. I/O Base Upper 16 Bits Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:0 IOBASE

RW

I/O base upper 16 bits. Defines the upper 16 bits of the lowest address of the I/O address range

that determines when to forward I/O transactions downstream. These bits correspond to address

bits [31:20] in the I/O address. The lower 20 bits are assumed to be 00000h.

10.6.1.26 I/O Limit Upper 16 Bits Register

This read/write register specifies the upper 16 bits of the I/O limit register. See 表 10-25 for a complete

description of the register contents.

PCI register offset:

Register type:

32h

Read/Write

0000h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-25. I/O Limit Upper 16 Bits Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:0 IOLIMIT

RW

I/O limit upper 16 bits. Defines the upper 16 bits of the top address of the I/O address range that

determines when to forward I/O transactions downstream. These bits correspond to address bits

[31:20] in the I/O address. The lower 20 bits are assumed to be FFFFFh.

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10.6.1.27 Capabilities Pointer Register

This read-only register provides a pointer into the PCI configuration header where the PCI power management

block resides. Since the PCI power-management registers begin at 50h, this register is hardwired to 50h.

PCI register offset:

Register type:

34h

Read only

50h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

1

0

1

0

10.6.1.28 Interrupt Line Register

This read/write register is programmed by the system and indicates to the software which interrupt line the

bridge has assigned to it. The default value of this register is FFh, indicating that an interrupt line has not yet

been assigned to the function. Since the bridge does not generate interrupts internally, this register is a

scratchpad register.

PCI register offset:

Register type:

3Ch

Read/Write

FFh

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

1

10.6.1.29 Interrupt Pin Register

The interrupt pin register is read-only 00h indicating that the bridge does not generate internal interrupts. While

the bridge does not generate internal interrupts, it does forward interrupts from the secondary interface to the

primary interface.

PCI register offset:

Register type:

3Dh

Read only

00h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

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10.6.1.30 Bridge Control Register

The bridge control register provides extensions to the command register that are specific to a bridge. See 表

10-26 for a complete description of the register contents.

PCI register offset:

Register type:

3Eh

Read only, Read/Write, Read/Clear

0000h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-26. Bridge Control Register Description

BIT

15:12

11

FIELD NAME

RSVD

ACCESS

DESCRIPTION

R

Reserved. Returns 0h when read.

DTSERR

RW

Discard timer SERR enable. Applies only in conventional PCI mode. This bit enables the

bridge to generate either an ERR_NONFATAL (by default) or ERR_FATAL transaction on

the primary interface when the secondary discard timer expires and a delayed transaction

is discarded from a queue in the bridge. The severity is selectable only if advanced error

reporting is supported.

0 = Do not generate ERR_NONFATAL or ERR_FATAL on the primary interface as a

result of the expiration of the secondary discard timer. Note that an error message

can still be sent if advanced error reporting is supported and bit 10

(DISCARD_TIMER_MASK) in the secondary uncorrectable error mask register

(offset 130h, see 节10.6.2.11) is clear (default).

1 = Generate ERR_NONFATAL or ERR_FATAL on the primary interface if the

secondary discard timer expires and a delayed transaction is discarded from a

queue in the bridges.

10

9

DTSTATUS

SEC_DT

RCU

Discard timer status. This bit indicates if a discard timer expires and a delayed transaction

is discarded.

0 = No discard timer error

1 = Discard timer error

RW selects the number of PCI clocks that the bridge waits for the 1394a OHCI master on

the secondary interface to repeat a delayed transaction request. The counter starts once

the delayed completion (the completion of the delayed transaction on the primary interface)

has reached the head of the downstream queue of the bridge (i.e., all ordering

requirements have been satisfied and the bridge is ready to complete the delayed

transaction with the initiating master on the secondary bus). If the master does not repeat

the transaction before the counter expires, the bridge deletes the delayed transaction from

its queue and sets the discard timer status bit.

0 = Secondary discard timer counts 2¹⁵PCI clock cycles (default).

1 = Secondary discard timer counts 2¹⁰PCI clock cycles.

8

7

PRI_DEC

FBB_EN

R

Primary discard timer. This bit has no meaning in PCIe and is hardwired to 0b.

RW

Fast back-to-back enable. This bit allows software to enable fast back-to-back transactions

on the secondary PCI interface.

0 = Fast back-to-back transactions are disabled (default).

1 = Secondary interface fast back-to-back transactions are enabled.

6

SRST

RW

Secondary bus reset. This bit is set when software wishes to reset all devices downstream

of the bridge. Setting this bit causes the PRST signal on the secondary interface to be

asserted.

0 = Secondary interface is not in reset state (default).

1 = Secondary interface is in the reset state.

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表10-26. Bridge Control Register Description (continued)

BIT

FIELD NAME

ACCESS

DESCRIPTION

5

MAM

RW

Master abort mode. This bit controls the behavior of the bridge when it receives a master

abort or an unsupported request.

0 = Do not report master aborts. Returns FFFF FFFFh on reads and discard data on

writes (default).

1 = Respond with an unsupported request on PCIe when a master abort is received on

PCI. Respond with target abort on PCI when an unsupported request completion on

PCIe is received. This bit also enables error signaling on master abort conditions on

posted writes.

4

3

VGA16

VGA

RW

VGA 16-bit decode. This bit enables the bridge to provide full 16-bit decoding for VGA I/O

addresses. This bit only has meaning if the VGA enable bit is set.

0 = Ignore address bits [15:10] when decoding VGA I/O addresses (default)

1 = Decode address bits [15:10] when decoding VGA I/O addresses

VGA enable. This bit modifies the response by the bridge to VGA compatible addresses. If

this bit is set, the bridge decodes and forwards the following accesses on the primary

interface to the secondary interface (and, conversely, block the forwarding of these

addresses from the secondary to primary interface):

Memory accesses in the range 000A 0000h to 000B FFFFh

I/O addresses in the first 64 KB of the I/O address space (address bits [31:16] are

0000h) and where address bits [9:0] are in the range of 3B0h to 3BBh or 3C0h to

3DFh (inclusive of ISA address aliases –address bits [15:10] may possess any

value and are not used in the decoding)

If this bit is set, forwarding of VGA addresses is independent of the value of bit 2 (ISA), the

I/O address and memory address ranges defined by the I/O base and limit registers, the

memory base and limit registers, and the prefetchable memory base and limit registers of

the bridge. The forwarding of VGA addresses is qualified by bits 0 (IO_ENB) and 1

(MEMORY_ENB) in the command register (offset 04h, see 节10.6.1.3).

0 = Do not forward VGA-compatible memory and I/O addresses from the primary to

secondary interface (addresses previously defined) unless they are enabled for

forwarding by the defined I/O and memory address ranges (default).

1 = Forward VGA-compatible memory and I/O addresses (addresses previously

defined) from the primary interface to the secondary interface (if the I/O enable and

memory enable bits are set) independent of the I/O and memory address ranges

and independent of the ISA enable bit.

2

ISA

RW

ISA enable. This bit modifies the response by the bridge to ISA I/O addresses. This applies

only to I/O addresses that are enabled by the I/O base and I/O limit registers and are in the

first 64 KB of PCI I/O address space (0000 0000h to 0000 FFFFh). If this bit is set, the

bridge blocks any forwarding from primary to secondary of I/O transactions addressing the

last 768 bytes in each 1-KB block. In the opposite direction (secondary to primary), I/O

transactions are forwarded if they address the last 768 bytes in each 1-KB block.

0 = Forward downstream all I/O addresses in the address range defined by the I/O

base and I/O limit registers (default)

1 = Forward upstream ISA I/O addresses in the address range defined by the I/O base

and I/O limit registers that are in the first 64 KB of PCI I/O address space (top 768

bytes of each 1-KB block)

1

SERR_EN

RW

SERR enable. This bit controls forwarding of system error events from the secondary

interface to the primary interface. The bridge forwards system error events when:

This bit is set.

Bit 8 (SERR_ENB) in the command register (offset 04h, see 节10.6.1.3) is set.

SERR is asserted on the secondary interface.

0 = Disable the forwarding of system error events (default)

1 = Enable the forwarding of system error events

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BIT

表10-26. Bridge Control Register Description (continued)

FIELD NAME

PERR_EN

ACCESS

DESCRIPTION

0

RW

Parity error response enable. Controls the bridge's response to data, uncorrectable

address, and attribute errors on the secondary interface. Also, the bridge always forwards

data with poisoning, from conventional PCI to PCIe on an uncorrectable conventional PCI

data error, regardless of the setting of this bit.

0 = Ignore uncorrectable address, attribute, and data errors on the secondary interface

(default)

1 = Enable uncorrectable address, attribute, and data error detection and reporting on

the secondary interface

10.6.1.31 PM Capability ID Register

This read-only register identifies the linked list item as the register for PCI power management. The register

returns 01h when read.

PCI register offset:

Register type:

50h

Read only

01h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

1

10.6.1.32 Next Item Pointer Register

The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This

register reads 80h pointing to the subsystem ID capabilities registers.

PCI register offset:

Register type:

51h

Read only

60h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

1

0

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10.6.1.33 Power Management Capabilities Register

This read-only register indicates the capabilities of the bridge related to PCI power management. See 表 10-27

for a complete description of the register contents.

PCI register offset:

Register type:

52h

Read only

0603h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

表10-27. Power Management Capabilities Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:11

PME_SUPPORT

R

PME support. This 5-bit field indicates the power states from which the bridge may assert

PME. Because the bridge never generates a PME except on a behalf of a secondary device,

this field is read only and returns 00000b.

10

9

D2_SUPPORT

D1_SUPPORT

AUX_CURRENT

DSI

R

This bit returns a 1b when read, indicating that the function supports the D2 device power

state.

This bit returns a 1b when read, indicating that the function supports the D1 device power

state.

8:6

5

3.3 V_AUXauxiliary current requirements. This field returns 000b since the bridge does not

generate PME from D3_cold

.

Device specific initialization. This bit returns 0b when read, indicating that the bridge does

not require special initialization beyond the standard PCI configuration header before a

generic class driver is able to use it.

4

3

RSVD

R

Reserved. Returns 0b when read.

PME_CLK

PM_VERSION

PME clock. This bit returns 0b indicating that the PCI clock is not needed to generate PME.

2:0

Power-management version. If bit 26 (PCI_PM_VERSION_CTRL) in the general control

register (offset D4h, see 节10.6.1.66) is 0b, this field returns 010b indicating revision 1.1

compatibility. If PCI_PM_VERSION_CTRL is 1b, this field returns 011b indicating revision

1.2 compatibility.

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10.6.1.34 Power Management Control/Status Register

This register determines and changes the current power state of the bridge. No internal reset is generated when

transitioning from the D3_hotstate to the D0 state. See 表 10-28 for a complete description of the register

contents.

PCI register offset:

Register type:

54h

Read only, Read/Write

0008h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

表10-28. Power Management Control/Status Register Description

BIT

15

14:13 DATA_SCALE

FIELD NAME

ACCESS

DESCRIPTION

PME_STAT

R

PME status. This bit is read only and returns 0b when read.

Data scale. This 2-bit field returns 00b when read since the bridge does not use the data

register.

12:9

8

DATA_SEL

PME_EN

R

Data select. This 4-bit field returns 0h when read since the bridge does not use the data

register.

RW

PME enable. This bit has no function and acts as scratchpad space. The default value for

this bit is 0b.

7:4

3

RSVD

R

Reserved. Returns 0h when read.

NO_SOFT_RESET

No soft reset. If bit 26 (PCI_PM_VERSION_CTRL) in the general control register (offset

D4h, see 节10.6.1.66) is 0b, this bit returns 0b for compatibility with version 1.1 of the PCI

Power Management Specification. If PCI_PM_VERSION_CTRL is 1b, this bit returns 1b

indicating that no internal reset is generated and the device retains its configuration

context when transitioning from the D3_hotstate to the D0 state.

2

RSVD

R

Reserved. Returns 0b when read.

1:0

PWR_STATE

RW

Power state. This 2-bit field determines the current power state of the function and sets the

function into a new power state. This field is encoded as follows:

00 = D0 (default)

01 = D1

10 = D2

11 = D3_hot

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10.6.1.35 Power Management Bridge Support Extension Register

This read-only register indicates to host software what the state of the secondary bus will be when the bridge is

placed in D3. See 表10-29 for a complete description of the register contents.

PCI register offset:

Register type:

56h

Read only

40h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

1

0

表10-29. PM Bridge Support Extension Register Description

BIT

FIELD NAME

BPCC

ACCESS

DESCRIPTION

7

R

Bus power/clock control enable. This bit indicates to the host software if the bus secondary

clocks are stopped when the bridge is placed in D3. The state of the BPCC bit is controlled

by bit 11 (BPCC_E) in the general control register (offset D4h, see 节10.6.1.66).

0 = Secondary bus clocks are not stopped in D3.

1 = Secondary bus clocks are stopped in D3.

6

BSTATE

RSVD

R

B2/B3 support. This bit is read-only 1b indicating that the bus state in D3 is B2.

Reserved. Returns 00 0000b when read.

5:0

10.6.1.36 Power Management Data Register

The read-only register is not applicable to the bridge and returns 00h when read.

PCI register offset:

Register type:

57h

Read only

00h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

10.6.1.37 MSI Capability ID Register

This read-only register identifies the linked list item as the register for message signaled interrupts capabilities.

The register returns 05h when read.

PCI register offset:

Register type:

60h

Read only

05h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

1

0

1

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10.6.1.38 Next Item Pointer Register

The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This

register reads 80h pointing to the subsystem ID capabilities registers.

PCI register offset:

Register type:

61h

Read only

80h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

1

0

10.6.1.39 MSI Message Control Register

This register controls the sending of MSI messages. See 表 10-30 for a complete description of the register

contents.

PCI register offset:

Register type:

62h

Read only, Read/Write

0088h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

表10-30. MSI Message Control Register Description

BIT

15:8

7

FIELD NAME

RSVD

ACCESS

DESCRIPTION

R

Reserved. Returns 00h when read.

64CAP

64-bit message capability. This bit is read-only 1b indicating that the bridge supports 64-bit

MSI message addressing.

6:4

MM_EN

RW

Multiple message enable. This bit indicates the number of distinct messages that the

bridge is allowed to generate.

000 = 1 message (default)

001 = 2 messages

010 = 4 messages

011 = 8 messages

100 = 16 messages

101 = Reserved

110 = Reserved

111 = Reserved

3:1

0

MM_CAP

MSI_EN

R

Multiple message capabilities. This field indicates the number of distinct messages that the

bridge is capable of generating. This field is read-only 100b, indicating that the bridge can

signal 1 interrupt for each IRQ supported on the serial IRQ stream up to a maximum of 16

unique interrupts.

RW

MSI enable. This bit enables MSI interrupt signaling. MSI signaling must be enabled by

software for the bridge to signal that a serial IRQ has been detected.

0 = MSI signaling is prohibited (default).

1 = MSI signaling is enabled.

备注

Enabling MSI messaging in the TSB82AF15-EP has no effect.

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10.6.1.40 MSI Message Lower Address Register

This register contains the lower 32 bits of the address that a MSI message writes to when a serial IRQ is

detected. See 表10-31 for a complete description of the register contents.

PCI register offset:

Register type:

64h

Read only, Read/Write

0000 0000h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-31. MSI Message Lower Address Register Description

BIT

31:2

1:0

FIELD NAME

ACCESS

DESCRIPTION

ADDRESS

RSVD

RW

R

System specified message address

Reserved. Returns 00b when read.

备注

Enabling MSI messaging in the TSB82AF15-EP has no effect.

10.6.1.41 MSI Message Upper Address Register

This register contains the upper 32 bits of the address that a MSI message writes to when a serial IRQ is

detected. If this register contains 0000 0000h, 32-bit addressing is used; otherwise, 64-bit addressing is used.

PCI register offset:

Register type:

68h

Read/Write

0000 0000h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

备注

Enabling MSI messaging in the TSB82AF15-EP has no effect.

English Data Sheet: SCPS271

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10.6.1.42 MSI Message Data Register

This register contains the data that software programmed the bridge to send when it send a MSI message. See

表10-32 for a complete description of the register contents.

PCI register offset:

Register type:

6Ch

Read/Write

0000h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-32. MSI Message Data Register Description

BIT

FIELD NAME

MSG

ACCESS

DESCRIPTION

15:4

RW

System specific message. This field contains the portion of the message that the bridge

forwards unmodified.

3:0

MSG_NUM

Message number. This portion of the message field may be modified to contain the

message number is multiple messages are enable. The number of bits that are modifiable

depends on the number of messages enabled in the message control register.

1 message = No message data bits can be modified (default).

2 messages = Bit 0 can be modified.

4 messages = Bits 1:0 can be modified.

8 messages = Bits 2:0 can be modified.

16 messages = Bits 3:0 can be modified.

备注

Enabling MSI messaging in the TSB82AF15-EP has no effect.

10.6.1.43 SSID/SSVID Capability ID Register

This read-only register identifies the linked list item as the register for subsystem ID and subsystem vendor ID

capabilities. The register returns 0Dh when read.

PCI register offset:

Register type:

80h

Read only

0Dh

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

1

0

1

10.6.1.44 Next Item Pointer Register

The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This

register reads 90h pointing to the PCI Express capabilities registers.

PCI register offset:

Register type:

81h

Read only

90h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

1

0

1

0

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10.6.1.45 Subsystem Vendor ID Register

This register, used for system and option card identification purposes, may be required for certain operating

systems. This read-only register is initialized through the EEPROM and can be written through the subsystem

alias register. This register shall only be reset by a fundamental reset ( FRST).

PCI register offset:

Register type:

84h

Read only

0000h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

10.6.1.46 Subsystem ID Register

This register, used for system and option card identification purposes, may be required for certain operating

systems. This read-only register is initialized through the EEPROM and can be written through the subsystem

alias register. This register shall only be reset by FRST.

PCI register offset:

Register type:

86h

Read only

0000h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

10.6.1.47 PCI Express Capability ID Register

This read-only register identifies the linked list item as the register for PCIe capabilities. The register returns 10h

when read.

PCI register offset:

Register type:

90h

Read only

10h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

1

0

10.6.1.48 Next Item Pointer Register

The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This

register reads 00h indicating no additional capabilities are supported.

PCI register offset:

Register type:

91h

Read only

00h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

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10.6.1.49 PCI Express Capabilities Register

This read-only register indicates the capabilities of the bridge related to PCIe. See 表 10-33 for a complete

description of the register contents.

PCI register offset:

Register type:

92h

Read only

0071h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

表10-33. PCI Express Capabilities Register Description

BIT

15:9

8

FIELD NAME

ACCESS

DESCRIPTION

Reserved. Returns 000 0000b when read.

Slot implemented. This bit is not valid for the bridge and is read-only 0b.

RSVD

R

SLOT

7:4

DEV_TYPE

Device/port type. This read-only field returns 0111b indicating that the device is a PCIe to

PCI bridge.

3:0

VERSION

R

Capability version. This field returns 1h indicating revision 1 of the PCIe capability.

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10.6.1.50 Device Capabilities Register

This register indicates the device-specific capabilities of the bridge. See 表 10-34 for a complete description of

the register contents.

PCI register offset:

Register type:

94h

Read only

0000 8002

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

表10-34. Device Capabilities Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:28

27:26

RSVD

R

Reserved. Returns 0h when read.

CSPLS

RU

Captured slot power limit scale. The value in this field is programmed by the host by issuing a

Set_Slot_Power_Limit message. When a Set_Slot_Power_Limit message is received, bits 9:8

are written to this field. The value in this field specifies the scale used for the slot power limit.

00 = 1.0x

01 = 0.1x

10 = 0.01x

11 = 0.001x1

25:18

CSPLV

RU

Captured slot power limit value. The value in this field is programmed by the host by issuing a

Set_Slot_Power_Limit message. When a Set_Slot_Power_Limit message is received, bits 7:0

are written to this field. The value in this field in combination with the slot power limit scale

value (bits 27:26) specifies the upper limit of power supplied to the slot. The power limit is

calculated by multiplying the value in this field by the value in the slot power limit scale field.

17:16

15

RSVD

RBER

R

Reserved. Return 000b when read.

Role-based error reporting. This bit is hardwired to 1 indicating that the TSB82AF15-EP

supports role-based error reporting.

14

13

PIP

R

Power indicator present. This bit is hardwired to 0b indicating that a power indicator is not

implemented.

AIP

Attention indicator present. This bit is hardwired to 0b indicating that an attention indicator is

not implemented.

12

ABP

R

Attention button present. This bit is hardwired to 0b indicating that an attention button is not

implemented.

11:9

EP_L1_LAT

RU

Endpoint L1 acceptable latency. This field indicates the maximum acceptable latency for a

transition from L1 to L0 state. This field can be programmed by writing to the L1_LATENCY

field (bits 15:13) in the general control register (offset D4h, see 节10.6.1.66). The default value

for this field is 000b, which indicates a range less than 1s. This field cannot be programmed to

be less than the latency for the PHY to exit the L1 state.

8:6

EP_L0S_LAT

RU

Endpoint L0s acceptable latency. This field indicates the maximum acceptable latency for a

transition from L0s to L0 state. This field can be programmed by writing to the L0s_LATENCY

field (bits 18:16) in the general control register (offset D4h, see 节10.6.1.66). The default value

for this field is 000b, which indicates a range less than 1s. This field cannot be programmed to

be less than the latency for the PHY to exit the L0s state.

5

ETFS

PFS

R

Extended tag field supported. This field indicates the size of the tag field not supported.

4:3

Phantom functions supported. This field is read-only 00b indicating that function numbers are

not used for phantom functions.

2:0

MPSS

R

Maximum payload size supported. This field indicates the maximum payload size that the

device can support for TLPs. This field is encoded as 010b indicating the maximum payload

size for a TLP is 512 bytes.

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10.6.1.51 Device Control Register

The device control register controls PCIe device-specific meters. See 表 10-35 for a complete description of the

register contents.

PCI register offset:

Register type:

98h

Read only, Read/Write

2800h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

表10-35. Device Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15

CFG_RTRY_ENB

RW

Configuration retry status enable. When this read/write bit is set to 1b, the bridge returns a

completion with completion retry status on PCIe if a configuration transaction forwarded to the

secondary interface did not complete within the implementation specific time-out period. When

this bit is set to 0b, the bridge does not generate completions with completion retry status on

behalf of configuration transactions. The default value of this bit is 0b.

14:12

MRRS

RW

Maximum read request size. This field is programmed by host software to set the maximum

size of a read request that the bridge can generate. The bridge uses this field in conjunction

with the cache line size register (offset 0Ch, see 节10.6.4.6) to determine how much data to

fetch on a read request. This field is encoded as:

000 = 128B

001 = 256B

010 = 512B (default)

011 = 1024B

100 = 2048B

101 = 4096B

110 = Reserved

111 = Reserved

11

ENS

RW

Enable no snoop. Controls the setting of the no snoop flag within the TLP header for upstream

memory transactions mapped to any traffic class mapped to a virtual channel (VC) other than

VC0 through the upstream decode windows.

0 = No snoop field is 0b.

1 = No snoop field is 1b (default).

10*

APPE

Auxiliary power PM enable. This bit has no effect in the bridge.

0 = AUX power is disabled (default).

1 = AUX power is enabled.

9

8

PFE

R

Phantom function enable. Since the bridge does not support phantom functions, this bit is

read-only 0b.

ETFE

MPS

Extended tag field enable. Since the bridge does not support extended tags, this bit is read-

only 0b.

7:5

RW

Maximum payload size. This field is programmed by host software to set the maximum size of

posted writes or read completions that the bridge can initiate. This field is encoded as:

000 = 128B (default)

001 = 256B

010 = 512B

011 = 1024B

100 = 2048B

101 = 4096B

110 = Reserved

111 = Reserved

4

3

ERO

R

Enable relaxed ordering. Since the bridge does not support relaxed ordering, this bit is read-

only 0b.

URRE

RW

Unsupported request reporting enable. If this bit is set, the bridge sends an ERR_NONFATAL

message to the root complex when an unsupported request is received.

0 = Do not report unsupported requests to the root complex (default)

1 = Report unsupported requests to the root complex

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表10-35. Device Control Register Description (continued)

BIT

FIELD NAME

ACCESS

DESCRIPTION

2

FERE

RW

Fatal error reporting enable. If this bit is set, the bridge is enabled to send ERR_FATAL

messages to the root complex when a system error event occurs.

0 = Do not report fatal errors to the root complex (default)

1 = Report fatal errors to the root complex

1

0

NFERE

CERE

RW

Nonfatal error reporting enable. If this bit is set, the bridge is enabled to send

ERR_NONFATAL messages to the root complex when a system error event occurs.

0 = Do not report nonfatal errors to the root complex (default)

1 = Report nonfatal errors to the root complex

Correctable error reporting enable. If this bit is set, the bridge is enabled to send ERR_COR

messages to the root complex when a system error event occurs.

0 = Do not report correctable errors to the root complex (default)

1 = Report correctable errors to the root complex

10.6.1.52 Device Status Register

The device status register provides PCIe device specific information to the system. See 表 10-36 for a complete

description of the register contents.

PCI register offset:

Register type:

9Ah

Read only

0000h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-36. Device Status Register Description

DESCRIPTION

BIT

15:6

5

FIELD NAME

ACCESS

RSVD

PEND

R

Reserved. Returns 00 0000 0000b when read.

RU

Transaction pending. This bit is set when the bridge has issued a nonposted transaction that has

not been completed.

4

3

APD

URD

RU

AUX power detected. This bit indicates that AUX power is present.

0 = No AUX power detected

1 = AUX power detected

RCU

Unsupported request detected. This bit is set by the bridge when an unsupported request is

received.

2

1

0

FED

RCU

Fatal error detected. This bit is set by the bridge when a fatal error is detected.

Nonfatal error detected. This bit is set by the bridge when a nonfatal error is detected.

Correctable error detected. This bit is set by the bridge when a correctable error is detected.

NFED

CED

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10.6.1.53 Link Capabilities Register

The link capabilities register indicates the link-specific capabilities of the bridge. See 表 10-37 for a complete

description of the register contents.

PCI register offset:

Register type:

9Ch

Read only

0006 XC11h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

1

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

x

1

0

1

0

1

表10-37. Link Capabilities Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:24 PORT_NUM

R

Port number. This field indicates port number for the PCIe link. This field is read-only 00h

indicating that the link is associated with port 0.

23:19 RSVD

R

Reserved. Return 00 0000b when read.

18

CLK_PM

Clock power management. This bit is hardwired to 1 to indicate that TSB82AF15-EP supports

clock power management through CLKREQ protocol.

17:15 L1_LATENCY

R

L1 exit latency. This field indicates the time that it takes to transition from the L1 state to the L0

state. Bit 6 (CCC) in the link control register (offset A0h, see 节10.6.1.54) equals 1b for a

common clock and equals 0b for an asynchronous clock.

For a common reference clock, the value of this field is determined by bits 20:18

(L1_EXIT_LAT_ASYNC) of the control and diagnostic register 1 (offset C4h, see 节10.6.1.63).

For an asynchronous reference clock, the value of this field is determined by bits 17:15

(L1_EXIT_LAT_COMMON) of the control and diagnostic register 1 (offset C4h, see 节

10.6.1.63).

14:12 L0S_LATENCY

R

L0s exit latency. This field indicates the time that it takes to transition from the L0s state to the

L0 state. Bit 6 (CCC) in the link control register (offset A0h, see 节10.6.1.54) equals 1b for a

common clock and equals 0b for an asynchronous clock.

For a common reference clock, the value of 011b indicates that the L1 exit latency falls between

256 ns to less than 512 ns.

For an asynchronous reference clock, the value of 100b indicates that the L1 exit latency falls

between 512 ns to less than 1 µs.

11:10 ASLPMS

Active-state link PM support. This field indicates the level of active-state power management

that the bridge supports. The value 11b indicates support for both L0s and L1 through active-

state power management.

9:4

3:0

MLW

MLS

R

Maximum link width. This field is encoded 00 0001b to indicate that the bridge only supports a

1× PCIe link.

Maximum link speed. This field is encoded 1h to indicate that the bridge supports a maximum

link speed of 2.5 Gb/s.

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10.6.1.54 Link Control Register

The link control register controls link-specific behavior. See 表 10-38 for a complete description of the register

contents.

PCI register offset:

Register type:

A0h

Read only, Read/Write

0000h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-38. Link Control Register Description

BIT

15:9

8

FIELD NAME

RSVD

ACCESS

DESCRIPTION

RW

Reserved. Returns 00h when read.

CPM_EN

Clock power management enable. This bit is used to enable TSB82AF15-EP to use

CLKREQ for clock power management

0 = Clock power management is disabled and TSB82AF15-EP shall hold the

CLKREQ signal low.

1 = Clock power management is enabled and TSB82AF15-EP is permitted to use

the CLKREQ signal to allow the REFCLK input to be stopped.

7

6

ES

RW

Extended synch. This bit forces the bridge to extend the transmission of FTS ordered sets

and an extra TS2 when exiting from L1 prior to entering to L0.

0 = Normal synch (default)

1 = Extended synch

CCC

Common clock configuration. When this bit is set, it indicates that the bridge and the

device at the opposite end of the link are operating with a common clock source. A value

of 0b indicates that the bridge and the device at the opposite end of the link are operating

with se te reference clock sources. The bridge uses this common clock configuration

information to report the correct L0s and L1 exit latencies.

0 = Reference clock is asynchronous (default).

1 = Reference clock is common.

5

4

3

RL

R

Retrain link. This bit has no function and is read-only 0b.

Link disable. This bit has no function and is read-only 0b.

LD

RCB

RW

Read completion boundary. This bit is an indication of the RCB of the root complex. The

state of this bit has no effect on the bridge, since the RCB of the bridge is fixed at 128

bytes.

0 = 64 bytes (default)

1 = 128 bytes

2

RSVD

R

Reserved. Returns 0b when read.

1:0

ASLPMC

RW

Active-state link PM control. This field enables and disables the active-state PM.

00 = Active-state PM disabled (default)

01 = L0s entry enabled

10 = L1 entry enabled

11 = L0s and L1 entry enabled

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10.6.1.55 Link Status Register

The link status register indicates the current state of the PCIe link. See 表10-39 for a complete description of the

register contents.

PCI register offset:

Register type:

A2h

Read only

1011h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

1

表10-39. Link Status Register Description

BIT

15:13

12

FIELD NAME

RSVD

ACCESS

DESCRIPTION

R

Reserved. Returns 000b when read.

SCC

Slot clock configuration. This bit indicates that the bridge uses the same physical reference

clock that the platform provides on the connector.

0 = Independent 125-MHz reference clock is used. This mode is not supported. This

bit should not be cleared

1 = Common 100-MHz reference clock is used. REFCLK_SEL must be driven logic

low to enable 100Mhz differential clock.

11

10

LT

R

Link training. This bit has no function and is read-only 0b.

TE

Retrain link. This bit has no function and is read-only 0b.

9:4

3:0

NLW

LS

Negotiated link width. This field is read-only 00 0001b indicating the lane width is 1×.

Link speed. This field is read-only 1h indicating the link speed is 2.5 Gb/s.

10.6.1.56 Serial-Bus Data Register

The serial-bus data register reads and writes data on the serial-bus interface. Write data is loaded into this

register prior to writing the serial-bus slave address register (offset B2h, see 节 10.6.1.58) that initiates the bus

cycle. When reading data from the serial bus, this register contains the data read after bit 5 (REQBUSY) of the

serial-bus control and status register (offset B3h, see 节10.6.1.59) is cleared. This register shall only be reset by

FRST.

PCI register offset:

Register type:

B0h

Read/Write

00h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

10.6.1.57 Serial-Bus Word Address Register

The value written to the serial-bus word address register represents the word address of the byte being read

from or written to the serial-bus device. The word address is loaded into this register prior to writing the serial-

bus slave address register (offset B2h, see 节 10.6.1.58) that initiates the bus cycle. This register shall only be

reset by FRST.

PCI register offset:

Register type:

B1h

Read/Write

00h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

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10.6.1.58 Serial-Bus Slave Address Register

The serial-bus slave address register indicates the slave address of the device being targeted by the serial-bus

cycle. This register also indicates if the cycle is a read or a write cycle. Writing to this register initiates the cycle

on the serial interface. See 表10-40 for a complete description of the register contents.

PCI register offset:

Register type:

B2h

Read/Write

00h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

表10-40. Serial-Bus Slave Address Register Descriptions

BIT

FIELD NAME

ACCESS

DESCRIPTION

7:1⁽¹⁾

SLAVE_ADDR

RW

Serial-bus slave address. This 7-bit field is the slave address for a serial-bus read or write

transaction. The default value for this field is 000 0000b.

0⁽¹⁾

RW_CMD

RW

Read/write command. This bit determines if the serial-bus cycle is a read or a write cycle.

0 = A single byte write is requested (default).

1 = A single byte read is requested.

(1) These bits shall only be reset by a fundamental reset ( FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

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10.6.1.59 Serial-Bus Control and Status Register

The serial-bus control and status register controls the behavior of the serial-bus interface. This register also

provides status information about the state of the serial bus. See 表 10-41 for a complete description of the

register contents.

PCI register offset:

Register type:

B3h

Read only, Read/Write, Read/Clear

00h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

表10-41. Serial-Bus Control and Status Register Description

BIT

FIELD NAME

PROT_SEL

ACCESS

DESCRIPTION

Protocol select. This bit selects the serial-bus address mode used.

0 = Slave address and word address are sent on the serial bus (default

1 = Only the slave address is sent on the serial bus.

Reserved. Returns 0b when read.

7⁽¹⁾

RW

6

RSVD

R

5⁽¹⁾

REQBUSY

RU

Requested serial-bus access busy. This bit is set when a software-initiated serial-bus cycle

is in progress.

0 = No serial-bus cycle

1 = Serial-bus cycle in progress

4⁽¹⁾

ROMBUSY

SBDETECT

RU

Serial EEPROM access busy. This bit is set when the serial EEPROM circuitry in the

bridge is downloading register defaults from a serial EEPROM.

0 = No EEPROM activity

1 = EEPROM download in progress

3⁽¹⁾

RWU

Serial EEPROM access busy. This bit is set when the serial EEPROM circuitry in the

bridge is downloading register defaults from a serial EEPROM.

Note: A serial EEPROM is only detected once following PERST.

0 = No EEPROM present, EEPROM load process does not happen. GPIO4//SCL

and GPIO5//SDA terminals are configured as GPIO signals.

1 = EEPROM present, EEPROM load process takes place. GPIO4//SCL and

GPIO5//SDA terminals are configured as serial-bus signals.

2⁽¹⁾

1⁽¹⁾

0⁽¹⁾

SBTEST

RW

RCU

Serial-bus test. This bit is used for internal test purposes. This bit controls the clock source

for the serial interface clock.

0 = Serial-bus clock at normal operating frequency ~60 kHz (default)

1 = Serial-bus clock frequency increased for test purposes ~4 MHz

SB_ERR

ROM_ERR

Serial-bus error. This bit is set when an error occurs during a software-initiated serial-bus

cycle.

0 = No error

1 = Serial-bus error

Serial EEPROM load error. This bit is set when an error occurs while downloading

registers from serial EEPROM.

0 = No error

1 = EEPROM load error

(1) These bits shall only be reset by a fundamental reset ( FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

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10.6.1.60 GPIO Control Register

This register controls the direction of the eight GPIO terminals. This register has no effect on the behavior of

GPIO terminals that are enabled to perform secondary functions. The secondary functions share GPIO4 (SCL)

and GPIO5 (SDA). See 表10-42 for a complete description of the register contents.

PCI register offset:

Register type:

B4h

Read only, Read/Write

0000h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-42. GPIO Control Register Description

BIT

15:8

7⁽¹⁾

FIELD NAME

RSVD

ACCESS

DESCRIPTION

R

Reserved. Return 00h when read.

GPIO7_DIR

GPIO6_DIR

GPIO5_DIR

GPIO4_DIR

GPIO3_DIR

GPIO2_DIR

GPIO1_DIR

GPIO0_DIR

RW

GPIO 7 data direction. This bit selects whether GPIO7 is in input or output mode.

0 = Input (default)

1 = Output

6⁽¹⁾

5⁽¹⁾

4⁽¹⁾

3⁽¹⁾

2⁽¹⁾

1⁽¹⁾

0⁽¹⁾

RW

GPIO 6 data direction. This bit selects whether GPIO6 is in input or output mode.

0 = Input (default)

1 = Output

GPIO 5 data direction. This bit selects whether GPIO5 is in input or output mode.

0 = Input (default)

1 = Output

GPIO 4 data direction. This bit selects whether GPIO4 is in input or output mode.

0 = Input (default)

1 = Output

GPIO 3 data direction. This bit selects whether GPIO3 is in input or output mode.

0 = Input (default)

1 = Output

GPIO 2 data direction. This bit selects whether GPIO2 is in input or output mode.

0 = Input (default)

1 = Output

GPIO 1 data direction. This bit selects whether GPIO1 is in input or output mode.

0 = Input (default)

1 = Output

GPIO 0 data direction. This bit selects whether GPIO0 is in input or output mode.

0 = Input (default)

1 = Output

(1) These bits shall only be reset by a fundamental reset ( FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

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10.6.1.61 GPIO Data Register

This register reads the state of the input-mode GPIO terminals and changes the state of the output-mode GPIO

terminals. Writing to a bit that is in input mode or is enabled for a secondary function is ignored. The secondary

functions share GPIO4 (SCL) and GPIO5 (SDA). The default value at power up depends on the state of the

GPIO terminals as they default to general-purpose inputs. See 表10-43 for a complete description of the register

contents.

PCI register offset:

Register type:

B6h

Read only, Read/Write

00XXh

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

x

表10-43. GPIO Data Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:8 RSVD

R

Reserved

7⁽¹⁾

6⁽¹⁾

5⁽¹⁾

4⁽¹⁾

3⁽¹⁾

2⁽¹⁾

1⁽¹⁾

0⁽¹⁾

GPIO7_DATA

RW

GPIO 7 data. This bit reads the state of GPIO7 when in input mode or changes the state of

GPIO7 when in output mode.

GPIO6_DATA

GPIO5_DATA

GPIO4_DATA

GPIO3_DATA

GPIO2_DATA

GPIO1_DATA

GPIO0_DATA

RW

GPIO 6 data. This bit reads the state of GPIO6 when in input mode or changes the state of

GPIO6 when in output mode.

GPIO 5 data. This bit reads the state of GPIO5 when in input mode or changes the state of

GPIO5 when in output mode.

GPIO 4 data. This bit reads the state of GPIO4 when in input mode or changes the state of

GPIO4 when in output mode.

GPIO 3 data. This bit reads the state of GPIO3 when in input mode or changes the state of

GPIO3 when in output mode.

GPIO 2 data. This bit reads the state of GPIO2 when in input mode or changes the state of

GPIO2 when in output mode.

GPIO 1 data. This bit reads the state of GPIO1 when in input mode or changes the state of

GPIO1 when in output mode.

GPIO 0 data. This bit reads the state of GPIO0 when in input mode or changes the state of

GPIO0 when in output mode.

(1) These bits shall only be reset by a fundamental reset ( FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

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10.6.1.62 Control and Diagnostic Register 0

The contents of this register are used for monitoring status and controlling behavior of the bridge. See 表 10-44

for a complete description of the register contents. It is recommended that all values within this register be left at

the default value. Improperly programming fields in this register may cause interoperability or other problems.

PCI register offset:

Register type:

C0h

Read/Write

0000 0000h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-44. Control and Diagnostic Register 0 Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

This field contains the captured primary bus number.

This field contains the captured primary device number.

31:24⁽¹⁾PRI_BUS_NUM

R

23:19⁽¹⁾PRI_DEVICE_NUM

18

ALT_ERROR_REP

DIS_BRIDGE_PME

RW

Alternate error reporting. This bit controls the method that the TSB82AF15-EP uses for

error reporting.

0 = Advisory nonratal error reporting supported (default)

1 = Advisory nonfatal error reporting not supported

17⁽²⁾

RW

Disable bridge PME input

0 = PME input signal to the bridge is enabled and connected to the PME signal

from the 1394 OHCI function (default).

1 = PME input signal to the bridge is disabled.

Disable OHCI_PME

16⁽²⁾

DIS_OHCI_PME

0 = OHCI_PME pin is enabled and connected to the PME signal from the 1394

OHCI function (default).

1 = OHCI_PME pin is disabled.

15:14⁽¹⁾FIFO_SIZE

13:12 RSVD

RW

R

FIFO size. This field contains the maximum size (in DW) of the FIFO.

Reserved. Returns 00b when read.

11

ALLOW_CFG_ANY_FN

RW

Allow configuration access to any function. When this bit is set, the bridge shall respond

to configuration accesses to any function number.

10

RETURN_PW_CREDITS

RW

Return PW packet credits. When this bit is set, the bridge shall return all the PW packet

credits.

9

8

RSVD

R

Reserved. Returns 0b when read.

RETURN_CPL_CREDITS

RW

Return completion credits. When this bit is set, the bridge shall return all completion

credits immediately.

7

EN_CACHE_LINE_CHECK

RW

Enable cache line check

0 = Bridge shall use side-band signals to determine the transaction size (default).

1 = Bridge shall use the cache line size register to determine the transaction size.

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BIT

表10-44. Control and Diagnostic Register 0 Description (continued)

FIELD NAME

ACCESS

DESCRIPTION

6⁽¹⁾

PREFETCH_4X

RW

Prefetch 4× enable

0 = Bridge prefetches up to two cache lines, as defined in the cache line size

register (offset 0Ch, see 节10.6.4.6) for upstream memory read multiple (MRM)

transactions (default).

1 = Bridge prefetches up to four cache lines, as defined in the cache line size

register (offset 0Ch, see 节10.6.4.6) for upstream memory read multiple (MRM)

transactions.

Note: When this bit is set and the FORCE_MRM bit in the general control register is set,

both upstream memory read multiple transactions and upstream memory transactions

prefetch up to four cache lines.

Note: When the READ_PREFETCH_DIS bit in the general control register is set, this bit

has no effect and only one DWORD will be fetched on a burst read.

This bit only affects the TSB82AF15-EP design when the EN_CACHE_LINE_CHECK bit

is set.

5:4⁽¹⁾

UP_REQ_BUF_VALUE

UP_REQ_BUF_CTRL

RW

PCI upstream req-res buffer threshold value. The value in this field controls the buffer

space that must be available for the device to accept a PCI bus transaction. If the cache

line size is not valid, the device will use eight DW for calculating the threshold value.

00 = 1 cache line + 4 DW (default)

01 = 1 cache line + 8 DW

10 = 1 cache line + 12 DW

11 = 2 cache lines + 4 DW

3⁽¹⁾

PCI upstream req-res buffer threshold control. This bit enables the PCI upstream req-res

buffer threshold control mode of the bridge.

0 = PCI upstream req-res buffer threshold control mode disabled (default)

1 = PCI upstream req-res buffer threshold control mode enabled

2⁽¹⁾

1⁽¹⁾

0

CFG_ACCESS_MEM_

REG

RW

R

Configuration access to memory-mapped registers. When this bit is set, the bridge

allows configuration access to memory-mapped configuration registers.

RSVD

Reserved. Bit 1 defaults to 0b. If this register is programmed via EEPROM or another

mechanism, the value written into this field must be 0b.

RSVD

Reserved. Returns 0b when read.

(1) These bits shall only be reset by a fundamental reset ( FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

(2) These bits are reset only by a global reset ( GRST) or the internally generated power-on reset.

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10.6.1.63 Control and Diagnostic Register 1

The contents of this register are used for monitoring status and controlling behavior of the bridge. See 表 10-45

for a complete description of the register contents. It is recommended that all values within this register be left at

the default value. Improperly programming fields in this register may cause interoperability or other problems.

PCI register offset:

Register type:

C4h

Read/Write

0012 0108h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

1

0

1

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

表10-45. Control and Diagnostic Register 1 Description

BIT

FIELD NAME

RSVD

ACCESS

DESCRIPTION

32:21

R

Reserved. Returns 000h when read.

20:18⁽¹⁾L1_EXIT_LAT_

ASYNC

RW

L1 exit latency for asynchronous clock. When bit 6 (CCC) of the link control register (offset

A0h, see 节10.6.1.54) is set, the value in this field is mirrored in bits 17:15 (L1_LATENCY)

field in the link capabilities register (offset 9Ch, see 节10.6.1.53). This field defaults to 100b.

17:15⁽¹⁾L1_EXIT_LAT_

COMMON

RW

L1 exit latency for common clock. When bit 6 (CCC) of the link control register (offset A0h, see

节10.6.1.54) is clear, the value in this field is mirrored in bits 17:15 (L1_LATENCY) field in the

link capabilities register (offset 9Ch, see 节10.6.1.53). This field defaults to 100b.

14:11⁽¹⁾RSVD

RW

Reserved. Bits 14:11 default to 0000b. If this register is programmed via EEPROM or another

mechanism, the value written into this field must be 0000b.

10⁽¹⁾

9:6⁽¹⁾

5:2⁽¹⁾

1:0⁽¹⁾

SBUS_RESET_

MASK

Secondary bus reset bit mask. When this bit is set, the bridge masks the reset caused by bit 6

(SRST) of the bridge control register (offset 3Eh, see 节10.6.1.30). This bit defaults to 0b.

L1ASPM_TIMER

L0s_TIMER

RSVD

L1ASPM entry timer. This field specifies the value (in 512-ns ticks) of the L1ASPM entry timer.

This field defaults to 0100b.

L0s entry timer. This field specifies the value (in 62.5-MHz clock ticks) of the L0s entry timer.

This field defaults to 0010b.

Reserved. Bits 1:0 default to 00b. If this register is programmed via EEPROM or another

mechanism, the value written into this field must be 00b.

(1) These bits shall only be reset by a fundamental reset ( FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

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10.6.1.64 PHY Control and Diagnostic Register 2

The contents of this register are used for monitoring status and controlling behavior of the PHY macro for

diagnostic purposes. See 表 10-46 for a complete description of the register contents. It is recommended that all

values within this register be left at the default value. Improperly programming fields in this register may cause

interoperability or other problems.

PCI register offset:

Register type:

C8h

Read/Write

3214 2000h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

1

0

1

0

1

0

1

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

表10-46. Control and Diagnostic Register 2 Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:24⁽¹⁾N_FTS_ ASYNC_

CLK

RW

N_FTS for asynchronous clock. When bit 6 (CCC) of the link control register (offset A0h,

see 节10.6.1.54) is clear, the value in this field is the number of FTS that are sent on a

transition from L0s to L0. This field shall default to 32h.

23:16⁽¹⁾N_FTS_COMMON_

CLK

RW

N_FTS for common clock. When bit 6 (CCC) of the link control register (offset A0h, see 节

10.6.1.54) is set, the value in this field is the number of FTS that are sent on a transition

from L0s to L0. This field defaults to 14h.

15:13 PHY_REV

12:8⁽¹⁾LINK_NUM

R

PHY revision number

Link number

RW

7

6

5

EN_L2_PWR_

SAVE

Enable L2 power savings

0 = Power savings not enabled when in L2

1 = Power savings enabled when in L2

BAR1_EN

BAR0_EN

RW

BAR 1 enable

0 = BAR at offset 14h is disabled (default).

1 = BAR at offset 14h is enabled.

BAR 0 enable

0 = BAR at offset 10h is disabled (default).

1 = BAR at offset 10h is enabled.

4

3

2

1

REQ_RECOVERY

REQ_RECONFIG

REQ_HOT_RESET

RW

REQ_RECOVERY to LTSSM

REQ_RECONFIGURE to LTSSM

REQ_HOT_RESET to LTSSM

REQ_DIS_

REQ_DISABLE_SCRAMBLER to LTSSM

SCRAMBLER

0

REQ_LOOPBACK

RW

REQ_LOOPBACK to LTSSM

(1) These bits shall only be reset by a fundamental reset ( FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

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10.6.1.65 Subsystem Access Register

The contents of this read/write register are aliased to the subsystem vendor ID and subsystem ID registers at

PCI offsets 84h and 86h. See 表10-47 for a complete description of the register contents.

PCI register offset:

Register type:

D0h

Read/Write

0000 0000h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-47. Subsystem Access Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:16⁽¹⁾SubsystemID

RW

Subsystem ID. The value written to this field is aliased to the subsystem ID register at PCI

offset 86h (see 节10.6.1.46).

15:0⁽¹⁾

SubsystemVendorID

RW

Subsystem vendor ID. The value written to this field is aliased to the subsystem vendor ID

register at PCI offset 84h (see 节10.6.1.45).

(1) These bits shall only be reset by a fundamental reset ( FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

10.6.1.66 General Control Register

This read/write register controls various functions of the bridge. See 表 10-48 for a complete description of the

register contents.

PCI register offset:

Register type:

D4h

Read only, Read/Write

8600 025Fh

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

1

0

1

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

1

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表10-48. General Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:30⁽¹⁾CFG_RETRY_

CNTR

RW

Configuration retry counter. Configures the amount of time that a configuration request must be

retried on the secondary PCI bus before it may be completed with configuration retry status on

the PCIe side.

00 = 25 µs

01 = 1 ms

10 = 25 ms (default)

11 = 50 ms

29:28⁽¹⁾ASPM_CTRL_

DEF_OVRD

RW

Active-state power-management control default override. These bits are used to determine the

power up default for bits 1:0 of the link control register in the PCIe capability structure.

00 = Power-on default indicates that the active-state power management is disabled (00b)

01 = (default).

10 = Power-on default indicates that the active-state power management is enabled for

11 = L0s (01b).

Power-on default indicates that the active-state power management is enabled for

L1s (10b).

Power-on default indicates that the active-state power management is enabled for

L0s and L1s (11b).

27⁽²⁾

26⁽¹⁾

LOW_POWER _

EN

RW

Low-power enable. When this bit is set, the half-ampitude, no preemphasis mode for the PCIe TX

drivers is enabled. The default for this bit is 0b.

PCI_PM_

VERSION_ CTRL

PCI power management version control. This bit controls the value reported in bits 2:0

(PM_VERSION) in the power management capabilities register (offset 52h, see 节10.6.1.33). It

also controls the value of bit 3 (NO_SOFT_RESET) in the power management control/status

register (offset 54h, see 节10.6.1.34).

0 = Version fields reports 010b and NO_SOFT_RESET reports 0b for Power

Management 1.1 compliance.

1 = Version fields reports 011b and NO_SOFT_RESET reports 1b for Power

Management 1.2 compliance (default).

25⁽¹⁾

STRICT_

PRIORITY_EN

RW

Strict priority enable. When this bit is 0, the default LOW_PRIORITY_COUNT will be 001. When

this bit is 1, the default LOW_PRIORITY_COUNT will be 000. This default value for this bit is 1.

When this bit is set and the LOW_PRIORITY_COUNT is 000, meaning that strict priority VC

arbitration is used and the extended virtual channel always receives priority over VC0 at the PCIe

port.

0 = Default LOW_PRIORITY_COUNT is 001b.

1 = Default LOW_PRIORITY_COUNT is 000b (default).

Force memory read multiple

24⁽¹⁾

FORCE_MRM

RW

0 = Memory read multiple transactions are disabled (default).

1 = All upstream memory read transactions initiated on the PCI bus are treated as though

they are memory read multiple transactions in which prefetching is supported for the

transaction. This bit shall only affect the TSB82AF15-EP design when the

EN_CACHE_LINE_CHECK bit in the TL control and diagnostic register is set.

23⁽¹⁾

CPM_EN_

DEF_OVRD

Clock power-management enable default override. This bit is used to determine the power up

default for bit 8 of the link control register in the PCIe capability structure.

0 = Power-on default indicates that clock power management is disabled (00b) (default).

1 = Power-on default indicates that clock power management is enabled for L0s and L1

(11b).

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表10-48. General Control Register Description (continued)

BIT

FIELD NAME

ACCESS

DESCRIPTION

22:20⁽¹⁾POWER_ OVRD

RW

Power override. This bit field determines how the bridge responds when the slot power limit is

less than the amount of power required by the bridge and the devices behind the bridge. This

field shall be hardwired to 000b since TSB82AF15-EP does not support slot power limit

functionality.

000 = Ignore slot power limit (default)

001 = Assert the PWR_OVRD terminal

010 = Disable secondary clocks selected by the clock mask register

011 = Disable secondary clocks selected by the clock mask register and assert the

PWR_OVRD terminal

100 = Respond with unsupported request to all transactions except for configuration

transactions (type 0 or type 1) and set slot power limit messages

101, 110, 111 = Reserved

19⁽¹⁾

READ_

PREFETCH_ DIS

RW

Read prefetch disable. This bit controls the prefetch functionality on PCI memory read

transactions.

0 = Prefetch to the next cache line boundary on a burst read (default)

1 = Fetch only a single DWORD on a burst read

Note: When this bit is set, the PREFETCH_4X bit in the TL control and diagnostic register shall

have no effect on the design. This bit shall only affect the TSB82AF15-EP when the

EN_CACHE_LINE_CHECK bit in the TL control and diagnostic register is set.

18:16⁽¹⁾L0s_LATENCY

RW

L0s maximum exit latency. This field programs the maximum acceptable latency when exiting the

L0s state. This sets bits 8:6 (EP_L0S_LAT) in the device capabilities register (offset 94h, see 节

10.6.1.50).

000 = Less than 64 ns (default)

001 = 64 ns up to less than 128 ns

010 = 128 ns up to less than 256 ns

011 = 256 ns up to less than 512 ns

100 = 512 ns up to less than 1 µs

101 = 1 s up to less than 2 µs

110 = 2µs to 4 µs

111 = More than 4 µs

15:13⁽¹⁾L1_LATENCY

RW

L1 maximum exit latency. This field programs the maximum acceptable latency when exiting the

L1 state. This sets bits 11:9 (EP_L1_LAT) in the device capabilities register (offset 94h, see 节

10.6.1.50).

000 = Less than 1 µs (default)

001 = 1 µs up to less than 2 µs

010 = 2 µs up to less than 4 µs

011 = 4 µs up to less than 8 µs

100 = 8 µs up to less than 16 µs

101 = 6 µs up to less than 32 µs

110 = 32 µs to 64 µs

111 = More than 64 µs

12⁽¹⁾

VC_CAP_EN

BPCC_E

R

VC capability structure enable. This bit enables the VC capability structure by changing the next

offset field of the advanced error reporting capability register at offset 102h. This bit is a read only

0b indicating that the VC capability structure is permanently disabled.

0 = VC capability structure disabled (offset field = 000h)

1 = VC capability structure enabled (offset field = 150h)

11⁽¹⁾

RW

Bus power clock control enable. This bit controls whether the secondary bus PCI clocks are

stopped when the TSB82AF15-EP is placed in the D3 state. It is assumed that if the secondary

bus clocks are required to be active that a reference clock continues to be provided on the PCIe

interface.

0 = Secondary bus clocks are not stopped in D3 (default).

1 = Secondary bus clocks are stopped on D3.

10⁽²⁾

BEACON_

ENABLE

RW

Beacon enable. This bit controls the mechanism for waking up the physical PCIe link when in L2.

0 = WAKE mechanism is used exclusively. Beacon is not used (default).

1 = Beacon and WAKE mechanisms are used.

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表10-48. General Control Register Description (continued)

BIT

FIELD NAME

ACCESS

DESCRIPTION

9:8⁽¹⁾

MIN_POWER_

SCALE

RW

Minimum power scale. This value is programmed to indicate the scale of bits 7:0

(MIN_POWER_VALUE).

00 = 1.0x

01 = 0.1x

10 = 0.01x (default)

11 = 0.001x

7:0⁽¹⁾

MIN_POWER_

VALUE

RW

Minimum power value. This value is programmed to indicate the minimum power requirements.

This value is multiplied by the minimum power scale field (bits 9:8) to determine the minimum

power requirements for the bridge. The default is 5Fh, indicating that TSB82AF15-EP requires

0.95 W of power. This field can be reprogrammed through an EEPROM or the system BIOS.

(1) These bits shall only be reset by a fundamental reset ( FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

(2) These bits are reset only by a global reset ( GRST) or the internally generated power-on reset.

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10.6.1.67 TI Proprietary Register

This read/write TI proprietary register is located at offset D8h and controls TI proprietary functions. This register

must not be changed from the specified default state. This register shall only be reset by FRST.

PCI register offset:

Register type:

D8h

Read only, Read/Write

00h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

10.6.1.68 TI Proprietary Register

This read/write TI proprietary register is located at offset D9h and controls TI proprietary functions. This register

must not be changed from the specified default state. This register shall only be reset by FRST.

PCI register offset:

Register type:

D9h

Read only, Read/Write

00h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

10.6.1.69 TI Proprietary Register

This read-only TI proprietary register is located at offset DAh and controls TI proprietary functions. This register

must not be changed from the specified default state. This register shall only be reset by FRST.

PCI register offset:

Register type:

DAh

Read only

00h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

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10.6.1.70 Arbiter Control Register

The arbiter control register controls the device's internal arbiter. The arbitration scheme used is a two-tier

rotational arbitration. The device is the only secondary bus master that defaults to the higher-priority arbitration

tier. See 表10-49 for a complete description of the register contents.

PCI register offset:

Register type:

DCh

Read/Write

40h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

1

0

表10-49. Arbiter Control Register Description

BIT

7⁽¹⁾

FIELD NAME

PARK

ACCESS

DESCRIPTION

RW

Bus parking mode. This bit determines where the internal arbiter parks the secondary bus.

When this bit is set, the arbiter parks the secondary bus on the bridge. When this bit is

cleared, the arbiter parks the bus on the last device mastering the secondary bus.

0 = Park the secondary bus on the last secondary bus master (default)

1 = Park the secondary bus on the bridge

6⁽¹⁾

BRIDGE_TIER_SEL

RW

Bridge tier select. This bit determines in which tier the bridge is placed in the arbitration

scheme.

0 = Lowest-priority tier

1 = Highest-priority tier (default)

5:1⁽¹⁾

0⁽¹⁾

RSVD

RW

Reserved. These bits are reserved and must not be changed from their default value of

00000b.

TIER_SEL0

GNT0 tier select. This bit determines in which tier GNT0 is placed in the arbitration

scheme.

0 = Lowest-priority tier (default)

1 = Highest-priority tier

(1) These bits shall only be reset by a fundamental reset ( FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

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10.6.1.71 Arbiter Request Mask Register

The arbiter request mask register enables and disables support for requests from specific masters on the

secondary bus. The arbiter request mask register also controls if a request input is automatically masked on an

arbiter time-out. See 表10-50 for a complete description of the register contents.

PCI register offset:

Register type:

DDh

Read/Write

00h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

表10-50. Arbiter Request Mask Register Description

BIT

7⁽¹⁾

FIELD NAME

ACCESS

DESCRIPTION

ARB_TIMEOUT

RW

Arbiter time-out. This bit enables the arbiter time-out feature. The arbiter time-out is defined

as the number of PCI clocks after the PCI bus has gone idle for a device to assert FRAME

before the arbiter assumes the device will not respond.

0 = Arbiter time disabled (default)

1 = Arbiter time-out set to 16 PCI clocks

6⁽¹⁾

AUTO_MASK

RW

Automatic request mask. This bit enables automatic request masking when an arbiter time-

out occurs.

0 = Automatic request masking disabled (default)

1 = Automatic request masking enabled

5:1⁽¹⁾RSVD

0⁽¹⁾

REQ0_MASK

RW

Reserved. These bits are reserved and must not be changed from their default value of

00000b.

Request 0 (REQ0) mask. Setting this bit forces the internal arbiter to ignore requests signal

on request input 0.

0 = Use 1394a OHCI request (default)

1 = Ignore 1394a OHCI request

(1) These bits shall only be reset by a fundamental reset ( FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

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10.6.1.72 Arbiter Time-Out Status Register

The arbiter time-out status register contains the status of each request (request 50) time-out. The time-out status

bit for the respective request is set if the device did not assert FRAME after the arbiter time-out value. See 表

10-51 for a complete description of the register contents.

PCI register offset:

Register type:

DEh

Read/Clear

00h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

表10-51. Arbiter Time-Out Status Register Description

BIT

FIELD NAME

RSVD

ACCESS

DESCRIPTION

7:6

5

R

Reserved. Returns 00b when read.

Request 5 time-out status

REQ5_TO

REQ4_TO

REQ3_TO

REQ2_TO

REQ1_TO

REQ0_TO

RCU

0 = No time-out

1 = Time-out has occurred.

4

3

2

1

0

RCU

Request 4 time-out status

0 = No time-out

1 = Time-out has occurred.

Request 3 time-out status

0 = No time-out

1 = Time-out has occurred.

Request 2 time-out status

0 = No time-out

1 = Time-out has occurred.

Request 1time-out status

0 = No time-out

1 = Time-out has occurred.

Request 0 time-out status

0 = No time-out

1 = Time-out has occurred.

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10.6.1.73 TI Proprietary Register

This read/write TI proprietary register is located at offset E0h and controls TI proprietary functions. This register

must not be changed from the specified default state. This register shall only be reset by FRST.

PCI register offset:

Register type:

E0h

Read only, Read/Write

00h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

10.6.1.74 TI Proprietary Register

This read/write TI proprietary register is located at offset E2h and controls TI proprietary functions. This register

must not be changed from the specified default state. This register shall only be reset by FRST.

PCI register offset:

Register type:

E2h

Read/Write

0000h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

10.6.1.75 TI Proprietary Register

This read/clear TI proprietary register is located at offset E4h and controls TI proprietary functions. This register

must not be changed from the specified default state.

PCI register offset:

Register type:

E4h

Read/Clear

0000h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

10.6.2 PCIe Extended Configuration Space

The programming model of the PCIe extended configuration space is compliant to the PCI Express Base

Specification and the PCI Express to PCI/PCI-X Bridge Specification programming models. The PCIe extended

configuration map uses the PCIe advanced error reporting capability and PCIe virtual channel (VC) capability

headers.

Sticky bits are reset by a global reset ( GRST) or the internally-generated power-on reset. EEPROM loadable

bits are reset by a PCIe reset ( PERST), GRST, or the internally-generated power-on reset. The remaining

register bits are reset by a PCIe hot reset, PERST, GRST, or the internally-generated power-on reset.

表10-52. PCIe Extended Configuration Register Map

REGISTER NAME

OFFSET

100h

104h

108h

10Ch

110h

Next capability offset/capability version

Advanced error reporting capabilities ID

Uncorrectable error status register⁽¹⁾

Uncorrectable error mask⁽¹⁾

Uncorrectable error severity⁽¹⁾

Correctable error status⁽¹⁾

Correctable error mask⁽¹⁾

114h

Advanced error capabilities and control⁽¹⁾

118h

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表10-52. PCIe Extended Configuration Register Map (continued)

REGISTER NAME

Header log⁽¹⁾

OFFSET

11Ch

Header log⁽¹⁾

120h

Header log⁽¹⁾

124h

Header log⁽¹⁾

128h

Secondary uncorrectable error status⁽¹⁾

Secondary uncorrectable error mask⁽¹⁾

Secondary uncorrectable error severity⁽¹⁾

Secondary error capabilities and control⁽¹⁾

Secondary header log⁽¹⁾

Reserved

12Ch

130h

134h

138h

13Ch

140h

144h

148h

14Ch FFCh

10.6.2.1 Advanced Error Reporting Capability ID Register

This read-only register identifies the linked list item as the register for PCIe advanced error reporting capabilities.

The register returns 0001h when read.

PCIe extended register offset:

Register type:

100h

Read only

0001h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

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10.6.2.2 Next Capability Offset/Capability Version Register

This read-only register identifies the next location in the PCIe extended capabilities link list. The upper 12 bits in

this register shall be 000h, indicating that the advanced error reporting capability is the last capability in the

linked list. The least significant four bits identify the revision of the current capability block as 1h.

PCIe extended register offset:

Register type:

102h

Read only

0001h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

10.6.2.3 Uncorrectable Error Status Register

The uncorrectable error status register reports the status of individual errors as they occur on the primary PCIe

interface. Software may only clear these bits by writing a 1b to the desired location. See 表 10-53 for a complete

description of the register contents.

PCIe extended register offset:

Register type:

104h

Read only, Read/Clear

0000h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-53. Uncorrectable Error Status Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:21 RSVD

R

Reserved. Returns 000 0000 0000b when read.

20⁽¹⁾

19⁽¹⁾

18⁽¹⁾

17⁽¹⁾

UR_ERROR

RCU

Unsupported request error. This bit is asserted when an unsupported request is received.

Extended CRC error. This bit is asserted when an extended CRC error is detected.

Malformed TLP. This bit is asserted when a malformed TLP is detected.

ECRC_ERROR

MAL_TLP

RX_OVERFLOW

Receiver overflow. This bit is asserted when the flow control logic detects that the

transmitting device has illegally exceeded the number of credits that were issued.

16⁽¹⁾

UNXP_CPL

RCU

Unexpected completion. This bit is asserted when a completion packet is received that

does not correspond to an issued request.

15⁽¹⁾

14⁽¹⁾

CPL_ABORT

RCU

Completed abort. This bit is asserted when the bridge signals a completed abort.

CPL_TIMEOUT

Completion time-out. This bit is asserted when no completion has been received for an

issued request before the time-out period.

13⁽¹⁾

FC_ERROR

RCU

Flow control error. This bit is asserted when a flow control protocol error is detected either

during initialization or during normal operation.

12⁽¹⁾

11:5

4⁽¹⁾

PSN_TLP

RSVD

RCU

R

Poisoned TLP. This bit is asserted when a poisoned TLP is received.

Reserved. Returns 000 0000b when read.

DLL_ERROR

RSVD

RCU

R

Data link protocol error. This bit is asserted if a data link layer protocol error is detected.

Reserved. Returns 0h when read.

3:0

(1) These bits shall only be reset by a fundamental reset ( FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

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10.6.2.4 Uncorrectable Error Mask Register

The uncorrectable error mask register controls the reporting of individual errors as they occur. When a mask bit

is set to 1b, the corresponding error status bit is not set, PCIe error messages are blocked, the header log is not

loaded, and the first error pointer is not updated. See 表 10-54 for a complete description of the register

contents.

PCIe extended register offset:

Register type:

108h

Read only, Read/Write

0000h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-54. Uncorrectable Error Mask Register Description

BIT

31:21 RSVD

FIELD NAME

ACCESS

DESCRIPTION

Reserved. Returns 000 0000 0000b when read.

Unsupported request error mask

R

20⁽¹⁾

19⁽¹⁾

18⁽¹⁾

17⁽¹⁾

16⁽¹⁾

15⁽¹⁾

14⁽¹⁾

13⁽¹⁾

12⁽¹⁾

UR_ERROR_MASK

ECRC_ERROR_MASK

MAL_TLP_MASK

RW

0 = Error condition is unmasked (default)..

1 = Error condition is masked.

RW

Extended CRC error mask

0 = Error condition is unmasked (default).

1 = Error condition is masked.

Malformed TLP mask

0 = Error condition is unmasked (default).

1 = Error condition is masked.

RX_OVERFLOW_MASK

UNXP_CPL_MASK

CPL_ABORT_MASK

CPL_TIMEOUT_MASK

FC_ERROR_MASK

PSN_TLP_MASK

Receiver overflow mask

0 = Error condition is unmasked (default).

1 = Error condition is masked.

Unexpected completion mask

0 = Error condition is unmasked (default).

1 = Error condition is masked.

Completer abort mask

0 = Error condition is unmasked (default).

1 = Error condition is masked.

Completion time-out mask

0 = Error condition is unmasked (default).

1 = Error condition is masked.

Flow control error mask

0 = Error condition is unmasked (default).

1 = Error condition is masked.

Poisoned TLP mask

0 = Error condition is unmasked (default).

1 = Error condition is masked.

11:5

4⁽¹⁾

RSVD

R

Reserved. Returns 000 0000b when read.

Data link protocol error mask

DLL_ERROR_MASK

RW

0 = Error condition is unmasked (default).

1 = Error condition is masked.

3:0

RSVD

R

Reserved. Returns 0h when read.

(1) These bits shall only be reset by a fundamental reset ( FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

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10.6.2.5 Uncorrectable Error Severity Register

The uncorrectable error severity register controls the reporting of individual errors as ERR_FATAL or

ERR_NONFATAL. When a bit is set, the corresponding error condition is identified as fatal. When a bit is

cleared, the corresponding error condition is identified as nonfatal. See 表 10-55 for a complete description of

the register contents.

PCIe extended register offset:

Register type:

10Ch

Read only, Read/Write

0006 2011h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

1

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

1

表10-55. Uncorrectable Error Severity Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:21 RSVD

R

Reserved. Returns 000 0000 0000b when read.

20⁽¹⁾

19⁽¹⁾

18⁽¹⁾

17⁽¹⁾

16⁽¹⁾

15⁽¹⁾

14⁽¹⁾

13⁽¹⁾

12⁽¹⁾

UR_ERROR_SEVRO

ECRC_ERROR_SEVRR

MAL_TLP_SEVR

RW

Unsupported request error severity

0 = Error condition is signaled using ERR_NONFATAL.

1 = Error condition is signaled using ERR_FATAL.

RW

Extended CRC error severity

0 = Error condition is signaled using ERR_NONFATAL.

1 = Error condition is signaled using ERR_FATAL.

Malformed TLP severity

0 = Error condition is signaled using ERR_NONFATAL.

1 = Error condition is signaled using ERR_FATAL.

RX_OVERFLOW_SEVR

UNXP_CPL_SEVRP

CPL_ABORT_SEVR

CPL_TIMEOUT_SEVR

FC_ERROR_SEVR

PSN_TLP_SEVR

Receiver overflow severity

0 = Error condition is signaled using ERR_NONFATAL.

1 = Error condition is signaled using ERR_FATAL.

Unexpected completion severity

0 = Error condition is signaled using ERR_NONFATAL.

1 = Error condition is signaled using ERR_FATAL.

Completed abort severity

0 = Error condition is signaled using ERR_NONFATAL.

1 = Error condition is signaled using ERR_FATAL.

Completion time-out severity

0 = Error condition is signaled using ERR_NONFATAL.

1 = Error condition is signaled using ERR_FATAL.

Flow control error severity

0 = Error condition is signaled using ERR_NONFATAL.

1 = Error condition is signaled using ERR_FATAL.

Poisoned TLP severity

0 = Error condition is signaled using ERR_NONFATAL.

1 = Error condition is signaled using ERR_FATAL.

11:6

5

RSVD

R

Reserved. Returns 000 000b when read.

Reserved. Returns 1h when read.

Data link protocol error severity

RSVD

4⁽¹⁾

DLL_ERROR_SEVR

RW

0 = Error condition is signaled using ERR_NONFATAL.

1 = Error condition is signaled using ERR_FATAL.

3:1

RSVD

R

Reserved. Returns 000b when read.

English Data Sheet: SCPS271

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BIT

表10-55. Uncorrectable Error Severity Register Description (continued)

FIELD NAME

ACCESS

DESCRIPTION

0

RSVD

R

Reserved. Returns 1h when read.

(1) These bits shall only be reset by a fundamental reset ( FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

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10.6.2.6 Correctable Error Status Register

The correctable error status register reports the status of individual errors as they occur. Software may only clear

these bits by writing a 1b to the desired location. See 表 10-56 for a complete description of the register

contents.t

PCIe extended register offset:

Register type:

110h

Read only, Read/Clear

0000 0000h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-56. Correctable Error Status Register Description

BIT

31:14 RSVD

13 ANFES

FIELD NAME

ACCESS

DESCRIPTION

R

Reserved. Returns 000 0000 0000 0000 0000b when read.

RCU

Advisory nonfatal error status. This bit is asserted when an advisory nonfatal error has been

reported.

12 ⁽¹⁾REPLAY_TMOUT

RCU

Replay timer time-out. This bit is asserted when the replay timer expires for a pending request

or completion that has not been acknowledged.

11:9

8⁽¹⁾

RSVD

R

Reserved. Returns 000b when read.

REPLAY_ROLL

RCU

REPLAY_NUM rollover. This bit is asserted when the replay counter rolls over after a pending

request or completion has not been acknowledged.

7⁽¹⁾

6⁽¹⁾

BAD_DLLP

BAD_TLP

RCU

Bad DLLP error. This bit is asserted when an 8b/10b error was detected by the PHY during

the reception of a DLLP.

Bad TLP error. This bit is asserted when an 8b/10b error was detected by the PHY during the

reception of a TLP.

5:1

0⁽¹⁾

RSVD

R

Reserved. Returns 00000b when read.

RX_ERROR

RCU

Receiver error. This bit is asserted when an 8b/10b error is detected by the PHY at any time.

(1) These bits shall only be reset by a fundamental reset ( FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

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10.6.2.7 Correctable Error Mask Register

The correctable error mask register controls the reporting of individual errors as they occur. When a mask bit is

set to 1b, the corresponding error status bit is not set, PCIe error messages are blocked, the header log is not

loaded, and the first error pointer is not updated. See 表 10-57 for a complete description of the register

contents.

PCIe extended register offset:

Register type:

114h

Read only, Read/Write

0000 2000h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

表10-57. Correctable Error Mask Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:14 RSVD

R

Reserved. Returns 000 0000 0000 0000 0000b when read.

Advisory nonfatal error mask

13

ANFEM

RW

0 = Error condition is unmasked.

1 = Error condition is masked (default).

12⁽¹⁾REPLAY_TMOUT_MASK

RW

Replay timer time-out mask

0 = Error condition is unmasked (default).

1 = Error condition is masked.

11:9 RSVD

R

Reserved. Returns 000b when read.

REPLAY_NUM rollover mask

8⁽¹⁾REPLAY_ROLL_MASK

RW

0 = Error condition is unmasked (default).

1 = Error condition is masked.

7⁽¹⁾BAD_DLLP_MASK

6⁽¹⁾BAD_TLP_MASK

RW

Bad DLLP error mask

0 = Error condition is unmasked (default).

1 = Error condition is masked.

Bad TLP error mask

0 = Error condition is unmasked (default).

1 = Error condition is masked.

5:1 RSVD

R

Reserved. Returns 00000b when read.

Receiver error mask

0⁽¹⁾RX_ERROR_MASK

RW

0 = Error condition is unmasked (default).

1 = Error condition is masked.

(1) These bits shall only be reset by a fundamental reset ( FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

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10.6.2.8 Advanced Error Capabilities and Control Register

The advanced error capabilities and control register allows the system to monitor and control the advanced error

reporting capabilities. See 表10-58 for a complete description of the register contents.

PCIe extended register offset:

Register type:

118h

Read only, Read/Write

0000 00A0h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

表10-58. Advanced Error Capabilities and Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

Reserved. Returns 000 0000 0000 0000 0000 0000b when read.

Extended CRC check enable

31:9

8⁽¹⁾

RSVD

R

ECRC_CHK_EN

RW

0 = Extended CRC checking is disabled.

1 = Extended CRC checking is enabled.

7

ECRC_CHK_CAPABLE

ECRC_GEN_EN

R

Extended CRC check capable. This read-only bit returns a value of 1b indicating that the

bridge is capable of checking extended CRC information.

6⁽¹⁾

RW

Extended CRC generation enable

0 = Extended CRC generation is disabled.

1 = Extended CRC generation is enabled.

5

ECRC_GEN_CAPABLE

R

Extended CRC generation capable. This read-only bit returns a value of 1b indicating

that the bridge is capable of generating extended CRC information.

4:0⁽¹⁾FIRST_ERR

RU

First error pointer. This 5-bit value reflects the bit position within the uncorrectable error

status register (offset 104h, see 节10.6.2.3) corresponding to the class of the first error

condition that was detected.

(1) These bits shall only be reset by a fundamental reset ( FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

10.6.2.9 Header Log Register

The header log register stores the TLP header for the packet that lead to the most recently detected error

condition. Offset 11Ch contains the first DWORD. Offset 128h contains the last DWORD (in the case of a 4DW

TLP header). Each DWORD is stored with the least significant byte representing the earliest transmitted. This

register shall only be reset by a fundamental reset ( FRST).

PCIe extended register offset:

Register type:

11Ch, 120h, 124h, and 128h

Read only

Default value:

0000 0000h

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

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10.6.2.10 Secondary Uncorrectable Error Status Register

The secondary uncorrectable error status register reports the status of individual PCI bus errors as they occur.

Software may only clear these bits by writing a 1b to the desired location. See 表 10-59 for a complete

description of the register contents.

PCIe extended register offset:

Register type:

12Ch

Read only, Read/Clear

0000 0000h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-59. Secondary Uncorrectable Error Status Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:13 RSVD

R

Reserved. Returns 000 0000 0000 0000 0000b when read.

12⁽¹⁾

11⁽¹⁾

10⁽¹⁾

9⁽¹⁾

SERR_DETECT

RCU

SERR assertion detected. This bit is asserted when the bridge detects the assertion of

SERR on the secondary bus.

PERR_DETECT

DISCARD_TIMER

UNCOR_ADDR

RCU

PERR assertion detected. This bit is asserted when the bridge detects the assertion of

PERR on the secondary bus.

Delayed transaction discard timer expired. This bit is asserted when the discard timer

expires for a pending delayed transaction that was initiated on the secondary bus.

Uncorrectable address error. This bit is asserted when the bridge detects a parity error

during the address phase of an upstream transaction.

8

RSVD

R

Reserved. Returns 0b when read.

7⁽¹⁾

UNCOR_DATA

RCU

Uncorrectable data error. This bit is asserted when the bridge detects a parity error during a

data phase of an upstream write transaction, or when the bridge detects the assertion of

PERR when forwarding read completion data to a PCI device.

6:4

3⁽¹⁾

RSVD

R

Reserved. Returns 000b when read.

MASTER_ABORT

RCU

Received master abort. This bit is asserted when the bridge receives a master abort on the

PCI interface.

2⁽¹⁾

1:0

TARGET_ABORT

RSVD

RCU

R

Received target abort. This bit is asserted when the bridge receives a target abort on the

PCI interface.

Reserved. Returns 00b when read.

(1) These bits shall only be reset by a fundamental reset ( FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

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10.6.2.11 Secondary Uncorrectable Error Mask Register

The secondary uncorrectable error mask register controls the reporting of individual errors as they occur. When

a mask bit is set to 1b, the corresponding error status bit is not set, PCIe error messages are blocked, the

header log is not loaded, and the first error pointer is not updated. See 表10-60 for a complete description of the

register contents.

PCIe extended register offset:

Register type:

130h

Read only, Read/Write

0000 17A8h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

表10-60. Secondary Uncorrectable Error Mask Register Description

BIT

31:14 RSVD

FIELD NAME

ACCESS

DESCRIPTION

R

Reserved. Returns 00 0000 0000 0000 0000b when read.

13⁽¹⁾

BRIDGE_ERROR_MASK

RW

Internal bridge error. This mask bit is associated with a PCI-X error and has no effect

on the bridge.

12⁽¹⁾

SERR_DETECT_MASK

PERR_DETECT_MASK

DISCARD_TIMER_MASK

UNCOR_ADDR_MASK

RW

SERR assertion detected

0 = Error condition is unmasked.

1 = Error condition is masked (default).

11⁽¹⁾

10⁽¹⁾

9⁽¹⁾

PERR assertion detectedi

0 = Error condition is unmasked.

1 = Error condition is masked (default).

Delayed transaction discard timer expired

0 = Error condition is unmasked.

1 = Error condition is masked (default).

Uncorrectable address error

0 = Error condition is unmasked.

1 = Error condition is masked (default).

8⁽¹⁾

7⁽¹⁾

ATTR_ERROR_MASK

UNCOR_DATA_MASK

RW

Uncorrectable attribute error. This mask bit is associated with a PCI-X error and has

no effect on the bridge.

Uncorrectable data error

0 = Error condition is unmasked.

1 = Error condition is masked (default).

6⁽¹⁾

5⁽¹⁾

SC_MSG_DATA_MASK

SC_ERROR_MASK

RW

Uncorrectable split completion message data error. This mask bit is associated with a

PCI-X error and has no effect on the bridge.

Unexpected split completion error. This mask bit is associated with a PCI-X error and

has no effect on the bridge.

4

RSVD

R

Reserved. Returns 0b when read.

Received master abort

3⁽¹⁾

MASTER_ABORT_MASK

RW

0 = Error condition is unmasked.

1 = Error condition is masked (default).

2⁽¹⁾

TARGET_ABORT_MASK

RW

Received target abort

0 = Error condition is unmasked.

1 = Error condition is masked (default).

1⁽¹⁾

0

SC_MSTR_ABORT_MASK

RSVD

RW

R

Master abort on split completion. This mask bit is associated with a PCI-X error and

has no effect on the bridge.

Reserved. Returns 0b when read.

(1) These bits shall only be reset by a fundamental reset ( FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

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10.6.2.12 Secondary Uncorrectable Error Severity

The uncorrectable error severity register controls the reporting of individual errors as ERR_FATAL or

ERR_NONFATAL. When a bit is set, the corresponding error condition is identified as fatal. When a bit is

cleared, the corresponding error condition is identified as nonfatal. See 表 10-61 for a complete description of

the register contents.

PCIe extended register offset:

Register type:

134h

Read only, Read/Write

0000 1340h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

1

0

表10-61. Secondary Uncorrectable Error Severity Register Description

BIT

31:14 RSVD

FIELD NAME

ACCESS

DESCRIPTION

R

Reserved. Returns 00 0000 0000 0000 0000b when read.

13⁽¹⁾

BRIDGE_ERROR_SEVR

RW

Internal bridge error. This severity bit is associated with a PCI-X error and has no effect

on the bridge.

12⁽¹⁾

SERR_DETECT_SEVR

PERR_DETECT_SEVR

DISCARD_TIMER_SEVR

UNCOR_ADDR_SEVR

RW

SERR assertion detected

0 = Error condition is signaled using ERR_NONFATAL.

1 = Error condition is signaled using ERR_FATAL (default).

11⁽¹⁾

10⁽¹⁾

9⁽¹⁾

PERR assertion detected

0 = Error condition is signaled using ERR_NONFATAL (default).

1 = Error condition is signaled using ERR_FATAL.

Delayed transaction discard timer expired

0 = Error condition is signaled using ERR_NONFATAL (default).

1 = Error condition is signaled using ERR_FATAL.

Uncorrectable address error

0 = Error condition is signaled using ERR_NONFATAL.

1 = Error condition is signaled using ERR_FATAL (default).

8⁽¹⁾

7⁽¹⁾

ATTR_ERROR_SEVR

UNCOR_DATA_SEVR

RW

Uncorrectable attribute error. This severity bit is associated with a PCI-X error and has

no effect on the bridge.

Uncorrectable data error

0 = Error condition is signaled using ERR_NONFATAL (default).

1 = Error condition is signaled using ERR_FATAL.

6⁽¹⁾

5⁽¹⁾

SC_MSG_DATA_SEVR

SC_ERROR_SEVR

RW

Uncorrectable split completion message data error. This severity bit is associated with

a PCI-X error and has no effect on the bridge.

Unexpected split completion error. This severity bit is associated with a PCI-X error and

has no effect on the bridge.

4

RSVD

R

Reserved. Returns 0b when read.

Received master abort

3⁽¹⁾

MASTER_ABORT_SEVR

RW

0 = Error condition is signaled using ERR_NONFATAL (default).

1 = Error condition is signaled using ERR_FATAL.

2⁽¹⁾

TARGET_ABORT_SEVR

RW

Received target abort

0 = Error condition is signaled using ERR_NONFATAL (default).

1 = Error condition is signaled using ERR_FATAL.

1⁽¹⁾

0

SC_MSTR_ABORT_SEVR

RSVD

RW

R

Master abort on split completion. This severity bit is associated with a PCI-X error and

has no effect on the bridge.

Reserved. Returns 0b when read.

(1) These bits shall only be reset by a fundamental reset ( FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

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10.6.2.13 Secondary Error Capabilities and Control Register

The secondary error capabilities and control register allows the system to monitor and control the secondary

advanced error reporting capabilities. See 表10-62 for a complete description of the register contents.

PCIe extended register offset:

Register type:

138h

Read only

0000 0000h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-62. Secondary Error Capabilities and Control Register Description

BIT

31:5

4:0⁽¹⁾SEC_FIRST_ERR

FIELD NAME

ACCESS

DESCRIPTION

RSVD

R

Reserved. Return 000 0000 0000 0000 0000 0000 0000b when read.

RU

First error pointer. This 5-bit value reflects the bit position within the secondary

uncorrectable error status register (offset12Ch, see 节10.6.2.10) corresponding to the

class of the first error condition that was detected.

(1) These bits shall only be reset by a fundamental reset ( FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

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10.6.2.14 Secondary Header Log Register

The secondary header log register stores the transaction address and command for the PCI bus cycle that led to

the most recently detected error condition. Offset 13Ch accesses register bits 31:0. Offset 140h accesses

register bits 63:32. Offset 144h accesses register bits 95:64. Offset 148h accesses register bits 127:96. See 表

10-63 for a complete description of the register contents.

PCIe extended register offset:

Register type:

13Ch, 140h, 144h, and 148h

Read only

Default value:

0000 0000h

BIT NUMBER

RESET STATE

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

0

BIT NUMBER

RESET STATE

111

110

109

108

107

106

105

104

103

102

101

100

99

98

97

96

0

BIT NUMBER

RESET STATE

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

0

BIT NUMBER

RESET STATE

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

0

BIT NUMBER

RESET STATE

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

0

BIT NUMBER

RESET STATE

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

0

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-63. Secondary Header Log Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

127:64⁽¹⁾ADDRESS

RU

Transaction address. The 64-bit value transferred on AD[31:0] during the first and

second address phases. The first address phase is logged to 95:64 and the second

address phase is logged to 127:96. In the case of a 32-bit address, bits 127:96 are set

to 0.

63:44

RSVD

R

Reserved. Returns 0 0000h when read.

43:40⁽¹⁾UPPER_CMD

RU

Transaction command upper. Contains the status of the C/BE terminals during the

second address phase of the PCI transaction that generated the error if using a dual-

address cycle.

39:36⁽¹⁾LOWER_CMD

RU

R

Transaction command lower. Contains the status of the C/BE terminals during the first

address phase of the PCI transaction that generated the error.

35:0

TRANS_ATTRIBUTE

Transaction attribute. Because the bridge does not support the PCI-X attribute

transaction phase, these bits have no function, and return 0 0000 0000h when read.

(1) These bits shall only be reset by a fundamental reset ( FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

10.6.3 Memory-Mapped TI Proprietary Register Space

The programming model of the memory-mapped TI proprietary register space is unique to this device. These

custom registers are specifically designed to provide enhanced features associated with upstream isochronous

applications.

Sticky bits are reset by a fundamental reset ( FRST).

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表10-64. Device Control Memory Window Register Map

REGISTER NAME

OFFSET

00h

Reserved

Revision ID

Device control map ID

Reserved

04h-3Ch

40h

GPIO data⁽¹⁾

Serial-bus control and status⁽¹⁾Serial-bus slave address⁽¹⁾

GPIO control⁽¹⁾

Serial-bus word address⁽¹⁾Serial-bus data⁽¹⁾

44h

10.6.3.1 Device Control Map ID Register

The device control map ID register identifies the TI proprietary layout for this device control map. The value 04h

identifies this as a PCIe-to-PCI bridge without isochronous capabilities.

Device control memory window register offset:

Register type:

00h

Read only

04h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

1

0

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10.6.3.2 Revision ID Register

Device control memory window register offset:

Register type:

01h

Read only

00h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

10.6.3.3 GPIO Control Register

This register controls the direction of the eight GPIO terminals. This register has no effect on the behavior of

GPIO terminals that are enabled to perform secondary functions. The secondary functions share GPIO4 (SCL)

and GPIO5 (SDA). This register is an alias of the GPIO control register in the classic PCI configuration space

(offset B4h, see 节10.6.1.60). See 表10-65 for a complete description of the register contents.

Device control memory window register offset:

Register type:

40h

Read only, Read/Write

0000h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-65. GPIO Control Register Description

BIT

15:8

7⁽¹⁾

FIELD NAME

RSVD

ACCESS

DESCRIPTION

R

Reserved. Returns 00h when read.

GPIO7_DIR

GPIO6_DIR

GPIO5_DIR

GPIO4_DIR

GPIO3_DIR

GPIO2_DIR

GPIO1_DIR

GPIO0_DIR

RW

GPIO 7 data direction. This bit selects whether GPIO7 is in input or output mode.

0 = Input (default)

1 = Output

6⁽¹⁾

5⁽¹⁾

4⁽¹⁾

3⁽¹⁾

2⁽¹⁾

1⁽¹⁾

0⁽¹⁾

RW

GPIO 6 data direction. This bit selects whether GPIO6 is in input or output mode.

0 = Input (default)

1 = Output

GPIO 5 data direction. This bit selects whether GPIO5 is in input or output mode.

0 = Input (default)

1 = Output

GPIO 4 data direction. This bit selects whether GPIO4 is in input or output mode.

0 = Input (default)

1 = Output

GPIO 3 data direction. This bit selects whether GPIO3 is in input or output mode.

0 = Input (default)

1 = Output

GPIO 2 data direction. This bit selects whether GPIO2 is in input or output mode.

0 = Input (default)

1 = Output

GPIO 1 data direction. This bit selects whether GPIO1 is in input or output mode.

0 = Input (default)

1 = Output

GPIO 0 data direction. This bit selects whether GPIO0 is in input or output mode.

0 = Input (default)

1 = Output

(1) These bits shall only be reset by a fundamental reset ( FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

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10.6.3.4 GPIO Data Register

This register reads the state of the input-mode GPIO terminals and changes the state of the output-mode GPIO

terminals. Writing to a bit that is in input mode or is enabled for a secondary function is ignored. The secondary

functions share GPIO4 (SCL) and GPIO5 (SDA). The default value at power up depends on the state of the

GPIO terminals as they default to general-purpose inputs. This register is an alias of the GPIO data register in

the classic PCI configuration space (offset B6h, see 节10.6.1.61). See 表10-66 for a complete description of the

register contents.

Device control memory window register offset:

Register type:

42h

Read only, Read/Write

00XXh

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

x

表10-66. GPIO Data Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:8

7⁽¹⁾

RSVD

R

Reserved

GPIO7_Data

RW

GPIO 7 data. This bit reads the state of GPIO7 when in input mode or changes the state of

GPIO7 when in output mode.

6⁽¹⁾

5⁽¹⁾

4⁽¹⁾

3⁽¹⁾

2⁽¹⁾

1⁽¹⁾

0⁽¹⁾

GPIO6_Data

GPIO5_Data

GPIO4_Data

GPIO3_Data

GPIO2_Data

GPIO1_Data

GPIO0_Data

RW

GPIO 6 data. This bit reads the state of GPIO6 when in input mode or changes the state of

GPIO6 when in output mode.

GPIO 5 data. This bit reads the state of GPIO5 when in input mode or changes the state of

GPIO5 when in output mode.

GPIO 4 data. This bit reads the state of GPIO4 when in input mode or changes the state of

GPIO4 when in output mode.

GPIO 3 data. This bit reads the state of GPIO3 when in input mode or changes the state of

GPIO3 when in output mode.

GPIO 2 data. This bit reads the state of GPIO2 when in input mode or changes the state of

GPIO2 when in output mode.

GPIO 1 data. This bit reads the state of GPIO1 when in input mode or changes the state of

GPIO1 when in output mode.

GPIO 0 data. This bit reads the state of GPIO0 when in input mode or changes the state of

GPIO0 when in output mode.

(1) These bits shall only be reset by a fundamental reset ( FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

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10.6.3.5 Serial-Bus Data Register

The serial-bus data register is used to read and write data on the serial-bus interface. When writing data to the

serial bus, this register must be written before writing to the serial-bus address register to initiate the cycle. When

reading data from the serial bus, this register will contain the data read after the REQBUSY (bit 5 serial-bus

control register) bit is cleared. This register is an alias for the serial-bus data register in the PCI header. This

register shall only be reset by FRST.

Device control memory window register offset:

Register type:

44h

Read/Write

00h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

1

10.6.3.6 Serial-Bus Word Address Register

The value written to the serial-bus index register represents the byte address of the byte being read or written

from the serial-bus device. The serial-bus index register must be written before the before initiating a serial bus

cycle by writing to the serial-bus slave address register. This register is an alias for the serial-bus index register

in the PCI header. This register shall only be reset by FRST.

Device control memory window register offset:

Register type:

45h

Read/Write

00h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

10.6.3.7 Serial-Bus Slave Address Register

The serial-bus slave address register is used to indicate the address of the device being targeted by the serial-

bus cycle. This register also indicates if the cycle will be a read or a write cycle. Writing to this register initiates

the cycle on the serial interface. This register is an alias for the serial-bus slave address register in the PCI

header.

Device control memory window register offset:

Register type:

46h

Read/Write

00h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

表10-67. Serial-Bus Slave Address Register Descriptions

BIT

FIELD NAME

ACCESS

DESCRIPTION

7:1⁽¹⁾

SLAVE_ADDR

RW

Serial-bus slave address. This 7-bit field is the slave address for a serial-bus read or write

transaction. The default value for this field is 000 0000b.

0⁽¹⁾

RW_CMD

RW

Read/write command. This bit determines if the serial-bus cycle is a read or a write cycle.

0 = A single-byte write is requested (default) .

1 = A single-byte read is requested.

(1) These bits shall only be reset by a fundamental reset ( FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

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10.6.3.8 Serial-Bus Control and Status Register

The serial-bus control and status register is used to control the behavior of the serial-bus interface. This register

also provides status information about the state of the serial bus. This register is an alias for the serial-bus

control and status register in the PCI header.

Device control memory window register offset:

Register type:

47h

Read only, Read/Write, Read/Clear

00h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

表10-68. Serial-Bus Control and Status Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

Protocol select. This bit selects the serial-bus address mode used.

0 = Slave address and word address are sent on the serial bus (default).

1 = Only the slave address is sent on the serial bus.

Reserved. Returns 0b when read.

7⁽¹⁾

PROT_SEL

RW

6

5

RSVD

R

REQBUSY

RU

Requested serial-bus access busy. This bit is set when a software-initiated serial-bus cycle

is in progress.

0 = No serial-bus cycle

1 = Serial-bus cycle in progresss

4⁽¹⁾

ROMBUSY

SBDETECT

RU

Serial EEPROM access busy. This bit is set when the serial EEPROM circuitry in the

bridge is downloading register defaults from a serial EEPROM.

0 = No EEPROM activity

1 = EEPROM download in progress

3⁽¹⁾

RWU

Serial EEPROM detected. This bit enables the serial-bus interface. The value of this bit

controls whether the GPIO4/SCL and GPIO5/SDA terminals are configured as GPIO

signals or as serial-bus signals. This bit is automatically set to 1b when a serial EEPROM

is detected.

Note: A serial EEPROM is only detected once following PERST.

0 = No EEPROM present, EEPROM load process does not happen. GPIO4//SCL and

GPIO5//SDA terminals are configured as GPIO signals.

1 = EEPROM present, EEPROM load process takes place. GPIO4/SCL and

GPIO5/SDA terminals are configured as serial-bus signals.

2⁽¹⁾

SBTEST

RW

Serial-bus test. This bit is used for internal test purposes. This bit controls the clock source

for the serial interface clock.

0 = Serial-bus clock at normal operating frequency ~60 kHz (default)

1 = Serial-bus clock frequency increased for test purposes ~4 MHz

1⁽¹⁾

SB_ERR

RCU

Serial-bus error. This bit is set when an error occurs during a software-initiated serial-bus

cycle.

0 = No error

1 = Serial-bus error

0⁽¹⁾

ROM_ERR

Serial EEPROM load error. This bit is set when an error occurs while downloading

registers from a serial EEPROM.

0 = No error

1 = EEPROM load error

(1) These bits shall only be reset by a fundamental reset ( FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

10.6.4 1394 OHCI PCI Configuration Space

The 1394 OHCI core is integrated as a PCI device behind the PCIe to PCI bridge. The configuration header for

the 1394b OHCI portion of the design is compliant with the PCI specification as a standard header. 表 10-69

shows the configuration header that includes both the predefined portion of the configuration space and the

user-definable registers.

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Since the 1394 OHCI configuration space is accessed over the bridge secondary PCI bus, PCIe type 1

configuration read and write transactions are required when accessing these registers. The 1394 OHCI

configuration register map is accessed as device number 0 and function number 0. Of course, the bus number is

determined by the value that is loaded into the secondary bus number field at offset 19h within the PCIe

configuration register map.

Sticky bits are reset by a fundamental reset ( FRST). The remaining register bits are reset by a PCIe hot reset,

PERST, GRST, or the internally-generated power-on reset.

表10-69. 1394 OHCI Configuration Register Map

REGISTER NAME

OFFSET

00h

Device ID

Status

Vendor ID

Command

Revision ID

04h

Class code

08h

BIST

Header type

Latency timer

Cache line size

0Ch

OHCI base address

TI extension base address

CIS base address

Reserved

10h

14h

18h

1Ch-27h

28h

CIS pointer

Subsystem ID⁽¹⁾

Subsystem vendor ID⁽¹⁾

2Ch

Reserved

30h

Reserved

Power management capabilities

34h

pointer

38h

3Ch

40h

44h

48h

Maximum latency⁽¹⁾

Minimum grant⁽¹⁾

PMCSR_BSE

Interrupt pin

Interrupt line

Capability ID

OHCI control

Next item pointer

Power management capabilities

Power management data

(reserved)

Power management control and status⁽¹⁾

Reserved

4Ch-E7h

E8h

Multifunction select

PCI PHY control⁽¹⁾

ECh

F0h

PCI miscellaneous configuration⁽¹⁾

Link enhancement control⁽¹⁾

Subsystem access⁽¹⁾

F4h

F8h

TI proprietary

FCh

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10.6.4.1 Vendor ID Register

The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the OHCI

controller. The vendor ID assigned to TI is 104Ch.

PCI register offset:

Register type:

00h

Read only

104Ch

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

1

0

10.6.4.2 Device ID Register

The device ID register contains a value assigned to the 1394 OHCI function by TI. The device identification for

the 1394 OHCI function is 823Fh.

PCI register offset:

Register type:

02h

Read only

823Fh

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

1

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10.6.4.3 Command Register

The command register provides control over the 1394b OHCI function interface to the PCI bus. All bit functions

adhere to the definitions in the PCI Local Bus Specification, as shown in the following bit descriptions. See 表

10-70 for a complete description of the register contents.

PCI register offset:

Register type:

04h

Read/Write, Read only

0000h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-70. Command Register Description

DESCRIPTION

BIT

FIELD NAME

TYPE

15-11 RSVD

R

Reserved. Return 0 0000b when read.

10

INT_DISABLE

Interrupt disable. When bit 10 is set to 1b, the OHCI controller is disabled from asserting an

interrupt. When cleared, the OHCI controller is able to send interrupts normally. This default

value for this bit is 0b.

9

8

FBB_ENB

R

Fast back-to-back enable. The 1394b OHCI controller does not generate fast back-to-back

transactions; therefore, bit 9 returns 0b when read.

SERR_ENB

RW

PCI_SERR enable. When bit 8 is set to 1b, the 1394b OHCI controller PCI_SERR driver is

enabled. PCI_SERR can be asserted after detecting an address parity error on the PCI bus.

The default value for this bit is 0b.

7

6

STEP_ENB

PERR_ENB

R

Address/data stepping control. The 1394b OHCI controller does not support address/data

stepping; therefore, bit 7 is hardwired to 0b.

RW

Parity error enable. When bit 6 is set to 1b, the 1394b OHCI controller is enabled to drive

PCI_PERR response to parity errors through the PCI_PERR signal. The default value for this

bit is 0b.

5

4

VGA_ENB

MWI_ENB

R

VGA palette snoop enable. The 1394b OHCI controller does not feature VGA palette snooping;

therefore, bit 5 returns 0b when read.

RW

Memory write and invalidate enable. When bit 4 is set to 1b, the OHCI controller is enabled to

generate MWI PCI bus commands. If this bit is cleared, the 1394b OHCI controller generates

memory write commands instead. The default value for this bit is 0b.

3

2

1

SPECIAL

R

Special cycle enable. The 1394b OHCI controller function does not respond to special cycle

transactions; therefore, bit 3 returns 0b when read.

MASTER_ENB

RW

Bus master enable. When bit 2 is set to 1b, the 1394b OHCI controller is enabled to initiate

cycles on the PCI bus. The default value for this bit is 0b.

MEMORY_ENB

IO_ENB

Memory response enable. Setting bit 1 to 1b enables the 1394b OHCI controller to respond to

memory cycles on the PCI bus. This bit must be set to access OHCI registers. The default

value for this bit is 0b.

0

R

I/O space enable. The 1394b OHCI controller does not implement any I/O-mapped

functionality; therefore, bit 0 returns 0b when read.

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10.6.4.4 Status Register

The status register provides status over the 1394b OHCI controller interface to the PCI bus. All bit functions

adhere to the definitions in the PCI Local Bus Specification, as shown in the following bit descriptions. See 表

10-71 for a complete description of the register contents.

PCI register offset:

Register type:

06h

Read/Clear/Update, Read only

0230h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

表10-71. Status Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

15

PAR_ERR

RCU

Detected parity error. Bit 15 is set to 1b when either an address parity or data parity error is

detected.

14

SYS_ERR

RCU

R

Signaled system error. Bit 14 is set to 1b when PCI_SERR is enabled and the 1394b OHCI

controller has signaled a system error to the host.

13

MABORT

Received master abort. Bit 13 is set to 1b when a cycle initiated by the 1394b OHCI controller

on the PCI bus has been terminated by a master abort.

12

TABORT_REC

TABORT_SIG

PCI_SPEEDO

Received target abort. Bit 12 is set to 1b when a cycle initiated by the 1394b OHCI controller on

the PCI bus was terminated by a target abort.

11

Signaled target abort. Bit 11 is set to 1b by the 1394b OHCI controller when it terminates a

transaction on the PCI bus with a target abort.

10-9

DEVSEL timing. Bits 10 and 9 encode the timing of PCI_DEVSEL and are hardwired to 01b,

indicating that the 1394b OHCI controller asserts this signal at a medium speed on

nonconfiguration cycle accesses.

8

DATAPAR

RCU

Data parity error detected. Bit 8 is set to 1b when the following conditions have been met:

a. PCI_PERR was asserted by any PCI device including the OHCI controller.

b. 1394b OHCI controller was the bus master during the data parity error.

c. Bit 6 (PERR_EN) in the command register at offset 04h in the PCI configuration space

(see 节10.6.4.3, Command Register) is set to 1b.

7

6

5

4

FBB_CAP

UDF

R

Fast back-to-back capable. The 1394b OHCI controller cannot accept fast back-to-back

transactions; therefore, bit 7 is hardwired to 0b.

User-definable features (UDFs) supported. The 1394b OHCI controller does not support the

UDF; therefore, bit 6 is hardwired to 0b.

66MHZ

CAPLIST

66-MHz capable. The 1394b OHCI controller operates at a maximum PCI_CLK frequency of 66

MHz; therefore, bit 5 is hardwired to 1b.

Capabilities list. Bit 4 returns 1b when read, indicating that capabilities additional to standard

PCI are implemented. The linked list of PCI power-management capabilities is implemented in

this function.

3

INT_STATUS

RSVD

RU

R

Interrupt status. This bit reflects the interrupt status of the function. Only when bit 10

(INT_DISABLE) in the command register (PCI offset 04h, see 节10.6.1.3) is a 0 and this bit is a

1, is the functions INTx signal asserted. Setting the INT_DISABLE bit to a 1 has no effect on the

state of this bit. This bit has been defined as part of the PCI Local Bus Specification (Revision

2.3).

2-0

Reserved. Bits 3-0 return 0h when read.

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10.6.4.5 Class Code and Revision ID Registers

The class code and revision ID registers categorize the 1394b OHCI controller as a serial bus controller (0Ch),

controlling an IEEE Std 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the TI chip

revision is indicated in the least significant byte. See 表10-72 for a complete description of the register contents.

PCI register offset:

Register type:

08h

Read only

0C00 1001h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

1

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

表10-72. Class Code and Revision ID Registers Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31-24 BASECLASS

R

Base class. This field returns 0Ch when read, which broadly classifies the function as a

serial bus controller.

23-16 SUBCLASS

R

Subclass. This field returns 00h when read, which specifically classifies the function as

controlling an IEEE Std 1394 serial bus.

15-8

7-0

PGMIF

Programming interface. This field returns 10h when read, which indicates that the

programming model is compliant with the 1394 Open Host Controller Interface

Specification.

CHIPREV

R

Silicon revision. This field returns 00h when read, which indicates the silicon revision of the

1394b OHCI controller.

10.6.4.6 Cache Line Size and Latency Timer Registers

The latency timer and class cache line size registers are programmed by the host BIOS to indicate system

cache-line size and the latency timer are associated with the 1394b OHCI controller. See 表 10-73 for a

complete description of the register contents.

PCI register offset:

Register type:

0Ch

Read/Write

0000h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-73. Latency Timer and Class Cache Line Size Registers Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15-8

LATENCY_TIMER

RW

PCI latency timer. The value in this register specifies the latency timer for the 1394b OHCI

controller, in units of PCI clock cycles. When the 1394b OHCI function is a PCI bus initiator

and asserts PCI_FRAME, the latency timer begins counting from zero. If the latency timer

expires before the 1394b OHCI functions transaction has terminated, the 1394b OHCI

function terminates the transaction when its PCI_GNT is deasserted.

7-0

CACHELINE_SZ

RW

Cache-line size. This value is used by the OHCI controller during memory write and

invalidate, memory-read line, and memory-read multiple transactions. The default value for

this field is 00h.

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10.6.4.7 Header Type and BIST Registers

The header type and built-in self-test (BIST) registers indicate the OHCI controller PCI header type and no built-

in self-test. See 表10-74 for a complete description of the register contents.

PCI register offset:

Register type:

0Eh

Read only

0000h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-74. Header Type and BIST Registers Description

BIT

FIELD NAME

BIST

TYPE

DESCRIPTION

15-8

R

Built-in self-test. The OHCI controller does not include a BIST; therefore, this field returns

00h when read.

7-0

HEADER_TYPE

R

PCI header type. The OHCI controller includes the standard PCI header, which is

communicated by returning 00h when this field is read. Since the 1394b OHCI core is

implemented as a single-function PCI device, bit 7 of this register must be 0b.

10.6.4.8 OHCI Base Address Register

The OHCI base address register is programmed with a base address referencing the memory-mapped OHCI

control. When the BIOS writes all 1s to this register, the value read back is FFFF F800h, indicating that at least

2K bytes of memory address space are required for the OHCI registers. See 表 10-75 for a complete description

of the register contents.

PCI register offset:

Register type:

10h

Read/Write, Read only

0000 0000h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-75. OHCI Base Address Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31-11 OHCIREG_PTR

RW

OHCI register pointer. This field specifies the upper 21 bits of the 32-bit OHCI base address

register. The default value for this field is all 0s.

10-4

3

OHCI_SZ

R

OHCI register size. This field returns 000 0000b when read, indicating that the OHCI

registers require a 2K-byte region of memory.

OHCI_PF

OHCI register prefetch. Bit 3 returns 0b when read, indicating that the OHCI registers are

nonprefetchable.

2-1

OHCI_MEMTYPE

OHCI memory type. This field returns 00b when read, indicating that the OHCI base

address register is 32 bits wide and mapping can be done anywhere in the 32-bit memory

space.

0

OHCI_MEM

R

OHCI memory indicator. Bit 0 returns 0b when read, indicating that the OHCI registers are

mapped into system memory space.

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10.6.4.9 TI Extension Base Address Register

The TI extension base address register is programmed with a base address referencing the memory-mapped TI

extension registers. When the BIOS writes all 1s to this register, the value read back is FFFF C000h, indicating

that at least 16K bytes of memory address space are required for the TI registers. See 表 10-76 for a complete

description of the register contents.

PCI register offset:

Register type:

14h

Read/Write, Read only

0000 0000h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-76. TI Base Address Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31-14 TIREG_PTR

RW

TI register pointer. This field specifies the upper 18 bits of the 32-bit TI base address

register. The default value for this field is all 0s.

13-4

3

TI_SZ

R

TI register size. This field returns 00 0000 0000b when read, indicating that the TI registers

require a 16K-byte region of memory.

TI_PF

TI register prefetch. Bit 3 returns 0b when read, indicating that the TI registers are

nonprefetchable.

2-1

0

TI_MEMTYPE

TI_MEM

TI memory type. This field returns 00b when read, indicating that the TI base address

register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space.

TI memory indicator. Bit 0 returns 0b when read, indicating that the TI registers are mapped

into system memory space.

10.6.4.10 CIS Base Address Register

The CARDBUS input to the 1394 OHCI core is tied high such that this register returns 0000 0000h when read.

PCI register offset:

Register type:

18h

Read only

0000 0000h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

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10.6.4.11 CIS Pointer Register

The CARDBUS input to the 1394 OHCI core is tied high such that this register returns 0000 0000h when read.

PCI register offset:

Register type:

28h

Read only

0000 0000h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

10.6.4.12 Subsystem Vendor ID and Subsystem ID Registers

The subsystem vendor ID and subsystem ID registers are used for system and option card identification

purposes. These registers can be initialized from the serial EEPROM or programmed via the subsystem access

register at offset F8h in the PCI configuration space (see 节 10.6.4.23). See 表 10-77 for a complete description

of the register contents.

PCI register offset:

Register type:

2Ch

Read/Update

0000 0000h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-77. Subsystem Vendor ID and Subsystem ID Registers Description

BIT

31-16⁽¹⁾OHCI_SSID

15-0⁽¹⁾

OHCI_SSVID

FIELD NAME

TYPE

DESCRIPTION

RU

Subsystem device ID. This field indicates the subsystem device ID.

Subsystem vendor ID. This field indicates the subsystem vendor ID.

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10.6.4.13 Power Management Capabilities Pointer Register

The power management capabilities pointer register provides a pointer into the PCI configuration header where

the power-management register block resides. The OHCI controller configuration header double words at offsets

44h and 48h provide the power-management registers. This register is read only and returns 44h when read.

PCI register offset:

Register type:

34h

Read only

44h

Default value:

BIT NUMBER

RESET STATE

7

6

5

4

3

2

1

0

1

0

1

0

10.6.4.14 Interrupt Line and Interrupt Pin Registers

The interrupt line and interrupt pin registers communicate interrupt line routing information. See 表 10-78 for a

complete description of the register contents.

PCI register offset:

Register type:

3Ch

Read/Write

01FFh

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

表10-78. Interrupt Line and Interrupt Pin Registers Description

BIT

FIELD NAME

TYPE

DESCRIPTION

15-8

INTR_PIN

R

Interrupt pin. This field returns 01h when read, indicating that the 1394 OHCI core signals

interrupts on the INTA terminal.

7-0

INTR_LINE

RW

Interrupt line. This field is programmed by the system and indicates to software which interrupt

line the OHCI controller INTA is connected to. The default value for this field is all FFh, indicating

that an interrupt line has not yet been assigned to the function.

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10.6.4.15 Minimum Grant and Minimum Latency Registers

The minimum grant and minimum latency registers communicate to the system the desired setting of bits 15–8

in the latency timer and class cache line size register at offset 0Ch in the PCI configuration space (see 节

10.6.4.6). If a serial EEPROM is detected, the contents of these registers are loaded through the serial EEPROM

interface. If no serial EEPROM is detected, these registers return a default value that corresponds to the

MAX_LAT = 4, MIN_GNT = 2. See 表10-79 for a complete description of the register contents.

PCI register offset:

Register type:

3Eh

Read/Update

0402h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

表10-79. Minimum Grant and Minimum Latency Registers Description

BIT

FIELD NAME

TYPE

DESCRIPTION

15-8⁽¹⁾

MAX_LAT

RU

Maximum latency. The contents of this field may be used by the host BIOS to assign an

arbitration priority level to the OHCI controller. The default for this register indicates that the

OHCI controller may access the PCI bus as often as every 0.25 µs; thus, an extremely high

priority level is requested. Bits 11-8 of this field may also be loaded through the serial EEPROM.

7-0⁽¹⁾

MIN_GNT

RU

Minimum grant. The contents of this field may be used by the host BIOS to assign a latency

timer register value to the OHCI controller. The default for this register indicates that the OHCI

controller may sustain burst transfers for nearly 64 µs and, thus, request a large value be

programmed in bits 15-8 of the OHCI controller latency timer and class cache line size register at

offset 0Ch in the PCI configuration space (see 节10.6.4.6). Bits 3-0 of this field may also be

loaded through the serial EEPROM.

10.6.4.16 OHCI Control Register

The PCI OHCI control register is defined by the 1394 Open Host Controller Interface Specification and provides

a bit for big endian PCI support. See 表10-80 for a complete description of the register contents.

PCI register offset:

Register type:

40h

Read/Write, Read only

0000 0000h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-80. OHCI Control Register Description

BIT

31-1 RSVD

GLOBAL_SWAP

FIELD NAME

TYPE

DESCRIPTION

R

Reserved. Bits 31-1 return 000 0000 0000 0000 0000 0000 0000 0000b when read.

0

RW

When bit 0 is set to 1b, all quadlets read from and written to the PCI interface are byte swapped (big

endian). The default value for this bit is 0b, which is little endian mode.

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10.6.4.17 Capability ID and Next Item Pointer Registers

The capability ID and next item pointer registers identify the linked-list capability item and provide a pointer to the

next capability item. See 表10-81 for a complete description of the register contents.

PCI register offset:

Register type:

44h

Read only

0001h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

表10-81. Capability ID and Next Item Pointer Registers Description

BIT

FIELD NAME

TYPE

DESCRIPTION

15-8

NEXT_ITEM

R

Next item pointer. The OHCI controller supports only one additional capability that is communicated

to the system through the extended capabilities list; therefore, this field returns 00h when read.

7-0

CAPABILITY_ID

R

Capability identification. This field returns 01h when read, which is the unique ID assigned by the PCI

SIG for PCI power-management capability.

10.6.4.18 Power Management Capabilities Register

The power management capabilities register indicates the capabilities of the OHCI core related to PCI power

management. See 表10-82 for a complete description of the register contents.

PCI register offset:

Register type:

46h

Read only

7E03h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

表10-82. Power Management Capabilities Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

15-11 PME_SUPPORT

R

PME support. This 5-bit field indicates the power states from which the OHCI core may assert PME.

This field returns a value of 01111b, indicating that PME is asserted from the D3hot, D2, D1, and D0

power states.

10 D2_SUPPORT

R

D2 support. Bit 10 is hardwired to 1b, indicating that the OHCI controller supports the D2 power state.

D1 support. Bit 9 is hardwired to 1b, indicating that the OHCI controller supports the D1 power state.

Auxiliary current. This 3-bit field reports the 3.3-V_AUXauxiliary current requirements. This field returns

9

D1_SUPPORT

8-6 AUX_CURRENT

000b, because the 1394a core is not powered by V_AUX

.

5

DSI

R

Device-specific initialization. This bit returns 0b when read, indicating that the OHCI controller does

not require special initialization beyond the standard PCI configuration header before a generic class

driver is able to use it.

4

3

RSVD

R

Reserved. Bit 4 returns 0b when read.

PME_CLK

PME clock. This bit returns 0b when read, indicating that no host bus clock is required for the OHCI

controller to generate PME.

2-0 PM_VERSION

R

Power-management version. If bit 7 (PCI_PM_VERSION_CTRL) in the PCI miscellaneous

configuration register at offset F0h (see 节10.6.4.21) is 0b, this field returns 010b indicating Revision

1.1 compatibility. If PCI_PM_VERSION_CTRL in the PCI miscellaneous configuration register is 1b,

this field returns 011b indicating Revision 1.2 compatibility.

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10.6.4.19 Power Management Control and Status Register

The power management control and status register implements the control and status of the PCI power-

management function. This register is not affected by the internally-generated reset caused by the transition

from the D3hot to D0 state. See 表10-83 for a complete description of the register contents.

PCI register offset:

Register type:

48h

Read/Write, Read only

0000h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-83. Power Management Control and Status Register Description

BIT

15

FIELD NAME

TYPE

DESCRIPTION

PME_STS

R

PME status. This bit returns 0b, because PME is not supported.

This field returns 00b, because the data register is not implemented.

This field returns 0h, because the data register is not implemented.

This bit returns 0b, because PME is not supported.

14-13

12-9

8

DATA_SCALE

DATA_SELECT

PME_ENB

R

7-2

RSVD

R

Reserved. Bits 7-2 return 00 0000b when read.

1-0⁽¹⁾

PWR_STATE

RW

Power state. This 2-bit field sets the 1394b OHCI controller power state and is encoded

as:

00 = Current power state is D0 (default).

01 = Current power state is D1.

10 = Current power state is D2.

11 = Current power state is D3.

10.6.4.20 Power Management Extension Registers

The power management extension registers provide extended power-management features not applicable to the

OHCI controller; thus, they are read only and returns 0000h when read. See 表 10-84 for a complete description

of the register contents.

PCI register offset:

Register type:

4Ah

Read only

0000h

Default value:

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-84. Power Management Extension Registers Description

BIT

15-0

FIELD NAME

RSVD

TYPE

DESCRIPTION

R

Reserved. Bits 15-0 return 0000h when read.

10.6.4.21 PCI Miscellaneous Configuration Register

The PCI miscellaneous configuration register provides miscellaneous PCI-related configuration. See 表10-85 for

a complete description of the register contents.

PCI register offset:

Register type:

F0h

Read/Write, Read only

0000 0A90h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

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BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7⁽¹⁾

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

(1) These bits shall only be reset by a fundamental reset ( FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

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表10-85. PCI Miscellaneous Configuration Register

BIT

FIELD NAME

TYPE

DESCRIPTION

31-16 RSVD

R

Reserved. Bits 31-16 return 0000h when read.

15

PME_D3COLD

PME support from D3cold. The 1394a OHCI core does not support PME generation from

D3cold. Therefore, this bit is tied to 0b.

14-12 RSVD

R

Reserved. Bits 14-12 return 000b when read.

11

PCI2_3_EN

PCI 2.3 enable. The 1394 OHCI core always conforms to the PCI 2.3 specification;

therefore, this bit is tied to 1b.

10

10 IGNORE_

MSTRINT_

ENA_FOR_PME

RW

IGNORE_MSTRINT_ENA_FOR_PME bit for PME generation. When set, this bit causes bit

26 of the OHCI vendor ID register (OHCI offset 40h, see 节10.6.5.15) to read 1b.

Otherwise, bit 26 reads 0b.

0 = PME behavior generated from unmasked interrupt bits and

IntMask.masterIntEnable bit (default)

1 = PME generation does not depend on the value of IntMask.masterIntEnable.

9-8⁽¹⁾

MR_ENHANCE

This field selects the read command behavior of the PCI master for read transactions of

greater than two data phases. For read transactions of one or two data phases, a memory

read command is used.

00 = Memory read line

01 = Memory read

10 = Memory read multiple (default)

11 = Reserved, behavior reverts to default

7⁽¹⁾

PCI_PM_

VERSION_CTRL

RW

PCI power-management version control. This bit controls the value reported in the Version

field of the power management capabilities register of the 1394 OHCI function.

0 = Version fields report 010b for Power Management 1.1 compliance.

1 = Version fields report 011b for Power Management 1.2 compliance (default).

Reserved. Bits 6-5 return 00b when read.

6-5

4⁽¹⁾

RSVD

R

DIS_TGT_ABT

RW

Disable target abort. Bit 4 controls the no-target-abort mode, in which the OHCI controller

returns indeterminate data instead of signaling target abort. The OHCI LLC is divided into

the PCLK and SCLK domains. If software tries to access registers in the link that are not

active because the SCLK is disabled, a target abort is issued by the link. On some

systems, this can cause a problem resulting in a fatal system error. Enabling this bit allows

the link to respond to these types of requests by returning FFh.

0 = Responds with OHCI-Lynx compatible target abort.

1 = Responds with indeterminate data equal to FFh. It is recommended that this bit be

set to 1b (default).

3⁽¹⁾

SB_EN

RW

Serial bus enable. In the bridge, the serial bus interface is controlled using the bridge

configuration registers. Therefore, this bit has no effect in the 1394b OHCI function. The

default value for this bit is 0b.

2⁽¹⁾

DISABLE_

SCLKGATE

Disable SCLK test feature. This bit controls locking or unlocking the SCLK to the 1394a

OHCI core PCI bus clock input. This is a test feature only and must be cleared to 0b (all

applications).

0 = Hardware decides auto-gating of the PHY clock (default).

1 = Disables auto-gating of the PHY clock

1⁽¹⁾

DISABLE_ PCIGATE

KEEP_PCLK

RW

Disable PCLK test feature. This bit controls locking or unlocking the PCI clock to the 1394a

OHCI core PCI bus clock input. This is a test feature only and must be cleared to 0b (all

applications).

0 = Hardware decides auto-gating of the PCI clock (default).

1 = Disables auto-gating of the PCI clock

0⁽¹⁾

Keep PCI clock running. This bit controls the PCI clock operation during the CLKRUN

protocol. Since the CLKRUN protocol is not supported in the TSB82AF15, this bit has no

effect. The default value for this bit is 0b.

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10.6.4.22 Link Enhancement Control Register

The link enhancement control register implements TI proprietary bits that are initialized by software or by a serial

EEPROM, if present. After these bits are set to 1b, their functionality is enabled only if bit 22

(aPhyEnhanceEnable) in the host controller control register at OHCI offset 50h/54h (see 节 10.6.5.16, Host

Controller Control Register) is set to 1. See 表10-86 for a complete description of the register contents.

PCI register offset:

Register type:

F4h

Read/Write, Read only

0000 4000h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

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表10-86. Link Enhancement Control Register Description

BIT

31-16

15⁽¹⁾

FIELD NAME

TYPE

DESCRIPTION

RSVD

R

Reserved. Bits 31-16 return 0000h when read.

dis_at_pipeline

RW

Disable AT pipelining. When bit 15 is set to 1b, out-of-order AT pipelining is disabled. The

default value for this bit is 0b.

14⁽¹⁾

ENAB_DRAFT

RW

Enable OHCI 1.2 draft features. When this bit is set, it enables some features beyond the

OHCI 1.1 specification. Specifically, this enables HCControl.LPS to be cleared by writing a 1

to the HCControlClear.LPS bit and enables the link to set bit 9 in the xfer status field of AR

and IR context control registers. This bit can be initialized from an attached EEPROM.

13-12⁽¹⁾atx_thresh

RW

This field sets the initial AT threshold value, which is used until the AT FIFO is underrun.

When the OHCI controller retries the packet, it uses a 4K-byte threshold, resulting in a store-

and-forward operation.

00 = Threshold ~4K bytes resulting in a store-and-forward operation (default)

01 = Threshold ~1.7K bytes

10 = Threshold ~1K bytes

11 = Threshold ~512 bytes

These bits fine tune the asynchronous transmit threshold. For most applications, the 1.7K-

byte threshold is optimal. Changing this value may increase or decrease the 1394 latency

depending on the average PCI bus latency.

Setting the AT threshold to 1.7K, 1K, or 512 bytes results in data being transmitted at these

thresholds or when an entire packet has been checked into the FIFO. If the packet to be

transmitted is larger than the AT threshold, the remaining data must be received before the AT

FIFO is emptied; otherwise, an underrun condition occurs, resulting in a packet error at the

receiving node. As a result, the link then commences store-and-forward operation. Wait until it

has the complete packet in the FIFO before retransmitting it on the second attempt to ensure

delivery.

An AT threshold of 4K results in store-and-forward operation, which means that asynchronous

data is not transmitted until an end-of-packet token is received. Restated, setting the AT

threshold to 4K results in only complete packets being transmitted.

Note that the OHCI controller will always use store-and-forward when the asynchronous

transmit retries register at OHCI offset 08h (see 节10.6.5.3, Asynchronous Transmit Retries

Register) is cleared.

11

RSVD

R

Reserved. Bit 11 returns 0b when read.

10⁽¹⁾

enab_mpeg_ts

RW

Enable MPEG CIP timestamp enhancement. When bit 9 is set to 1b, the enhancement is

enabled for MPEG CIP transmit streams (FMT = 20h). The default value for this bit is 0b.

9

RSVD

R

Reserved. Bit 9 returns 0b when read.

8⁽¹⁾

enab_dv_ts

RW

Enable DV CIP timestamp enhancement. When bit 8 is set to 1b, the enhancement is enabled

for DV CIP transmit streams (FMT = 00h). The default value for this bit is 0b.

7⁽¹⁾

enab_unfair

RW

Enable asynchronous priority requests (OHCI-Lynx compatible). Setting bit 7 to 1b enables

the link to respond to requests with priority arbitration. It is recommended that this bit be set to

1b. The default value for this bit is 0b.

6-3

2⁽¹⁾

1⁽¹⁾

RSVD

R

Reserved. Bits 6-3 return 0h when read.

RSVD

RW

Reserved. Bit 2 defaults to 0b and must remain 0b for normal operation of the OHCI core.

enab_accel

Enable acceleration enhancements (OHCI-Lynx compatible). When bit 1 is set to 1b, the PHY

is notified that the link supports the IEEE Std 1394a-2000 acceleration enhancements, that is,

ack-accelerated, fly-by concatenation, etc. It is recommended that this bit be set to 1b. The

default value for this bit is 0b.

0⁽¹⁾

RSVD

R

Reserved. Bit 0 returns 0b when read.

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10.6.4.23 Subsystem Access Register

Write access to the subsystem access register identically updates the subsystem ID registers to OHCI-Lynx. The

system ID value written to this register may also be read back from this register. See 表 10-87 for a complete

description of the register contents.

PCI register offset:

Register type:

F8h

Read/Write

0000 0000h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-87. Subsystem Access Register Description

BIT

31-16⁽¹⁾SUBDEV_ID

15-0⁽¹⁾

SUBVEN_ID

FIELD NAME

TYPE

DESCRIPTION

RW

Subsystem device ID alias. This field indicates the subsystem device ID.

Subsystem vendor ID alias. This field indicates the subsystem vendor ID.

RW

10.6.5 1394 OHCI Memory-Mapped Register Space

The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory mapped into a

2K-byte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space

(see 节10.6.4.8). These registers are the primary interface for controlling the IEEE Std 1394 link function.

This section provides the register interface and bit descriptions. Several set/clear register pairs in this

programming model are implemented to solve various issues with typical read-modify-write control registers.

There are two addresses for a set/clear register — RegisterSet and RegisterClear (see 表 10-88 for register

listing). A 1 bit written to RegisterSet causes the corresponding bit in the set/clear register to be set to 1b; a 0 bit

leaves the corresponding bit unaffected. A 1 bit written to RegisterClear causes the corresponding bit in the set/

clear register to be cleared; a 0 bit leaves the corresponding bit in the set/clear register unaffected.

Typically, a read from either RegisterSet or RegisterClear returns the contents of the set or clear register,

respectively. However, sometimes reading the RegisterClear provides a masked version of the set or clear

register. The interrupt event register is an example of this behavior.

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表10-88. OHCI Register Map

DMA CONTEXT

REGISTER NAME

ABBREVIATION

OFFSET

00h

OHCI version

GUID ROM

Version

GUID_ROM

ATRetries

04h

Asynchronous transmit retries

CSR data

08h

CSRData

0Ch

10h

CSR compare

CSRCompareData

CSRControl

ConfigROMhdr

BusID

CSR control

14h

Configuration ROM header

Bus identification

Bus options⁽¹⁾

18h

1Ch

20h

BusOptions

GUIDHi

GUID high⁽¹⁾

24h

GUID low⁽¹⁾

GUIDLo

28h

Reserved⁽¹⁾

2Ch-30h

34h

Configuration ROM mapping

Posted write address low

Posted write address high

Vendor ID

ConfigROMmap

PostedWriteAddressLo

PostedWriteAddressHi

VendorID

38h

3Ch

40h

Reserved

44h-4Ch

50h

Host controller control ⁽¹⁾

HCControlSet

HCControlClr

54h

Reserved

58h-5Ch

60h

Self-ID

Reserved

Self-ID buffer pointer

Self-ID count

SelfIDBuffer

SelfIDCount

64h

68h

Reserved

6Ch

70h

Isochronous receive channel mask high

IRChannelMaskHiSet

IRChannelMaskHiClear

IRChannelMaskLoSet

IRChannelMaskLoClear

74h

Isochronous receive channel mask low

78h

7Ch

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表10-88. OHCI Register Map (continued)

DMA CONTEXT

REGISTER NAME

ABBREVIATION

OFFSET

80h

Interrupt event

Interrupt mask

IntEventSet

IntEventClear

84h

IntMaskSet

88h

IntMaskClear

8Ch

Isochronous transmit interrupt event

Isochronous transmit interrupt mask

Isochronous receive interrupt event

Isochronous receive interrupt mask

IsoXmitIntEventSet

IsoXmitIntEventClear

IsoXmitIntMaskSet

IsoXmitIntMaskClear

IsoRecvIntEventSet

IsoRecvIntEventClear

IsoRecvIntMaskSet

IsoRecvIntMaskClear

InitialBandwidthAvailable

InitialChannelsAvailableHi

InitialChannelsAvailableLo

90h

94h

98h

9Ch

A0h

A4h

A8h

ACh

Initial bandwidth available

Initial channels available high

Initial channels available low

Reserved

B0h

B4h

B8h

BCh-D8h

DCh

Fairness control

FairnessControl

LinkControlSet

LinkControlClear

NodeID

Link control ⁽¹⁾

E0h

E4h

Node identification

PHY control

E8h

PhyControl

ECh

Isochronous cycle timer

Reserved

Isocyctimer

F0h

F4h-FCh

100h

104h

108h

10Ch

110h

114h

118h

11Ch

120h

124h-17Ch

180h

184h

188h

18Ch

190h-19Ch

1A0h

1A4h

1A8h

1ACh

1B0h-1BCh

Asynchronous request filter high

AsyncRequestFilterHiSet

AsyncRequestFilterHiClear

AsyncRequestFilterLoSet

AsyncRequestFilterLoClear

PhysicalRequestFilterHiSet

PhysicalRequestFilterHiClear

PhysicalRequestFilterLoSet

PhysicalRequestFilterLoClear

PhysicalUpperBound

Asynchronous request filter low

Physical request filter high

Physical request filter low

Physical upper bound

Reserved

Asynchronous Request

Transmit

Asynchronous context control

ContextControlSet

ContextControlClear

(ATRQ)

Reserved

Asynchronous context command pointer

Reserved

CommandPtr

Asynchronous Response

Transmit

Asynchronous context control

ContextControlSet

ContextControlClear

(ATRS)

Reserved

Asynchronous context command pointer

Reserved

CommandPtr

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表10-88. OHCI Register Map (continued)

DMA CONTEXT

REGISTER NAME

ABBREVIATION

OFFSET

1C0h

Asynchronous Request

Receive

Asynchronous context control

ContextControlSet

ContextControlClear

1C4h

(ARRQ)

Reserved

1C8h

Asynchronous context command pointer

Reserved

CommandPtr

1CCh

1D0h-1DCh

1E0h

Asynchronous Response

Receive

Asynchronous context control

ContextControlSet

ContextControlClear

1E4h

(ARRS)

Reserved

1E8h

Asynchronous context command pointer

Reserved

CommandPtr

1ECh

1F0h-1FCh

200h + 16*n

204h + 16*n

208h + 16*n

20Ch + 16*n

210h-3FCh

400h + 32*n

404h + 32*n

408h + 32*n

40Ch + 32*n

410h + 32*n

Isochronous Transmit

Context n

n = 0, 1, 2, 3, ..., 7

Isochronous transmit context control

ContextControlSet

ContextControlClear

Reserved

Isochronous transmit context command pointer

Reserved

CommandPtr

Isochronous Receive

Context n

Isochronous receive context control

ContextControlSet

ContextControlClear

n = 0, 1, 2, 3

Reserved

Isochronous receive context command pointer

Isochronous receive context match

CommandPtr

ContextMatch

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10.6.5.1 OHCI Version Register

The OHCI version register indicates the OHCI version support and whether or not the serial EEPROM is present.

See 表10-89 for a complete description of the register contents.

OHCI register offset:

Register type:

00h

Read only

0X01 0010h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

X

0

1

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

表10-89. OHCI Version Register Description

DESCRIPTION

BIT

FIELD NAME

TYPE

31-25 RSVD

R

Reserved. Bits 31-25 return 000 0000b when read.

24⁽¹⁾GUID_ROM

23-16 version

15-8 RSVD

RU

The controller sets bit 24 to 1b if the serial EEPROM is detected. If the serial EEPROM is present, the

Bus_Info_Block is automatically loaded on system (hardware) reset. The default value for this bit is 0b.

R

Major version of the OHCI. The controller is compliant with the 1394 Open Host Controller Interface

Specification, Release 1.2; thus, this field reads 01h.

R

Reserved. Bits 15-8 return 00h when read.

7-0

revision

Minor version of the OHCI. The controller is compliant with the 1394 Open Host Controller Interface

Specification, Release 1.2; thus, this field reads 10h.

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10.6.5.2 GUID ROM Register

The GUID ROM register accesses the serial EEPROM, and is only applicable if bit 24 (GUID_ROM) in the OHCI

version register at OHCI offset 00h (see 节 10.6.5.1) is set to 1b. See 表 10-90 for a complete description of the

register contents.

OHCI register offset:

Register type:

04h

Read/Set/Update, Read/Update, Read only

00XX 0000h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

X

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-90. GUID ROM Register Description

BIT

FIELD NAME

addrReset

TYPE

DESCRIPTION

31

RSU

Software sets bit 31 to 1b to reset the GUID ROM address to 0. When the controller

completes the reset, it clears this bit. The controller does not automatically fill bits 23-16

(rdData field) with the 0 byte.

30-26 RSVD

R

Reserved. Bits 30-26 return 00 0000b when read.

25

rdStart

RSU

A read of the currently addressed byte is started when bit 25 is set to 1b. This bit is

automatically cleared when the controller completes the read of the currently addressed

GUID ROM byte.

24

RSVD

R

RU

R

Reserved. Bit 24 returns 0b when read.

23-16 rdData

This field contains the data read from the GUID ROM.

Reserved. Bits 15-8 return 00h when read.

15-8

7-0

RSVD

miniROM

R

The miniROM field defaults to 00h indicating that no miniROM is implemented. If an

EEPROM is implemented, all eight bits of this miniROM field are downloaded from

EEPROM word offset 28h. For this device, the miniROM field must be greater than 39h to

indicate a valid miniROM offset into the EEPROM.

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10.6.5.3 Asynchronous Transmit Retries Register

The asynchronous transmit retries register indicates the number of times the controller attempts a retry for

asynchronous DMA request transmit and for asynchronous physical and DMA response transmit. See 表 10-91

for a complete description of the register contents.

OHCI register offset:

Register type:

08h

Read/Write, Read only

0000 0000h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-91. Asynchronous Transmit Retries Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31-29 secondLimit

28-16 cycleLimit

15-12 RSVD

R

The second limit field returns 000b when read, because outbound dual-phase retry is

not implemented.

R

The cycle limit field returns 0 0000 0000 0000b when read, because outbound dual-

phase retry is not implemented.

R

Reserved. Bits 15-12 return 0h when read.

11-8

maxPhysRespRetries

RW

This field tells the physical response unit how many times to attempt to retry the transmit

operation for the response packet when a busy acknowledge or ack_data_error is

received from the target node. The default value for this field is 0h.

7-4

maxATRespRetries

maxATReqRetries

RW

This field tells the asynchronous transmit response unit how many times to attempt to

retry the transmit operation for the response packet when a busy acknowledge or

ack_data_error is received from the target node. The default value for this field is 0h.

3-0

This field tells the asynchronous transmit DMA request unit how many times to attempt

to retry the transmit operation for the response packet when a busy acknowledge or

ack_data_error is received from the target node. The default value for this field is 0h.

10.6.5.4 CSR Data Register

The CSR data register accesses the bus-management CSR registers from the host through compare-swap

operations. This register contains the data to be stored in a CSR if the compare is successful.

OHCI register offset:

Register type:

0Ch

Read only

XXXX XXXXh

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

X

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

X

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10.6.5.5 CSR Compare Register

The CSR compare register accesses the bus-management CSR registers from the host through compare-swap

operations. This register contains the data to be compared with the existing value of the CSR resource.

OHCI register offset:

Register type:

10h

Read only

XXXX XXXXh

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

X

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

X

10.6.5.6 CSR Control Register

The CSR control register accesses the bus-management CSR registers from the host through compare-swap

operations. This register controls the compare-swap operation and selects the CSR resource. See 表10-92 for a

complete description of the register contents.

OHCI register offset:

Register type:

14h

Read/Write, Read/Update, Read only

8000 000Xh

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

1

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

X

表10-92. CSR Control Register Description

BIT

FIELD NAME

csrDpme

TYPE

DESCRIPTION

31

RU

Bit 31 is set to 1b by the controller when a compare-swap operation is complete. It is

cleared whenever this register is written.

32-2

1-0

RSVD

csrSel

R

Reserved. Bits 30-2 return 0 0000 0000 0000 0000 0000 0000 0000b when read.

This field selects the CSR resource as follows:

RW

00 = BUS_MANAGER_ID

01 = BANDWIDTH_AVAILABLE

10 = CHANNELS_AVAILABLE_HI

11 = CHANNELS_AVAILABLE_LO

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10.6.5.7 Configuration ROM Header Register

The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM, offset

FFFF F000 0400h. See 表10-93 for a complete description of the register contents.

OHCI register offset:

Register type:

18h

Read/Write

0000 XXXXh

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

X

表10-93. Configuration ROM Header Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31-24 info_length

RW

Information length. IEEE Std 1394 bus-management field. Must be valid when bit 17

(linkEnable) in the host controller control register at OHCI offset 50h/54h (see 节10.6.5.16) is

set to 1b. The default value for this field is 0h.

23-16 crc_length

RW

CRC length. IEEE Std 1394 bus-management field. Must be valid when bit 17 (linkEnable) in

the host controller control register at OHCI offset 50h/54h (see 节10.6.5.16) is set to 1b. The

default value for this field is 0h.

15-0

rom_crc_value

ROM CRC value. IEEE Std 1394 bus-management field. Must be valid at any time bit 17

(linkEnable) in the host controller control register at OHCI offset 50h/54h (see 节10.6.5.16) is

set to 1b.

10.6.5.8 Bus Identification Register

The bus identification register externally maps to the first quadlet in the Bus_Info_Block and contains the

constant 3133 3934h, which is the ASCII value of 1394.

OHCI register offset:

Register type:

1Ch

Read only

3133 3934h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

1

0

1

0

1

0

1

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

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10.6.5.9 Bus Options Register

The bus options register externally maps to the second quadlet of the Bus_Info_Block. See 表 10-94 for a

complete description of the register contents.

OHCI register offset:

Register type:

20h

Read/Write, Read only

0000 B0X3h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

X

0

1

表10-94. Bus Options Register Description

BIT

FIELD NAME

irmc

TYPE

DESCRIPTION

31

30

29

28

27

RW

Isochronous resource-manager capable. IEEE Std 1394 bus-management field. Must be valid when

bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see 节10.6.5.16) is

set to 1b. The default value for this bit is 0b.

cmc

isc

RW

Cycle master capable. IEEE Std 1394 bus-management field. Must be valid when bit 17 (linkEnable)

in the host controller control register at OHCI offset 50h/54h (see 节10.6.5.16) is set to 1b. The

default value for this bit is 0b.

Isochronous support capable. IEEE Std 1394 bus-management field. Must be valid when bit 17

(linkEnable) in the host controller control register at OHCI offset 50h/54h (see 节10.6.5.16) is set to

1b. The default value for this bit is 0b.

bmc

pmc

Bus manager capable. IEEE Std 1394 bus-management field. Must be valid when bit 17 (linkEnable)

in the host controller control register at OHCI offset 50h/54h (see 节10.6.5.16) is set to 1b. The

default value for this bit is 0b.

Power-management capable. IEEE Std 1394 bus-management field. When bit 27 is set to 1b, this

indicates that the node is power-management capable. Must be valid when bit 17 (linkEnable) in the

host controller control register at OHCI offset 50h/54h (see 节10.6.5.16) is set to 1b. The default

value for this bit is 0b.

26-24 RSVD

R

Reserved. Bits 26-24 return 000b when read.

23-16 cyc_clk_acc

RW

Cycle master clock accuracy (in parts per million). IEEE Std 1394 bus-management field. Must be

valid when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see 节

10.6.5.16) is set to 1b. The default value for this field is 00h.

15-12⁽¹⁾max_rec

RW

Maximum request. IEEE Std 1394 bus-management field. Hardware initializes this field to indicate

the maximum number of bytes in a block request packet that is supported by the implementation.

This value, max_rec_bytes, must be 512 or greater, and is calculated by 2^(max_rec + 1). Software

may change this field; however, this field must be valid at any time bit 17 (linkEnable) in the host

controller control register at OHCI offset 50h/54h (see 节10.6.5.16) is set to 1b. A received block

write request packet with a length greater than max_rec_bytes may generate an ack_type_error.

This field is not affected by a software reset, and defaults to value indicating 4096 bytes on a system

(hardware) reset. The default value for this field is Bh.

11-8 RSVD

R

Reserved. Bits 11-8 return 0h when read.

7-6

g

RW

Generation counter. This field is incremented if any portion of the configuration ROM has been

incremented since the prior bus reset.

5-3

2-0

RSVD

R

Reserved. Bits 5-3 return 000b when read.

Lnk_spd

Link speed. This field returns 011b, indicating that the link speeds of 100M bit/s, 200M bit/s, 400M

bit/s, and 800M bit/s are supported.

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10.6.5.10 GUID High Register

The GUID high register represents the upper quadlet in a 64-bit global unique ID (GUID), which maps to the third

quadlet in the Bus_Info_Block. This register contains node_vendor_ID and chip_ID_hi fields. This register

initializes to 0000 0000h on a system (hardware) reset, which is an illegal GUID value. If a serial EEPROM is

detected, the contents of this register are loaded through the serial EEPROM interface. At that point, the

contents of this register cannot be changed. If no serial EEPROM is detected, the contents of this register are

loaded by the BIOS. At that point, the contents of this register cannot be changed. This register is reset by a

PCIe reset ( PERST), GRST, or the internally-generated power-on reset.

OHCI register offset:

Register type:

24h

Read only

0000 0000h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3⁽¹⁾

2⁽¹⁾

1⁽¹⁾

0⁽¹⁾

0

10.6.5.11 GUID Low Register

The GUID low register represents the lower quadlet in a 64-bit global unique ID (GUID), which maps to

chip_ID_lo in the Bus_Info_Block. This register initializes to 0000 0000h on a system (hardware) reset and

behaves identical to the GUID high register at OHCI offset 24h (see 节 10.6.5.10). This register is reset by

PERST, GRST, or the internally-generated power-on reset.

OHCI register offset:

Register type:

28h

Read only

0000 0000h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3⁽¹⁾

2⁽¹⁾

1⁽¹⁾

0⁽¹⁾

0

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10.6.5.12 Configuration ROM Mapping Register

The configuration ROM mapping register contains the start address within system memory that maps to the start

address of 1394 configuration ROM for this node. See 表 10-95 for a complete description of the register

contents.

OHCI register offset::

Register type:

34h

Read/Write

0000 0000h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-95. Configuration ROM Mapping Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31-10 configROMaddr

RW

Configuration ROM address. If a quadlet read request to 1394 offset FFFF F000 0400h through

offset FFFF F000 07FFh is received, the low-order ten bits of the offset are added to this register to

determine the host memory address of the read request. The default value for this field is all 0s.

9-0

RSVD

R

Reserved. Bits 9-0 return 00 0000 0000b when read.

10.6.5.13 Posted Write Address Low Register

The posted write address low register communicates error information if a write request is posted and an error

occurs while the posted data packet is being written. See 表 10-96 for a complete description of the register

contents.

OHCI register offset:

Register type:

38h

Read/Update

XXXX XXXXh

Default value:

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

X

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

X

表10-96. Posted Write Address Low Register Description

BIT

31-0

FIELD NAME

offsetLo

TYPE

DESCRIPTION

RU

Offset low. The lower 32 bits of the 1394 destination offset of the write request that failed.

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10.6.5.14 Posted Write Address High Register

The posted write address high register communicates error information if a write request is posted and an error

occurs while writing the posted data packet. See 表10-97 for a complete description of the register contents.

OHCI register offset:

Register type:

3Ch

Read/Update

XXXX XXXXh

Default value:

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

X

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

X

表10-97. Posted Write Address High Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31-16 sourceID

RU

Source identification. This field is the 10-bit bus number (bits 31-22) and 6-bit node number

(bits 21-16) of the node that issued the write request that failed.

15-0

offsetHi

RU

Offset high. The upper 16 bits of the 1394 destination offset of the write request that failed.

10.6.5.15 Vendor ID Register

The vendor ID register holds the company ID of an organization that specifies any vendor-unique registers. The

controller implements TI unique behavior with regards to OHCI. Thus, this register is read only and returns 0x08

0028h when read.

OHCI register offset:

Register type:

40h

Read only

0x08 0028h

Default value:

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

0

x

1

0

1

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

10.6.5.16 Host Controller Control Register

The host controller control set/clear register pair provides flags for controlling the controller. See 表 10-98 for a

complete description of the register contents.

OHCI register offset:

50h set register

54h clear register

Register type:

Default value:

Read/Set/Clear/Update, Read/Set/Clear, Read/Clear, Read only

0080 0000h

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

1

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

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表10-98. Host Controller Control Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31

BIBimageValid

RSU When bit 31 is set to 1b, the physical response unit is enabled to respond to block read

requests to host configuration ROM and to the mechanism for atomically updating

configuration ROM. Software creates a valid image of the bus_info_block in host

configuration ROM before setting this bit.

When this bit is cleared, the controller returns ack_type_error on block read requests to host

configuration ROM. Also, when this bit is cleared and a 1394 bus reset occurs, the

configuration ROM mapping register at OHCI offset 34h (see 节10.6.5.12), configuration

ROM header register at OHCI offset 18h (see 节10.6.5.7), and bus options register at OHCI

offset 20h (see 节10.6.5.9) are not updated.

Software can set this bit only when bit 17 (linkEnable) is 0b. Once bit 31 is set to 1b, it can be

cleared by a system (hardware) reset, a software reset, or if a fetch error occurs when the

controller loads bus_info_block registers from host memory.

30

29

noByteSwapData

ack_Tardy_enable

RSC Bit 30 controls whether physical accesses to locations outside the controller itself, as well as

any other DMA data accesses are byte swapped.

RSC Bit 29 controls the acknowledgement of ack_tardy. When bit 29 is set to 1b, ack_tardy may

be returned as an acknowledgment to accesses from the 1394 bus to the controller, including

accesses to the bus_info_block. The controller returns ack_tardy to all other asynchronous

packets addressed to the node. When the controller sends ack_tardy, bit 27 (ack_tardy) in

the interrupt event register at OHCI offset 80h/84h (see 节10.6.5.21) is set to 1b to indicate

the attempted asynchronous access.

Software ensures that bit 27 (ack_tardy) in the interrupt event register is 0b. Software also

unmasks wake-up interrupt events such as bit 19 (phy) and bit 27 (ack_tardy) in the interrupt

event register before placing the controller into the D1 power mode.

Software must not set this bit if the node is the 1394 bus manager.

28-24 RSVD

23⁽¹⁾

programPhyEnable

R

Reserved. Bits 28-24 return 00000b when read.

RC

Bit 23 informs upper-level software that lower-level software has consistently configured the

IEEE Std 1394a-2000 enhancements in the link and PHYs. When this bit is 1b, generic

software such as the OHCI driver is responsible for configuring IEEE Std 1394a-2000

enhancements in the PHY and bit 22 (aPhyEnhanceEnable). When this bit is 0b, the generic

software may not modify the IEEE Std 1394a-2000 enhancements in the PHY and cannot

interpret the setting of bit 22 (aPhyEnhanceEnable). This bit is initialized from serial

EEPROM.

22

aPhyEnhanceEnable

RSC When bits 23 (programPhyEnable) and 17 (linkEnable) are 11b, the OHCI driver can set bit

22 to 1b to use all IEEE Std 1394a-2000 enhancements. When bit 23 (programPhyEnable) is

cleared to 0b, the software does not change PHY enhancements or this bit.

21-20 RSVD

R

Reserved. Bits 21 and 20 return 00b when read.

19

LPS

RSC Bit 19 controls the link power status. Software must set this bit to 1b to permit the link-PHY

communication. A 0b prevents link-PHY communication.

The OHCI link is divided into two clock domains (PCLK and PHY_SCLK). If software tries to

access any register in the PHY_SCLK domain while the PHY_SCLK is disabled, a target

abort is issued by the link. This problem can be avoided by setting bit 4 (DIS_TGT_ABT) to

1b in the PCI miscellaneous configuration register at offset F0h in the PCI configuration

space (see 节10.6.4.21). This allows the link to respond to these types of request by

returning all Fs (hex).

OHCI registers at offsets DCh-F0h and 100h-11Ch are in the PHY_SCLK domain.

After setting LPS, software must wait approximately 10 ms before attempting to access any

of the OHCI registers. This gives the PHY_SCLK time to stabilize.

18

17

postedWriteEnable

linkEnable

RSC Bit 18 enables (1) or disables (0) posted writes. Software changes this bit only when bit 17

(linkEnable) is 0b.

RSC Bit 17 is cleared to 0b by either a system (hardware) or software reset. Software must set this

bit to 1b when the system is ready to begin operation and then force a bus reset. This bit is

necessary to keep other nodes from sending transactions before the local system is ready.

When this bit is cleared, the controller is logically and immediately disconnected from the

1394 bus, no packets are received or processed, nor are packets transmitted.

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BIT

表10-98. Host Controller Control Register Description (continued)

FIELD NAME

TYPE

DESCRIPTION

16

SoftReset

RSCU When bit 16 is set to 1b, all states are reset, all FIFOs are flushed, and all OHCI registers are

set to their system (hardware) reset values, unless otherwise specified. PCI registers are not

affected by this bit. This bit remains set to 1b while the software reset is in progress and

reverts back to 0b when the reset has completed.

15-0

RSVD

R

Reserved. Bits 15-0 return 0000h when read.

10.6.5.17 Self-ID Buffer Pointer Register

The self-ID buffer pointer register points to the 2K-byte-aligned base address of the buffer in host memory where

the self-ID packets are stored during bus initialization. Bits 31-11 are read/write accessible. Bits 10-0 are

reserved and return 000 0000 0000b when read.

OHCI register offset:

Register type:

64h

Read/Write, Read only

XXXX XX00h

Default value:

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

X

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

X

0

10.6.5.18 Self-ID Count Register

The self-ID count register keeps a count of the number of times the bus self-ID process has occurred, flags self-

ID packet errors, and keeps a count of the self-ID data in the self-ID buffer. See 表 10-99 for a complete

description of the register contents.

OHCI register offset:

Register type:

68h

Read/Update, Read only

X0XX 0000h

Default value:

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

X

0

X

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-99. Self-ID Count Register Description

BIT

31

FIELD NAME

selfIDError

TYPE

Description

RU

Self-ID error. When bit 31 is set to 1b, an error was detected during the most recent self-ID

packet reception. The contents of the self-ID buffer are undefined. This bit is cleared after a

self-ID reception in which no errors are detected. Note that an error can be a hardware error or

a host bus write error.

30-24 RSVD

R

Reserved. Bits 30-24 return 000 0000b when read.

23-16 selfIDGeneration

RU

Self-ID generation. The value in this field increments each time a bus reset is detected. This

field rolls over to 0 after reaching 255.

15-11 RSVD

R

Reserved. Bits 15-11 return 00000b when read.

10-2

1-0

selfIDSize

RSVD

RU

Self-ID size. This field indicates the number of quadlets that have been written into the self-ID

buffer for the current bits 23-16 (selfIDGeneration field). This includes the header quadlet and

the self-ID data. This field is cleared to 0 0000 0000b when the self-ID reception begins.

R

Reserved. Bits 1 and 0 return 00b when read.

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10.6.5.19 Isochronous Receive Channel Mask High Register

The isochronous receive channel mask high set/clear register enables packet receives from the upper 32

isochronous data channels. A read from either the set or clear register returns the content of the isochronous

receive channel mask high register. See 表10-100 for a complete description of the register contents.

OHCI register offset:

70h set register

74h clear register

Register type:

Default value:

Read/Set/Clear

XXXX XXXXh

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

X

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

X

表10-100. Isochronous Receive Channel Mask High Register Description

BIT

FIELD NAME

TYPE

RSC

DESCRIPTION

31 isoChannel63

30 isoChannel62

29 isoChannel61

28 isoChannel60

27 isoChannel59

26 isoChannel58

25 isoChannel57

24 isoChannel56

23 isoChannel55

22 isoChannel54

21 isoChannel53

20 isoChannel52

19 isoChannel51

18 isoChannel50

17 isoChannel49

16 isoChannel48

15 isoChannel47

14 isoChannel46

13 isoChannel45

12 isoChannel44

11 isoChannel43

10 isoChannel42

When bit 31 is set to 1b, the controller is enabled to receive from isochronous channel number 63.

When bit 30 is set to 1b, the controller is enabled to receive from isochronous channel number 62.

When bit 29 is set to 1b, the controller is enabled to receive from isochronous channel number 61.

When bit 28 is set to 1b, the controller is enabled to receive from isochronous channel number 60.

When bit 27 is set to 1b, the controller is enabled to receive from isochronous channel number 59.

When bit 26 is set to 1b, the controller is enabled to receive from isochronous channel number 58.

When bit 25 is set to 1b, the controller is enabled to receive from isochronous channel number 57.

When bit 24 is set to 1b, the controller is enabled to receive from isochronous channel number 56.

When bit 23 is set to 1b, the controller is enabled to receive from isochronous channel number 55.

When bit 22 is set to 1b, the controller is enabled to receive from isochronous channel number 54.

When bit 21 is set to 1b, the controller is enabled to receive from isochronous channel number 53.

When bit 20 is set to 1b, the controller is enabled to receive from isochronous channel number 52.

When bit 19 is set to 1b, the controller is enabled to receive from isochronous channel number 51.

When bit 18 is set to 1b, the controller is enabled to receive from isochronous channel number 50.

When bit 17 is set to 1b, the controller is enabled to receive from isochronous channel number 49.

When bit 16 is set to 1b, the controller is enabled to receive from isochronous channel number 48.

When bit 15 is set to 1b, the controller is enabled to receive from isochronous channel number 47.

When bit 14 is set to 1b, the controller is enabled to receive from isochronous channel number 46.

When bit 13 is set to 1b, the controller is enabled to receive from isochronous channel number 45.

When bit 12 is set to 1b, the controller is enabled to receive from isochronous channel number 44.

When bit 11 is set to 1b, the controller is enabled to receive from isochronous channel number 43.

When bit 10 is set to 1b, the controller is enabled to receive from isochronous channel number 42.

When bit 9 is set to 1b, the controller is enabled to receive from isochronous channel number 41.

When bit 8 is set to 1b, the controller is enabled to receive from isochronous channel number 40.

When bit 7 is set to 1b, the controller is enabled to receive from isochronous channel number 39.

When bit 6 is set to 1b, the controller is enabled to receive from isochronous channel number 38.

When bit 5 is set to 1b, the controller is enabled to receive from isochronous channel number 37.

When bit 4 is set to 1b, the controller is enabled to receive from isochronous channel number 36.

When bit 3 is set to 1b, the controller is enabled to receive from isochronous channel number 35.

When bit 2 is set to 1b, the controller is enabled to receive from isochronous channel number 34.

When bit 1 is set to 1b, the controller is enabled to receive from isochronous channel number 33.

9

8

7

6

5

4

3

2

1

isoChannel41

isoChannel40

isoChannel39

isoChannel38

isoChannel37

isoChannel36

isoChannel35

isoChannel34

isoChannel33

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表10-100. Isochronous Receive Channel Mask High Register Description (continued)

BIT

FIELD NAME

TYPE

DESCRIPTION

0

isoChannel32

RSC

When bit 0 is set to 1b, the controller is enabled to receive from isochronous channel number 32.

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10.6.5.20 Isochronous Receive Channel Mask Low Register

The isochronous receive channel mask low set/clear register enables packet receives from the lower 32

isochronous data channels. See 表10-101 for a complete description of the register contents.

OHCI register offset:

78h set register

7Ch clear register

Register type:

Default value:

Read/Set/Clear

XXXX XXXXh

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

X

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

X

表10-101. Isochronous Receive Channel Mask Low Register Description

BIT

FIELD NAME

TYPE

Description

31

30

isoChannel31

isoChannel30

RSC When bit 31 is set to 1b, the controller is enabled to receive from isochronous channel number 31.

RSC When bit 30 is set to 1b, the controller is enabled to receive from isochronous channel number 30.

RSC Bits 29-2 (isoChanneln, where n = 29, 28, 27, ..., 2) follow the same pattern as bits 31 and 30.

RSC When bit 1 is set to 1b, the controller is enabled to receive from isochronous channel number 1.

RSC When bit 0 is set to 1b, the controller is enabled to receive from isochronous channel number 0.

29-2 isoChanneln

1

0

isoChannel1

isoChannel0

10.6.5.21 Interrupt Event Register

The interrupt event set/clear register reflects the state of the various interrupt sources. The interrupt bits are set

to 1b by an asserting edge of the corresponding interrupt signal or by writing a 1b in the corresponding bit in the

set register. The only mechanism to clear a bit in this register is to write a 1b to the corresponding bit in the clear

register.

This register is fully compliant with the 1394 Open Host Controller Interface Specification, and the controller adds

a vendor-specific interrupt function to bit 30. When the interrupt event register is read, the return value is the bit-

wise AND function of the interrupt event and interrupt mask registers. See 表 10-102 for a complete description

of the register contents.

OHCI register offset:

80h

84h

set register

clear register [returns the content of the interrupt event register bit-wise ANDed with

the interrupt mask register when read]

Register type:

Default value:

Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read only

XXXX 0XXXh

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

0

X

0

X

0

X

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

X

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BIT

表10-102. Interrupt Event Register Description

FIELD NAME

TYPE

DESCRIPTION

31

30

RSVD

R

Reserved. Bit 31returns 0b when read.

vendorSpecific

RSC

This vendor-specific interrupt event is reported when either of the general-purpose interrupts

are asserted. The general-purpose interrupts are enabled by setting the corresponding bits

INT_3EN and INT_2EN (bits 31 and 23, respectively) to 1 in the GPIO control register at offset

FCh in the PCI configuration space.

29

28

27

SoftInterrupt

RSVD

RSC

R

Bit 29 is used by software to generate an interrupt for its own use.

Reserved. Bit 28 returns 0b when read.

ack_tardy

RSCU Bit 27 is set to 1b when bit 29 (AckTardyEnable) in the host controller control register at OHCI

offset 50h/54h (see 节10.6.5.16) is set to 1b and any of the following conditions occur:

a. Data is present in a receive FIFO that is to be delivered to the host.

b. The physical response unit is busy processing requests or sending responses.

c. The controller sent an ack_tardy acknowledgment.

26

25

phyRegRcvd

cycleTooLong

RSCU The controller has received a PHY register data byte that can be read from bits 23-16 in the

PHY control register at OHCI offset ECh (see 节10.6.5.33).

RSCU

If bit 21 (cycleMaster) in the link control register at OHCI offset E0h/E4h (see 节10.6.5.30) is

set to 1b, this indicates that over 125 µs has elapsed between the start of sending a cycle start

packet and the end of a subaction gap. Bit 21 (cycleMaster) in the link control register is

cleared by this event.

24

unrecoverableError

RSCU This event occurs when the controller encounters any error that forces it to stop operations on

any or all of its subunits, for example, when a DMA context sets its dead bit to 1b. While bit 24

is set to 1b, all normal interrupts for the context(s) that caused this interrupt are blocked from

being set to 1b.

23

22

cycleInconsistent

cycleLost

RSCU A cycle start was received that had values for the cycleSeconds and cycleCount fields that are

different from the values in bits 31-25 (cycleSeconds field) and bits 24-12 (cycleCount field) in

the isochronous cycle timer register at OHCI offset F0h (see 节10.6.5.34).

RSCU A lost cycle is indicated when no cycle_start packet is sent or received between two

successive cycleSynch events. A lost cycle can be predicted when a cycle_start packet does

not immediately follow the first subaction gap after the cycleSynch event or if an arbitration

reset gap is detected after a cycleSynch event without an intervening cycle start. Bit 22 may

be set to 1b either when a lost cycle occurs or when logic predicts that one will occur.

21

20

cycle64Seconds

cycleSynch

RSCU Indicates that the seventh bit of the cycle second counter has changed

RSCU Indicates that a new isochronous cycle has started. Bit 20 is set to 1b when the low-order bit of

the cycle count toggles.

19

18

phy

RSCU Indicates that the PHY requests an interrupt through a status transfer

regAccessFail

RSCU Indicates that a register access has failed due to a missing SCLK clock signal from the PHY.

When a register access fails, bit 18 is set to 1b before the next register access.

17

16

busReset

RSCU Indicates that the PHY has entered bus reset mode

selfIDcomplete

RSCU A self-ID packet stream has been received. It is generated at the end of the bus initialization

process. Bit 16 is turned off simultaneously when bit 17 (busReset) is turned on.

15

selfIDcomplete2

RSCU Secondary indication of the end of a self-ID packet stream. Bit 15 is set to 1b by the controller

when it sets bit 16 (selfIDcomplete), and retains the state, independent of bit 17 (busReset).

14-10 RSVD

R

Reserved. Bits 14-10 return 00000b when read.

9

8

7

lockRespErr

RSCU Indicates that the controller sent a lock response for a lock request to a serial bus register, but

did not receive an ack_complete

postedWriteErr

isochRx

RSCU Indicates that a host bus error occurred while the controller was trying to write a 1394 write

request, which had already been given an ack_complete, into system memory

RU

Isochronous receive DMA interrupt. Indicates that one or more isochronous receive contexts

have generated an interrupt. This is not a latched event; it is the logical OR of all bits in the

isochronous receive interrupt event register at OHCI offset A0h/A4h (see 节10.6.5.25) and

isochronous receive interrupt mask register at OHCI offset A8h/ACh (see 节10.6.5.26). The

isochronous receive interrupt event register indicates which contexts have been interrupted.

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表10-102. Interrupt Event Register Description (continued)

BIT

FIELD NAME

TYPE

DESCRIPTION

6

isochTx

RU

Isochronous transmit DMA interrupt. Indicates that one or more isochronous transmit contexts

have generated an interrupt. This is not a latched event; it is the logical OR of all bits in the

isochronous transmit interrupt event register at OHCI offset 90h/94h (see 节10.6.5.23) and

isochronous transmit interrupt mask register at OHCI offset 98h/9Ch (see 节10.6.5.24). The

isochronous transmit interrupt event register indicates which contexts have been interrupted.

5

4

3

2

1

0

RSPkt

RSCU Indicates that a packet was sent to an asynchronous receive response context buffer and the

descriptor xferStatus and resCount fields have been updated

RQPkt

RSCU Indicates that a packet was sent to an asynchronous receive request context buffer and the

descriptor xferStatus and resCount fields have been updated

ARRS

RSCU Asynchronous receive response DMA interrupt. Bit 3 is conditionally set to 1b upon completion

of an ARRS DMA context command descriptor.

ARRQ

RSCU Asynchronous receive request DMA interrupt. Bit 2 is conditionally set to 1b upon completion

of an ARRQ DMA context command descriptor.

respTxComplete

reqTxCompleter

RSCU Asynchronous response transmit DMA interrupt. Bit 1 is conditionally set to 1b upon

completion of an ATRS DMA command.

RSCU Asynchronous request transmit DMA interrupt. Bit 0 is conditionally set to 1b upon completion

of an ATRQ DMA command.

10.6.5.22 Interrupt Mask Register

The interrupt mask set/clear register enables the various interrupt sources. Reads from either the set register or

the clear register always return the contents of the interrupt mask register. In all cases except masterIntEnable

(bit 31) and vendorSpecific (bit 30), the enables for each interrupt event align with the interrupt event register bits

detailed in 表10-102.

This register is fully compliant with the 1394 Open Host Controller Interface Specification, and the controller adds

an interrupt function to bit 30. See 表10-103 for a complete description of bits 31 and 30.

OHCI register offset:

88h set register

8Ch clear register

Register type:

Default value:

Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read only

XXXX 0XXXh

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

X

0

X

0

X

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

X

表10-103. Interrupt Mask Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31

masterIntEnable

RSCU Master interrupt enable. If bit 31 is set to 1b, external interrupts are generated in accordance

with the interrupt mask register. If this bit is cleared, external interrupts are not generated,

regardless of the interrupt mask register settings.

30

29

VendorSpecific

SoftInterrupt

RSC

When this bit and bit 30 (vendorSpecific) in the interrupt event register at OHCI offset 80h/84h

(see 节10.6.5.21) are set to 11b, this vendor-specific interrupt mask enables interrupt

generation.

RSC

When this bit and bit 29 (SoftInterrupt) in the interrupt event register at OHCI offset 80h/84h

(see 节10.6.5.21) are set to 11b, this soft-interrupt mask enables interrupt generation.

28

27

RSVD

R

Reserved. Bit 28 returns 0b when read.

ack_tardy

RSC

When this bit and bit 27 (ack_tardy) in the interrupt event register at OHCI offset 80h/84h (see

节10.6.5.21) are set to 11b, this acknowledge-tardy interrupt mask enables interrupt

generation.

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BIT

表10-103. Interrupt Mask Register Description (continued)

FIELD NAME

TYPE

DESCRIPTION

26

25

24

23

phyRegRcvd

RSC

When this bit and bit 26 (phyRegRcvd) in the interrupt event register at OHCI offset 80h/84h

(see 节10.6.5.21) are set to 11b, this PHY register interrupt mask enables interrupt

generation.

cycleTooLong

RSC

When this bit and bit 25 (cycleTooLong) in the interrupt event register at OHCI offset 80h/84h

(see 节10.6.5.21) are set to 11b, this cycle-too-long interrupt mask enables interrupt

generation.

unrecoverableError

cycleInconsistent

When this bit and bit 24 (unrecoverableError) in the interrupt event register at OHCI offset

80h/84h (see 节10.6.5.21) are set to 11b, this unrecoverable-error interrupt mask enables

interrupt generation.

When this bit and bit 23 (cycleInconsistent) in the interrupt event register at OHCI offset

80h/84h (see 节10.6.5.21) are set to 11b, this inconsistent-cycle interrupt mask enables

interrupt generation.

22

21

cycleLost

RSC

When this bit and bit 22 (cycleLost) in the interrupt event register at OHCI offset 80h/84h (see

节10.6.5.21) are set to 11b, this lost-cycle interrupt mask enables interrupt generation.

cycle64Seconds

When this bit and bit 21 (cycle64Seconds) in the interrupt event register at OHCI offset

80h/84h (see 节10.6.5.21) are set to 11b, this 64-s cycle interrupt mask enables interrupt

generation.

20

cycleSynch

RSC

When this bit and bit 20 (cycleSynch) in the interrupt event register at OHCI offset 80h/84h

(see 节10.6.5.21) are set to 11b, this isochronous-cycle interrupt mask enables interrupt

generation.

19

18

phy

RSC

When this bit and bit 19 (phy) in the interrupt event register at OHCI offset 80h/84h (see 节

10.6.5.21) are set to 11b, this PHY-status-transfer interrupt mask enables interrupt generation.

regAccessFail

When this bit and bit 18 (regAccessFail) in the interrupt event register at OHCI offset 80h/84h

(see 节10.6.5.21) are set to 11b, this register-access-failed interrupt mask enables interrupt

generation.

17

16

busReset

RSC

When this bit and bit 17 (busReset) in the interrupt event register at OHCI offset 80h/84h (see

节10.6.5.21) are set to 11b, this bus-reset interrupt mask enables interrupt generation.

selfIDcomplete

When this bit and bit 16 (selfIDcomplete) in the interrupt event register at OHCI offset 80h/84h

(see 节10.6.5.21) are set to 11b, this self-ID-complete interrupt mask enables interrupt

generation.

15

selfIDcomplete2

RSC

When this bit and bit 15 (selfIDcomplete2) in the interrupt event register at OHCI offset

80h/84h (see 节10.6.5.21) are set to 11b, this second self-ID-complete interrupt mask

enables interrupt generation.

14-10 RSVD

lockRespErr

R

Reserved. Bits 14-10 return 00000b when read.

9

8

7

6

5

4

3

RSC

When this bit and bit 9 (lockRespErr) in the interrupt event register at OHCI offset 80h/84h

(see 节10.6.5.21) are set to 11b, this lock-response-error interrupt mask enables interrupt

generation.

postedWriteErr

isochRx

isochTx

RSPkt

RSC

When this bit and bit 8 (postedWriteErr) in the interrupt event register at OHCI offset 80h/84h

(see 节10.6.5.21) are set to 11b, this posted-write-error interrupt mask enables interrupt

generation.

When this bit and bit 7 (isochRx) in the interrupt event register at OHCI offset 80h/84h (see 节

10.6.5.21) are set to 11b, this isochronous-receive-DMA interrupt mask enables interrupt

generation.

When this bit and bit 6 (isochTx) in the interrupt event register at OHCI offset 80h/84h (see 节

10.6.5.21) are set to 11b, this isochronous-transmit-DMA interrupt mask enables interrupt

generation.

When this bit and bit 5 (RSPkt) in the interrupt event register at OHCI offset 80h/84h (see 节

10.6.5.21) are set to 11b, this receive-response-packet interrupt mask enables interrupt

generation.

RQPkt

When this bit and bit 4 (RQPkt) in the interrupt event register at OHCI offset 80h/84h (see 节

10.6.5.21) are set to 11b, this receive-request-packet interrupt mask enables interrupt

generation.

ARRS

When this bit and bit 3 (ARRS) in the interrupt event register at OHCI offset 80h/84h (see 节

10.6.5.21) are set to 11b, this asynchronous-receive-response-DMA interrupt mask enables

interrupt generation.

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表10-103. Interrupt Mask Register Description (continued)

BIT

FIELD NAME

TYPE

DESCRIPTION

2

ARRQ

RSC

When this bit and bit 2 (ARRQ) in the interrupt event register at OHCI offset 80h/84h (see 节

10.6.5.21) are set to 11b, this asynchronous-receive-request-DMA interrupt mask enables

interrupt generation.

1

0

respTxComplete

reqTxComplete

RSC

When this bit and bit 1 (respTxComplete) in the interrupt event register at OHCI offset 80h/84h

(see 节10.6.5.21) are set to 11b, this response-transmit-complete interrupt mask enables

interrupt generation.

When this bit and bit 0 (reqTxComplete) in the interrupt event register at OHCI offset 80h/84h

(see 节10.6.5.21) are set to 11b, this request-transmit-complete interrupt mask enables

interrupt generation.

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10.6.5.23 Isochronous Transmit Interrupt Event Register

The isochronous transmit interrupt event set/clear register reflects the interrupt state of the isochronous transmit

contexts. An interrupt is generated on behalf of an isochronous transmit context if an OUTPUT_LAST* command

completes and its interrupt bits are set to 1. Upon determining that the isochTx (bit 6) interrupt has occurred in

the interrupt event register at OHCI offset 80h/84h (see 节 10.6.5.21), software can check this register to

determine which context caused the interrupt. The interrupt bits are set to 1 by an asserting edge of the

corresponding interrupt signal, or by writing a 1b in the corresponding bit in the set register. The only mechanism

to clear a bit in this register is to write a 1b to the corresponding bit in the clear register. See 表 10-104 for a

complete description of the register contents.

OHCI register offset:

90h set register

94h clear register (returns the contents of the isochronous transmit interrupt event register bit-wise

ANDed with the isochronous transmit interrupt mask register when read)

Register type:

Default value:

Read/Set/Clear, Read only

0000 00XXh

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

X

表10-104. Isochronous Transmit Interrupt Event Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31-8

7

RSVD

R

Reserved. Bits 31-8 return 0000h when read.

isoXmit7

isoXmit6

isoXmit5

isoXmit4

isoXmit3

isoXmit2

isoXmit1

isoXmit0

RSC

Isochronous transmit context 7 caused the interrupt event register bit 6 (isochTx) interrupt.

Isochronous transmit context 6 caused the interrupt event register bit 6 (isochTx) interrupt.

Isochronous transmit context 5 caused the interrupt event register bit 6 (isochTx) interrupt.

Isochronous transmit context 4 caused the interrupt event register bit 6 (isochTx) interrupt.

Isochronous transmit context 3 caused the interrupt event register bit 6 (isochTx) interrupt.

Isochronous transmit context 2 caused the interrupt event register bit 6 (isochTx) interrupt.

Isochronous transmit context 1 caused the interrupt event register bit 6 (isochTx) interrupt.

Isochronous transmit context 0 caused the interrupt event register bit 6 (isochTx) interrupt.

6

5

4

3

2

1

0

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10.6.5.24 Isochronous Transmit Interrupt Mask Register

The isochronous transmit interrupt mask set/clear register enables the isochTx interrupt source on a per-channel

basis. Reads from either the set register or the clear register always return the contents of the isochronous

transmit interrupt mask register. In all cases, the enables for each interrupt event align with the isochronous

transmit interrupt event register bits detailed in 表10-104.

OHCI register offset:

98h set register

9Ch clear register

Register type:

Default value:

Read/Set/Clear, Read only

0000 00XX

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

X

10.6.5.25 Isochronous Receive Interrupt Event Register

The isochronous receive interrupt event set/clear register reflects the interrupt state of the isochronous receive

contexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_* command

completes and its interrupt bits are set to 1. Upon determining that the isochRx (bit 7) interrupt in the interrupt

event register at OHCI offset 80h/84h (see 节 10.6.5.21) has occurred, software can check this register to

determine which context(s) caused the interrupt. The interrupt bits are set to 1 by an asserting edge of the

corresponding interrupt signal or by writing a 1b in the corresponding bit in the set register. The only mechanism

to clear a bit in this register is to write a 1b to the corresponding bit in the clear register. See 表 10-105 for a

complete description of the register contents.

OHCI register offset:

A0h

A4h

set register

clear register (returns the contents of isochronous receive interrupt event register bit-wise

ANDed with the isochronous receive mask register when read)

Register type:

Default value:

Read/Set/Clear, Read only

0000 000Xh

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

X

表10-105. Isochronous Receive Interrupt Event Register Description

BIT

FIELD NAME

TYPE

Description

31-4 RSVD

R

Reserved. Bits 31-4 return 000 0000h when read.

3

2

1

0

isoRecv3

RSC

Isochronous receive channel 3 caused the interrupt event register bit 7 (isochRx) interrupt.

Isochronous receive channel 2 caused the interrupt event register bit 7 (isochRx) interrupt.

Isochronous receive channel 1 caused the interrupt event register bit 7 (isochRx) interrupt.

Isochronous receive channel 0 caused the interrupt event register bit 7 (isochRx) interrupt.

isoRecv2

isoRecv1

isoRecv0

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10.6.5.26 Isochronous Receive Interrupt Mask Register

The isochronous receive interrupt mask set/clear register enables the isochRx interrupt source on a per-channel

basis. Reads from either the set register or the clear register always return the contents of the isochronous

receive interrupt mask register. In all cases, the enables for each interrupt event align with the isochronous

receive interrupt event register bits detailed in 表10-105.

OHCI register offset:

A8h set register

ACh clear register

Register type:

Default value:

Read/Set/Clear, Read only

0000 0000h

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

10.6.5.27 Initial Bandwidth Available Register

The initial bandwidth available register value is loaded into the corresponding bus-management CSR register on

a system (hardware) or software reset. See 表10-106 for a complete description of the register contents.

OHCI register offset:

Register type:

B0h

Read only, Read/Write

0000 1333h

Default value:

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

表10-106. Initial Bandwidth Available Register Description

BIT

31-13 RSVD

12-0 InitBWAvailable

FIELD NAME

TYPE

DESCRIPTION

R

Reserved. Bits 31-13 return 000 0000 0000 0000 0000b when read.

RW

This field is reset to 1333h on a system (hardware) or software reset, and is not affected by a

1394 bus reset. The value of this field is loaded into the BANDWIDTH_AVAILABLE CSR

register upon a GRST, PERST, PRST, or 1394 bus reset.

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10.6.5.28 Initial Channels Available High Register

The initial channels available high register value is loaded into the corresponding bus-management CSR register

on a system (hardware) or software reset. See 表10-107 for a complete description of the register contents.

OHCI register offset:

Register type:

B4h

Read/Write

FFFF FFFFh

Default value:

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

1

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

表10-107. Initial Channels Available High Register Description

BIT

31-0

FIELD NAME

TYPE

Description

InitChanAvailHi

RW

This field is reset to FFFF_FFFFh on a system (hardware) or software reset, and is not affected by a

1394 bus reset. The value of this field is loaded into the CHANNELS_AVAILABLE_HI CSR register

upon a GRST, PERST, PRST, or 1394 bus reset.

10.6.5.29 Initial Channels Available Low Register

The initial channels available low register value is loaded into the corresponding bus-management CSR register

on a system (hardware) or software reset. See 表10-108 for complete description of the register contents.

OHCI register offset:

Register type:

B8h

Read/Write

FFFF FFFFh

Default value:

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

1

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

表10-108. Initial Channels Available Low Register Description

BIT

31-0

FIELD NAME

TYPE

DESCRIPTION

InitChanAvailLo

RW

This field is reset to FFFF_FFFFh on a system (hardware) or software reset, and is not affected by a

1394 bus reset. The value of this field is loaded into the CHANNELS_AVAILABL_LO CSR register

upon a GRST, PRST, PRST, or 1394 bus reset.

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10.6.5.30 Fairness Control Register

The fairness control register provides a mechanism by which software can direct the host controller to transmit

multiple asynchronous requests during a fairness interval. See 表 10-109 for a complete description of the

register contents.

OHCI register offset:

Register type:

DCh

Read only, Read/Write

0000 0000h

Default value:

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-109. Fairness Control Registre Description

DESCRIPTION

BIT

FIELD NAME

TYPE

R

31-8

7-0

RSVD

Reserved. Bits 31-8 return 00 0000h when read.

pri_req

RW

Priority requests. This field specifies the maximum number of priority arbitration requests for

asynchronous request packets that the link is permitted to make of the PHY during a fairness

interval. The default value for this field is 00h.

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10.6.5.31 Link Control Register

The link control set/clear register provides the control flags that enable and configure the link core protocol

portions of the controller. It contains controls for the receiver and cycle timer. See 表 10-110 for a complete

description of the register contents.

OHCI register offset:

E0h set register

E4h clear register

Register type:

Default value:

Read/Set/Clear/Update, Read/Set/Clear, Read only

00X0 0X00h

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

0

X

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

X

0

表10-110. Link Control Register Description

DESCRIPTION

BIT

FIELD NAME

TYPE

31-23 RSVD

R

Reserved. Bits 31-23 return 0 0000 0000b when read.

22

21

cycleSource

RSC When bit 22 is set to 1b, the cycle timer uses an external source (CYCLEIN) to determine when

to roll over the cycle timer. When this bit is cleared, the cycle timer rolls over when the timer

reaches 3072 cycles of the 24.576-MHz clock (125 µs).

cycleMaster

RSCU When bit 21 is set to 1b and the controller is root, it generates a cycle start packet every time the

cycle timer rolls over, based on the setting of bit 22 (cycleSource). When the controller is not root,

regardless of the setting of bit 21, the controller accepts received cycle start packets to maintain

synchronization with the node that is sending them. Bit 21 is automatically cleared when bit 25

(cycleTooLong) in the interrupt event register at OHCI offset 80h/84h (see 节10.6.5.21) is set to

1b. Bit 21 cannot be set to 1b until bit 25 (cycleTooLong) is cleared.

20

CycleTimerEnable

RSC When bit 20 is set to 1b, the cycle timer offset counts cycles of the 24.576-MHz clock and rolls

over at the appropriate time, based on the settings of the previous bits. When this bit is cleared,

the cycle timer offset does not count.

19-11 RSVD

R

Reserved. Bits 19-11 return 0 0000 0000b when read.

10

RcvPhyPkt

RSC When bit 10 is set to 1b, the receiver accepts incoming PHY packets into the AR request context

if the AR request context is enabled. This bit does not control receipt of self-ID packets.

9

RcvSelfID

RSC When bit 9 is set to 1b, the receiver accepts incoming self-ID packets. Before setting this bit to

1b, software must ensure that the self-ID buffer pointer register contains a valid address.

8-7

6⁽¹⁾

RSVD

R

Reserved. Bits 8 and 7 return 00b when read.

tag1SyncFilterLock

RS

When bit 6 is set to 1b, bit 6 (tag1SyncFilter) in the isochronous receive context match register

(see 节10.6.5.46) is set to 1b for all isochronous receive contexts. When bit 6 is cleared, bit 6

(tag1SyncFilter) in the isochronous receive context match register has read/write access.

5-0

RSVD

R

Reserved. Bits 5-0 return 00 0000b when read.

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10.6.5.32 Node Identification Register

The node identification register contains the address of the node on which the OHCI-Lynx chip resides, and

indicates the valid node number status. The 16-bit combination of the busNumber field (bits 15-6) and the

NodeNumber field (bits 5-0) is referred to as the node ID. See 表 10-111 for a complete description of the

register contents.

OHCI register offset:

Register type:

E8h

Read/Write/Update, Read/Update, Read only

0000 FFXXh

Default value:

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

X

表10-111. Node Identification Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31

IDValid

RU

Identification valid. Bit 31 indicates whether or not the controller has a valid node number. It is

cleared when a 1394 bus reset is detected and set to 1b when the controller receives a new node

number from its PHY.

30

root

RU

R

Root. Bit 30 is set to 1b during the bus reset process if the attached PHY is root.

Reserved. Bits 29 and 28 return 00b when read.

29-28 RSVD

27 CPS

26-16 RSVD

RU

R

Cable power status. Bit 27 is set to 1b if the PHY is reporting that cable power status is OK.

Reserved. Bits 26-16 return 000 0000 0000b when read.

15-6

busNumber

RWU Bus number. This field identifies the specific 1394 bus the controller belongs to when multiple 1394-

compatible buses are connected via a bridge. The default value for this field is all 1s.

5-0

NodeNumber

RU

Node number. This field is the physical node number established by the PHY during self

identification. It is automatically set to the value received from the PHY after the self-identification

phase. If the PHY sets the NodeNumber to 63, software must not set bit 15 (run) in the

asynchronous context control register (see 节10.6.5.40) for either of the AT DMA contexts.

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10.6.5.33 PHY Control Register

The PHY control register reads from or writes to a PHY register. See 表 10-112 for a complete description of the

register contents.

OHCI register offset:

Register type:

ECh

Read/Write/Update, Read/Write, Read/Update, Read only

0000 0000h

Default value:

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-112. PHY Control Register Description

BIT

31

FIELD NAME

rdDone

TYPE

DESCRIPTION

RU

Read done. Bit 31 is cleared to 0b by the controller when either bit 15 (rdReg) or bit 14 (wrReg) is set

to 1b. This bit is set to 1b when a register transfer is received from the PHY.

30-28 RSVD

27-24 rdAddr

23-16 rdData

R

Reserved. Bits 30-28 return 000b when read.

RU

Read address. This field is the address of the register most recently received from the PHY.

Read data,\. This field is the contents of a PHY register that has been read.

15

rdReg

RWU Read register. Bit 15 is set to 1b by software to initiate a read request to a PHY register, and is

cleared by hardware when the request has been sent. Bits 14 (wrReg) and 15 (rdReg) must not both

be set to 1b simultaneously.

14

wrReg

RWU Write register. Bit 14 is set to 1b by software to initiate a write request to a PHY register, and is

cleared by hardware when the request has been sent. Bits 14 (wrReg) and 15 (rdReg) must not both

be set to 1b simultaneously.

13-12 RSVD

R

Reserved. Bits 13 and 12 return 00b when read.

11.8

regAddr

RW

Register address. This field is the address of the PHY register to be written or read. The default

value for this field is 0h.

7.0

wrData

RW

Write data. This field is the data to be written to a PHY register and is ignored for reads. The default

value for this field is 00h.

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10.6.5.34 Isochronous Cycle Timer Register

The isochronous cycle timer register indicates the current cycle number and offset. When the controller is cycle

master, this register is transmitted with the cycle start message. When the controller is not cycle master, this

register is loaded with the data field in an incoming cycle start. In the event that the cycle start message is not

received, the fields can continue incrementing on their own (if programmed) to maintain a local time reference.

See 表10-113 for a complete description of the register contents.

OHCI register offset:

Register type:

F0h

Read/Write/Update

XXXX XXXXh

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

X

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

X

表10-113. Isochronous Cycle Timer Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31-25 cycleSeconds

24-12 cycleCount

RWU Cycle seconds. This field counts seconds [rollovers from bits 24-12 (cycleCount field)] modulo 128.

RWU Cycle count. This field counts cycles [rollovers from bits 11-0 (cycleOffset field)] modulo 8000.

11-0

cycleOffset

RWU Cycle offset. This field counts 24.576-MHz clocks modulo 3072, that is, 125 µs. If an external 8-kHz

clock configuration is being used, this field must be cleared to 000h at each tick of the external clock.

10.6.5.35 Asynchronous Request Filter High Register

The asynchronous request filter high set/clear register enables asynchronous receive requests on a per-node

basis, and handles the upper node IDs. When a packet is destined for either the physical request context or the

ARRQ context, the source node ID is examined. If the bit corresponding to the node ID is not set to 1b in this

register, the packet is not acknowledged and the request is not queued. The node ID comparison is done if the

source node is on the same bus as the controller. Nonlocal bus-sourced packets are not acknowledged unless

bit 31 in this register is set to 1b. See 表10-114 for a complete description of the register contents.

OHCI register offset:

100h set register

104 h clear register

Register type:

Default value:

Read/Set/Clear

0000 0000h

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

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表10-114. Asynchronous Request Filter High Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31 asynReqAllBuses

RSC If bit 31 is set to 1b, all asynchronous requests received by the controller from nonlocal bus nodes

are accepted.

30 asynReqResource62 RSC If bit 30 is set to 1b for local bus node number 62, asynchronous requests received by the controller

from that node are accepted.

29 asynReqResource61 RSC If bit 29 is set to 1b for local bus node number 61, asynchronous requests received by the controller

from that node are accepted.

28 asynReqResource60 RSC If bit 28 is set to 1b for local bus node number 60, asynchronous requests received by the controller

from that node are accepted.

27 asynReqResource59 RSC If bit 27 is set to 1b for local bus node number 59, asynchronous requests received by the controller

from that node are accepted.

26 asynReqResource58 RSC If bit 26 is set to 1b for local bus node number 58, asynchronous requests received by the controller

from that node are accepted.

25 asynReqResource57 RSC If bit 25 is set to 1b for local bus node number 57, asynchronous requests received by the controller

from that node are accepted.

24 asynReqResource56 RSC If bit 24 is set to 1b for local bus node number 56, asynchronous requests received by the controller

from that node are accepted.

23 asynReqResource55 RSC If bit 23 is set to 1b for local bus node number 55, asynchronous requests received by the controller

from that node are accepted.

22 asynReqResource54 RSC If bit 22 is set to 1b for local bus node number 54, asynchronous requests received by the controller

from that node are accepted.

21 asynReqResource53 RSC If bit 21 is set to 1b for local bus node number 53, asynchronous requests received by the controller

from that node are accepted.

20 asynReqResource52 RSC If bit 20 is set to 1b for local bus node number 52, asynchronous requests received by the controller

from that node are accepted.

19 asynReqResource51 RSC If bit 19 is set to 1b for local bus node number 51, asynchronous requests received by the controller

from that node are accepted.

18 asynReqResource50 RSC If bit 18 is set to 1b for local bus node number 50, asynchronous requests received by the controller

from that node are accepted.

17 asynReqResource49 RSC If bit 17 is set to 1b for local bus node number 49, asynchronous requests received by the controller

from that node are accepted.

16 asynReqResource48 RSC If bit 16 is set to 1b for local bus node number 48, asynchronous requests received by the controller

from that node are accepted.

15 asynReqResource47 RSC If bit 15 is set to 1b for local bus node number 47, asynchronous requests received by the controller

from that node are accepted.

14 asynReqResource46 RSC If bit 14 is set to 1b for local bus node number 46, asynchronous requests received by the controller

from that node are accepted.

13 asynReqResource45 RSC If bit 13 is set to 1b for local bus node number 45, asynchronous requests received by the controller

from that node are accepted.

12 asynReqResource44 RSC If bit 12 is set to 1b for local bus node number 44, asynchronous requests received by the controller

from that node are accepted.

11 asynReqResource43 RSC If bit 11 is set to 1b for local bus node number 43, asynchronous requests received by the controller

from that node are accepted.

10 asynReqResource42 RSC If bit 10 is set to 1b for local bus node number 42, asynchronous requests received by the controller

from that node are accepted.

9

8

7

6

asynReqResource41 RSC If bit 9 is set to 1b for local bus node number 41, asynchronous requests received by the controller

from that node are accepted.

asynReqResource40 RSC If bit 8 is set to 1b for local bus node number 40, asynchronous requests received by the controller

from that node are accepted.

asynReqResource39 RSC If bit 7 is set to 1b for local bus node number 39, asynchronous requests received by the controller

from that node are accepted.

asynReqResource38 RSC If bit 6 is set to 1b for local bus node number 38, asynchronous requests received by the controller

from that node are accepted.

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表10-114. Asynchronous Request Filter High Register Description (continued)

BIT

FIELD NAME

TYPE

DESCRIPTION

5

asynReqResource37 RSC If bit 5 is set to 1b for local bus node number 37, asynchronous requests received by the controller

from that node are accepted.

4

3

2

1

0

asynReqResource36 RSC If bit 4 is set to 1b for local bus node number 36, asynchronous requests received by the controller

from that node are accepted.

asynReqResource35 RSC If bit 3 is set to 1b for local bus node number 35, asynchronous requests received by the controller

from that node are accepted.

asynReqResource34 RSC If bit 2 is set to 1b for local bus node number 34, asynchronous requests received by the controller

from that node are accepted.

asynReqResource33 RSC If bit 1 is set to 1b for local bus node number 33, asynchronous requests received by the controller

from that node are accepted.

asynReqResource32 RSC If bit 0 is set to 1b for local bus node number 32, asynchronous requests received by the controller

from that node are accepted.

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10.6.5.36 Asynchronous Request Filter Low Register

The asynchronous request filter low set/clear register enables asynchronous receive requests on a per-node

basis, and handles the lower node IDs. Other than filtering different node IDs, this register behaves identically to

the asynchronous request filter high register. See 表10-115 for a complete description of the register contents.

OHCI register offset:

108h set register

10Ch clear register

Register type:

Default value:

Read/Set/Clear

0000 0000h

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-115. Asynchronous Request Filter Low Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31

30

29-2

1

asynReqResource31

RSC

If bit 31 is set to 1b for local bus node number 31, asynchronous requests received by the

controller from that node are accepted.

asynReqResource30

asynReqResourcen

asynReqResource1

asynReqResource0

RSC

If bit 30 is set to 1b for local bus node number 30, asynchronous requests received by the

controller from that node are accepted.

Bits 29 through 2 (asynReqResourcen, where n = 29, 28, 27, ..., 2) follow the same

pattern as bits 31 and 30.

If bit 1 is set to 1b for local bus node number 1, asynchronous requests received by the

controller from that node are accepted.

0

If bit 0 is set to 1b for local bus node number 0, asynchronous requests received by the

controller from that node are accepted.

10.6.5.37 Physical Request Filter High Register

The physical request filter high set/clear register enables physical receive requests on a per-node basis, and

handles the upper node IDs. When a packet is destined for the physical request context and the node ID has

been compared against the ARRQ registers, the comparison is done again with this register. If the bit

corresponding to the node ID is not set to 1b in this register, the request is handled by the ARRQ context instead

of the physical request context. The node ID comparison is done if the source node is on the same bus as the

controller. Nonlocal bus-sourced packets are not acknowledged unless bit 31 in this register is set to 1b. See 表

10-116 for a complete description of the register contents.

OHCI register offset:

110h set register

114h clear register

Register type:

Default value:

Read/Set/Clear

0000 0000h

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

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表10-116. Physical Request Filter High Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31 physReqAllBusses

RSC

If bit 31 is set to 1b, all asynchronous requests received by the controller from nonlocal bus nodes

are accepted. Bit 31 is not cleared by a PRST.

30 physReqResource6

2

RSC

If bit 30 is set to 1b for local bus node number 62, physical requests received by the controller from

that node are handled through the physical request context.

29 physReqResource6

1

If bit 29 is set to 1b for local bus node number 61, physical requests received by the controller from

that node are handled through the physical request context.

28 physReqResource6

0

If bit 28 is set to 1b for local bus node number 60, physical requests received by the controller from

that node are handled through the physical request context.

27 physReqResource5

9

If bit 27 is set to 1b for local bus node number 59, physical requests received by the controller from

that node are handled through the physical request context.

26 physReqResource5

8

If bit 26 is set to 1b for local bus node number 58, physical requests received by the controller from

that node are handled through the physical request context.

25 physReqResource5

7

If bit 25 is set to 1b for local bus node number 57, physical requests received by the controller from

that node are handled through the physical request context.

24 physReqResource5

6

If bit 24 is set to 1b for local bus node number 56, physical requests received by the controller from

that node are handled through the physical request context.

23 physReqResource5

5

If bit 23 is set to 1b for local bus node number 55, physical requests received by the controller from

that node are handled through the physical request context.

22 physReqResource5

4

If bit 22 is set to 1b for local bus node number 54, physical requests received by the controller from

that node are handled through the physical request context.

21 physReqResource5

3

If bit 21 is set to 1b for local bus node number 53, physical requests received by the controller from

that node are handled through the physical request context.

20 physReqResource5

2

If bit 20 is set to 1b for local bus node number 52, physical requests received by the controller from

that node are handled through the physical request context.

19 physReqResource5

1

If bit 19 is set to 1b for local bus node number 51, physical requests received by the controller from

that node are handled through the physical request context.

18 physReqResource5

0

If bit 18 is set to 1b for local bus node number 50, physical requests received by the controller from

that node are handled through the physical request context.

17 physReqResource4

9

If bit 17 is set to 1b for local bus node number 49, physical requests received by the controller from

that node are handled through the physical request context.

16 physReqResource4

8

If bit 16 is set to 1b for local bus node number 48, physical requests received by the controller from

that node are handled through the physical request context.

15 physReqResource4

7

If bit 15 is set to 1b for local bus node number 47, physical requests received by the controller from

that node are handled through the physical request context.

14 physReqResource4

6

If bit 14 is set to 1b for local bus node number 46, physical requests received by the controller from

that node are handled through the physical request context.

13 physReqResource4

5

If bit 13 is set to 1b for local bus node number 45, physical requests received by the controller from

that node are handled through the physical request context.

12 physReqResource4

4

If bit 12 is set to 1b for local bus node number 44, physical requests received by the controller from

that node are handled through the physical request context.

11 physReqResource4

3

If bit 11 is set to 1b for local bus node number 43, physical requests received by the controller from

that node are handled through the physical request context.

10 physReqResource4

2

If bit 10 is set to 1b for local bus node number 42, physical requests received by the controller from

that node are handled through the physical request context.

9

8

7

6

physReqResource4

1

If bit 9 is set to 1b for local bus node number 41, physical requests received by the controller from

that node are handled through the physical request context.

physReqResource4

0

If bit 8 is set to 1b for local bus node number 40, physical requests received by the controller from

that node are handled through the physical request context.

physReqResource3

9

If bit 7 is set to 1b for local bus node number 39, physical requests received by the controller from

that node are handled through the physical request context.

physReqResource3

8

If bit 6 is set to 1b for local bus node number 38, physical requests received by the controller from

that node are handled through the physical request context.

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表10-116. Physical Request Filter High Register Description (continued)

BIT

FIELD NAME

TYPE

DESCRIPTION

5

physReqResource3

7

RSC

If bit 5 is set to 1b for local bus node number 37, physical requests received by the controller from

that node are handled through the physical request context.

4

3

2

1

0

physReqResource3

6

RSC

If bit 4 is set to 1b for local bus node number 36, physical requests received by the controller from

that node are handled through the physical request context.

physReqResource3

5

If bit 3 is set to 1b for local bus node number 35, physical requests received by the controller from

that node are handled through the physical request context.

physReqResource3

4

If bit 2 is set to 1b for local bus node number 34, physical requests received by the controller from

that node are handled through the physical request context.

physReqResource3

3

If bit 1 is set to 1b for local bus node number 33, physical requests received by the controller from

that node are handled through the physical request context.

physReqResource3

2

If bit 0 is set to 1b for local bus node number 32, physical requests received by the controller from

that node are handled through the physical request context.

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10.6.5.38 Physical Request Filter Low Register

The physical request filter low set/clear register enables physical receive requests on a per-node basis, and

handles the lower node IDs. When a packet is destined for the physical request context and the node ID has

been compared against the asynchronous request filter registers, the node ID comparison is done again with this

register. If the bit corresponding to the node ID is not set to 1b in this register, the request is handled by the

asynchronous request context instead of the physical request context. See 表 10-117 for a complete description

of the register contents.

OHCI register offset:

118h set register

11Ch clear register

Register type:

Default value:

Read/Set/Clear

0000 0000h

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-117. Physical Request Filter Low Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31

physReqResource31 RSC If bit 31 is set to 1b for local bus node number 31, physical requests received by the controller

from that node are handled through the physical request context.

30

29-2

1

physReqResource30 RSC If bit 30 is set to 1b for local bus node number 30, physical requests received by the controller

from that node are handled through the physical request context.

physReqResourcen

physReqResource1

physReqResource0

RSC Bits 29 through 2 (physReqResourcen, where n = 29, 28, 27, ..., 2) follow the same pattern as

bits 31 and 30.

RSC If bit 1 is set to 1b for local bus node number 1, physical requests received by the controller from

that node are handled through the physical request context.

0

RSC If bit 0 is set to 1b for local bus node number 0, physical requests received by the controller from

that node are handled through the physical request context.

10.6.5.39 Physical Upper Bound Register (Optional Register)

The physical upper bound register is an optional register and is not implemented. This register returns 0000

0000h when read.

OHCI register offset:

Register type:

120h

Read only

0000 0000h

Default value:

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

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10.6.5.40 Asynchronous Context Control Register

The asynchronous context control set/clear register controls the state and indicates status of the DMA context.

See 表10-118 for a complete description of the register contents.

OHCI register offset:

180h

184h

1A0h

1A4h

1C0h

1C4h

1E0h

1E4h

set register

clear register

set register

clear register

set register

clear register

set register

clear register

(ATRQ)

[ATRS]

(ARRQ)

(ARRS)

Register type:

Default value:

Read/Set/Clear/Update, Read/Set/Update, Read/Update, Read only

0000 X0XXh

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

X

0

X

表10-118. Asynchronous Context Control Register Description

BIT

31-16 RSVD

15 run

FIELD NAME

TYPE

DESCRIPTION

R

Reserved. Bits 31-16 return 0000h when read.

RSCU Run. Bit 15 is set to 1b by software to enable descriptor processing for the context and cleared by

software to stop descriptor processing. The controller changes this bit only on a system

(hardware) or software reset.

14-13 RSVD

R

Reserved. Bits 14 and 13 return 00b when read.

12

wake

RSU

Wake. Software sets bit 12 to 1b to cause the controller to continue or resume descriptor

processing. The controller clears this bit on every descriptor fetch.

11

dead

RU

Dead. The controller sets bit 11 to 1b when it encounters a fatal error, and clears the bit when

software clears bit 15 (run). Asynchronous contexts supporting out-of-order pipelining provide

unique ContextControl.dead functionality. See Section 7.7 in the 1394 Open Host Controller

Interface Specification, Release 1.1 for more information.

10

9

active

RU

Active. The controller sets bit 10 to 1b when it is processing descriptors.

betaFrame

Beta frame. Set to 1 when the PHY indicates that the received packet is sent in beta format. A

response to a request sent using beta format also uses beta format.

8

RSVD

spd

R

Reserved. Bit 8 returns 0b when read.

7-5

RU

Speed. This field indicates the speed at which a packet was received or transmitted and only

contains meaningful information for receive contexts. This field is encoded as:

000 = 100M bit/s

001 = 200M bit/s

010 = 400M bit/s

011 = 800M bit/s0

All other values are reserved.

4-0

eventcode

RU

Event code. This field holds the acknowledge sent by the link core for this packet or an internally-

generated error code if the packet was not transferred successfully.

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10.6.5.41 Asynchronous Context Command Pointer Register

The asynchronous context command pointer register contains a pointer to the address of the first descriptor

block that the controller accesses when software enables the context by setting bit 15 (run) in the asynchronous

context control register (see 节 10.6.5.40) to 1b. See 表 10-119 for a complete description of the register

contents.

OHCI register offset:

18Ch

1ACh

1CCh

1ECh

(ATRQ)

(ATRS)

(ARRQ)

(ARRS)

Register type:

Default value:

Read/Write/Update

XXXX XXXXh

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

X

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

X

表10-119. Asynchronous Context Command Pointer Register Description

BIT

FIELD NAME

descriptorAddress

Z

TYPE

DESCRIPTION

31-4

3-0

RWU Contains the upper 28 bits of the address of a 16-byte aligned descriptor block.

RWU Indicates the number of contiguous descriptors at the address pointed to by the descriptor

address. If Z is 0h, it indicates that the descriptorAddress field (bits 31-4) is not valid.

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10.6.5.42 Isochronous Transmit Context Control Register

The isochronous transmit context control set/clear register controls options, state, and status for the isochronous

transmit DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2,

3, ..., 7). See 表10-120 for a complete description of the register contents.

OHCI register offset:

200h + (16 * n) set register

204h + (16 * n) clear register

Register type:

Default value:

Read/Set/Clear/Update, Read/Set/Clear, Read/Set/Update, Read/Update, Read only

XXXX X0XXh

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

X

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

X

0

X

表10-120. Isochronous Transmit Context Control Register Description ⁽¹⁾

BIT

31

FIELD NAME

TYPE

DESCRIPTION

cycleMatchEnable

RSCU When bit 31 is set to 1b, processing occurs such that the packet described by the context first

descriptor block is transmitted in the cycle whose number is specified in the cycleMatch field

(bits 30-16). The cycleMatch field (bits 30-16) must match the low-order two bits of

cycleSeconds and the 13-bit cycleCount field in the cycle start packet that is sent or received

immediately before isochronous transmission begins. Since the isochronous transmit DMA

controller may work ahead, the processing of the first descriptor block may begin slightly in

advance of the actual cycle in which the first packet is transmitted.

The effects of this bit, however, are impacted by the values of other bits in this register and are

explained in the 1394 Open Host Controller Interface Specification. Once the context has

become active, hardware clears this bit.

30-16 cycleMatch

RSC

This field contains a 15-bit value, corresponding to the low-order two bits of the isochronous

cycle timer register at OHCI offset F0h (see 节10.6.5.34) cycleSeconds field (bits 31-25) and

the cycleCount field (bits 24-12). If bit 31 (cycleMatchEnable) is set to 1b, this isochronous

transmit DMA context becomes enabled for transmits when the low-order two bits of the

isochronous cycle timer register at OHCI offset F0h cycleSeconds field (bits 31-25) and the

cycleCount field (bits 24-12) value equal this field (cycleMatch) value.

15

run

Bit 15 is set to 1b by software to enable descriptor processing for the context and cleared by

software to stop descriptor processing. The controller changes this bit only on a system

(hardware) or software reset.

14-13 RSVD

R

Reserved. Bits 14 and 13 return 00b when read.

12

wake

RSU

Software sets bit 12 to 1b to cause the controller to continue or resume descriptor processing.

The controller clears this bit on every descriptor fetch.

11

dead

RU

The controller sets bit 11 to 1b when it encounters a fatal error, and clears the bit when software

clears bit 15 (run) to 0b.

10

9-5

4-0

active

RU

R

The controller sets bit 10 to 1b when it is processing descriptors.

Reserved. Bits 9-5 return 00000b when read.

RSVD

eent code

RU

Following an OUTPUT_LAST* command, the error code is indicated in this field. Possible

values are ack_complete, evt_descriptor_read, evt_data_read, and evt_unknown.

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10.6.5.43 Isochronous Transmit Context Command Pointer Register

The isochronous transmit context command pointer register contains a pointer to the address of the first

descriptor block that the controller accesses when software enables an isochronous transmit context by setting

bit 15 (run) in the isochronous transmit context control register (see 节 10.6.5.42) to 1b. The isochronous

transmit DMA context command pointer can be read when a context is active. The n value in the following

register addresses indicates the context number (n = 0, 1, 2, 3, ..., 7).

OHCI register offset:

Register type:

20Ch + (16 * n)

Read only

Default value:

XXXX XXXXh

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

X

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

X

10.6.5.44 Isochronous Receive Context Control Register

The isochronous receive context control set/clear register controls options, state, and status for the isochronous

receive DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2,

3). See 表10-121 for a complete description of the register contents.

OHCI register offset:

400h + (32 * n) set register

404h + (32 * n) clear register

Register type:

Default value:

Read/Set/Clear/Update, Read/Set/Clear, Read/Set/Update, Read/Update, Read only

XX00 X0XXh

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

X

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

X

0

X

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表10-121. Isochronous Receive Context Control Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31

bufferFill

RSC

Buffer fill. When bit 31 is set to 1b, received packets are placed back to back to completely fill

each receive buffer. When this bit is cleared, each received packet is placed in a single buffer. If

bit 28 (multiChanMode) is set to 1b, this bit must also be set to 1b. The value of this bit must not

be changed while bit 10 (active) or bit 15 (run) is set to 1b.

30

isochHeader

RSC

Isochronous header. When bit 30 is set to 1b, received isochronous packets include the

complete 4-byte isochronous packet header seen by the link layer. The end of the packet is

marked with a xferStatus in the first doublet, and a 16-bit timestamp indicating the time of the

most recently received (or sent) cycleStart packet.

When this bit is cleared, the packet header is stripped from received isochronous packets. The

packet header, if received, immediately precedes the packet payload. The value of this bit must

not be changed while bit 10 (active) or bit 15 (run) is set to 1b.

29

28

cycleMatchEnable

multiChanMode

RSCU Cycle match enable. When bit 29 is set to 1b and the 13-bit cycleMatch field (bits 24-12) in the

isochronous receive context match register (See 节10.6.5.46) matches the 13-bit cycleCount

field in the cycleStart packet, the context begins running. The effects of this bit, however, are

impacted by the values of other bits in this register. Once the context has become active,

hardware clears this bit. The value of this bit must not be changed while bit 10 (active) or bit 15

(run) is set to 1b.

RSC

Multichannel mode. When bit 28 is set to 1b, the corresponding isochronous receive DMA

context receives packets for all isochronous channels enabled in the isochronous receive

channel mask high register at OHCI offset 70h/74h (see 节10.6.5.19) and isochronous receive

channel mask low register at OHCI offset 78h/7Ch (see 节10.6.5.20). The isochronous channel

number specified in the isochronous receive context match register (see 节10.6.5.46) is

ignored.

When this bit is cleared, the isochronous receive DMA context receives packets for the single

channel specified in the isochronous receive context match register (see 节10.6.5.46). Only one

isochronous receive DMA context may use the isochronous receive channel mask registers (see

节10.6.5.19, and 节10.6.5.20). If more than one isochronous receive context control register

has this bit set, the results are undefined. The value of this bit must not be changed while bit 10

(active) or bit 15 (run) is set to 1b.

27

dualBufferMode

RSC

Dual-buffer mode. When bit 27 is set to 1b, receive packets are separated into first and second

payload and streamed independently to the firstBuffer series and secondBuffer series as

described in Section 10.2.3 in the 1394 Open Host Controller Interface Specification. Also, when

bit 27 is set to 1b, both bits 28 (multiChanMode) and 31 (bufferFill) are cleared to 00b. The value

of this bit does not change when either bit 10 (active) or bit 15 (run) is set to 1b.

26-16

15

RSVD

run

R

Reserved. Bits 26-16 return 000 0000 0000b when read.

RSCU Run. Bit 15 is set to 1b by software to enable descriptor processing for the context and cleared

by software to stop descriptor processing. The controller changes this bit only on a system

(hardware) or software reset.

14-13

12

RSVD

wake

R

Reserved. Bits 14 and 13 return 00b when read.

RSU

Wake. Software sets bit 12 to 1b to cause the controller to continue or resume descriptor

processing. The controller clears this bit on every descriptor fetch.

11

dead

RU

Dead. The controller sets bit 11 to 1b when it encounters a fatal error, and clears the bit when

software clears bit 15 (run).

10

9

active

RU

Active. The controller sets bit 10 to 1b when it is processing descriptors.

betaFrame

Beta frame. Set to 1 when the PHY indicates that the received packet is sent in beta format. A

response to a request sent using beta format also uses beta format.

9-8

7-8

RSVD

spd

R

Reserved. Bit 8 returns 0b when read.

RU

Speed. This field indicates the speed at which the packet was received.

000 = 100M bit/s

001 = 200M bit/s

010 = 400M bit/s

011 = 800M bit/s0

All other values are reserved.

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BIT

表10-121. Isochronous Receive Context Control Register Description (continued)

FIELD NAME

TYPE

DESCRIPTION

4-0

event code

RU

For bufferFill mode, possible values are ack_complete, evt_descriptor_read, evt_data_write, and

evt_unknown. Packets with data errors (either dataLength mismatches or dataCRC errors) and

packets for which a FIFO overrun occurred are backed out. For packet-per-buffer mode,

possible values are ack_complete, ack_data_error, evt_long_packet, evt_overrun,

evt_descriptor_read, evt_data_write, and evt_unknown.

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10.6.5.45 Isochronous Receive Context Command Pointer Register

The isochronous receive context command pointer register contains a pointer to the address of the first

descriptor block that the controller accesses when software enables an isochronous receive context by setting

bit 15 (run) in the isochronous receive context control register (see 节 10.6.5.44) to 1b. The n value in the

following register addresses indicates the context number (n = 0, 1, 2, 3).

OHCI register offset:

Register type:

40Ch + (32 * n)

Read only

Default value:

XXXX XXXXh

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

X

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

X

10.6.5.46 Isochronous Receive Context Match Register

The isochronous receive context match register starts an isochronous receive context running on a specified

cycle number, filters incoming isochronous packets based on tag values, and waits for packets with a specified

sync value. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3). See 表

10-122 for a complete description of the register contents.

OHCI register offset:

Register type:

410h + (32 * n)

Read/Write, Read only

XXXX XXXXh

Default value:

BIT NUMBER

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

RESET STATE

X

0

X

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

X

表10-122. Isochronous Receive Context Match Register Description

BIT

FIELD NAME

TYPE

RW

R

DESCRIPTION

31

30

29

28

27

tag3

tag2

tag1

tag0

RSVD

If bit 31 is set to 1b, this context matches on isochronous receive packets with a tag field of 11b.

If bit 30 is set to 1b, this context matches on isochronous receive packets with a tag field of 10b.

If bit 29 is set to 1b, this context matches on isochronous receive packets with a tag field of 01b.

If bit 28 is set to 1b, this context matches on isochronous receive packets with a tag field of 00b.

Reserved. Bit 27 returns 0b when read.

26-12 cycleMatch

RW

This field contains a 15-bit value corresponding to the two low-order bits of cycleSeconds and the 13-

bit cycleCount field in the cycleStart packet. If cycleMatchEnable (bit 29) in the isochronous receive

context control register (see 节10.6.5.44) is set to 1b, this context is enabled for receives when the

two low-order bits of the isochronous cycle timer register at OHCI offset F0h (see 节10.6.5.34)

cycleSeconds field (bits 31-25) and cycleCount field (bits 24-12) value equal this field (cycleMatch)

value.

11-8 sync

RW

This 4-bit field is compared to the sync field of each isochronous packet for this channel when the

command descriptor w field is set to 11b.

7

6

RSVD

R

Reserved. Bit 7 returns 0b when read.

tag1SyncFilter

RW

If bit 6 and bit 29 (tag1) are set to 11b, packets with tag 01b are accepted into the context if the two

most significant bits of the packet sync field are 00b. Packets with tag values other than 01b are

filtered according to bit 28 (tag0), bit 30 (tag2), and bit 31 (tag3) without any additional restrictions.

If this bit is cleared, this context matches on isochronous receive packets as specified in bits 28-31

(tag0-tag3) with no additional restrictions.

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表10-122. Isochronous Receive Context Match Register Description (continued)

BIT

FIELD NAME

TYPE

DESCRIPTION

5-0

channelNumber

RW

This 6-bit field indicates the isochronous channel number for which this isochronous receive DMA

context accepts packets.

10.6.6 1394 OHCI Memory-Mapped TI Extension Register Space

The TI extension base address register provides a method of accessing memory-mapped TI extension registers.

See 节 10.6.4.9, TI Extension Base Address Register, for register bit field details. See 表 10-123 for the TI

extension register listing.

表10-123. TI Extension Register Map

REGISTER NAME

OFFSET

00h-A7Fh

A80h

Reserved

Isochronous receive digital video enhancement set

Isochronous receive digital video enhancement clear

Link enhancement control set

A84h

A88h

Link enhancement control clear

A8Ch

Isochronous transmit context 0 timestamp offset

Isochronous transmit context 1 timestamp offset

Isochronous transmit context 2 timestamp offset

Isochronous transmit context 3 timestamp offset

Isochronous transmit context 4 timestamp offset

Isochronous transmit context 5 timestamp offset

Isochronous transmit context 6 timestamp offset

Isochronous transmit context 7 timestamp offset

Reserved

A90h

A94h

A98h

A9Ch

AA0h

AA4h

AA8h

AACh

AB0h-FFFh

10.6.6.1 Digital Video (DV) and MPEG2 Timestamp Enhancements

The DV timestamp enhancements are enabled by bit 8 (enab_dv_ts) in the link enhancement control register

located at PCI offset F4h, and are aliased in TI extension register space at offset A88h (set) and A8Ch (clear).

The DV and MPEG transmit enhancements are enabled separately by bits in the link enhancement control

register located in PCI configuration space at PCI offset F4h. The link enhancement control register is also

aliased as a set/clear register in TI extension space at offset A88h (set) and A8Ch (clear).

Bit 8 (enab_dv_ts) of the link enhancement control register enables DV timestamp support. When enabled, the

link calculates a timestamp based on the cycle timer and the timestamp offset register and substitutes it in the

SYT field of the CIP once per DV frame.

Bit 10 (enab_mpeg_ts) of the link enhancement control register enables MPEG timestamp support. Two MPEG

timestamp modes are supported. The default mode calculates an initial delta that is added to the calculated

timestamp in addition to a user-defined offset. The initial offset is calculated as the difference in the intended

transmit cycle count and the cycle count field of the timestamp in the first TSP of the MPEG2 stream. The use of

the initial delta can be controlled by bit 31 (DisableInitialOffset) in the timestamp offset register (see 节10.6.6.5).

The MPEG2 timestamp enhancements are enabled by bit 10 (enab_mpeg_ts) in the link enhancement control

register located at PCI offset F4h, and aliased in TI extension register space at offset A88h (set) and A8Ch

(clear).

When bit 10 (enab_mpeg_ts) is set to 1b, the hardware applies the timestamp enhancements to isochronous

transmit packets that have the tag field equal to 01b in the isochronous packet header and a FMT field equal to

10h.

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10.6.6.2 Isochronous Receive Digital Video Enhancements

The DV frame sync and branch enhancement provides a mechanism in buffer-fill mode to synchronize 1394 DV

data that is received in the correct order to DV frame-sized data buffers described by several INPUT_MORE

descriptors (see 1394 Open Host Controller Interface Specification, Release 1.1). This is accomplished by

waiting for the start-of-frame packet in a DV stream before transferring the received isochronous stream into the

memory buffer described by the INPUT_MORE descriptors. This can improve the DV capture application

performance by reducing the amount of processing overhead required to strip the CIP header and copy the

received packets into frame-sized buffers.

The start of a DV frame is represented in the 1394 packet as a 16-bit pattern of 1FX7h (first byte 1Fh and

second byte X7h) received as the first two bytes of the third quadlet in a DV isochronous packet.

10.6.6.3 Isochronous Receive Digital Video Enhancement Registers

The isochronous receive digital video enhancement registers enable the DV enhancements in the controller. The

bits in these registers may only be modified when both the active (bit 10) and run (bit 15) bits of the

corresponding context control register are 00b. See 表10-124 for a complete description of the register contents.

TI extension register offset:

A80h set register

A84h clear register

Register type:

Default value:

Read/Set/Clear, Read only

0000 0000h

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-124. Isochronous Receive Digital Video Enhancement Registers Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31-14 RSVD

R

Reserved. Bits 31-14 return 00 0000 0000 0000 0000b when read.

13

12

DV_Branch3

RSC When bit 13 is set to 1b, the isochronous receive context 3 synchronizes reception to the DV frame

start tag in bufferfill mode if input_more.b = 01b, and jumps to the descriptor pointed to by

frameBranch if a DV frame start tag is received out of place. This bit is only interpreted when bit 12

(CIP_Strip3) is set to 1b and bit 30 (isochHeader) in the isochronous receive context control register

at OHCI offset 460h/464h (see 节10.6.5.44) is cleared to 0b.

CIP_Strip3

RSC When bit 12 is set to 1b, the isochronous receive context 3 strips the first two quadlets of payload.

This bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control

register at OHCI offset 460h/464h (see 节10.6.5.44) is cleared to 0b.

11-10 RSVD

R

Reserved. Bits 11 and 10 return 00b when read.

9

DV_Branch2

RSC When bit 9 is set to 1b, the isochronous receive context 2 synchronizes reception to the DV frame

start tag in bufferfill mode if input_more.b = 01b, and jumps to the descriptor pointed to by

frameBranch if a DV frame start tag is received out of place. This bit is only interpreted when bit 8

(CIP_Strip2) is set to 1b and bit 30 (isochHeader) in the isochronous receive context control register

at OHCI offset 440h/444h (see 节10.6.5.44) is cleared to 0b.

8

CIP_Strip2

RSC When bit 8 is set to 1b, the isochronous receive context 2 strips the first two quadlets of payload. This

bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control register at

OHCI offset 440h/444h (see 节10.6.5.44) is cleared to 0b.

7-6

5

RSVD

R

Reserved. Bits 7 and 6 return 00b when read.

DV_Branch1

TSC When bit 5 is set to 1b, the isochronous receive context 1 synchronizes reception to the DV frame

start tag in bufferfill mode if input_more.b = 01b, and jumps to the descriptor pointed to by

frameBranch if a DV frame start tag is received out of place. This bit is only interpreted when bit 4

(CIP_Strip1) is set to 1b and bit 30 (isochHeader) in the isochronous receive context control register

at OHCI offset 420h/424h (see 节10.6.5.44) is cleared to 0b.

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表10-124. Isochronous Receive Digital Video Enhancement Registers Description (continued)

BIT

FIELD NAME

TYPE

DESCRIPTION

4

CIP_Strip1

RSC When bit 4 is set to 1b, the isochronous receive context 1 strips the first two quadlets of payload. This

bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control register at

OHCI offset 420h/424h (see 节10.6.5.44) is cleared to 0b.

3-2

1

RSVD

R

Reserved. Bits 3 and 2 return 00b when read.

DV_Branch0

RSC When bit 1 is set to 1b, the isochronous receive context 0 synchronizes reception to the DV frame

start tag in bufferfill mode if input_more.b = 01b and jumps to the descriptor pointed to by

frameBranch a DV frame start tag is received out of place. This bit is only interpreted when bit 0

(CIP_Strip0) is set to 1b and bit 30 (isochHeader) in the isochronous receive context control register

at OHCI offset 400h/404h (see 节10.6.5.44) is cleared to 0b.

0

CIP_Strip0

RSC When bit 0 is set to 1b, the isochronous receive context 0 strips the first two quadlets of payload. This

bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control register at

OHCI offset 400h/404h (see 节10.6.5.44) is cleared to 0b.

10.6.6.4 Link Enhancement Control Registers

These registers are a memory-mapped set/clear registers that are an alias of the link enhancement control

register at PCI offset F4h. These bits may be initialized by software. Some of the bits may also be initialized by a

serial EEPROM, if one is present, as noted in the following bit descriptions. If the bits are to be initialized by

software, the bits must be initialized prior to setting bit 19 (LPS) in the host controller control register at OHCI

offset 50h/54h (see 节10.6.5.16). See 表10-125 for a complete description of the register contents.

TI extension register offset:

A88h set register

A8Ch clear register

Register type:

Default value:

Read/Set/Clear, Read only

0000 0000h

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

表10-125. Link Enhancement Control Registers Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31-16 RSVD

R

Reserved. Bits 31-16 return 0000h when read.

15⁽¹⁾

dis_at_pipleline

RW

Disable AT pipelining. When bit 15 is set to 1b, out-of-order AT pipelining is disabled. The default

value for this bit is 0b.

14⁽¹⁾

RSVD

RW

Reserved. Bit 14 defaults to 0b and must remain 0b for normal operation of the OHCI core.

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表10-125. Link Enhancement Control Registers Description (continued)

BIT

FIELD NAME

TYPE

DESCRIPTION

13-12 ⁽¹⁾atx_thresh

RW

This field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When the

OHCI controller retries the packet, it uses a 2K-byte threshold, resulting in a store-and-forward

operation.

00 = Threshold ~2K bytes resulting in a store-and-forward operation

01 = Threshold ~1.7K bytes (default)

10 = Threshold ~1K bytes

11 = Threshold ~512 bytes

These bits fine tune the asynchronous transmit threshold. For most applications the 1.7K-byte

threshold is optimal. Changing this value may increase or decrease the 1394 latency depending on

the average PCI bus latency.

Setting the AT threshold to 1.7K, 1K, or 512 bytes results in data being transmitted at these

thresholds or when an entire packet has been checked into the FIFO. If the packet to be transmitted

is larger than the AT threshold, the remaining data must be received before the AT FIFO is emptied;

otherwise, an underrun condition occurs, resulting in a packet error at the receiving node. As a

result, the link then commences store-and-forward operation. Wait until it has the complete packet

in the FIFO before retransmitting it on the second attempt to ensure delivery.

An AT threshold of 2K results in store-and-forward operation, which means that asynchronous data

will not be transmitted until an end-of-packet token is received. Restated, setting the AT threshold to

2K results in only complete packets being transmitted.

Note that the OHCI controller will always use store-and-forward when the asynchronous transmit

retries register at OHCI offset 08h (see 节10.6.5.3, Asynchronous Transmit Retries Register) is

cleared.

11

RSVD

R

Reserved. Bit 11 returns 0b when read.

10⁽¹⁾

enab_mpeg_ts

RW

Enable MPEG timestamp enhancement. When this bit is set, Cheetah-Express shall apply time

stamp enhancements to isochronous transmit packets that have the tag field equal to 2b01 in the

isochronous packet header and a FMT field equal to 6h10.

9

RSVD

R

Reserved. Bit 9 returns 0b when read.

8⁽¹⁾

enab_dv_ts

RW

Enable DV CIP timestamp enhancement. When bit 8 is set to 1b, the enhancement is enabled for

DV CIP transmit streams (FMT = 00h). The default value for this bit is 0b.

7⁽¹⁾

enab_unfair

RW

Enable asynchronous priority requests (OHCI-Lynx compatible). Setting bit 7 to 1b enables the link

to respond to requests with priority arbitration. It is recommended that this bit be set to 1b. The

default value for this bit is 0b.

6-3

2⁽¹⁾

RSVD

R

Reserved. Bits 6-3 return 0h when read.

enab_insert_idle

RW

Enable insert idle (OHCI-Lynx compatible). When the PHY has control of the Ct[0:1] internal control

lines and D[0:8] internal data lines and the link requests control, the PHY drives 11b on the Ct[0:1]

lines. The link can then start driving these lines immediately. Setting this bit to 1 inserts an idle

state, so the link waits one clock cycle before it starts driving the lines (turnaround time). It is

recommended that this bit be set to 1. For use with TI phys this bit should be set to 0. If a serial

EEPROM is implemented this bit is initialized with the value of EEPROM word 0x05 bit 2.

1⁽¹⁾

enab_accel

RSVD

RW

R

Enable acceleration enhancements (OHCI-Lynx compatible). When bit 1 is set to 1b, the PHY is

notified that the link supports the IEEE Std 1394a-2000 acceleration enhancements, that is, ack-

accelerated, fly-by concatenation, etc. It is recommended that this bit be set to 1b. The default value

for this bit is 0b.

0

Reserved. Bit 0 returns 0b when read.

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10.6.6.5 Timestamp Offset Registers

The value of these registers is added as an offset to the cycle timer value when using the MPEG, DV, and CIP

enhancements. A timestamp offset register is implemented per isochronous transmit context. The n value

following the offset indicates the context number (n = 0, 1, 2, 3, ..., 7). These registers are programmed by

software as appropriate. See 表10-126 for a complete description of the register contents.

TI extension register offset:

Register type:

A90h + (4*n)

Read/Write, Read only

0000 0000h

Default value:

BIT NUMBER

RESET STATE

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

0

BIT NUMBER

RESET STATE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

表10-126. Timestamp Offset Registers Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31

DisableInitialOffset

RW

Bit 31 disables the use of the initial timestamp offset when the MPEG2 enhancements are

enabled. A value of 0b indicates the use of the initial offset, a value of 1b indicates that the

initial offset must not be applied to the calculated timestamp. This bit has no meaning for the

DV timestamp enhancements. The default value for this bit is 0b.

3-=25 RSVD

R

Reserved. Bits 30-25 return 000 0000b when read.

24-12 CycleCount

RW

This field adds an offset to the cycle count field in the timestamp when the DV or MPEG2

enhancements are enabled. The cycle count field is incremented modulo 8000; therefore,

values in this field must be limited between 0 and 7999. The default value for this field is all 0s.

11-0

CycleOffset

RW

This field adds an offset to the cycle offset field in the timestamp when the DV or MPEG2

enhancements are enabled. The cycle offset field is incremented modulo 3072; therefore,

values in this field must be limited between 0 and 3071. The default value for this field is all 0s.

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11 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

11.1 Known exceptions to functional specification (errata).

11.1.1 Errata # 1: UR bit incorrectly set in the uncorrectable error status register when the ANFES bit is

set

11.1.1.1 Detailed Description

After a configuration transaction to an invalid function or a memory transaction to in an invalid memory window of

the TSB82AF15, the Unsupported Request bit in the Uncorrectable Error Status Register and the Advisory Non-

Fatal Error Status bit in the Correctable Error Status Register are both set. In this scenario, only the Advisory

Non-Fatal Error Status bit should be set as this does not result in an uncorrectable error.

11.1.1.2 Overall Impact

This causes a failure in the PCI SIG PTC Gold suite testing to Spec. revision 1.1. Revision 1.0a will continue to

pass.

11.1.1.3 Workaround Proposal

None at this time as software does not implement AER.

11.1.1.4 Corrective Action

None for current device.

11.1.2 Errata #2: File Transfer Fails When L1 is Enabled

11.1.2.1 Detailed Description

The system will hang or the device will drop when L1 is enabled. The link will successfully enter L1, but when the

root complex requests to exit L1 the TSB82AF15 is unresponsive. This is seen during prolonged file transfers.

The following is observed:

1. Endpoint requests to go into L1

2. Root complex acknowledges the L1 request

3. Link goes into L1

4. Some unknown packet types are sent from the endpoint

5. Root complex wants to exit L1 and sends TS1 (not due to the unknown packet types sent from endpoint)

6. There is no response from endpoint

7. After some time, root complex tries to retrain the link but still no response from endpoint

8. Root complex goes into Link State Poll_Compliance

11.1.2.2 Overall Impact

This will cause the system to hang or the device to drop.

11.1.2.3 Workaround Proposal

Do not enable L1.

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11.1.2.4 Corrective Action

None for current device.

11.2 Application Information

Typical application of the TSB82AF15-EP PCIe to OHCI controller is on the PCIe backplane of a host computer

or laptop allowing connection to a 1394 phy with one or more ports.

11.2.1 Typical Application

Computer

FPGA or ASIC

TSB82AF15-EP

PCIe to OHCI

controller

PCIe x1

1394 Phy

1394

device

1394

device

1394

device

图11-1. Typical application example

11.2.2 Application Curves

图 11-2 shows representative eye diagram of TSB82AF15-EP driving through PCIe 1.1 backplane connector on

a PCI-SIG R2.0 PCIe reference baseboard.

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图11-2. TSB82AF15-EP Eye Diagram

11.2.3 Design Requirements

Proper design information for PCIe revision 1.1 can be obtained from the PCI SIG website. Best practices for

schematic and card layout can be found.

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12 Power Supply Recommendations

Power supply filtering is required to filter digital supplies from the analog supplies. Each power supply pin should

have decoupling capacitance placed as near as possible to the supply pin. Values of 1uF, 0.1uF, 0.01uF and

1000pF are recommended. Each power supply pin ending with _COMB should only have decoupling

capacitance placed near each pin. These pins must not be externally loaded nor tied to external power rails.

Values of 1uF, 0.01uF, and 0.001uF are recommended for each of the three _COMB pins.

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13 Layout

13.1 Layout Guidelines

Proper layout information for PCIe revision 1.1 cards and connectors can be obtained from the PCI SIG website.

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14 Device and Documentation Support

14.1 Device Support

14.1.1 Device Nomenclature

14.1.1.1 Documents Conventions

Throughout this data manual, several conventions are used to convey information. These conventions are:

• To identify a binary number or field, a lower-case b follows the numbers. For example, 000b is a 3-bit binary

field.

• To identify a hexadecimal number or field, a lower-case h follows the numbers. For example, 8AFh is a 12-bit

hexadecimal field.

• All other numbers that appear in this document that do not have either a b or h following the number are

assumed to be decimal format.

• If the signal or terminal name has a bar above the name (for example, GRST), this indicates the logical NOT

function. When asserted, this signal is a logic low, 0, or 0b.

• Differential signal names end with P, N, +, or –designators. The P or + designators signify the positive signal

associated with the differential pair. The N or –designators signify the negative signal associated with the

differential pair.

• RSVD indicates that the referenced item is reserved.

14.2 Documentation Support

14.2.1 Related Documentation

• PCI Express™ to PCI/PCI-X Bridge Specification, Revision 1.0

• PCI Express™ Base Specification, Revision 1.1

• PCI Express™ Card Electromechanical Specification, Revision 1.1

• PCI Local Bus Specification, Revision 2.3 and Revision 3.0

• PCI-to-PCI Bridge Architecture Specification, Revision 1.1

• PCI Bus Power-Management Interface Specification, Revision 1.1 and Revision 1.2

• 1394 Open Host Controller Interface (OHCI) Specification, Release 1.2

• High-Performance Serial Bus, IEEE Std 1394-1995

• High-Performance Serial Bus, Amendment 1, IEEE Std 1394a-2000

• High-Performance Serial Bus, Amendment 2, IEEE Std 1394b-2002

• Express Card Standard, Release 1.0 and Release 1.1

• PCI Express™ Jitter and BER white paper

• PCI Mobile Design Guide, Revision 1.1

14.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

14.4 支持资源

TI E2E^™中文支持论坛是工程师的重要参考资料，可直接从专家处获得快速、经过验证的解答和设计帮助。搜索

现有解答或提出自己的问题，获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的使用条款。

14.5 Trademarks

PCI Express^™is a trademark of PCI-SIG.

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is a trademark of PCI SIG.

OHCI-Lynx^™and TI E2E^™are trademarks of Texas Instruments.

所有商标均为其各自所有者的财产。

14.6 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

14.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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15 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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15.1 Mechanical Data

MECHANICAL DATA

MTQF012B – OCTOBER 1994 – REVISED DECEMBER 1996

PZT (S-PQFP-G100)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

75

M

0,08

51

50

76

26

100

0,13 NOM

1

25

12,00 TYP

Gage Plane

14,20

SQ

13,80

16,20

SQ

0,25

15,80

0,05 MIN

0°–7°

1,05

0,95

0,75

0,45

Seating Plane

1,20 MAX

0,08

4073179/B 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

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PLASTIC QUAD FLATPACK

PZT (S-PQFP-G100)

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MECHANICAL DATA

MTQF012B – OCTOBER 1994 – REVISED DECEMBER 1996

PZT (S-PQFP-G100)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

75

M

0,08

50

51

76

26

100

0,13 NOM

1

25

12,00 TYP

Gage Plane

14,20

SQ

13,80

16,20

SQ

0,25

15,80

0,05 MIN

0°–7°

1,05

0,95

0,75

0,45

Seating Plane

1,20 MAX

0,08

4073179/B 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

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型号：	V62/19608-01XE
厂家：	TEXAS INSTRUMENTS
描述：	增强型产品 PCI 基于 EXPRESS® 的 IEEE 1394b OHCI 主机控制器 \| PZT \| 100 \| -40 to 110 PC 控制器
文件：	总179页 (文件大小：2764K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

V62/19608-01XE [TI]

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