VFC320BP [TI]

Voltage-to-Frequency and Frequency-to-Voltage CONVERTER; 电压 - 频率和频率 - 电压转换器


型号：	VFC320BP
厂家：	TEXAS INSTRUMENTS
描述：	Voltage-to-Frequency and Frequency-to-Voltage CONVERTER 电压 - 频率和频率 - 电压转换器转换器模拟特殊功能转换器光电二极管 PC
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VFC320

SBVS017A – AUGUST 2001

Voltage-to-Frequency

and Frequency-to-Voltage

CONVERTER

FEATURES

DESCRIPTION

ꢀ HIGH LINEARITY: 12 to 14 bits

±0.005% max at 10kHz FS

±0.03% max at 100kHz FS

±0.1% typ at 1MHz FS

The VFC320 monolithic voltage-to-frequency and frequency-to-

voltage converter provides a simple low cost method of convert-

ing analog signals into digital pulses. The digital output is an

open collector and the digital pulse train repetition rate is propor-

tional to the amplitude of the analog input voltage. Output pulses

are compatible with TTL, and CMOS logic families.

ꢀ V/F OR F/V CONVERSION

ꢀ 6-DECADE DYNAMIC RANGE

ꢀ GAIN DRIFT: 20ppm/°C max

ꢀ OUTPUT TTL/CMOS COMPATIBLE

High linearity (0.005%, max at 10kHz FS) is achieved with

relatively few external components. Two external resistors and

two external capacitors are required to operate. Full scale fre-

quency and input voltage are determined by a resistor in series

with –In and two capacitors (one-shot timing and input amplifier

integration). The other resistor is a non-critical open collector

pull-up (f_OUTto +V_CC). The VFC320 is available in two perfor-

mance grades. The VFC320 is specified for the –25°C to +85°C,

range.

APPLICATIONS

ꢀ INEXPENSIVE A/D AND D/A CONVERTER

ꢀ DIGITAL PANEL METERS

ꢀ TWO-WIRE DIGITAL TRANSMISSION WITH

NOISE IMMUNITY

ꢀ FM MOD/DEMOD OF TRANSDUCER

SIGNALS

ꢀ PRECISION LONG TERM INTEGRATOR

ꢀ HIGH RESOLUTION OPTICAL LINK FOR

ISOLATION

ꢀ AC LINE FREQUENCY MONITOR

ꢀ MOTOR SPEED MONITOR AND CONTROL

+V_CC

V_OUT

f_IN

–In

+In

Flip-

f_OUT

Comparators

flop

–7.5V Ref

One-shot

–V_CC

C₁

Common

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

www.ti.com

ELECTRICAL CHARACTERISTICS

At T_A= +25°C and ±15VDC power supply, unless otherwise noted.

VFC320BP

TYP

VFC320CP

TYP

PARAMETER

CONDITIONS

MIN

MAX

MIN

MAX

UNITS

V/F CONVERTER f_OUT= V_IN/7.5 R₁C₁, Figure 4

INPUT TO OP AMP

Voltage Range⁽¹⁾

Fig. 4 with e₂= 0

Fig. 4 with e₁= 0

I_IN= V_IN/R_IN

+0.25

Note 2

–10

+750

µA

Current Range⁽¹⁾

Bias Current

ꢀ

Inverting Input

±0.15

ꢀ

µV/°C

kΩ || pF

Noninverting Input

Offset Voltage⁽³⁾

Offset Voltage Drift

Differential Impedance

Common-Mode

Impedance

±5

ꢀ

300 || 5 650 || 5

ꢀ

300 || 3 500 || 3

ꢀ

kΩ || pF

ACCURACY

Linearity Error^{(1) (4) (5)}

Fig. 4 with e₂= 0⁽⁶⁾

0.01Hz ≤ f_OUT≤ 10kHz

0.1Hz ≤ f_OUT≤ 100kHz

1Hz ≤ f_OUT≤ 1MHz

±0.004

±0.008

±0.1

±0.005

±0.030

±0.0015

±0.002

ꢀ

% FSR

ꢀ

Offset Error Input

Offset Voltage⁽³⁾

±15

ꢀ

ppm FSR

ppm FSR/°C

% FSR

ppm FSR/°C

Offset Drift⁽⁷⁾

±0.5

±5

ꢀ

Gain Error⁽³⁾

Gain Drift⁽⁷⁾

Full Scale Drift

±10

ꢀ

f = 10kHz

(Offset Drift and Gain Drift)^(7)(8)(9)

Power Supply Sensitivity

±V_CC= 14VDC to 18VDC

C_LOAD≤ 50pF

±0.015

ꢀ

% FSR%

DYNAMIC RESPONSE

Full Scale Frequency

Dynamic Range

MHz

Decades

ꢀ

Settling Time

(V/F) to Specified Linearity

For a Full Scale Input Step

<50% Overload

Note 10

ꢀ

Overload Recovery

OPEN COLLECTOR OUTPUT

Voltage, Logic “0”

Leakage Current, Logic “1”

Voltage, Logic “1”

_SINK= 8mA, max

0.4

1.0

ꢀ

µA

_O= 15V

0.01

ꢀ

External Pull-up Resistor

Required (See Figure 4)

For Best Linearity

V_PU

ꢀ

Duty Cycle at FS

Fall Time

100

ꢀ

I_OUT= 5mA, C_LOAD= 500pF

F/V CONVERTER V_OUT= 7.5 R₁C₁f_IN, Figure 9

INPUT TO COMPARATOR

Impedance

Logic “1”

Logic “0”

Pulse-width Range

50 || 10 150 || 10

ꢀ

kΩ || pF

+1.0

–V_CC

0.25

+V_CC

–0.05

ꢀ

µs

OUTPUT FROM OP AMP

Voltage

Current

Impedance

Capacitive Load

_O= 6mA

_O= 7VDC

Closed-Loop

Without Oscillation

0 to +10

+10

ꢀ

Ω

0.1

100

ꢀ

POWER SUPPLY

Rated Voltage

Voltage Range

Quiescent Current

±15

ꢀ

±13

±20

±7.5

ꢀ

±6.5

TEMPERATURE RANGE

Specification

B and C Grades

S Grade

–25

–55

+85

+125

ꢀ

°C

Operating

B and C Grades

S Grade

Storage

–40

–55

–65

+85

+125

+150

ꢀ

°C

ꢀ

Specification the same as for VFC320BP.

NOTES: (1) A 25% duty cycle at full scale (0.25mA input current) is recommended where possible to achieve best linearity. (2) Determined by R_INand full scale current range

constraints. (3) Adjustable to zero. See Offset and Gain Adjustment section. (4) Linearity error at any operating frequency is defined as the deviation from a straight line drawn between

the full scale frequency and 0.1% of full scale frequency. See Discussion of Specifications section. (5) When offset and gain errors are nulled, at an operating temperature, the linearity

error determines the final accuracy. (6) For e₁= 0 typical linearity errors are: 0.01% at 10kHz, 0.2% at 100kHz, 0.1% at 1MHz. (7) Exclusive of external components’ drift.

(8) FSR = Full Scale Range (corresponds to full scale and full scale input voltage.) (9) Positive drift is defined to be increasing frequency with increasing temperature.

(10) One pulse of new frequency plus 50ns typical.

VFC320

SBVS017A

ABSOLUTE MAXIMUM RATINGS

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-

ments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

Supply Voltage ................................................................................... ±20V

Output Sink Current at f_OUT............................................................... 50mA

Output Current at V_OUT................................................................... +20mA

Input Voltage, –Input .......................................................................... ±V_CC

Input Voltage, +Input.......................................................................... ±V_CC

Storage Temperature Range .......................................... –65°C to +150°C

Lead Temperature (soldering, 10s) ............................................... +300°C

ESD damage can range from subtle performance degradation

to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

PACKAGE/ORDERING INFORMATION

PACKAGE

SPECIFIED

DRAWING

NUMBER

PACKAGE

DESIGNATOR

TEMPERATURE

RANGE

PACKAGE

MARKING

ORDERING

NUMBER⁽¹⁾

TRANSPORT

MEDIA

PRODUCT

PACKAGE

VFC320BP

DIP-14

010

–40°C to +85°C

VFC320CP

DIP-14

NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces

of “VFC320BP/2K5” will get a single 2500-piece Tape and Reel.

PIN CONFIGURATION

Top View

DIP

–In

+In

V_OUT

Input

Amp

+V_CC

Common

–V_CC

One-Shot

Capacitor

Comparator

Input

One-

shot

f_OUT

VFC320

SBVS017A

FREQUENCY STABILITY VS TEMPERATURE

DISCUSSION OF

SPECIFICATIONS

LINEARITY

The full scale frequency drift of the VFC320 versus tem-

perature is expressed as parts per million of full scale range

per °C. As shown in Figure 3, the drift increases above

10kHz. To determine the total accuracy drift over tempera-

ture, the drift coefficients of external components (espe-

cially R₁and C₁) must be added to the drift of the VFC320.

Linearity is the maximum deviation of the actual transfer

function from a straight line drawn between the end points

(100% full scale input or frequency and 0.1% of full scale

called zero.) Linearity is the most demanding measure of

voltage-to-frequency converter performance, and is a func-

tion of the full scale frequency. Refer to Figure 1 to deter-

mine typical linearity error for your application. Once the

full scale frequency is chosen, the linearity is a function of

operating frequency as it varies between zero and full scale.

Examples for 10kHz full scale are shown in Figure 2. Best

linearity is achieved at lower gains (∆f_OUT/∆_VIN) with opera-

tion as close to the chosen full scale frequency as possible

1000

100

B and S Grades

The high linearity of the VFC320 makes the device an

excellent choice for use as the front end of Analog-to-Digital

(A/D) converters with 12- to 14-bit resolution, and for

highly accurate transfer of analog data over long lines in

noisy environments (2-wire digital transmission.)

C Grade

10k

100k

Full Scale Frequency (Hz)

Figure 3. Full Scale Drift vs Full Scale Frequency.

0.10

RESPONSE

Response of the VFC320 to changes in input signal level is

specified for a full scale step, and is 50ns plus 1 pulse of the

new frequency. For a 10V input signal step with the VFC320

operating at 100kHz full scale, the settling time to within

±0.01% of full scale is 10µs.

0.01

T_A= +25°C

D_FS= 0.25

THEORY OF OPERATION

0.001

10k

100k

The VFC320 monolithic voltage-to-frequency converter pro-

vides a digital pulse train output whose repetition rate is

directly proportional to the analog input voltage. The circuit

shown in Figure 4 is composed of an input amplifier, two

comparators and a flip-flop (forming a on-shot), two switched

current sinks, and an open collector output transistor stage.

Essentially the input amplifier acts as an integrator that

produces a two-part ramp. The first part is a function of the

input voltage, and the second part is dependent on the input

voltage and current sink. When a positive input voltage is

applied at V_IN, a current will flow through the input resistor,

causing the voltage at V_OUTto ramp down toward zero,

according to dV/dt = V_IN/R₁C₁. During this time the con-

stant current sink is disabled by the switch. Note, this period

is only dependent on V_INand the integrating components.

Full Scale Frequency (Hz)

Figure 1. Linearity Error vs Full Scale Frequency.

Figure

0.003

f_{FULL SCALE}= 10kHz

0.002

0.001

B Grade

C Grade

–0.001

–0.002

–0.003

Typical, T_A= +25°C

When the ramp reaches a voltage close to zero, comparator

A sets the flip-flop. This closes the current sink switches as

well as changing f_OUTfrom logic 0 to logic 1. The ramp now

9k 10k

Operating Frequency (Hz)

begins to ramp up, and 1mA charges through C₁until V_C1

–7.5V. Note this ramp period is dependent on the 1mA

current sink, connected to the negative input of the op amp,

as well as the input voltage. At this –7.5V threshold point

C₁, comparator B resets the flip-flop, and the ramp voltage

Figure 2. Linearity Error vs Operating Frequency.

Figure

VFC320

SBVS017A

C₂

+V_PULL-UP(V_PU

(5V to 15V Typically)

)

+V_CC

Integrating

Capacitor

V_OUT

f_IN

Input Resistor

R₁

Pull-up

R₂

Input

Amp

Resitor

I_IN

e₁

Flip-

flop

I_B

Comparators

f_OUT

–7.5V

Ref

Q₁

Constant

Current Sinks

(1mA)

I_A

V_IN

e₂

f_OUT

7.5 R₁C₁

Switch

One-shot

Common

C₁

One-shot

Capacitor

–V_CC

V_IN:

For Postive Input Voltages use e₁, short e₂.

For Negative Input Voltages use e₂, short e₁.

For Differental Input Voltages use e_{1 and}e₂.

FIGURE 4. Functional Block Diagram of the VFC320.

begins to ramp down again before the input amplifier has a

chance to saturate. In effect the comparators and flip-flop

form a one-shot whose period is determined by the internal

reference and a 1mA current sink plus the external capacitor,

C₁. After the one-shot resets, f_OUTchanges back to logic 0

and the cycle begins again.

In the time t₁+ t₂the integrator capacitor C₂charges and

discharges but the net voltage change is zero.

Thus ∆Q = 0 = I_INt₁+ (I_IN– I_A) t₂

(2)

(3)

So that I_IN(t₁+ t₂) = I_At₂

V_IN

f_OUT

But since t₁+ t₂=

and I_IN

(4), (5)

(6)

R₁

The transfer function for the VFC320 is derived for the

circuit shown in Figure 4. Detailed waveforms are shown in

Figure 5.

V_IN

f_OUT

I_AR₂R₂

f_OUT

(1)

In the time t₁, I_Bcharges the one-shot capacitor C₁until its

voltage reaches –7.5V and trips comparator B.

t₁+ t₂

C_IN7.5

Thus t₂=

(7)

(8)

I_B

V_IN

I_B

Using (7) in (6) yield f_OUT

•

7.5R₁C₁I_A

–7.5V

Since I_A= I_Bthe result is

V_IN

(9)

f_OUT

7.5 R₁C₁

∆V_OUT

Since the integrating capacitor, C₂, affects both the rising

and falling segments of the ramp voltage, its tolerance and

temperature coefficient do not affect the output frequency. It

should, however, have a leakage current that is small com-

pared to I_IN, since this parameter will add directly to the gain

error of the VFC. C₁, which controls the one-shot period,

should be very precise since its tolerance and temperature

coefficient add directly to the errors in the transfer function.

t₁

t₂

FIGURE 5. Integrator and VFC Output Timing.

VFC320

SBVS017A

The operation of the VFC320 as a highly linear frequency-

to-voltage converter, follows the same theory of operation as

the voltage-to-frequency converter. e₁and e₂are shorted and

F_INis disconnected from V_OUT. F_INis then driven with a

signal which is sufficient to trigger comparator A. The one-

shot period will then be determined by C₁as before, but the

cycle repetition frequency will be dictated by the digital

input at F_IN.

C₂

Integrator Capacitor

Gain Adjustment

I_IN

V_IN

R₁

R₃

R₄

+15V

Input

Amp

(1)

12 +V_CC

R₅

(1)

–V_CC

DUTY CYCLE

–15V

Offset Adj.

The duty cycle (D) of the VFC is the ratio of the one-shot

period (t₂) or pulse width, PW, to the total VFC period (t₁+

t₂). For the VFC320, t₂is fixed and t₁+ t₂varies as the input

voltage. Thus the duty cycle, D, is a function of the input

voltage. Of particular interest is the duty cycle at full scale

frequency, D_FS, which occurs at full scale input. D_FSis a user

determined parameter which affects linearity.

C₁

One-shot

Capacitor

One-

shot

+V_PU

R₂

f_OUT

Pin numbers in squares

refer to DIP package.

NOTE: (1) Bypass with 0.01µF

t₂

D_FS

= PW • f_FS

FIGURE 7. Connection Diagram for V/F Conversion,

Negative Input Voltages.

t₁+ t₂

Best linearity is achieved when D_FSis 25%. By reducing

equations (7) and (9) it can be shown that

EXTERNAL COMPONENT SELECTION

In general, the design sequence consists of: (1) choosing

f_MAX, (2) choosing the duty cycle at full scale (D_FS= 0.25

typically), (3) determining the input resistor, R₁(Figure 4),

(4) calculating the one-shot capacitor, C₁, (5) selecting the

integrator capacitor C₂, and (6) selecting the output pull-up

resistor, R₂.

I_INmax

1mA

V_INmax / R₁

1mA

D_FS

Thus D_FS= 0.25 corresponds to I_INmax = 0.25mA.

INSTALLATION AND

OPERATING INSTRUCTIONS

VOLTAGE-TO-FREQUENCY CONVERSION

Input Resistors R₁and R₃

The input resistance (R₁and R₃in Figures 6 and 7) is

calculated to set the desired input current at full scale input

voltage. This is normally 0.25mA to provide a 25% duty

cycle at full scale input and output. Values other than D_FS

0.25 may be used but linearity will be affected.

The VCF320 can be connected to operate as a V/F converter

that will accept either positive or negative input voltages, or

an input current. Refer to Figures 6 and 7.

The nominal value is R₁is

V_INmax

C₂

Integrator Capacitor

R₁=

Gain Adjustment

0.25mA

(10)

If gain trimming is to be done, the nominal value is reduced

by the tolerance of C₁and the desired trim range. R₁should

have a very-low temperature coefficient since its drift adds

directly to the errors in the transfer function.

I_IN

V_IN

R₃

R₁

R₄

+15V

Input

Amp

(1)

12 +V_CC

R₅

(1)

One-Shot Capacitor, C₁

–V_CC

–15V

This capacitor determines the duration of the one-shot pulse.

From equation (9) the nominal value is

Offset Adj.

C₁

One-shot

capacitor

One-

shot

V_IN

C_{1 NOM}

+V_PU

7.5 R₁f_OUT

(11)

R₂

f_OUT

For the usual 25% duty at f_MAX= V_IN/R₁= 0.25mA there is

approximately 15pF of residual capacitance so that the

design value is

Pin numbers in squares

refer to DIP package.

NOTE: (1) Bypass with 0.01µF

33 • 10⁶

FIGURE 6. Connection Diagram for V/F Conversion,

Positive Input Voltages.

C₁(pF) =

– 15

f_FS

(12)

VFC320

SBVS017A

where f_FSis the full scale output frequency in Hz. The

temperature drift of C₁is critical since it will add directly to

the errors of the transfer function. An NPO ceramic type is

recommended. Every effort should be made to minimize

stray capacitance associated with C₁. It should be mounted

as close to the VFC320 as possible. Figure 8 shows pulse

width and full scale frequency for various values of C₁at

D_FS= 25%.

OFFSET AND GAIN ADJUSTMENT PROCEDURES

To null errors to zero, follow this procedure:

1. Apply an input voltage that should produce an output

frequency of 0.001 • full scale.

2. Adjust R₅for proper output.

3. Apply the full scale input voltage.

4. Adjust R₃for proper output.

5. Repeat stems 1 through 4.

If nulling is unnecessary for the application, delete R₄and

R₅, and replace R₃with a short circuit.

10,000

1000

100

10⁶

10⁵

10⁴

Full Scale Frequency

POWER SUPPLY CONSIDERATIONS

The power supply rejection ratio of the VFC320 is 0.015%

of FSR/% max. To maintain ±0.015% conversion, power

supplies which are stable to within ±1% are recommended.

These supplies should be bypassed as close as possible to the

converter with 0.01µF capacitors.

Pulse Width

10³

10²

Internal circuitry causes some current to flow in the common

connection (pin 11 on DIP package). Current flowing into

the f_OUTpin (logic sink current) will also contribute to this

current. It is advisable to separate this common lead ground

from the analog ground associated with the integrator input

to avoid errors produced by these currents flowing through

any ground return impedance.

10¹

10²

10³

10⁴

10⁵

Capacitance C₁(pF)

FIGURE 8. Output Pulse Width (D_FS= 0.25) and Full Scale

Frequency vs External One-shot Capacitance.

Integrating Capacitor, C₂

DESIGN EXAMPLE

Since C₂does not occur in the V/F transfer function equation

(9), its tolerance and temperature stability are not important;

however, leakage current in C₂causes a gain error. A

ceramic type is sufficient for most applications. The value of

C₂determines the amplitude of V_OUT. Input amplifier satu-

ration, noise levels for the comparators and slew rate limit-

ing of the integrator determine a range of acceptable values,

Given a full scale input of +10V, select the values of R₁, R₂,

R₃, C₁, and C₂for a 25% duty cycle at 100kHz maximum

operation into one TTL load. See Figure 6.

Selecting C₁(D_FS= 0.25)

C₁= [(33 • 10⁶)/f_MAX] – 15

[(66 • 10⁶)/f_MAX] – 15

if D_FS= 0.5

100/f_FS; if f_FS≤ 100kHz

C₂(µF) = 0.001; if 100kHz < f_FS≤ 500kHz

0.0005; if f_FS> 500kHz

(13)

= [(33 • 10⁶)/100kHz] – 15

= 315pF

Choose a 300pF NPO ceramic capacitor with 1% to 10%

tolerance.

Output Pull Up Resistor R₂

The open collector output can sink up to 8mA and still be

TTL-compatible. Select R₂according to this equation:

Selecting R₁and R₃(D_RS= 0.25)

R₂min (Ω) V_PULLUP/(8mA – I_LOAD

)

R₁+ R₃= V_INmax/0.25mA

V_INmax/0.5mA

if D_FS= 0.5

A 10% carbon film resistor is suitable for use as R₂.

= 10V/0.25mA

Trimming Components R₃, R₄, R₅

= 40kΩ

R₅nulls the offset voltage of the input amplifier. It should

have a series resistance between 10kΩ and 100kΩ and a

temperature coefficient less than 100ppm/°C. R₄can be a

10% carbon film resistor with a value of 10MΩ.

Choose 32.4kΩ metal film resistor with 1% tolerance and

R₃= 10kΩ cermet potentiometer.

R₃nulls the gain errors of the converter and compensates for

initial tolerances of R₁and C₁. Its total resistance should be

at least 20% of R₁, if R₁is selected 10% low. Its temperature

coefficient should be no greater than five times that of R₁to

maintain a low drift of the R₃- R₁series combination.

Selecting C₂

C₂= 10²/F_MAX

= 10²/100kHz

= 0.001µF

Choose a 0.001µF capacitor with ±5% tolerance.

VFC320

SBVS017A

Selecting R₂

pin 10 should be biased closer to zero to insure that the input

signal at pin 10 crosses the zero threshold.

R₂= V_PULLUP/(8mA – I_LOAD

)

Errors are nulled using 0.001 • full scale frequency to null

offset, and full scale frequency to null the gain error. The

procedure is given on this page. Use equations from V/F

calculations to find R₁, R₃, R₄, C₁and C₂.

=5V/(8mA – 1.6mA), one TTL-load = 1.6mA

=781Ω

Choose a 750Ω 1/4-watt carbon compensation resistor with

±5% tolerance.

TYPICAL APPLICATIONS

FREQUENCY-TO-VOLTAGE CONVERSION

To operate the VFC320 as a frequency-to-voltage converter,

connect the unit as shown in Figure 9. To interface with

TTL-logic, the input should be coupled through a capacitor,

and the input to pin 10 biased near +2.5V. The converter will

detect the falling edges of the input pulse train as the voltage

at pin 10 crosses zero. Choose C₃to make t = 0.1t (see

Figure 9). For input signals with amplitudes less than 5V,

Excellent linearity, wide dynamic range, and compatible

TTL, DTL, and CMOS digital output make the VFC320

ideal for a variety of VFC applications. High accuracy

allows the VFC320 to be used where absolute or exact

readings must be made. It is also suitable for systems

requiring high resolution up to 14 bits

Figures 10-14 show typical applications of the VFC320.

R₁

R₃

C₂

Integrator Capacitor

+15V

R₄

R₅

V_OUT

(1)

–15V

+V_CC

Input

Amp

+1V

12kΩ

(1)

R₆

–V_CC

C₃

One-shot

Capacitor

(t)

2.5V

f_IN

C₁

0.001µF

R₇

2.2kΩ

One-

shot

f_OUT

Pin numbers in squares

refer to DIP package.

F_FS= 100kHz

NOTE: (1) Bypass with 0.01µF

FIGURE 9. Connection Diagram for F/V Conversion.

f_OUT

V_IN

Counter

Sensor

INA101

VFC320

Parallel

Data

–

High Noise

Immunity

Computer

Instrumentation

Amp

Clock

FIGURE 10. Inexpensive A/D with Two-Wire Digital Transmission Over Twisted Pair.

V_IN

e₁

e₂

f_OUT

Differential

Input

BDC

Counter

VFC320

Driver/Display

Clock

FIGURE 11. Inexpensive Digital Panel Meter.

VFC320

SBVS017A

f_IN

V_OUT

VFC320

F/V

Analog

Output

Digital

Output

V_IN

f_OUT

VFC320

V/F

BCD

Counter

INA101

Transducer

FOT

FOR

0.005% Linearity

Precision DC

levels down to

10mV full scale

Driver

Instrumentation

Amp

Clock

Display

FIGURE 12. Remote Transducer Readout via Fiber Optic Link (Analog and Digital Output).

R₁

R₂

R₃

+15V

11kΩ

100kΩ

40.2kΩ

Gain Adjust

Integrator

Current

0.01µF

D₁

IN4154

C₂

+10V to –10V

0.01µF

30kΩ

R₄

Input

+15V

–

f_OUT

2kΩ

V_IN

VFC320

3510B

8.66kΩ

e₁

10V

20kΩ

Bipolar

Input

Q₁

VFC320

REF101

C₁

3270pF

2N2222

0 to

10kHz

Output

Sign Bit

Out

4.7kΩ

3300pF

–15V

+V_CC

FIGURE 13. Bipolar input is accomplished by offsetting the

input to the VFC with a reference voltage.

Accurately matched resistors in the REF101

provide a stable half-scale output frequency at

zero volts input.

FIGURE 14. Absolute value circuit with the VFC320. Op

amp, D₁and Q₁(its base-emitter junction

functioning as a diode) provide full-wave

rectification of bipolar input voltages. VFC

output frequency is proportional to | e₁|. The

sign bit output provides indication of the input

polarity.

VFC320

SBVS017A

PACKAGE DRAWING

MPDI002B – JANUARY 1995 – REVISED FEBRUARY 2000

N (R-PDIP-T**)

PLASTIC DUAL-IN-LINE PACKAGE

16 PINS SHOWN

PINS **

DIM

0.775

(19,69)

0.775

(19,69)

0.920

(23,37)

0.975

(24,77)

A MAX

0.745

(18,92)

0.745

(18,92)

0.850

(21,59)

0.940

(23,88)

A MIN

0.260 (6,60)

0.240 (6,10)

0.070 (1,78) MAX

0.325 (8,26)

0.300 (7,62)

0.035 (0,89) MAX

0.020 (0,51) MIN

0.015 (0,38)

Gauge Plane

0.200 (5,08) MAX

Seating Plane

0.010 (0,25) NOM

0.125 (3,18) MIN

0.100 (2,54)

0.010 (0,25)

0.430 (10,92) MAX

0.021 (0,53)

0.015 (0,38)

14/18 PIN ONLY

4040049/D 02/00

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001).

VFC320

SBVS017A

PACKAGE OPTION ADDENDUM

www.ti.com

9-Dec-2004

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

VFC320BG

VFC320BM

VFC320BM2

VFC320BP

VFC320CG

VFC320CM

VFC320CM1

VFC320CP

VFC320SM

OBSOLETE

CDIP

None

Call TI

OBSOLETE TO-100

LME

Call TI

ACTIVE

PDIP

CDIP

Level-NA-NA-NA

Call TI

OBSOLETE

OBSOLETE TO-100

LME

Call TI

ACTIVE

PDIP

Level-NA-NA-NA

Call TI

OBSOLETE TO-100

LME

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free).

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,

including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

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solutions:

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Amplifiers

amplifier.ti.com

www.ti.com/audio

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dataconverter.ti.com

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www.ti.com/automotive

DSP

dsp.ti.com

Broadband

Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

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Post Office Box 655303 Dallas, Texas 75265

VFC320BP [TI]

相关型号：

VFC320BP/2K5

VFC320BPG4

VFC320CG

VFC320CG

VFC320CL-BS

VFC320CL-BSS3

VFC320CM

VFC320CM

VFC320CM-BS

VFC320CM-BSS1

VFC320CM-BSS4

VFC320CM1