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VSP5324-Q1

ZHCSH90A –JANUARY 2015–REVISED DECEMBER 2017

VSP5324-Q1 4 通道、12 位、80MSPS ADC

1 特性

2 应用

1

•

适用于汽车类应用

具有符合 AEC-Q100 标准的下列结果

•

深度传感：

–

位置和接近传感

–

器件温度等级 2：–40°C 至 +105°C

3D 扫描

器件人体放电模型(HBM) ESD 分类等级 2

器件充电模型 (CDM) ESD 分类等级 C4B

3D 机器视觉

安全和监控

手势控制

•

针对低功耗而设计：

–

单信道接口：

50MSPS 时，每通道 65mW

3 说明

VSP5324-Q1 器件是一款低功耗、12 位、80MSPS、

四通道模数转换器 (ADC)。低功耗和在一个紧凑封装

内的多通道集成使得此器件对于 3D 时差测距 (ToF) 系

统具有很大的吸引力。

–

双信道接口：

80MSPS 时，每通道 82mW

•

动态性能：

–

5MHz 输入频率，80MSPS

信噪比 (SNR)：70dBFS

串行低压差分信令 (LVDS) 输出减少了接口线路的数量

并实现高度系统集成。

无杂散动态范围 (SFDR)：85dBc

串行低压差分信令 (LVDS) 模数转换器 (ADC) 数据

输出

此器件采用紧凑型 9mm x 9mm VQFN-64 封装。

•

多种 LVDS 测试模式以验证数据捕捉

封装：9mm x 9mm VQFN-64

工作温度：–40°C 至 +105°C

器件信息⁽¹⁾

器件型号

封装

VQFN (64)

封装尺寸（标称值）

VSP5324-Q1

9.00mm x 9.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

简化的原理图

信噪比与输入信号频率间的关系

18-V

AVDD LVDD

18-V

71.1

70.6

70.1

69.6

69.1

68.6

VSP5324-Q1

SPI Control

Register

control

Time of Flight

Sensor

Analog Inputs

4-Channel

12-bit ADC

Bit Clock

Frame Clock

LVDS Data

Host

Serializer

Common Mode Voltage (optional)

Reference (optional)

Power

Down

Sampling

Clock

0

10

20

30

40

50

60

70

80

Input Signal Frequency (MHz)

D007

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLES275

VSP5324-Q1

ZHCSH90A –JANUARY 2015–REVISED DECEMBER 2017

www.ti.com.cn

7.2 Functional Block Diagrams ..................................... 19

7.3 Feature Description................................................. 20

7.4 Device Functional Modes........................................ 26

7.5 Programming........................................................... 27

7.6 Register Maps......................................................... 29

Application and Implementation ........................ 51

8.1 Application Information............................................ 51

8.2 Typical Application ................................................. 51

Power Supply Recommendations...................... 53

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 6

6.1 Absolute Maximum Ratings ...................................... 6

6.2 ESD Ratings.............................................................. 6

6.3 Recommended Operating Conditions....................... 6

6.4 Thermal Information.................................................. 7

6.5 Electrical Characteristics: Dynamic Performance..... 7

6.6 Electrical Characteristics: General............................ 8

6.7 Electrical Characteristics: Digital............................... 9

6.8 Timing Requirements................................................ 9

8

9

10 Layout................................................................... 53

10.1 Layout Guidelines ................................................. 53

10.2 Layout Example .................................................... 54

11 器件和文档支持 ..................................................... 55

11.1 器件支持................................................................ 55

11.2 文档支持................................................................ 56

11.3 接收文档更新通知 ................................................. 56

11.4 社区资源................................................................ 56

11.5 商标....................................................................... 57

11.6 静电放电警告......................................................... 57

11.7 Glossary................................................................ 57

12 机械、封装和可订购信息....................................... 57

6.9 LVDS Timing at Different Sampling Frequencies

(One-Lane Interface, 12x Serialization) ................... 10

6.10 LVDS Timing at Different Sampling Frequencies

(Two-Lane Interface, 6x Serialization) ..................... 10

6.11 Serial Interface Timing Requirements................... 10

6.12 Typical Characteristics.......................................... 12

Detailed Description ............................................ 19

7.1 Overview ................................................................. 19

7

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (December 2014) to Revision A

Page

•

已更改将器件可见性从定制更改为目录.................................................................................................................................. 1

已添加接收文档更新通知和社区资源 ................................................................................................................................... 56

2

VSP5324-Q1

www.ti.com.cn

ZHCSH90A –JANUARY 2015–REVISED DECEMBER 2017

5 Pin Configuration and Functions

RGC Package

64-Pin VQFN With Exposed Thermal Pad

Top View

1

2

3

4

5

6

7

8

9

IN1_P

IN1_M

AGND

NC

48

IN4_M

47 IN4_P

46 AGND

45 NC

NC

42

43

AGND

IN2_P

IN2_M

AGND

42 IN3_M

41 IN3_P

40 AGND

39 NC

Thermal Pad

NC 10

NC

11

12

NC

38

37

LGND

AGND

PD 13

LGND 14

36 LGND

LVDD

35

34

33

OUT1A_P 15

OUT4A_M

OUT4A_P

OUT1A_M

16

NC - No internal connection

Pin Functions

TYPE

DESCRIPTION

NAME

NO.

24

23

3

ADCLKM

ADCLKP

Digital output

Negative LVDS differential frame clock output pin

Positive LVDS differential frame clock output pin

6

9

AGND

37

40

43

46

50

57

60

Ground

Analog ground pin

AVDD

CLKM

Supply

Analog supply pin, 1.8 V

Negative clock input

Differential clock input: apply differential clocks (sine wave, LVPECL, and LVDS) to CLKP and

CLKM. Single-ended clock input: apply a CMOS clock to CLKP and tie CLKM to ground.

59

Analog input

3

VSP5324-Q1

ZHCSH90A –JANUARY 2015–REVISED DECEMBER 2017

www.ti.com.cn

Pin Functions (continued)

TYPE

DESCRIPTION

NAME

NO.

Positive clock input

CLKP

58

Analog input

Differential clock input: apply differential clocks (sine wave, LVPECL, and LVDS) to CLKP and

CLKM. Single-ended clock input: apply a CMOS clock to CLKP and tie CLKM to ground.

CS

61

2

Digital input

Analog input

Serial interface enable pin

IN1_M

IN1_P

IN2_M

IN2_P

IN3_M

IN3_P

IN4_M

IN4_P

Channel 1 negative differential analog input

Channel 1 positive differential analog input

Channel 2 negative differential analog input

Channel 2 positive differential analog input

Channel 3 negative differential analog input

Channel 3 positive differential analog input

Channel 4 negative differential analog input

Channel 4 positive differential analog input

1

8

7

42

41

48

47

Internal and external reference control input pin

Logic high: device uses internal reference

Logic low: device uses external reference

INT/EXT

56

Digital input

LCLKM

LCLKP

26

25

12

14

36

35

4

Digital output

Negative LVDS differential bit clock output pin

Positive LVDS differential bit clock output pin

LGND

LVDD

Ground

Supply

Digital ground pin

Digital and LVDS supply pin, 1.8 V

5

10

11

38

39

44

45

51

NC

—

Unused; do not connect

Channel 1A negative LVDS differential output pin.

This pin can be used with either one- or two-lane interface.

OUT1A_M

OUT1A_P

OUT1B_M

OUT1B_P

OUT2A_M

OUT2A_P

OUT2B_M

OUT2B_P

OUT3A_M

OUT3A_P

16

15

18

17

20

19

22

21

30

29

Interface

Channel 1A positive LVDS differential output pin.

This pin can be used with either one- or two-lane interface.

Channel 1B negative LVDS differential output pin. This pin is used with two-lane interface.

In one-lane interface, this pin is unused and must be floated without a 100-Ω termination.

Channel 1B positive LVDS differential output pin. This pin is used with two-lane interface.

In one-lane interface, this pin is unused and must be floated without a 100-Ω termination.

Channel 2A negative LVDS differential output pin.

This pin can be used with either one- or two-lane interface.

Channel 2A positive LVDS differential output pin.

This pin can be used with either one- or two-lane interface.

Channel 2B negative LVDS differential output pin. This pin is used with two-lane interface.

In one-lane interface, this pin is unused and must be floated without a 100-Ω termination.

Channel 2B positive LVDS differential output pin. This pin is used with two-lane interface.

In one-lane interface, this pin is unused and must be floated without a 100-Ω termination.

Channel 3A negative LVDS differential output pin.

This pin can be used with either one- or two-lane interface.

Channel 3A positive LVDS differential output pin.

This pin can be used with either one- or two-lane interface.

4

VSP5324-Q1

www.ti.com.cn

ZHCSH90A –JANUARY 2015–REVISED DECEMBER 2017

Pin Functions (continued)

TYPE

DESCRIPTION

NAME

NO.

Channel 3B negative LVDS differential output pin. This pin is used with two-lane interface.

In one-lane interface, this pin is unused and must be floated without a 100-Ω termination.

OUT3B_M

OUT3B_P

OUT4A_M

OUT4A_P

OUT4B_M

OUT4B_P

PD

28

Interface

Digital input

Channel 3B positive LVDS differential output pin. This pin is used with two-lane interface.

In one-lane interface, this pin is unused and must be floated without a 100-Ω termination.

27

34

33

32

31

13

Channel 4A negative LVDS differential output pin.

This pin can be used with either one- or two-lane interface.

Channel 4A positive LVDS differential output pin.

This pin can be used with either one- or two-lane interface.

Channel 4B negative LVDS differential output pin. This pin is used with two-lane interface.

In one-lane interface, this pin is unused and must be floated without a 100-Ω termination.

Channel 4B positive LVDS differential output pin. This pin is used with two-lane interface.

In one-lane interface, this pin is unused and must be floated without a 100-Ω termination.

Power-down control input pin

Logic high: device is in power-down state; logic low: normal operation

Reference bottom voltage pin

Internal reference mode: the reference bottom voltage (0.45 V) is output on this pin.

External reference mode: the reference bottom voltage (0.45 V) must be externally applied to this

pin. There are no required decoupling capacitors on this pin.

REFB

REFT

54

55

Analog input

Reference top voltage pin

Internal reference mode: the reference top voltage (1.45 V) is output on this pin.

External reference mode: reference top voltage (1.45 V) must be externally applied to this pin.

There are no required decoupling capacitors on this pin.

RESET

SCLK

64

63

62

52

Digital input

Digital output

Serial interface reset pin; active low

Serial interface clock pin

SDATA

SDOUT

Serial interface data pin

Serial interface readout pin

Control input pin synchronizes test patterns across channels.

When unused, this pin should be tied to ground.

SYNC

49

Digital input

Common-mode voltage pin

VCM

53

Analog output Internal reference mode: common-mode voltage output pin, 0.95 V.

External reference mode: reference voltage must be externally applied to this pin.

5

VSP5324-Q1

ZHCSH90A –JANUARY 2015–REVISED DECEMBER 2017

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range, unless otherwise noted.⁽¹⁾

MIN

–0.3

MAX

2.2

UNIT

V

AVDD

Supply voltage

LVDD

2.2

V

Ground voltage

Between AGND and LGND

differences

–0.3

0.3

V

Digital outputs

Digital inputs (CLKN, CLKP⁽²⁾, RESET, SCLK,

SDATA, CS, SYNC, PD, INT/EXT)

lesser of 2.2 or (LVDD + 0.3)

Input voltage

Analog inputs

Input current (all pins except supplies)

Ambient temperature, under bias, T_A

Junction temperature, T_J

–0.3

–10

–40

lesser of 2.2 or (LVDD + 0.3)

V

10

mA

°C

105

125

Storage temperature, T_stg

–55

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) When AVDD is turned off, TI recommends switching off the input clock (or ensuring the voltage on CLKP, CLKN is less than |0.3 V|).

This setting prevents the ESD protection diodes at the clock input pins from turning on.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per AEC Q100-002⁽¹⁾

Other pins

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per AEC

Q100-011

Corner pins (1, 16, 17,

32, 33, 48, 49, and 64)

±750

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

Over operating free-air temperature range, unless otherwise noted.

MIN

1.7

NOM

1.8

MAX

1.9

UNIT

V_(AVDD)

V_(LVDD)

V_ID

Analog supply voltage

Digital supply voltage

V

1.7

1.8

1.9

Differential input voltage

Input common-mode voltage

2

V_PP

mV

V_IC

V_IC± 50

Two-lane LVDS interface

One-lane LVDS interface

Sine wave, ac-coupled

LVPECL, ac-coupled

10

80

50

MSPS

V_PP

V

Input clock sample rate

1.5

1.6

0.7

3.3

50%

5

(V_CLKP

–

Input clock amplitude

differential

V_CLKM

)

LVDS, ac-coupled

LVCMOS, single-ended, ac-coupled

Duty cycle

35%

–40

65%

105

C_LOAD

R_LOAD

T_A

Maximum external capacitance from each output pin to DRGND

Differential resistance between LVDS output pairs (LVDS mode)

Operating free-air

pF

Ω

100

°C

6

VSP5324-Q1

www.ti.com.cn

ZHCSH90A –JANUARY 2015–REVISED DECEMBER 2017

6.4 Thermal Information

VSP5324-Q1

THERMAL METRIC⁽¹⁾

RGC (VQFN)

UNIT

64 PINS

20.6

6.1

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

2.7

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

2.6

R_θJC(bot)

0.4

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics: Dynamic Performance

Typical values are at 25°C, V_(AVDD)= 1.8 V, V_(LVDD)= 1.8 V, sampling frequency = 80 MSPS, 50% clock duty cycle, and –1-

dBFS differential analog input, unless otherwise noted. Minimum and maximum values are across the full temperature range

of T_MIN= –40°C to T_MAX= 105°C, V_(AVDD)= 1.8 V, V_(LVDD)= 1.8 V.

PARAMETER

Resolution

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Bits

12

ƒ_IN= 5 MHz

68

70

69.5

69.8

69.2

85

dBFS

dBc

SNR

Signal-to-noise ratio

ƒ_IN= 30 MHz

ƒ_IN= 5 MHz

ƒ_IN= 30 MHz

ƒ_IN= 5 MHz

ƒ_IN= 30 MHz

ƒ_IN= 5 MHz

ƒ_IN= 30 MHz

ƒ_IN= 5 MHz

ƒ_IN= 30 MHz

ƒ_IN= 5 MHz

ƒ_IN= 30 MHz

ƒ_IN= 5 MHz

ƒ_IN= 30 MHz

SINAD

SFDR

THD

Signal-to-noise and distortion ratio

Spurious-free dynamic range

Total harmonic distortion

Second-harmonic distortion

Third-harmonic distortion

64

63

64

82

dBc

81.5

78

dBc

90

dBc

HD2

86

dBc

85

dBc

HD3

82

dBc

91

dBc

Worst spur

(other than second and third harmonics)

83

dBc

ƒ1 = 8 MHz, ƒ2 = 10 MHz,

each tone at –7 dBFS

IMD

Two-tone intermodulation distortion

Crosstalk (far channel)

83

95

1

dBc

10-MHz full-scale signal on aggressor

channel; no input signal applied on victim

channel

dB

Recovery to within 1% (of full-scale) for

6-dB overload with sine-wave input

Clock

cycle

Input overload recovery

For 50-mV_PPsignal on AVDD supply,

up to 10 MHz, no signal applied to analog

inputs

PSRR

AC power-supply rejection ratio

50

dB

ENOB

DNL

INL

Effective number of bits

Differential nonlinearity

Integral nonlinearity

ƒ_IN= 5 MHz

11.3

±0.2

±0.3

Bits

–0.8

0.8

1

LSBs

7

VSP5324-Q1

ZHCSH90A –JANUARY 2015–REVISED DECEMBER 2017

www.ti.com.cn

6.6 Electrical Characteristics: General

Typical values are at 25°C, V_(AVDD)= 1.8 V, V_(LVDD)= 1.8 V, sampling frequency = 80 MSPS, 50% clock duty cycle, and –1-

dBFS differential analog input, unless otherwise noted. Minimum and maximum values are across the full temperature range

of T_MIN= –40°C to T_MAX= 105°C, V_(AVDD)= 1.8 V, V_(LVDD)= 1.8 V.

PARAMETER

ANALOG INx_PUT

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Voltage range

2

V_PP

kΩ

Differential

input

V_ID

Resistance, at dc

Capacitance, at dc

2.2

550

pF

Analog input bandwidth

MHz

Analog input common-mode current

(per input pin)

µA/

MSPS

1.6

V_OC

Common-mode output voltage

VCM output current capability

0.95

5

V

I_O(VCM)

mA

DC ACCURACY

Offset error

±5

±20

2

mV

Gain error resulting from internal

reference inaccuracy alone

EGREF

–2

%FS

EGCHAN Gain error of channel alone

0.5

POWER SUPPLY

80 MSPS

50 MSPS

114

86

135

85

mA

IAVDD

Analog supply current

Output buffer supply current

Analog power

Two-lane LVDS interface, 80 MSPS,

350-mV swing with 100-Ω external

termination

69

56

mA

ILVDD

One-lane LVDS interface, 50 MSPS,

350-mV swing with 100-Ω external

termination

80 MSPS

50 MSPS

205

155

mW

Two-lane LVDS interface, 80 MSPS,

350-mV swing with 100-Ω external

termination

124

101

mW

Digital power LVDS interface

Total power

One-lane LVDS interface, 50 MSPS,

350-mV swing with 100-Ω external

termination

80 MSPS, two-lane LVDS interface

50 MSPS, one-lane LVDS interface

329

256

mW

Global power-down

Standby power

40

135

8

VSP5324-Q1

www.ti.com.cn

ZHCSH90A –JANUARY 2015–REVISED DECEMBER 2017

6.7 Electrical Characteristics: Digital

At V_(AVDD)= 1.8 V, V_(LVDD)= 1.8 V, unless otherwise noted. The DC specifications refer to the condition where the digital

outputs do not switch, but are tied permanently to a valid logic level 0 or 1.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INx_PUTS (RESET, SCLK, SDATA, CS, PDN, SYNC, INT/EXT)

All digital inputs support 1.8-V and 3.3-V CMOS

logic levels

V_IH

V_IL

High-level input voltage

Low-level input voltage

> 1.3

V

All digital inputs support 1.8-V and 3.3-V CMOS

logic levels

< 0.4

I_IH

I_IL

High-level input current

Low-level input current

V_IH= 1.8 V

V_IL= 0 V

6

µA

< 0.1

DIGITAL OUTPUTS

AVDD –

0.1

V_OH

V_OL

High-level output voltage

CMOS interface (SDOUT)

V

Low-level output voltage

0.1

LVDS interface (OUTP, OUTM, LCLKP, LCLKM,

ADCLKP, ADCLKM), with an external 100-Ω

termination

High-level output differential

voltage

V_OD(H)

245

420

mV

LVDS interface (OUTP, OUTM, LCLKP, LCLKM,

ADCLKP, ADCLKM), with an external 100-Ω

termination

Low-level output differential

voltage

V_OD(L)

V_OC

–420

–245

mV

V

Output common-mode voltage

1.05

6.8 Timing Requirements⁽¹⁾

Typical values are at 25°C, V_(AVDD)= 1.8 V, V_(LVDD)= 1.8 V, sampling frequency = 80 MSPS, sine wave input clock, C_(LOAD)= 5

pF, and R_(LOAD)= 100 Ω, unless otherwise noted. Minimum and maximum values are across the full temperature range of T_MIN

= –40°C to T_MAX= 105°C, V_(AVDD)= 1.8 V, and V_(LVDD)= 1.7 V to 1.9 V.

MIN

NOM

MAX

UNIT

Aperture delay

4

ns

Aperture delay

matching⁽²⁾⁽³⁾

Between the two channels of the same device

±175

ps

Between two devices at the same temperature and

LVDD supply

Aperture delay variation

Aperture jitter (RMS)

2.5

320

5

ns

fs

Time to valid data after coming out of partial

power-down mode

50

µs

Wakeup time

ADC latency

Time to valid data after coming out of global

power-down mode

100

11

500

µs

Clock

cycles

One-lane LVDS output interface

Two-lane LVDS output interface

Clock

cycles

15

Data valid to zero crossing of LCLKP, 80 MSPS,

two-lane LVDS

t_su

t_h

Data setup time

Data hold time⁽⁴⁾

0.61

0.74

ns

Zero crossing of LCLKP to data becoming invalid,

80 MSPS, two-lane LVDS

Input clock rising edge crossover to frame clock

rising edge crossover, two-lane LVDS for

10 ≤ ƒ_S≤ 80 MSPS

(11 / 12) ×

t_S+ t_d

ns

t_p

Clock propagation delay

Delay time

Input clock rising edge crossover to frame clock

rising edge crossover, one-lane LVDS for

10 ≤ ƒ_S≤ 65 MSPS

(9 / 12) ×

t_S+ t_d

ns

t_d

6.8

9

11.8

(1) Timing parameters are ensured by design and characterization and are not tested in production.

(2) C_(LOAD)is the effective external single-ended load capacitance between each output pin and ground.

(3) R_(LOAD)is the differential load resistance between the LVDS output pair.

(4) Data valid refers to a logic high of 100 mV and a logic low of –100 mV.

9

VSP5324-Q1

ZHCSH90A –JANUARY 2015–REVISED DECEMBER 2017

www.ti.com.cn

Timing Requirements⁽¹⁾(continued)

Typical values are at 25°C, V_(AVDD)= 1.8 V, V_(LVDD)= 1.8 V, sampling frequency = 80 MSPS, sine wave input clock, C_(LOAD)= 5

pF, and R_(LOAD)= 100 Ω, unless otherwise noted. Minimum and maximum values are across the full temperature range of T_MIN

= –40°C to T_MAX= 105°C, V_(AVDD)= 1.8 V, and V_(LVDD)= 1.7 V to 1.9 V.

MIN

NOM

MAX

UNIT

LVDS bit clock duty cycle

Data fall time

Differential clock duty cycle (LCLKP – LCLKM)

50

%

Rise time measured from –100 mV to 100 mV,

10 MSPS ≤ sampling frequency ≤ 80 MSPS

t_f

t_r

0.2

ns

Rise time measured from –100 mV to 100 mV,

10 MSPS ≤ sampling frequency ≤ 80 MSPS

Data rise time

Rise time measured from –100 mV to 100 mV,

10 MSPS ≤ sampling frequency ≤ 80 MSPS

t_r(CLK)Output clock rise time

t_f(CLK)Output clock fall time

0.18

Rise time measured from –100 mV to 100 mV,

10 MSPS ≤ sampling frequency ≤ 80 MSPS

6.9 LVDS Timing at Different Sampling Frequencies (One-Lane Interface, 12x Serialization)

See 图 1 and 图 2.

MIN

0.75

0.47

0.25

0.62

0.38

0.19

MAX

UNIT

ƒ_(SAMPLE)= 40 MSPS

ƒ_(SAMPLE)= 50 MSPS

ƒ_(SAMPLE)= 65 MSPS

ƒ_(SAMPLE)= 40 MSPS

ƒ_(SAMPLE)= 50 MSPS

ƒ_(SAMPLE)= 65 MSPS

LCLKP zero-crossing to data becoming

invalid (both edges)

t_h

ns

Data valid to LCLKP zero-crossing (both

edges)

t_su

ns

6.10 LVDS Timing at Different Sampling Frequencies (Two-Lane Interface, 6x Serialization)

See 图 1 and 图 2.

MIN

1.9

MAX

UNIT

ƒ_(SAMPLE)= 40 MSPS

ƒ_(SAMPLE)= 50 MSPS

ƒ_(SAMPLE)= 65 MSPS

ƒ_(SAMPLE)= 40 MSPS

ƒ_(SAMPLE)= 50 MSPS

ƒ_(SAMPLE)= 65 MSPS

LCLKP zero-crossing to data becoming

invalid (both edges)

t_h

1.55

1.1

ns

1.44

1.02

0.64

Data valid to LCLKP zero-crossing (both

edges)

t_su

ns

6.11 Serial Interface Timing Requirements

See 图 3.

MIN

MAX

UNIT

MHz

ns

ƒ_(SCLK)

t_su(LOADS)

t_su(LOADH)

t_su(D)

SCLK frequency = 1 / t_SCLK

SEN to SCLK setup time

SCLK to SEN hold time

SDATA setup time

> DC

33

ns

33

ns

t_h(D)

SDATA hold time

33

ns

10

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ZHCSH90A –JANUARY 2015–REVISED DECEMBER 2017

OUTx_P

Logic 0

V_OD(L)= -350 mV⁽¹⁾

Logic 1

V_OD(H)= 350 mV⁽¹⁾

OUTx_M

VVIC

OCM

IC

GND

(1) With an external 100-Ω termination..

图 1. LVDS Output Voltage Levels

CLKM

CLKP

Input

Clock

t

PDI

ADCLKM

Frame

Clock

ADCLKP

LCLKM

t

su

t

h

Bit

Clock

LCLKP

t

h

su

h

su

OUT1A, OUT1B

OUT2A, OUT2B

OUT3B, OUT3A

OUT4B, OUT4A

Output

Data

Dn⁽¹⁾

Dn + 1⁽¹⁾

图 2. LVDS Mode Timing

11

VSP5324-Q1

ZHCSH90A –JANUARY 2015–REVISED DECEMBER 2017

www.ti.com.cn

Register Address

Register Data

D15

D14

D13

D12

D11

D10

D7

D6

D5

D4

D3

D2

D1

D0

A7

A6

A5

A4

A3

A2

A1

A0

D9

D8

SDATA

SCLK

t_h(D)

t_su(D)

t_su(LOADH)

t_(SCLK)

t_su(LOADS)

CS

RESET

图 3. Serial Interface Timing

6.12 Typical Characteristics

Typical values are at 25°C, V_(AVDD)= 1.8 V, V_(LVDD)= 1.8 V, 80-MSPS sampling clock frequency, 50% clock duty cycle, and

–1-dBFS differential analog input, unless otherwise noted.

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-100

-110

-120

-130

-140

0

10

20

30

40

0

10

20

30

40

Frequency (MHz)

D001

D002

SNR = 69.6 dBFS

SFDR = 89.3 dBc

SINAD = 69.5 dBFS

THD = 85.9 dBc

SNR = 69.6 dBFS

SFDR = 84.8 dBc

SINAD = 69.4 dBFS

THD = 83.2 dBc

Sample Rate = 80 MSPS

图 4. FFT for 5-MHz Input Signal

图 5. FFT for 15-MHz Input Signal

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-100

-110

-120

-130

-140

0

10

20

30

40

0

5

10

15

20

Frequency (MHz)

D003

D004

SNR = 68.5 dBFS

SFDR = 76.5 dBc

SINAD = 67.8 dBFS

THD = 75 dBc

SNR = 69.8 dBFS

SFDR = 85.1 dBc

SINAD = 69.7 dBFS

THD = 84.7 dBc

Sample Rate = 80 MSPS

Sample Rate = 40 MSPS

图 6. FFT for 65-MHz Input Signal

图 7. FFT For 5-MHz Input Signal

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Typical Characteristics (接下页)

Typical values are at 25°C, V_(AVDD)= 1.8 V, V_(LVDD)= 1.8 V, 80-MSPS sampling clock frequency, 50% clock duty cycle, and

–1-dBFS differential analog input, unless otherwise noted.

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-100

-110

-120

-130

-140

0

5

10

15

20

0

5

10

15

20

Frequency (MHz)

D005

D006

SNR = 69.6 dBFS

SFDR = 86.8 dBc

SINAD = 69.5 dBFS

THD = 84 dBc

SNR = 67.2 dBFS

SFDR = 76.5 dBc

SINAD = 66.6 dBFS

THD = 74 dBc

Sample Rate = 40 MSPS

图 8. FFT for 15-MHz Input Signal

图 9. FFT for 65-MHz Input Signal

71.1

70.6

70.1

69.6

69.1

68.6

90

88

86

84

82

80

78

76

0

10

20

30

40

50

60

70

80

0

10

20

30

40

50

60

70

80

Input Signal Frequency (MHz)

D007

D008

图 10. Signal-to-Noise Ratio (SNR) vs Input Signal

图 11. Spurious-Free-Dynamic Range (SFDR) vs Input Signal

Frequency

72

70

68

66

64

62

60

88

f_IN= 10.05 (MHz)

f_IN= 76.85 (MHz)

f_IN= 10.05 (MHz)

f_IN= 76.85 (MHz)

86

84

82

80

78

76

74

0

1

2

3

4

5

6

7

8

9

10 11 12

0

1

2

3

4

5

6

7

8

9

10 11 12

Digital Gain (dB)

D009

D010

图 12. SNR vs Digital Gain

图 13. SFDR vs Digital Gain

13

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www.ti.com.cn

Typical Characteristics (接下页)

Typical values are at 25°C, V_(AVDD)= 1.8 V, V_(LVDD)= 1.8 V, 80-MSPS sampling clock frequency, 50% clock duty cycle, and

–1-dBFS differential analog input, unless otherwise noted.

76

74

72

70

68

66

64

120

100

80

60

40

20

0

72

71.5

71

88

SNR

SFDR

87.5

87

70.5

70

86.5

86

69.5

69

85.5

85

SNR

SFDR (dBc)

SFDR (dBFS)

68.5

68

84.5

84

-50

-40

-30

-20

-10

0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

2.2

Input Amplitude (dBFS)

Input Clock Amplitude, Differential (V_PP

)

D011

D012

ƒ_IN= 5 MHz

图 14. Performance vs Input Signal Amplitude

图 15. Performance vs Input Clock Amplitude

73

72.5

72

88

73

72

71

70

69

68

95

90

85

80

75

70

SNR

THD

SNR

SFDR

87.5

87

71.5

71

86.5

86

70.5

70

85.5

85

69.5

69

84.5

84

68.5

68

83.5

83

35

40

45

50

55

60

65

0.8

0.85

0.9

0.95

1

1.05

1.1

Input Clock Duty Cycle (%)

Analog Input Common-Mode Voltage (V)

D013

D014

ƒ_IN= 5 MHz

图 16. Performance vs Input Clock Duty Cycle

图 17. Performance vs Input Common-Mode

73

90

88

86

84

82

80

78

76

74

72

70

70.2

70.1

70

SNR

SFDR

V_(AVDD)= 1.65 V

V_(AVDD)= 1.7 V

V_(AVDD)= 1.8 V

V_(AVDD)= 1.9 V

V_(AVDD)= 1.95 V

72.5

72

71.5

71

69.9

69.8

69.7

69.6

69.5

69.4

70.5

70

69.5

69

68.5

68

1.3

1.4

1.5

1.6

1.7

-40 -27.5 -15 -2.5 10 22.5 35 47.5 60 72.5 85

External Reference Input (V)

Temperature (èC)

D0135

D016

ƒ_IN= 5 MHz

External reference using the VCM pin

ƒ_IN= 5 MHz

图 18. Performance in External Reference Mode

图 19. SNR vs AVDD and Temperature

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Typical Characteristics (接下页)

Typical values are at 25°C, V_(AVDD)= 1.8 V, V_(LVDD)= 1.8 V, 80-MSPS sampling clock frequency, 50% clock duty cycle, and

–1-dBFS differential analog input, unless otherwise noted.

85

84

83

82

81

80

79

78

77

70.2

70.1

70

V_(DVDD)= 1.65 V

V_(DVDD)= 1.7 V

V_(DVDD)= 1.8 V

V_(DVDD)= 1.9 V

V_(DVDD)= 1.95 V

69.9

69.8

69.7

69.6

69.5

69.4

V_(AVDD)= 1.65 V

V_(AVDD)= 1.7 V

V_(AVDD)= 1.8 V

V_(AVDD)= 1.9 V

V_(AVDD)= 1.95 V

-40 -27.5 -15 -2.5 10 22.5 35 47.5 60 72.5 85

Temperature (èC)

D017

D018

ƒ_IN= 5 MHz

图 20. SFDR vs AVDD and Temperature

图 21. SNR vs DVDD and Temperature

85

84

83

82

81

80

79

78

77

70

69.9

69.8

69.7

69.6

69.5

69.4

V_(DVDD)= 1.65 V

V_(DVDD)= 1.7 V

V_(DVDD)= 1.8 V

V_(DVDD)= 1.9 V

V_(DVDD)= 1.95 V

-40 -27.5 -15 -2.5 10 22.5 35 47.5 60 72.5 85

Temperature (èC)

D019

D020

ƒ_IN= 5 MHz

A 0.7-V_PP5-MHz sine-wave input is applied on the INx_P pin

The INx_M pin is connected to the device VCM pin

图 22. SFDR vs DVDD and Temperature

图 23. SNR vs Temperature For Single-Ended Input

74

0.2

73.5

73

0.1

0

72.5

72

71.5

71

-0.1

70.5

70

-0.2

-40 -27.5 -15 -2.5 10 22.5 35 47.5 60 72.5 85

250

750

1250

1750

2250

2750

3250

3750

Temperature (èC)

Output Codes (LSB)

D021

D022

A 0.7-V_PP5-MHz sine-wave input is applied on the INx_P pin

The INx_M pin is connected to the device VCM pin

图 24. SFDR vs Temperature for Single-ended Input

图 25. Integral Nonlinearity

15

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www.ti.com.cn

Typical Characteristics (接下页)

Typical values are at 25°C, V_(AVDD)= 1.8 V, V_(LVDD)= 1.8 V, 80-MSPS sampling clock frequency, 50% clock duty cycle, and

–1-dBFS differential analog input, unless otherwise noted.

55

50

45

40

35

30

25

0.4

0.3

0.2

0.1

0

-0.1

-0.2

-0.3

-0.4

240

740

1240

1740

2240

2740

3240

3740

0

10

20

30

40

50

60

70

Output Codes (LSB)

Frequency of CMRR Signal (MHz)

D023

D024

ƒ_IN= 3 MHz

50-mV_PPsignal superimposed on the input

common-mode

图 27. CMRR vs Frequency

图 26. Differential Nonlinearity

5

-5

50

40

Low-pass

Band-pass 1

Band-pass 2

High-pass

30

-15

-25

-35

-45

-55

-65

-75

-85

20

10

0

-10

-20

-30

-40

-50

-60

-70

-80

Low-pass

High-pass

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Frequency (f_IN/f_S)

0

0.1

0.2

0.3

0.4

0.5

Normalized Frequency (f_IN/f_S)

D025

D026

图 28. Filter Response (Decimate-by-2)

图 29. Filter Response (Decimate-by-4)

3

0

-3

-6

-9

0

-10

-20

-30

-40

-12

-15

-18

-21

-24

-27

-30

-33

-36

-39

-42

-45

-50

-60

K = 2

-70

K = 3

K = 4

K = 5

K = 6

K = 7

K = 8

K = 9

K = 10

-80

-90

-100

-110

-120

-130

-140

0.02

0.1

1

10

20

0

5

10

15

20

Frequency (MHz)

D027

D028

SNR = 70.8 dBFS

THD = 87.3 dBc

SINAD = 70.7 dBFS

SFDR = 88.7 dBc

Decimate-by-2 filter enabled

图 30. Digital High-Pass Filter Response

图 31. FFT for 5-MHz Input Signal

(Sample Rate = 80 MSPS With Decimation Filter = 2)

16

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Typical Characteristics (接下页)

Typical values are at 25°C, V_(AVDD)= 1.8 V, V_(LVDD)= 1.8 V, 80-MSPS sampling clock frequency, 50% clock duty cycle, and

–1-dBFS differential analog input, unless otherwise noted.

0

-10

0

HPF disabled

HPF enabled, K = 2

-10

-20

-30

-40

-50

-60

-70

-60

-80

-70

-90

-80

-100

-110

-120

-130

-140

-90

-100

-110

-120

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

0

10

20

30

40

Input Signal Frequency (MHz)

Frequency (MHz)

D029

D030

SNR = 70.8 dBFS

SFDR = 88.7 dBc

SINAD = 70.7 dBFS

THD = 87.3 dBc

图 32. FFT With HPF Enabled and Disabled

图 33. FFT (Full-Band) for 5-MHz Input Signal

(No Input Signal)

(Sample Rate = 80 MSPS With Low-Frequency Noise

Suppression Enabled)

0

-10

0

LF-noise supression enabled

LF-noise supression disabled

LF-noise supression enabled

LF-noise supression disabled

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-100

-110

-120

-130

-140

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Frequency (MHz)

1

39 39.1 39.2 39.3 39.4 39.5 39.6 39.7 39.8 39.9 40

Frequency (MHz)

D031

D032

图 34. FFT (0 MHz to 1 MHz) for 5-MHz Input Signal

(Sample Rate = 80 MSPS With Low-Frequency Noise

Suppression Enabled)

图 35. FFT (39 MHz to 40 MHz) for 5-MHz Input Signal

(Sample Rate = 80 MSPS With Low-Frequency Noise

Suppression Enabled)

120

220

110

100

90

200

180

160

140

120

100

80

70

60

50

10

20

30

40

50

60

70

80

10

20

30

40

50

60

70

80

Sampling Frequency (MHz)

D033

D034

图 36. Analog Supply Current

图 37. Power Consumption on Analog Supply

17

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www.ti.com.cn

Typical Characteristics (接下页)

Typical values are at 25°C, V_(AVDD)= 1.8 V, V_(LVDD)= 1.8 V, 80-MSPS sampling clock frequency, 50% clock duty cycle, and

–1-dBFS differential analog input, unless otherwise noted.

130

120

110

100

90

240

220

200

180

160

140

120

100

80

Two-wire

One-wire

One-wire, decimate-by-2

Two-wire

One-wire

One-wire, decimate-by-2

80

70

60

50

40

30

60

10

20

30

40

50

60

70

80

10

20

30

40

50

60

70

80

Sampling Frequency (MHz)

D035

D036

图 38. Digital Supply Current

图 39. Power Consumption on Digital Supply

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ZHCSH90A –JANUARY 2015–REVISED DECEMBER 2017

7 Detailed Description

7.1 Overview

The VSP5324-Q1 device is a high-performance, 12-bit, quad-channel, analog-to-digital converter (ADC) with

sample rates up to 80 MSPS. The conversion process is initiated by a rising edge of the external input clock and

when the analog input signal is sampled. The sampled signal is sequentially converted by a series of small

resolution stages, with the outputs combined in a digital correction logic block. At every clock edge the sample

propagates through the pipeline, resulting in a data latency of 11 clock cycles. The output is available as 12-bit

data, in serial (low-voltage differential signaling) LVDS format, coded in either offset binary or binary twos

complement format.

7.2 Functional Block Diagrams

AVDD AGND

LVDD

LGND

Device

OUT1A_P

OUT1A_M

Serializer

IN1_P

IN1_M

12-Bit

ADC

Digital

OUT1B_P

OUT1B_M

OUT2A_P

OUT2A_M

Serializer

IN2_P

IN2_M

12-Bit

ADC

Digital

OUT2B_P

OUT2B_M

OUT3A_P

OUT3A_M

Serializer

IN3_P

IN3_M

12-Bit

ADC

OUT3B_P

OUT3B_M

OUT4A_P

OUT4A_M

Serializer

IN4_P

IN4_M

12-Bit

ADC

OUT4B_P

OUT4B_M

DC

Clocking

Sync

Signal

Serializer

Clocks

Bit Clock, 3x

LCLKP

LCLKM

Differential and

Single-Ended

Input Clock

CLKP

CLKM

Clock

Buffer

PLL

CLOCKGEN

Frame Clock, 1x

ADCLKP

ADCLKM

ADC Control

Serial

Interface

Reference

SDOUT

图 40. Quad ADC, One-Lane Configuration

19

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ZHCSH90A –JANUARY 2015–REVISED DECEMBER 2017

www.ti.com.cn

Functional Block Diagrams (接下页)

AVDD AGND

LVDD

LGND

Device

OUT1A_P

OUT1A_M

Serializer

IN1_P

IN1_M

12-Bit

ADC

Digital

OUT1B_P

OUT1B_M

OUT2A_P

OUT2A_M

Serializer

IN2_P

IN2_M

12-Bit

ADC

Digital

OUT2B_P

OUT2B_M

OUT3A_P

OUT3A_M

Serializer

IN3_P

IN3_M

12-Bit

ADC

OUT3B_P

OUT3B_M

OUT4A_P

OUT4A_M

Serializer

IN4_P

IN4_M

12-Bit

ADC

OUT4B_P

OUT4B_M

DC

Clocking

Sync

Signal

Serializer

Clocks

Bit Clock, 3x

LCLKP

LCLKM

Differential and

Single-Ended

Input Clock

CLKP

CLKM

Clock

Buffer

PLL

CLOCKGEN

Frame Clock, 1x

ADCLKP

ADCLKM

ADC Control

Serial

Interface

Reference

SDOUT

图 41. Quad ADC, Two-Lane Configuration

7.3 Feature Description

7.3.1 Analog Input

The analog input consists of a switched-capacitor-based differential sample-and-hold architecture, as shown in

图 42. This differential topology results in very good AC performance even for high-input frequencies at high

sampling rates. The INx_P and INx_M pins must be externally biased around a common-mode voltage of 0.95 V,

available on the VCM pin. For a full-scale differential input, each input pin (INx_P, INx_M) must swing

symmetrically between VCM + 0.5 V and VCM – 0.5 V, resulting in a 2-V_PPdifferential input swing. The input

sampling circuit has a high 3-dB bandwidth that extends up to 550 MHz (measured from the input pins to the

sampled voltage).

20

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Feature Description (接下页)

SZ

S

R_(ON)

C_(PAR3)

25 W

100 W

0.3 pF

Sampling

Switch

L_(PKG)

2 nH

S

Sampling

Capacitor

15 W

INx_P

R_(ON)

C_(PAR2)

1 pF

C_(SAMP)

4 pF

C_(BOND)

10 W

1 kW

0.5 pF

R_(ESR)

C_(PAR1)

0.1 pF

R_(ON)

40 Ω

V_IC

200 W

L_(PKG)

2 nH

C_(SAMP)

C_(PAR2)

1 pF

R_(ON)

4 pF

15 W

10 W

INx_M

Sampling

Capacitor

C_(BOND)

0.5 pF

Sampling

Switch

S

R_(ON)

R_(ESR)

25 W

100 W

200 W

C_(PAR3)

0.3 pF

S

SZ

图 42. Analog Input Equivalent Circuit

7.3.1.1 Large- and Small-Signal Input Bandwidth

The analog input circuit small-signal bandwidth is high, approximately 550 MHz. When using an amplifier to drive

the VSP5324-Q1 device, the total amplifier noise up to small-signal bandwidth must be considered. The device

large-signal bandwidth depends on the input signal amplitude. The VSP5324-Q1 device supports 2-V_PP

amplitude for input signal frequencies up to 80 MHz. For higher frequencies (greater than 80 MHz), the input

signal amplitude must be decreased proportionally. For example, at 160 MHz, the device supports a maximum of

1-V_PPsignal.

7.3.2 Digital Processing Block

The VSP5324-Q1 device integrates a set of commonly-used digital functions that can be used to ease system

design such as test patterns and gain.

7.3.2.1 Digital Gain

The VSP5324-Q1 device includes programmable digital gain settings from 0 dB to 12 dB in 1-dB steps. The

benefit of digital gain is to obtain improved SFDR performance. SFDR improvement is achieved at the expense

of SNR; for each gain setting, SNR degrades by approximately 1 dB. Therefore, gain can be used to trade-off

between SFDR and SNR.

For each gain setting, the analog input full-scale range support scales proportionally, as shown in 表 1. After

reset, the device is in 0-dB gain mode. To use other gain settings, program the GAIN_CHx bits in registers 2Ah

(see the Register 2Ah (offset = 2Ah) [reset = 0] section) and 2Bh (see the Register 2Bh (offset = 2Bh) [reset = 0]

section).

21

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www.ti.com.cn

表 1. Analog Input Full-Scale

Range Across Gains

DIGITAL GAIN

(dB)

FULL-SCALE

(V_PP

)

0

1

2

1.78

1.59

1.42

1.26

1.12

1.00

0.89

0.80

0.71

0.63

0.56

0.50

2

3

4

5

6

7

8

9

10

11

12

7.3.2.2 ADC Input Polarity Inversion

Normally, the INx_P pin represents the positive analog input pin and INx_M represents the complementary

negative input. Setting the INVERT_ CH[4:1] bits listed in 表 2 (which provide individual control for each channel)

causes the inputs to be swapped. INN now represents the positive input and INx_P represents the negative

input.

表 2. Polarity Inversion

ADDRESS

(HEX)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

INVERT_

CH4

INVERT_

CH3

INVERT_

CH2

INVERT_

CH1

24

PRBS_SEED[22:16]

X⁽¹⁾

X

(1) X = don't care.

7.3.2.3 SYNC Function

The SYNC function can be used to synchronize the RAMP test patterns across channels. This function can be

enabled using either the hardware pin (SYNC) or software register bits.

To enable the software sync, set the register bit, EN_SYNC. To use the SYNC pin, set the EN_SYNC and

HARD_SYNC_TP register bits. Note that SYNC pin is disabled after reset.

7.3.2.4 Output Data Format

Two output data formats are supported: twos complement and offset binary. These modes can be selected using

the BTC_MODE serial interface register bit.

For a positive overload, the D[11:0] output data bits are FFFh in offset binary output format and 7FFh in twos

complement output format. For a negative input overload, the output code is 000h in offset binary output format

and 800h in twos complement output format.

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7.3.3 Serial LVDS Interface

The VSP5324-Q1 device offers several flexible output options which makes interfacing to an (application-specific

integrated circuit) ASIC or an (field-programmable gate array) FPGA easy. Each option can be easily

programmed using the serial interface. 表 3 lists a summary of all options. This table also lists the default values

after power-up and reset and a detailed description of each option. The output interface options are one-lane and

two-lane serialization, and are described in the One-Lane, 12x Serialization with DDR Bit Clock and 1x Frame

Clock and Two-Lane, 6x Serialization with DDR Bit Clock and 0.5x Frame Clock sections, respectively.

表 3. Summary of Output Interface Options

AVAILABLE IN

ONE-

LANE

TWO-

LANE

DEFAULT AFTER

RESET

FEATURE

OPTIONS

DESCRIPTION

One-lane: ADC data are sent serially

over one pair of LVDS pins

Two-lane: ADC data are split and

sent serially over two pairs of LVDS

pins

Lane interface

One and two lanes

Yes

One-lane

Serialization factor

12x

6x

Yes

No

12x

—

6x

—

DDR bit clock frequency

3x

Yes

No

Only with two-lane interface

—

1x sample rate

1/2x sample rate

Byte-wise

Bit-wise

Yes

No

1x

Frame clock frequency

Yes

—

Only with two-lane interface

No

Byte-wise

These options are available only with

two-lane interface.

Byte wise: ADC data are split into

upper and lower bytes that are output

on separate lanes.

No

Bit sequence

Bit wise: ADC data are split into even

and odd bits that are output on

separate lanes.

Word-wise

No

Yes

Byte-wise

Word wise: Successive ADC data

samples are sent over separate

lanes.

7.3.3.1 One-Lane, 12x Serialization with DDR Bit Clock and 1x Frame Clock

The 12-bit ADC data are serialized and output over one LVDS pair per channel along with a 6x bit clock and 1x

frame clock, as shown in 图 43. The output data rate is 12x sample rate and is therefore suited for low sample

rates (typically up to 50 MSPS).

Input Clock

CLK Frequency = f_S

Frame Clock

ADCLK Frequency = 1x ƒ_S

Bit Clock

LCLK Frequency = 6x ƒ_S

Output Data⁽¹⁾

D11

(D0)

D10

(D1)

D9

(D2)

D8

(D3)

D7

(D4)

D6

(D5)

D5

(D6)

D4

(D7)

D3

(D8)

D2

(D9)

D1

(D10)

D0

(D11)

D11

(D0)

D10

(D1)

OUT1A, OUT2A, OUT3A, OUT4A

Data Rate = 12x ƒ_S

Sample N

Sample N + 1

(1) Upper number is the data bit in MSB-first mode. Lower number in parenthesis is the data bit in LSB-first mode.

图 43. LVDS Output Interface, One-Lane, 12x Serialization

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7.3.3.2 Two-Lane, 6x Serialization with DDR Bit Clock and 0.5x Frame Clock

In the two-lane serialization option, the 12-bit ADC data are serialized and output over two LVDS pairs per

channel. The output data rate is a 6x sample rate with a 3x bit clock and a 1x frame clock.

Compared to the one-line scenario, the two-line output data rate is half the amount. This difference allows the

device to be used up to the maximum sampling rate. Two-lane serialization is available in bit-, byte-, and word-

wise modes. 图 44 shows the bit- and byte-wise modes and 图 45 shows the word-wise mode.

Input Clock

CLK Frequency = ƒ_S

FRAME Clock

ADCLKP, ADCLKM

Frequency = 0.5x ƒ_S

DDR Bit Clock

LCLK Frequency = 3x ƒS_S

Output Data⁽¹⁾⁽²⁾

OUT1B, OUT2B

OUT3B, OUT4B

D11

(D0)

D10

(D1)

D9

(D2)

D8

(D3)

D7

(D4)

D6

(D5)

D11

(D0)

D10

(D1)

D9

(D2)

D8

(D3)

D7

(D4)

D6

(D5)

Output Data⁽¹⁾⁽²⁾

OUT1A, OUT2A

OUT3A, OUT4A

D5

(D6)

D4

(D7)

D3

(D8)

D2

(D9)

D1

(D10)

D0

(D11)

D5

(D6)

D4

(D7)

D3

(D8)

D2

(D9)

D1

(D10)

D0

(D11)

Output Data⁽¹⁾⁽²⁾

OUT1B, OUT2B,

OUT3B, OUT4B

D10

(D1)

D8

(D3)

D6

(D5)

D4

(D7)

D2

(D9)

D0

(D11)

D10

(D1)

D8

(D3)

D6

(D5)

D4

(D7)

D2

(D9)

D0

(D11)

Output Data⁽¹⁾⁽²⁾

OUT1A, OUT2A,

OUT3A, OUT4A

D11

(D0)

D9

(D2)

D7

(D4)

D5

(D6)

D3

(D8)

D1

(D10)

D11

(D0)

D9

(D2)

D7

(D4)

D5

(D6)

D3

(D8)

D1

(D10)

(1) The upper number is the data bit in MSB-first mode. The lower number in parenthesis is the data bit in LSB-first mode.

(2) The unshaded cells indicate sample N data. The shaded cells indicate sample N + 1 data.

图 44. LVDS Output Interface, Two-Lane, 6x Serialization, Byte-Wise and Bit-Wise Modes

Input Clock

CLK Frequency = ƒ_S

FRAME Clock

ADCLKP, ADCLKM

Frequency = 0.5x ƒ_S

DDR Bit Clock

LCLK Frequency = 3x ƒ_S

Output Data⁽¹⁾⁽²⁾

OUT1A, OUT2A

OUT3A, OUT4A

D0

(D11)

D1

(D10)

D2

(D9)

D3

(D8)

D4

(D7)

D5

(D6)

D6

(D5)

D7

(D4)

D8

(D3)

D9

(D2)

D10

(D1)

D11

(D0)

Output Data⁽¹⁾⁽²⁾

OUT1B, OUT2B

OUT3B, OUT4B

D0

(D11)

D1

(D10)

D2

(D9)

D3

(D8)

D4

(D7)

D5

(D6)

D67

(D54)

D7

(D4)

D8

(D3)

D9

(D2)

D10

(D1)

D11

(D0)

(1) The upper number is the data bit in MSB-first mode. The lower number in parenthesis is the data bit in LSB-first mode.

(2) The unshaded cells indicate sample N data. The shaded cells indicate sample N + 1 data.

图 45. LVDS Output Interface, Two-Lane, 6x Serialization, Word-Wise Mode

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7.3.4 Bit Clock Programmability

The VSP5324-Q1 output interface is normally a DDR interface with the LCLK rising and falling edge transitions in

the middle of alternate data windows. 图 46 shows this default phase.

ADCLKP

LCLKP

OUTxy_P

图 46. LCLK Default Phase (PHASE_DDR[1:0] = 10)

The LCLK phase can be programmed relative to the output frame clock and data using the PHASE_DDR[1:0]

bits in 表 4. 图 47 shows the LCLK phase modes.

表 4. Clock Programmability

ADDRESS

(HEX)

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

EN_REF_

VCM0

EN_REF_

VCM1

42

X⁽¹⁾

X

PHASE_DDR[1:0]

X

(1) X = don't care.

ADCLKP

LCLKP

ADCLKP

LCLKP

OUTxy_P

a) PHASE_DDR[1:0] = 00

b) PHASE_DDR[1:0] = 10

ADCLKP

LCLKP

ADCLKP

LCLKP

OUTxy_P

c) PHASE_DDR[1:0] = 01

d) PHASE_DDR[1:0] = 11

图 47. LCLK Phase Programmability Modes

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7.3.5 LVDS Output Data and Clock Buffers

图 48 shows the equivalent circuit of each LVDS output buffer. After reset, the buffer presents a 100-Ω output

impedance to match the external 100-Ω termination.

The V_IDvoltage is nominally 350 mV, resulting in an output swing of ±350 mV with 100-Ω external termination.

The buffer output impedance behaves in the same way as a source-side series termination. By absorbing

reflections from the receiver end, the buffer helps improve signal integrity.

Device

V_ID

OUTxy_P

External

100-W Load

OUTxy_M

R_O

1.1 V

V_ID

图 48. LVDS Buffer Equivalent Circuit

7.4 Device Functional Modes

7.4.1 External Reference Mode Of Operation

The VSP5324-Q1 device supports an external reference mode of operation either by:

•

Forcing the reference voltages on the REFT and REFB pins, or by

Applying the reference voltage on the VCM pin.

This mode can be used to operate multiple VSP5324-Q1 chips with the same (externally applied) reference

voltage.

7.4.1.1 Using the REF Pins

For normal operation, the device requires two reference voltages, REFT and REFB. By default, the device

generates these two voltages internally. To enable the external reference mode, set the register bits as listed in

表 5. This procedure powers down the internal reference amplifier and the two reference voltages can be forced

directly on the REFT and REFB pins as (V_(REFT)= 1.45 V ± 50 mV) and (V_(REFB)= 0.45 V ±50 mV).

Use to calculate the relationship between the ADC full-scale input voltage (V_FS) and the applied reference

voltages.

V_FS= 2 ´ (V_(REFT)- V_(REFB)

)

(1)

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Device Functional Modes (接下页)

7.4.1.2 Using the VCM Pin

In this mode, an external reference voltage (VREFIN) can be applied to the VCM pin. Use公式 2 to calculate the

relationship between the ADC full-scale input voltage and VREFIN.

V_FS= 2 ´ VREFIN

(2)

To enable this mode, set the register bits as listed in 表 5. This action changes the function of the VCM pin to an

external reference input pin. The voltage applied on VCM must be 1.5 V ±50 mV.

表 5. External Reference Function

FUNCTION

EN_HIGH_ADDRS

EN_EXT_REF

EXT_REF_VCM

External reference using the REFT and REFB pins

External reference using the VCM pin

1

00

11

7.5 Programming

7.5.1 Serial Interface

The VSP5324-Q1 device has a set of internal registers that can be accessed by the serial interface formed by

the CS (serial interface enable), SCLK (serial interface clock), and SDATA (serial interface data) pins. When CS

is low the following occurs:

•

The serial shift of bits into the device is enabled.

Serial data (on the SDATA pin) are latched at every SCLK rising edge.

The serial data are loaded into the register at every 24th SCLK rising edge.

If the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of

24-bit words within a single active CS pulse.

The first eight bits form the register address and the remaining 16 bits form the register data. The interface can

function with SCLK frequencies from 15 MHz down to very low speeds (of few Hertz) and also with a non-50%

SCLK duty cycle.

7.5.2 Register Initialization

After power-up, the internal registers must be initialized to the default values. This reset can be accomplished in

one of two ways:

1. A hardware reset is applied by a low-going pulse on the RESET pin (widths greater than 10 ns), as shown in

图 3 and Serial Interface Timing Requirements.

2. A software reset is applied by using the serial interface and setting the RST bit (register 00h, bit D0) high.

This setting initializes the internal registers to default values and then self-resets the RST bit low. In this

case, the RESET pin is kept high (inactive).

See the Serial Interface Timing Requirements section and 图 3 for timing information.

7.5.3 Serial Register Readout

The device includes a mode where the contents of the internal registers can be readback on the SDOUT pin, as

shown in 图 49. This mode can useful as a diagnostic check to verify the serial interface communication between

the external controller and ADC.

By default, after power-up and device reset, the SDOUT pin is high-impedance. When readout mode is enabled

using the READOUT register bit, the SDOUT pin outputs the contents of the selected register serially in the

following sequence:

1. The READOUT register bit must be set to 1 in order for the device to enter readout mode. This setting

disables any further writes into the internal registers, except for the register at address 01h. Note that the

READOUT bit is also located in this register. The device can exit readout mode by writing the READOUT bit

to 0. Only the register contents of address 01h are unable to be read in register readout mode.

2. The read cycle is initiated by clocking the register address A[7:0] on the SDIN pin.

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Programming (接下页)

3. The device serially outputs the contents (D[15:0]) of the selected register on the SDOUT pin.

4. The external controller latches the contents at the SCLK rising edge.

5. The READOUT register bit is set to 0 to exit serial readout mode, which enables all registers of the device to

be written to. At this point, the SDOUT pin enters a high-impedance state.

Register Address (A[7:0]) = 01h

Register Data (D[15:0]) = 0001h

0

1

0

1

SDATA

SCLK

CS

Pin SDOUT becomes active

and forces low.

Pin SDOUT is in the high-impedance state.

SDOUT

a) Enable Serial Readout (READOUT = 1)

Register Data (D[15:0]) = XXXX (don’t care)

Register Address (A[7:0]) = 0Fh

A7

D15

D14

D13

D12

D11

D10

SDATA

SCLK

A6

A5

A4

A3

A2

A1

A0

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

CS

0

SDOUT

0

1

Pin SDOUT outputs contents of register 0x0F in the same cycle, MSB first.

b) Read contents of register 0Fh. This register is initialized with 0200h (previously, the device was in global power down).

图 49. Serial Readout Timing

After reset, the device default states include the following:

•

The device is in normal operation mode with 12x serialization enabled for all channels.

Output interface is one-lane, 12x serialization with a 6x bit clock and a 1x frame clock frequency.

Data format is LSB-first and offset binary.

Serial readout is disabled.

The PD pin is configured as a global power-down pin.

Digital gain is set to 0 dB.

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7.6.1 Serial Registers

7.6.1.1 Register 00h (offset = 00h) [reset = 0]

This is a general register.

图 50. Register 00h

D15

D7

D14

D6

D13

D5

D12

D11

D10

D2

D9

D1

D8

X

W-0

D4

X

D3

D0

RST

W-0

表 7. Register 00h Field Descriptions

Bit

Field

X

Type

W

Reset

Description

D15-D1

D0

0

Don't care bits

RST

W

Reset

0 = Normal operation (default)

1 = Self-clearing software reset (after reset, this bit is set to

0)

7.6.1.2 Register 01h (offset = 01h) [reset = 0]

This is a general register.

图 51. Register 01h

D15

D7

D14

D13

D5

D12

D11

D10

D9

D1

D8

X

W-0

D6

X

D4

D3

D2

X

D0

EN_HIGH_ADD

RS

READOUT

W-0

表 8. Register 01h Field Descriptions

Bit

Field

Type

W

Reset

Description

D15-D5

D4

X

0

Don't care bits

EN_HIGH_ADDRS

W

Register F0h access

0 = Disables access to register F0h (default)

1 = Enables access to register F0h

D3-D1

D0

X

W

0

Don't care bits

READOUT

Register mode readout

0 = Normal operation (default)

1 = Register mode readout

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7.6.1.3 Register 02h (offset = 02h) [reset = 0]

This is a general register.

图 52. Register 02h

D15

D7

D14

D6

D13

D12

D11

D10

X

D9

D1

D8

D0

X

EN_SYNC

R/W-0

D5

D4

D3

D2

X

R/W-0

表 9. Register 02h Field Descriptions

Bit

Field

Type

R/W

Reset

Description

D15-D14

D13

X

0

Don't care bits

SYNC enable⁽¹⁾

EN_SYNC

0 = Normal operation; SYNC feature disabled (default)

1 = SYNC feature enabled to synchronize test patterns

D12-D0

X

R/W

0

Don't care bits

(1) This bit must be set to 1 when the software or hardware SYNC feature is used; see bits D15 and D8 in the Register 25h (offset = 25h)

[reset = 0] section.

7.6.1.4 Register 0Ah (offset = 0Ah) [reset = 0]

This is a general register.

图 53. Register 0Ah

D15

D7

D14

D6

D13

D5

D12

D11

D10

D2

D9

D1

D8

D0

RAMP_PAT_RESET_VAL

R/W-0

D4

D3

RAMP_PAT_RESET_VAL

R/W-0

表 10. Register 0Ah Field Descriptions

Bit

Field

Type

Reset

Description

D15-D0 RAMP_PAT_RESET_VAL

R/W

0

These bits determine the initial value of the ramp pattern after

reset.

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7.6.1.5 Register 0Fh (offset = 0Fh) [reset = 0]

This is a power-down mode register. All bits default to 0 after reset.

图 54. Register 0Fh

D15

D14

D13

X

D12

D4

D11

D10

D9

D8

PDN_PIN_CFG

PDN_

COMPLETE

PDN_PARTIAL

R/W-0

D7

D6

X

D5

D3

D2

D1

X

D0

PDN_CH4

R/W-0

PDN_CH3

R/W-0

X

PDN_CH2

R/W-0

PDN_CH1

R/W-0

表 11. Register 0Fh Field Descriptions

Bit

D15-D11

D10

Field

Type

R/W

Reset

Description

X

0

Don't care bits

PDN_PIN_CFG

PD pin configuration

0 = PD pin configured for complete power-down mode

1 = PD pin configured for partial power-down mode

D9

D8

D7

PDN_ COMPLETE

R/W

0

Complete power-down

0 = Normal operation

1

= Register mode for complete power-down (slower

recovery)

PDN_PARTIAL

PDN_CH4

Partial power-down

0 = Normal operation

1 = Partial power-down mode (fast recovery from power-

down)

ADC power-down mode for channel 4

0 = Normal operation

1 = Partial power-down mode (fast recovery from power-

down)

D6

D5

X

R/W

0

Don't care bit

PDN_CH3

ADC power-down mode for channel 3

0 = Normal operation

1 = ADC power-down mode for channel 3

Don't care bits

D4-D3

D2

X

R/W

0

PDN_CH2

ADC power-down mode for channel 2

0 = Normal operation

1 = ADC power-down mode for channel 2

Don't care bit

D1

D0

X

R/W

0

PDN_CH1

ADC power-down mode for channel 1

0 = Normal operation

1 = ADC power-down mode for channel 1

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7.6.1.6 Register 14h (offset = 14h) [reset = 0]

This is a general register.

图 55. Register 14h

D15

D14

D13

D12

D11

D10

D9

D8

X

R/W-0

D7

D6

X

D5

D4

D3

D2

D1

X

D0

LFNS_CH4

R/W-0

LFNS_CH3

R/W-0

X

LFNS_CH2

R/W-0

LFNS_CH1

R/W-0

表 12. Register 14h Field Descriptions

Bit

D15-D8

D7

Field

Type

R/W

Reset

Description

X

0

Don't care bits

LFNS_CH4

Noise-suppression mode selection for channel 4

0 = LFNS disabled (default)

1 = Low-frequency noise-suppression mode enable for

channel 4

D6

D5

X

R/W

0

Don't care bit

LFNS_CH3

Noise-suppression mode selection for channel 3

0 = LFNS disabled (default)

1 = Low-frequency noise-suppression mode enable for

channel 3

D4-D3

D2

X

R/W

0

Don't care bits

LFNS_CH2

Noise-suppression mode selection for channel 2

0 = LFNS disabled (default)

1 = Low-frequency noise-suppression mode enable for

channel 2

D1

D0

X

R/W

0

Don't care bit

LFNS_CH1

Noise-suppression mode selection for channel 1

0 = LFNS disabled (default)

1 = Low-frequency noise-suppression mode enable for

channel 1

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7.6.1.7 Register 1Ch (offset = 1Ch) [reset = 0]

This is a test pattern register. All bits default to 0 after reset.

图 56. Register 1Ch

D15

X

D14

D13

D12

D11

D10

D9

D1

D8

D0

EN_FRAME_P

AT

ADCLKOUT[11:0]

R/W-0

D7

R/W-0

D6

R/W-0

D5

D4

D3

D2

ADCLKOUT[11:0]

R/W-0

X

R/W-0

表 13. Register 1Ch Field Descriptions

Bit

Field

Type

R/W

Reset

Description

D15

D14

X

0

Don't care bit

EN_FRAME_PAT

Frame pattern enable

0 = Normal frame clock operation

1 = Enables the output frame clock to be programmed

through a pattern

D13-D2 ADCLKOUT[11:0]

R/W

0

ADCLK pin frame clock pattern

These bits determine the 12-bit pattern for the frame clock on

the ADCLKP and ADCLKN pins.

D1-D0

X

Don't care bits

7.6.1.8 Register 23h (offset = 23h) [reset = 0]

This is a test pattern register.

图 57. Register 23h

D15

D7

D14

D6

D13

D5

D12

PRBS_SEED[15:0]

R/W-0

D11

D10

D2

D9

D1

D8

D0

D4

D3

PRBS_SEED[15:0]

R/W-0

表 14. Register 23h Field Descriptions

Bit

Field

Type

Reset

Description

D15-D0 PRBS_SEED[15:0]

R/W

0

PRBS pattern seed value, lower bits

These bits determine the PRBS pattern starting seed value of

the lower 16 bits. (Default = 0)

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7.6.1.9 Register 24h (offset = 24h) [reset = 0]

This is a test pattern register. All bits default to 0 after reset.

图 58. Register 24h

D15

D14

D13

D12

PRBS_SEED[22:16]

R/W-0

D11

D10

D9

D8

X

R/W-0

D7

D6

X

D5

D4

D3

D2

D1

X

D0

INVERT_CH4

R/W-0

INVERT_CH3

R/W-0

X

R/W-0

INVERT_CH2

R/W-0

INVERT_CH1

R/W-0

表 15. Register 24h Field Descriptions

Bit

Field

Type

Reset

Description

D15-D9 PRBS_SEED[22:16]

R/W

0

PRBS pattern seed value, upper bits

These bits determine the PRBS pattern starting seed value of

the upper seven bits.

D8

D7

X

R/W

0

Don't care bit

INVERT_CH4

Analog input pin polarity for channel 4

0 = Normal configuration (default)

1 = Electrically swaps the analog input pin polarity for

channel 4

D6

D5

X

R/W

0

Don't care bit

INVERT_CH3

Analog input pin polarity for channel 3

0 = Normal configuration (default)

1 = Electrically swaps the analog input pin polarity for

channel 3

D4-D3

D2

X

R/W

0

Don't care bits

INVERT_CH2

Analog input pin polarity for channel 2

0 = Normal configuration (default)

1 = Electrically swaps the analog input pin polarity for

channel 2

D1

D0

X

R/W

0

Don't care bit

INVERT_CH1

Analog input pin polarity for channel 1

0 = Normal configuration (default)

1 = Electrically swaps the analog input pin polarity for

channel 1

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7.6.1.10 Register 25h (offset = 25h) [reset = 0]

This is a test pattern register. All bits default to 0 after reset.

图 59. Register 25h

D15

D14

D13

D12

D11

D10

X

D9

D1

D8

HARD_SYNC_ PRBS_SEED_ PRBS_MODE_ PRBS_TP_EN

TP_SOFT_SYN

C

TP

FROM_REG

R/W-0

2

R/W-0

D4

R/W-0

D2

R/W-0

D0

D7

X

D6

D5

D3

EN_RAMP

DUAL_CUSTO SINGLE_CUST

BITS_CUSTOM2[13:12]

BITS_CUSTOM1[13:12]

M_PAT

OM_PAT

R/W-0

表 16. Register 25h Field Descriptions

Bit

Field

Type

Reset

Description

D15

HARD_SYNC_TP

R/W

0

Sync test pattern selection

0 = Inactive

1

= External SYNC feature enabled for syncing test

patterns

D14

PRBS_SEED_FROM_REG

R/W

0

PRBS seed selection

0 = Disabled

1 = Selection of PRBS seed from registers 23h and 24h

enabled

D13

D12

PRBS_MODE_2

PRBS_TP_EN

R/W

0

PRBS mode selection

This bit sets the PRBS mode of the 9-bit LFSR (the 23-bit LFSR

is default).

PRBS test pattern selection

0 = PRBS test pattern disabled

1 = PRBS test pattern enable bit

Don't care bits

D11-D9

D8

X

R/W

0

TP_SOFT_SYNC

Test pattern software sync

0 = No sync

1 = Software sync bit for test patterns on all eight channels

Don't care bit

D7

D6

X

R/W

0

EN_RAMP

Ramp pattern enable

0 = Normal operation

1 = Enables a repeating full-scale ramp pattern on the

outputs. Ensure that bits D4 and D5 are 0.

D5

D4

DUAL_CUSTOM_PAT

SINGLE_CUSTOM_PAT

BITS_CUSTOM2[13:12]

R/W

0

Output toggles between two codes

0 = Normal operation

1 = Enables mode where the output toggles between two

defined codes. Ensure that bits D4 and D6 are 0.

Output is defined code

0 = Normal operation

1 = Enables mode where the output is a constant specified

code. Ensure that bits D5 and D6 are 0.

D3-D2

MSB selection for dual patterns

These bits determine two MSBs for the second code of the dual

custom patterns.

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表 16. Register 25h Field Descriptions (接下页)

Bit

Field

Type

Reset

Description

D1-D0

BITS_CUSTOM1[13:12]

R/W

0

MSB selection for single patterns

These bits define two MSBs for the single custom pattern (and

for the first code of the dual custom patterns).

7.6.1.11 Register 26h (offset = 26h) [reset = 0]

This is a test pattern register.

图 60. Register 26h

D15

D14

D13

D5

D12

D11

D10

D2

D9

D1

D8

D0

BITS_CUSTOM1[9:0]

R/W-0

D7

D6

D4

D3

BITS_CUSTOM1[9:0]

R/W-0

X

R/W-0

表 17. Register 26h Field Descriptions

Bit

Field

Type

Reset

Description

D15-D6 BITS_CUSTOM1[9:0]

R/W

0

Lower single custom pattern bits

These bits determine the 10 lower bits for the single custom

pattern (and the first code of the dual custom pattern).

D5-D0

X

R/W

0

Don't care bits

7.6.1.12 Register 27h (offset = 27h) [reset = 0]

This is a test pattern register.

图 61. Register 27h

D15

D14

D13

D5

D12

D11

D10

D2

D9

D1

D8

D0

BITS_CUSTOM2[9:0]

R/W-0

D7

D6

D4

D3

BITS_CUSTOM2[9:0]

R/W-0

X

R/W-0

表 18. Register 27h Field Descriptions

Bit

Field

Type

Reset

Description

D15-D6 BITS_CUSTOM2[9:0]

R/W

0

Lower dual custom pattern bits

These bits determine the 10 lower bits for the second code of

the dual custom pattern.

D5-D0

X

R/W

0

Don't care bits

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7.6.1.13 Register 28h (offset = 28h) [reset = 0]

This is an output interface mode register. All bits default to 0 after reset.

图 62. Register 28h

D15

EN_BITORDER

R/W-0

D14

D6

D13

D5

D12

D4

D11

D3

D10

D2

D9

D1

D8

X

BIT_WISE

R/W-0

D7

D0

EN_WORDWISE_BY_CH[7:0]

R/W-0

表 19. Register 28h Field Descriptions

Bit

Field

Type

Reset

Description

Bit order enable⁽¹⁾

D15

EN_BITORDER

R/W

0

This bit enables the bit order output in two-lane mode.

0 = Byte-wise

1 = Word-wise

Don't care bit

D14-D9

D8

X

R/W

0

BIT_WISE

Bit- or byte-wise selection

This bit selects between byte-wise and bit-wise format.

0 = Byte-wise, the upper bits come are on one lane and the

lower bits are on other lane

1 = Bit-wise, the odd bits come out on one lane and the

even bits come out on other lane

D7-D0

EN_WORDWISE_BY_CH[7:0]

R/W

0

Word-wise enable with channels 7 to 0

0 = Data comes out in two-lane mode with the upper set of

bits on one channel and the lower set of bits on the other

channel

1 = Output format is one sample on one LVDS lane with

the next sample on the other LVDS lane

(1) This bit must set 1 to enable bits D[8:0].

7.6.1.14 Register 29h (offset = 29h) [reset = 0]

This is a digital filter mode register. All bits default to 0 after reset.

图 63. Register 29h

D15

D7

D14

D6

D13

D5

D12

D4

D11

D3

D10

D2

D9

D1

D8

X

R/W-0

D0

X

GLOBAL_EN_F

ILTER

R/W-0

表 20. Register 29h Field Descriptions

Bit

Field

Type

R/W

Reset

Description

D15-D2

D1

X

0

Don't care bits

GLOBAL_EN_FILTER

Filter block enable

0 = Inactive

1 = Global control filter blocks enabled

Don't care bit

D0

X

R/W

0

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7.6.1.15 Register 2Ah (offset = 2Ah) [reset = 0]

This is a digital gain mode register. All bits default to 0 after reset.

图 64. Register 2Ah

D15

D7

D14

D6

D13

D5

D12

D4

D11

D3

D10

GAIN_CH2[3:0]

R/W-0

D9

D8

D0

X

R/W-0

D2

D1

X

GAIN_CH1[3:0]

R/W-0

表 21. Register 2Ah Field Descriptions

Bit

D15-D12

Field

Type

R/W

Reset

Description

X

0

Don't care bits

D11-D8 GAIN_CH2[3:0]

Channel 2 gain

These bits set the programmable gain of channel 2

Don't care bits

D7-D4

D3-D0

X

R/W

0

GAIN_CH3[3:0]

Channel 1 gain

These bits set the programmable gain of channel 1

7.6.1.16 Register 2Bh (offset = 2Bh) [reset = 0]

This is a digital gain mode register. All bits default to 0 after reset.

图 65. Register 2Bh

D15

D7

D14

D6

D13

D5

D12

D4

D11

D3

D10

GAIN_CH3[3:0]

R/W-0

D9

D8

D0

X

R/W-0

D2

D1

X

GAIN_CH4[3:0]

R/W-0

表 22. Register 2Bh Field Descriptions

Bit

D15-D12

Field

Type

R/W

Reset

Description

X

0

Don't care bits

D11-D8 GAIN_CH3[3:0]

Channel 3 gain

These bits set the programmable gain of channel 3

Don't care bits

D7-D4

D3-D0

X

R/W

0

GAIN_CH4[3:0]

Channel 4 gain

These bits set the programmable gain of channel 4

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7.6.1.17 Register 2Eh (offset = 2Eh) [reset = 0]

This is a digital filter mode register. All bits default to 0 after reset.

图 66. Register 2Eh

D15

X

D14

HPF_EN_CH1

R/W-0

D13

D12

D11

D10

D9

D8

HPF_CORNER _CH1[3:0]

R/W-0

FILTER1_COEFF_SET[2:0]

R/W-0

D7

D6

D5

D4

D3

X

D2

D1

X

D0

FILTER1_COE

FF_SET[2:0]

FILTER1_RATE[2:0]

ODD_TAP1

USE_FILTER1

R/W-0

表 23. Register 2Eh Field Descriptions

Bit

Field

Type

R/W

Reset

Description

D15

D14

X

0

Don't care bit

HPF_EN_CH1

Channel 1 HPF filter enable

0 = Disabled

1 = HPF filter enable for channel 1

D13-D10 HPF_CORNER _CH1[3:0]

R/W

0

HPF corner for channel 1

These bits set the HPF corner in values from 2k to 10k.

D9-D7

D6-D4

FILTER1_COEFF_SET[2:0]

FILTER1_RATE[2:0]

Filter 1 coefficient set

These bits select the stored coefficient set for filter 1.

Filter 1 decimation factor

These bits set the decimation factor for filter 2.

Don't care bit

D3

D2

X

R/W

0

ODD_TAP1

Filter 1 odd tap

This bit uses odd tap filter 1.

Don't care bit

D1

D0

X

R/W

0

USE_FILTER1

Channel 1 filter

0 = Disabled

1 = Enables filter for channel 1

41

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7.6.1.18 Register 30h (offset = 30h) [reset = 0]

This is a digital filter mode register. All bits default to 0 after reset.

图 67. Register 30h

D15

X

D14

HPF_EN_CH2

R/W-0

D13

D12

D11

D10

D9

D8

HPF_CORNER _CH2[3:0]

R/W-0

FILTER2_COEFF_SET[2:0]

R/W-0

D7

D6

D5

D4

D3

X

D2

D1

X

D0

FILTER2_COE

FF_SET[2:0]

FILTER2_RATE[2:0]

ODD_TAP2

USE_FILTER2

R/W-0

表 24. Register 30h Field Descriptions

Bit

Field

Type

R/W

Reset

Description

D15

D14

X

0

Don't care bit

HPF_EN_CH2

Channel 2 HPF filter enable

0 = Disabled

1 = HPF filter enable for channel 2

D13-D10 HPF_CORNER _CH2[3:0]

R/W

0

HPF corner for channel 2

These bits set the HPF corner in values from 2k to 10k.

D9-D7

D6-D4

FILTER2_COEFF_SET[2:0]

FILTER2_RATE[2:0]

Filter 2 coefficient set

These bits select the stored coefficient set for filter 2.

Filter 2 decimation factor

These bits set the decimation factor for filter 2.

Don't care bit

D3

D2

X

R/W

0

ODD_TAP2

Filter 2 odd tap

This bit uses odd tap filter 2.

Don't care bit

D1

D0

X

R/W

0

USE_FILTER2

Channel 2 filter

0 = Disabled

1 = Enables filter for channel 2

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7.6.1.19 Register 33h (offset = 33h) [reset = 0]

This is a digital filter mode register. All bits default to 0 after reset.

图 68. Register 33h

D15

X

D14

HPF_EN_CH3

R/W-0

D13

D12

D11

D10

D9

D8

HPF_CORNER _CH3[3:0]

R/W-0

FILTER3_COEFF_SET[2:0]

R/W-0

D7

D6

D5

D4

D3

X

D2

D1

D0

FILTER3_COE

FF_SET[2:0]

FILTER3_RATE[2:0]

ODD_TAP3

USE_FILTER3

R/W-0

表 25. Register 33h Field Descriptions

Bit

Field

Type

R/W

Reset

Description

D15

D14

X

0

Don't care bit

HPF_EN_CH3

Channel 3 HPF filter enable

0 = Disabled

1 = HPF filter enable for channel 3

D13-D10 HPF_CORNER _CH3[3:0]

R/W

0

HPF corner for channel 3

These bits set the HPF corner in values from 2k to 10k.

D9-D7

D6-D4

FILTER3_COEFF_SET[2:0]

FILTER3_RATE[2:0]

Filter 3 coefficient set

These bits select the stored coefficient set for filter 3.

Filter 3 decimation factor

These bits set the decimation factor for filter 3.

Don't care bit

D3

D2

X

R/W

0

ODD_TAP3

Filter 3 odd tap

This bit uses odd tap filter 3.

Don't care bit

D1

D0

X

R/W

0

USE_FILTER3

Channel 3 filter

0 = Disabled

1 = Enables filter for channel 3

43

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7.6.1.20 Register 35h (offset = 35h) [reset = 0]

This is a digital filter mode register. All bits default to 0 after reset.

图 69. Register 35h

D15

X

D14

HPF_EN_CH4

R/W-0

D13

D12

D11

D10

D9

D8

HPF_CORNER _CH4[3:0]

R/W-0

FILTER4_COEFF_SET[2:0]

R/W-0

D7

D6

D5

D4

D3

X

D2

D1

X

D0

FILTER4_COE

FF_SET[2:0]

FILTER4_RATE[2:0]

ODD_TAP4

USE_FILTER4

R/W-0

表 26. Register 35h Field Descriptions

Bit

Field

Type

R/W

Reset

Description

D15

D14

X

0

Don't care bit

HPF_EN_CH4

Channel 4 HPF filter enable

0 = Disabled

1 = HPF filter enable for channel 4

D13-D10 HPF_CORNER _CH4[3:0]

R/W

0

HPF corner for channel 4

These bits set the HPF corner in values from 2k to 10k.

D9-D7

D6-D4

FILTER4_COEFF_SET[2:0]

FILTER4_RATE[2:0]

Filter 4 coefficient set

These bits select the stored coefficient set for filter 4.

Filter 4 decimation factor

These bits set the decimation factor for filter 4.

Don't care bit

D3

D2

X

R/W

0

ODD_TAP4

Filter 4 odd tap

This bit uses odd tap filter 4.

Don't care bit

D1

D0

X

R/W

0

USE_FILTER4

Channel 4 filter

0 = Disabled

1 = Enables filter for channel 4

7.6.1.21 Register 38h (offset = 38h) [reset = 0x0000]

This is an output interface mode register.

图 70. Register 38h

D15

D7

D14

D6

D13

D5

D12

D11

D10

D2

D9

D1

D8

D0

X

R/W-

D4

D3

X

DATA_RATE[1:0]

R/W-

表 27. Register 38h Field Descriptions

Bit

Field

Type

R/W

Reset

Description

D15-D2

D1-D0

X

0

Don't care bits

DATA_RATE[1:0]

Clock rate selection

These bits select the output frame clock rate. (Default = 0)

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7.6.1.22 Register 42h (offset = 42h) [reset = 0]

This is an output interface mode register.

图 71. Register 42h

D15

D14

D13

D12

D11

X

D10

D2

D9

D8

D0

EN_REF_VCM

0

R/W-0

D3

D7

X

D6

D5

D4

X

D1

X

PHASE_DDR[1:0]

R/W-0

EN_REF_VCM

1

R/W-0

表 28. Register 42h Field Descriptions

Bit

Field

Type

Reset

Description

D15

EN_REF_VCM0

R/W

0

To enable the external reference mode, the EN_EXT_REF

register bit (register F0h) must be set to 1.

00 = In external reference mode, apply the reference on the

REFT, REFB pins

01, 10 = Don't use

11 = In external reference mode, apply the reference on the

VCM pin

D14-D7

D6-D5

X

R/W

0

Don't care bits

PHASE_DDR[1:0]

These bits control the LCLK output phase relative to data.

(Default = 10)

D4

D3

X

R/W

0

Don't care bit

EN_REF_VCM1

To enable the external reference mode, the EN_EXT_REF

register bit (register F0h) must be set to 1.

00 = In external reference mode, apply the reference on the

REFT, REFB pins

01, 10 = Don't use

11 = In external reference mode, apply the reference on the

VCM pin

D2-D0

X

R/W

0

Don't care bits

45

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7.6.1.23 Register 45h (offset = 45h) [reset = 0]

This is a test pattern register. All bits default to 0 after reset.

图 72. Register 45h

D15

D7

D14

D6

D13

D5

D12

D4

D11

D10

D2

D9

D8

X

R/W-0

D3

D1

D0

X

PAT_SYNC

R/W-0

PAT_DESKEW

R/W-0

表 29. Register 45h Field Descriptions

Bit

Field

Type

R/W

Reset

Description

D15-D2

D1

X

0

Don't care bits

PAT_SYNC

Sync pattern enable

0 = Inactive

1 = Sync pattern mode enabled; ensure that D0 is 0

D0

PAT_DESKEW

R/W

0

Deskew pattern enable

0 = Inactive

1 = Deskew pattern mode enabled; ensure that D1 is 0

7.6.1.24 Register 46h (offset = 46h) [reset = 0]

This is an output interface mode register. All bits default to 0 after reset.

图 73. Register 46h

D15

ENABLE 46

R/W-0

D14

X

D13

FALL_SDR

R/W-0

D12

X

D11

D10

D9

D8

X

EN_16BIT

R/W-0

EN_14BIT

R/W-0

EN_12BIT

R/W-0

D7

D6

X

D5

D4

D3

D2

D1

X

D0

EN_SDR

R/W-0

MSB_FIRST

R/W-0

BTC_MODE

R/W-0

EN_2LANE

R/W-0

表 30. Register 46h Field Descriptions

Bit

Field

ENABLE 46

Type

Reset

Description

Enable register 46⁽¹⁾

This bit enables register 46.

Don't care bit

D15

R/W

0

D14

D13

X

R/W

0

FALL_SDR

SDR output mode

0 = At data window edge

1 = The LCLK rising or falling edge control comes in the

middle of the data window when operating in SDR output

mode

D12

D11

X

R/W

0

Don't care bit

EN_16BIT

16-bit mode enable

0 = Inactive

1 = 16-bit serialization mode enabled; ensure bits D[10:9]

are 0

(1) This bit must be set to 1 to enable bits D[13:0].

46

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表 30. Register 46h Field Descriptions (接下页)

Bit

Field

Type

Reset

Description

D10

EN_14BIT

R/W

0

14-bit mode enable

0 = Inactive

1 = 14-bit serialization mode enabled; ensure bits D11 and

D9 are 0

D9

EN_12BIT

R/W

0

12-bit mode enable

0 = Inactive

1 = 12-bit serialization mode enabled; ensure bits D[11:10]

are 0

D8-D5

D4

X

R/W

0

Don't care bits

EN_SDR

Bit clock selection

0 = DDR bit clock

1 = SDR bit clock

D3

D2

MSB_FIRST

BTC_MODE

R/W

0

MSB first selection

0 = LSB first

1 = MSB first

Binary mode selection

0 = Binary offset (ADC data output format)

1 = Binary twos complement (ADC data output format)

Don't care bit

D1

D0

X

R/W

0

EN_2LANE

LVDS output lane selection

0 = One-lane LVDS output

1 = Two-lane LVDS output

7.6.1.25 Register 50h (offset = 50h) [reset = 0]

This is a programmable LVDS mapping mode register. All bits default to 0 after reset.

图 74. Register 50h

D15

ENABLE 50

R/W-0

D14

D13

D12

D4

D11

X

D10

D9

D1

D8

D0

R/W-0

D7

D6

D5

D3

D2

MAP_CH12_TO_OUT1B[3:0]

R/W-0

MAP_CH12_TO_OUT1A[3:0]

R/W-0

表 31. Register 50h Field Descriptions

Bit

Field

Type

Reset

Description

Enable for register 50h⁽¹⁾

This bit enables register 50h.

Don't care bits

D15

ENABLE 50

R/W

0

D14-D8

D7-D4

X

R/W

0

MAP_CH12_TO_OUT1B[3:0]

OUT1B pin to channel mapping

These bits select the OUT1B pin pair to channel data mapping.

D3-D0

MAP_CH12_TO_OUT1A[3:0]

R/W

0

OUT1A pin to channel mapping

These bits select the OUT1A pin pair to channel data mapping.

(1) This bit must be set to 1 to enable bits D[7:0].

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7.6.1.26 Register 51h (offset = 51h) [reset = 0]

This is a programmable LVDS mapping mode register. All bits default to 0 after reset.

图 75. Register 51h

D15

ENABLE 51

R/W-0

D14

D13

X

D12

D4

D11

D3

D10

D9

D8

D0

MAP_CH12_TO_OUT2B[3:0]

R/W-0

D7

D6

D5

D2

D1

MAP_CH12_TO_OUT2A[3:0]

R/W-0

X

R/W-0

表 32. Register 51h Field Descriptions

Bit

Field

Type

Reset

Description

Enable for register 51h⁽¹⁾

D15

ENABLE 51

R/W

0

This bit enables register 51h.

Don't care bits

D14-D12

X

R/W

0

D11-D8 MAP_CH12_TO_OUT2B[3:0]

OUT2B pin to channel mapping

These bits select the OUT2B pin pair to channel data mapping.

D7-D4

D3-D0

MAP_CH12_TO_OUT2A[3:0]

X

R/W

0

OUT2A pin to channel mapping

These bits select the OUT2A pin pair to channel data mapping.

Don't care bits

(1) This bit must be set to 1 to enable bits D[7:0].

7.6.1.27 Register 53h (offset = 53h) [reset = 0]

This is a programmable LVDS mapping mode register. All bits default to 0 after reset.

图 76. Register 53h

D15

ENABLE 53

R/W-0

D14

D6

D13

X

D12

D4

D11

D3

D10

D9

D8

D0

MAP_CH34_TO_OUT3B[3:0]

R/W-0

D7

D5

D2

D1

X

R/W-0

表 33. Register 53h Field Descriptions

Bit

Field

ENABLE 53

Type

Reset

Description

Enable register 53h⁽¹⁾

This bit enables register 53h.

Don't care bits

D15

R/W

0

D14-D12

X

R/W

0

D11-D8 MAP_CH34_TO_OUT3B[3:0]

OUT3B pin to channel mapping

These bits select the OUT3B pin pair to channel data mapping.

Don't care bits

D7-D0

X

R/W

0

(1) This bit must be set to 1 to enable bits D[7:0].

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7.6.1.28 Register 54h (offset = ) [reset = 0]

This is a programmable LVDS mapping mode register. All bits default to 0 after reset.

图 77. Register 54h

D15

ENABLE 54

R/W-0

D14

D6

D13

D5

D12

D4

D11

X

D10

D2

D9

D1

D8

D0

R/W-0

D7

D3

X

MAP_Ch34_to_OUT3A[3:0]

R/W-0

表 34. Register 54h Field Descriptions

Bit

Field

ENABLE 54

Type

Reset

Description

Enable register 54h⁽¹⁾

This bit enables register 54h.

Don't care bits

D15

R/W

0

D14-D4

D3-D0

X

R/W

0

MAP_Ch34_to_OUT3A[3:0]

OUT3A pin to channel mapping

These bits select the OUT3A pin pair to channel data mapping.

(1) This bit must be set to 1 to enable bits D[7:0].

7.6.1.29 Register 55h (offset = 55h) [reset = 0]

This is a programmable LVDS mapping mode register. All bits default to 0 after reset.

图 78. Register 55h

D15

ENABLE 55

R/W-0

D14

D13

D12

D4

D11

X

D10

D9

D1

D8

D0

R/W-0

D7

D6

D5

D3

D2

MAP_CH34_TO_OUT4A[3:0]

R/W-0

MAP_CH34_TO_OUT4B[3:0]

R/W-0

表 35. Register 55h Field Descriptions

Bit

Field

Type

Reset

Description

Enable register 55h⁽¹⁾

This bit enables register 55h.

Don't care bits

D15

ENABLE 55

R/W

0

D14-D8

D7-D4

X

R/W

0

MAP_CH34_TO_OUT4A[3:0]

OUT4A pin to channel mapping

These bits select the OUT4A pin pair to channel data mapping.

D3-D0

MAP_CH34_TO_OUT4B[3:0]

R/W

0

OUT4B pin to channel mapping

These bits select the OUT4B pin pair to channel data mapping.

(1) This bit must be set to 1 to enable bits D[7:0].

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7.6.1.30 Register F0h (offset = F0h) [reset = 0]

This is a general register.

注

The EN_HIGH_ADDRS bit (register 01h, bit D4) must be set to 1 in order to access this

register.

图 79. Register F0h

D15

EN_EXT_REF

R/W-0

D14

D6

D13

D5

D12

D11

X

D10

D2

D9

D1

D8

D0

R/W-0

D7

D4

D3

X

R/W-0

表 36. Register F0h Field Descriptions

Bit

Field

EN_EXT_REF

Type

Reset

Description

D15

R/W

0

Reference mode selection

0 = Internal reference mode enabled (default)

External reference mode enabled. The voltage

1

=

reference can be applied on either the REFP and REFB

pins or the VCM pin.

D7-D0

X

R/W

0

Don't care bits

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The VSP5324-Q1 device is a low power 12-bit, 4-channel ADC customized for time-of-flight applications. The

device accepts four single-ended or differential analog inputs and can be configured to output the digitized data

on 4 or 8 LVDS lanes as per the requirements of the external host receiver. The sampling clock can be fed to the

device using a single-ended or a differential signal. High-speed sampling rates of up to 80 MSPS can be used to

speed up the sensor readout and therefore use longer sensor exposure times without taking a hit on the frame-

rate. The device is controlled using a simple 4-wire SPI. Power constrained systems can additionally make use of

the power-down pin (PD) to take the device quickly in and out of low-power mode. The device uses an internal

reference and internal common-mode voltage by default and has a provision for the use of external reference

and external common-mode voltage inputs.

8.2 Typical Application

18-V

AVDD LVDD

VSP5324-Q1

SPI Control

Register

control

Time of Flight

Sensor

Analog Inputs

4-Channel

12-bit ADC

Bit Clock

Frame Clock

LVDS Data

Host

Serializer

Common Mode Voltage (optional)

Reference (optional)

Power

Down

Sampling

Clock

图 80. Application Schematic

8.2.1 Design Requirements

For optimum performance, the analog inputs must be driven differentially. If the inputs are driven in a single-

ended manner, capacitors must be placed on the INx_M signals and close to the INx_M pins. An optional 5-Ω to

15-Ω resistor in series with each input pin can be kept to damp out ringing caused by package parasitics. The

drive circuit may have to be designed to minimize the impact of kick-back noise generated by sampling switches

opening and closing inside the ADC, as well as ensuring low insertion loss over the desired frequency range and

matched impedance to the source.

8.2.2 Detailed Design Procedure

8.2.2.1 Drive Circuit Requirements

For optimum performance, the analog inputs must be driven differentially, as shown in 图 81. This architecture

improves the common-mode noise immunity and even-order harmonic rejection. A 5-Ω to 15-Ω resistor in series

with each input pin is recommended to damp out ringing caused by package parasitic. The drive circuit shows an

R-C filter across the analog input pins. The purpose of the filter is to absorb glitches caused by the sampling

capacitors opening and closing.

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Typical Application (接下页)

0.1 mF

10 W

INx_P

Differential

Input

2 pF

Device

INx_M

10 W

0.1 mF

图 81. Analog Input Drive Circuit

8.2.2.2 Clock Input

The VSP5324-Q1 device can function with either single-ended or differential clock inputs. The device can

automatically detect if a single-ended or differential clock is applied. To operate with a single-ended input clock,

CLKP must be driven by a CMOS clock with CLKM tied to GND. 图 82 and 图 83 show the typical single-ended

and differential clock termination schemes (respectively).

CMOS

Clock Input

CLKP

Device

CLKM

图 82. Single-Ended Clock Driving Circuit

0.1 mF

CLKP

R_(TERM)

Device

R_(TERM)

Device

0.1 mF

CLKM

R_(TERM)

a) Differential Sine-Wave Clock Input

b) Differential LVPECL Clock Input

c) Differential LVDS Clock Input

图 83. Differential Clock Driving Circuit

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Typical Application (接下页)

8.2.3 Application Curves

73

72

71

70

69

68

95

90

85

80

75

70

69.9

69.8

69.7

69.6

69.5

69.4

SNR

SFDR

0.8

0.85

0.9

0.95

1

1.05

1.1

-40 -27.5 -15 -2.5 10 22.5 35 47.5 60 72.5 85

Analog Input Common-Mode Voltage (V)

Temperature (èC)

D014

D020

ƒ_IN= 5 MHz

A 0.7-V_PP5-MHz sine-wave input is applied on the INx_P pin

The INx_M pin is connected to the device VCM pin

图 84. Performance vs Input Common-Mode

图 85. SNR vs Temperature For Single-Ended Input

9 Power Supply Recommendations

Using an LDO supply with minimal noise on the AVDD supply is recommended. The LVDD supply can be

connected to an LDO or a DC-DC converter. A capacitor with a value of 100 nF per supply pin is recommended

in addition to a 1-µF common decoupling capacitor per rail.

10 Layout

10.1 Layout Guidelines

10.1.1 General Guidelines

The following list includes general layout guidelines. Refer to 图 86 as needed.

•

Route the clock input as a differential pair when a differential clock input is used.

When single ended inputs are used, place 100-nF capacitors close to the pins on the INx_M inputs to ensure

that the reference rail is stable. When differential inputs are used, the inputs must be routed as differential

pairs.

•

Route the LVDS clock and data output pairs with 100-Ω differential impedance and length matched as per the

sampling frequency.

10.1.2 Grounding

A single ground plane is sufficient to provide good performance, provided that the analog, digital, and clock

sections of the board are cleanly partitioned.

10.1.3 Supply Decoupling

Minimal external decoupling can be used without loss in performance because the VSP5324-Q1 device already

includes internal decoupling. Note that decoupling capacitors can help filter external power-supply noise, thus the

optimum number of capacitors depends on the actual application. The decoupling capacitors should be placed

very close to the converter supply pins.

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Layout Guidelines (接下页)

10.1.4 Exposed Pad

In addition to providing a path for heat dissipation, the pad is also electrically connected to the digital ground

internally. Therefore, soldering the exposed pad to the ground plane is necessary to achieve the best thermal

and electrical performance. For detailed information, see application notes QFN Layout Guidelines and

QFN/SON PCB Attachment.

10.2 Layout Example

Analog input pins

Clock inputs

LVDS clock and data output pairs

Pin 1

The layout in this example uses four single-ended inputs and four LVDS-data outputs. The components that require

special layout attention are shown and are listed in the General Guidelines section. For the two-lane output option,

eight LVDS data pairs are used.

图 86. VSP5324-Q1 Layout Example

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11 器件和文档支持

11.1 器件支持

11.1.1 器件命名规则

模拟带宽

孔径延迟

基频功率相对低频值下降 3dB 时的模拟输入频率。

输入采样时钟上升沿与发生采样的实际时间之间的延迟时间。该延迟在各通道中会有所不同。最大差

值被定义为孔径延迟差异（通道间）。

孔径不确定性（抖动）采样之间孔径延迟时间的变化。

时钟脉宽和占空比时钟占信号空比是时钟信号保持逻辑高电平的时间（时钟脉宽）与一个时钟信号周期的比率。

占空比通常以百分比的形式表示。理想差分正弦波时钟的占空比为 50%。

最大转换速率行指定操作时所采用的最大采样率。除非另有说明，所有参数测试均以该采样率执行。

最小转换速率 ADC 正常工作时的最小采样率。

微分非线性 (DNL) 理想 ADC 对模拟输入值进行编码转换时以 1 LSB 为步长。DNL 是指任意单个步长与这一理想

值之间的偏差（以 LSB 为计量单位）。

积分非线性 (INL) INL 是 ADC 传递函数与其最小二乘法曲线拟合所确定的最佳拟合曲线的偏差（以 LSB 为计量单

位）。

增益误差

增益误差是指 ADC 实际输入满量程范围与其理想值的偏差。增益误差以理想输入满量程范围的百分

比形式表示，由两部分组成：基准不精确导致的误差和通道导致的误差。两种误差均以独立形式标

注，分别为 E_G(REF)和 E_G(CHAN)。对于一阶近似值，总增益误差为 (E_tot~ E_G(REF)+ E_G(CHAN))。例如，

如果 E_tot= ±0.5%，则满量程输入范围为 [(1 – 0.5 / 100) × ƒ_S(ideal)] 至 [(1 + 0.5 / 100) × ƒ_S(ideal)]。

偏移误差

温度漂移

偏移误差是指 ADC 实际平均空闲通道输出编码与理想平均空闲通道输出编码之间的差值（以 LSB 数

表示）。该数量通常转换为毫伏。

温度漂移系数（相对于增益误差和偏移误差）指定了参数从 T_MIN到 T_MAX每摄氏度的变化量。此系数

由参数在 T_MIN至 T_MAX范围内的最大变化量除以 T_MAX– T_MIN的差值计算得出。

信噪比 (SNR) SNR 是指基频功率 (P_S) 与噪底功率 (P_N) 的比值，后者不包括直流功率和前 9 个谐波的功率。当基

频的绝对功率用作基准时，SNR 以 dBc（相对于载波的分贝数）为单位；当基频功率被外推至转换

器满量程范围时，SNR 以 dBFS（相对于满量程的分贝数）为单位。

P_S

SNR = 10 Log¹⁰

P_N

(3)

信噪比和失真 (SINAD) SINAD 是指基频功率 (P_S) 与所有其他频谱成分（包括噪声 (P_N) 和失真 (P_(HD))，但不包括

直流）功率的比值。当基频的绝对功率用作基准时，SINAD 以 dBc（相对于载波的分贝数）为单位；

当基频功率被外推至转换器满量程范围时，SINAD 以 dBFS（相对于满量程的分贝数）为单位。

P_S

SINAD = 10 Log¹⁰

P_N+ P_(HD)

(4)

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器件支持 (接下页)

有效位数 (ENOB) ENOB 测量的是转换器相对于理论限值（基于量化噪声）的性能。

SINAD - 1.76

ENOB =

6.02

(5)

总谐波失真 (THD) THD 是指基频功率 (P_S) 与前 9 个谐波的功率 (P_(HD)) 的比值。THD 通常以 dBc 为单位（相对

于载波的分贝数）。

P_S

THD = 10 Log¹⁰

P_N

(6)

无杂散动态范围 (SFDR) 基频功率与最高的其他频谱成分（毛刺或谐波）功率的比值。SFDR 通常以 dBc 为单位

（相对于载波的分贝数）。

双频互调失真 (IMD3) IMD3 是基频（ƒ1 和 ƒ2 频率处）功率与最差频谱成分（2 ƒ1 – ƒ2 或 2 ƒ2 – ƒ1 频率处）功

率的比值。当基频的绝对功率用作基准时，IMD3 以 dBc（相对于载波的分贝数）为单位；当基频功

率被外推至转换器满量程范围时，IMD3 以 dBFS（相对于满量程的分贝数）为单位。

直流电源抑制比 (DC PSRR) DC PSSR 是偏移误差变化量与模拟电源电压变化量的比值。DC PSRR 通常以 mV/V

为单位进行表示。

交流电源抑制比 (AC PSRR) AC PSRR 测量的是 ADC 对电源电压变化的抑制能力。如果 ΔV_(AVDD)表示电源电压

的变化，ΔV_O表示 ADC 输出代码的相应变化（以输入为基准），则：

DV_O

PSRR = 20 Log¹⁰

(Expressed in dBc)

DV_(AVDD)

(7)

电压过载恢复使过载的模拟输入端的误差恢复至 1% 以下所需的时钟周期数。该技术参数的测试方法是分别施加

具有 6dB 正过载和负过载的正弦波信号。然后记录下过载后前几个采样（相对于期望值）的偏差。

共模抑制比 (CMRR) CMRR 测量的是 ADC 对模拟输入共模变化的抑制能力。如果 ΔV_IC为输入引脚的共模电压变

化值，ΔV_O为 ADC 输出代码的相应变化（以输入为基准），则：

DV_O

CMRR = 20 Log¹⁰

(Expressed in dBc)

DV_IC

(8)

串扰（仅限于多通道 ADC）串扰测量的是目标通道与其相邻通道之间的内部信号耦合。串扰分两种情况：一种是

与紧邻通道（近端通道）之间的耦合，另一种是与跨封装通道（远端通道）之间的耦合。通常采用对

邻近通道施加满量程信号的方式来测量串扰。串扰是指耦合信号功率（在目标通道的输出端测得）与

邻近通道输入端所施加信号功率的比值。串扰通常以 dBc 为单位进行表示。

11.2 文档支持

11.2.1 相关文档

请参阅如下相关文档：

•

《QFN 布局指南》

《QFN/SON PCB 连接》

11.3 接收文档更新通知

如需接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.4 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

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11.5 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.6 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修

订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。

57

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Feb-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

VSP5324TRGCRQ1

VQFN

RGC

64

2000

330.0

16.4

9.3

1.5

12.0

16.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

12-Feb-2019

*All dimensions are nominal

Device

Package Type Package Drawing Pins

VQFN RGC 64

SPQ

Length (mm) Width (mm) Height (mm)

350.0 350.0 43.0

VSP5324TRGCRQ1

2000

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RGC 64

9 x 9, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224597/A

www.ti.com

PACKAGE OUTLINE

VQFN - 1 mm max height

RGC0064A

PLASTIC QUADFLAT PACK- NO LEAD

9.15

8.85

A

B

9.15

8.85

PIN 1 INDEX AREA

(0.2)TYP

(0.1)TYP

DETAIL 'A'

OPTION1

OPTION2

1 MAX

C

SEATING PLANE

0.08 C

0.05

0.00

2X

7.5

EXPOSED

7.25±0.1

THERMAL PAD

32

17

16

33

SEE DETAIL 'A'

60X

0.5

SYMM

65

2X

7.5

0.3

0.18

64X

0.1

C A B

C

48

1

0.05

PIN1 ID

64

49

(OPTIONAL)

SYMM

0.5

0.3

64X

4219009/A 10/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

VQFN - 1 mm max height

RGC0064A

PLASTIC QUADFLAT PACK- NO LEAD

2X(8.8)

2X(7.5)

SEE SOLDER MASK

DETAIL

64X(0.6)

(

7.25)

64

49

1

48

64X(0.24)

60X(0.5)

65

SYMM

2X

2X(7.5)

(8.8)

4X

(1.14)

2X

(1.1)

(0.05)

(TYP)

33

16

45X (Ø0.2)

(TYP) VIA

4X

(1.14)

SYMM

32

17

2X

(1.1)

LAND PATTERN EXAMPLE

SCALE: 10X

SOLDER MASK

OPENING

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

EXPOSED METAL

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4219009/A 10/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

VQFN - 1 mm max height

RGC0064A

PLASTIC QUADFLAT PACK- NO LEAD

2X (8.8)

2X(7.5)

SYMM

36X

(0.94)

64x(0.6)

64

49

1

48

65

64X(0.24)

60X(0.5)

2X(0.57)

2X(8.8)

SYMM

2X(7.5)

4X(1.14)

(R0.05)

TYP

33

16

EXPOSED METAL

17

32

4X(1.14)

2X(0.57)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

60% PRINTED COVERAGE BY AREA

SCALE: 12X

4219009/A 10/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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型号：	VSP5324-Q1
厂家：	TEXAS INSTRUMENTS
描述：	汽车类 4 通道 12 位 80MSPS 模数转换器 (ADC) 转换器模数转换器
文件：	总65页 (文件大小：3110K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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