XISOW7740DFMR [TI]
ISOW774x Quad-Channel Digital Isolator with Integrated Low-Emissions, Low-Noise DC-DC Converter;
| 型号： | XISOW7740DFMR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ISOW774x Quad-Channel Digital Isolator with Integrated Low-Emissions, Low-Noise DC-DC Converter |
| 文件： | 总62页 (文件大小：4699K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISOW7740, ISOW7741, ISOW7742, ISOW7743, ISOW7744
SLLSFK1B – SEPTEMBER 2021 – REVISED JANUARY 2022
ISOW774x Quad-Channel Digital Isolator with Integrated Low-Emissions, Low-Noise
DC-DC Converter
1 Features
2 Applications
•
•
100 Mbps data rate
Integrated DC-DC converter with low-emissions,
low-noise
•
•
•
•
•
Factory automation
Motor control
Grid infrastructure
Medical equipment
Test and measurement
– Emission optimized to meet CISPR 32 and EN
55032 Class B with >5 dB margin on 2 layer
board
– Low frequency power converter at 25 MHz
enabling low noise performance
– Low output ripple: 24 mV
High efficiency output power
– Efficiency at max load: 46%
– Up to 0.55-W output power
– VISOOUT accuracy of 5%
– 5 V to 5 V: Max available load current = 110 mA
– 5 V to 3.3 V: Max available load current = 140
mA
– 3.3 V to 3.3 V: Max available load current = 60
mA
3 Description
The ISOW77xx family of devices are galvanically-
isolated quad-channel digital isolator with an
integrated high-efficiency power converter with low
emissions. The integrated DC-DC converter provides
up to 550 mW of isolated power, eliminating the
need for a separate isolated power supply in space-
constrained isolated designs.
•
Device Information
ISOW774x
ISOW774xB
FEATURE
ISOW774xF
ISOW774xFB
Protection Level
Surge Test Voltage
Isolation Rating
Reinforced
10 kVPK
Basic
•
•
Independent power supply for channel isolator &
power converter
7.8 kVPK
5000 VRMS
5000 VRMS
– Logic supply (VIO): 1.71-V to 5.5-V
– Power converter supply (VDD): 3-V to 5.5-V
Robust electromagnetic compatibility (EMC)
– System-level ESD, EFT, and surge immunity
– ±8 kV IEC 61000-4-2 contact discharge
protection across isolation barrier
1000 VRMS
1500VPK
/
1000 VRMS
1500VPK
/
Working Voltage
Package
DFM (20)
DFM (20)
12.83 mm × 7.5
mm
12.83 mm × 7.5
mm
Body Size (Nom)
•
•
•
Reinforced and Basic isolation options
High CMTI: 100-kV/µs (typical)
Safety Related Certifications (Planned):
VISOIN
VIO
EN_IO2
OUTA
– VDE reinforced and basic insulation per DIN
VDE V 0884-11:2017-01
– UL 1577 component recognition program
– IEC 62368-1, IEC 61010-1, IEC 60601-1 and
GB 4943.1-2011 certifications
Tx
Tx
INA
INB
Rx
Rx
Rx
Tx
OUTB
OUTC
IND
INC
Tx
Rx
OUTD
•
•
Extended temperature range: –40°C to +125°C
20-pin wide body SOIC package
EN_IO1
GNDIO
GISOIN
GND1
GN
D2
VSEL
VDD
DC-DC
Primary
DC-DC
Secondary
EN/FLT
GND1
VISOOUT
GND2
ISOW7741 Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ISOW7740, ISOW7741, ISOW7742, ISOW7743, ISOW7744
SLLSFK1B – SEPTEMBER 2021 – REVISED JANUARY 2022
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 8
7.1 Absolute Maximum Ratings........................................ 8
7.2 ESD Ratings............................................................... 8
7.3 Recommended Operating Conditions.........................9
7.4 Thermal Information..................................................10
7.5 Power Ratings...........................................................10
7.6 Insulation Specifications............................................11
7.7 Safety-Related Certifications.................................... 12
7.8 Safety Limiting Values...............................................12
7.9 Electrical Characteristics - Power Converter............ 13
7.10 Supply Current Characteristics - Power
Converter.....................................................................14
7.11 Electrical Characteristics Channel Isolator -
VIO, VISOIN = 5-V..........................................................15
7.12 Supply Current Characteristics Channel
Isolator - VIO, VISOIN = 5-V...........................................15
7.13 Electrical Characteristics Channel Isolator -
VIO, VISOIN = 3.3-V.......................................................18
7.14 Supply Current Characteristics Channel
7.18 Supply Current Characteristics Channel
Isolator - VIO, VISOIN = 1.8-V........................................24
7.19 Switching Characteristics - 5-V Supply...................27
7.20 Switching Characteristics - 3.3-V Supply................28
7.21 Switching Characteristics - 2.5-V Supply................29
7.22 Switching Characteristics - 1.8-V Supply................30
7.23 Insulation Characteristics Curves........................... 31
7.24 Typical Characteristics............................................32
8 Parameter Measurement Information..........................37
9 Detailed Description......................................................39
9.1 Overview...................................................................39
9.2 Functional Block Diagram.........................................40
9.3 Feature Description...................................................41
9.4 Device Functional Modes..........................................44
10 Application and Implementation................................46
10.1 Application Information........................................... 46
10.2 Typical Application.................................................. 46
11 Power Supply Recommendations..............................50
12 Layout...........................................................................51
12.1 Layout Guidelines................................................... 51
12.2 Layout Example...................................................... 52
13 Device and Documentation Support..........................53
13.1 Device Support....................................................... 53
13.2 Documentation Support.......................................... 53
13.3 Receiving Notification of Documentation Updates..53
13.4 Support Resources................................................. 53
13.5 Trademarks.............................................................53
13.6 Electrostatic Discharge Caution..............................53
13.7 Glossary..................................................................53
14 Mechanical, Packaging, and Orderable
Isolator - VIO, VISOIN = 3.3-V........................................18
7.15 Electrical Characteristics Channel Isolator -
VIO, VISOIN = 2.5-V.......................................................21
7.16 Supply Current Characteristics Channel
Isolator - VIO, VISOIN = 2.5-V........................................21
7.17 Electrical Characteristics Channel Isolator -
Information.................................................................... 54
VIO, VISOIN = 1.8-V.......................................................24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (October 2021) to Revision B (January 2022)
Page
•
Added ISOW7740, ISOW7742, ISOW7743, and ISOW7744 to data sheet....................................................... 1
Changes from Revision * (September 2021) to Revision A (October 2021)
Page
•
Updated device status to Production Data......................................................................................................... 1
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SLLSFK1B – SEPTEMBER 2021 – REVISED JANUARY 2022
5 Description (continued)
The high-efficiency of the power converter allows for operation at a wide operating ambient temperature range
of –40°C to +125°C. This device provides improved emissions performance, allowing for simplified board design
and has provisions for ferrite beads to further attenuate emissions. The ISOW774x has been designed with
enhanced protection features in mind, including soft-start to limit inrush current, over-voltage and under-voltage
lock out, fault detection on the EN/FLT pin, overload and short-circuit protection, and thermal shutdown.
The ISOW77xx family of devices provide high electromagnetic immunity while isolating CMOS or LVCMOS
digital I/Os. The signal-isolation channel has a logic input and output buffer separated by a double capacitive
silicon dioxide (SiO2) insulation barrier, whereas, power isolation uses on-chip transformers separated by thin
film polymer as insulating material. There are five orderable configurations of four channel ISOW77xx flavor
using the last part number digit to note the number of reverse channels. For example, the ISOW7740 has 4
forward channels and 0 reverse channels, while the ISOW7743 would have 1 forward channel and 3 reverse
channels. If the input signal is lost, the default output is high for the ISOW77xx devices without the F suffix and
low for the ISOW77xx devices with the F suffix. The ISOW774x can operate from a single supply voltage of 3 V
to 5.5 V by connecting VIO and VDD together on PCB. If lower logic levels are required, these devices support
1.71 V to 5.5 V logic supply (VIO) that can be independent from the power converter supply (VDD) of 3 V to 5.5 V.
VISOIN and VISOOUT needs to be connected on board with either a ferrite bead or fed through a LDO.
These devices help prevent noise currents on data buses, such as UART, SPI, RS-485, RS-232, and CAN,
or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. Through
innovative chip design and layout techniques, electromagnetic compatibility of the device has been significantly
enhanced to ease system-level ESD, EFT, surge and emissions compliance. The device is available in a 20-pin
SOIC wide-body (SOIC-WB) DFM package.
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SLLSFK1B – SEPTEMBER 2021 – REVISED JANUARY 2022
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6 Pin Configuration and Functions
VIO
INA
INB
1
2
3
20
19
18
VISOIN
OUTA
OUTB
INC
IND
4
5
6
17
16
15
OUTC
OUTD
GNDIO
GISOIN
EN_IO1
7
14
EN_IO2
EN/FLT
VDD
8
13
12
11
VSEL
VISOOUT
GND2
9
GND1
10
Figure 6-1. ISOW7740 DFM Package 20-Pin SOIC-WB Top View
VIO
INA
INB
1
2
3
20
19
18
VISOIN
OUTA
OUTB
INC
4
5
6
17
16
15
OUTC
IND
OUTD
GNDIO
GISOIN
EN_IO1
7
14
EN_IO2
EN/FLT
VDD
8
13
12
11
VSEL
VISOOUT
GND2
9
GND1
10
Figure 6-2. ISOW7741 DFM Package 20-Pin SOIC-WB Top View
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SLLSFK1B – SEPTEMBER 2021 – REVISED JANUARY 2022
VIO
INA
INB
1
2
3
20
19
18
VISOIN
OUTA
OUTB
OUTC
OUTD
GNDIO
4
5
6
17
16
15
INC
IND
GISOIN
EN_IO1
7
14
EN_IO2
EN/FLT
VDD
8
13
12
11
VSEL
VISOOUT
GND2
9
GND1
10
Figure 6-3. ISOW7742 DFM Package 20-Pin SOIC-WB Top View
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VIO
INA
1
2
3
20
19
18
VISOIN
OUTA
INB
OUTB
OUTC
OUTD
GNDIO
4
5
6
17
16
15
INC
IND
GISOIN
EN_IO1
7
14
EN_IO2
EN/FLT
VDD
8
13
12
11
VSEL
VISOOUT
GND2
9
GND1
10
Figure 6-4. ISOW7743 DFM Package 20-Pin SOIC-WB Top View
VIO
1
2
3
20
19
18
VISOIN
INA
OUTA
OUTB
INB
OUTC
OUTD
GNDIO
4
5
6
17
16
15
INC
IND
GISOIN
EN_IO1
7
14
EN_IO2
EN/FLT
VDD
8
13
12
11
VSEL
VISOOUT
GND2
9
GND1
10
Figure 6-5. ISOW7744 DFM Package 20-Pin SOIC-WB Top View
PIN
NO.
I/O
DESCRIPTION
NAME
ISOW7740
ISOW7741
ISOW7742
ISOW7743
ISOW7744
Ground connection for VIO. GND1 and GNDIO needs to
be shorted on board.
GNDIO
GND1
6
6
6
6
6
—
—
Ground connection for VDD. GND1 and GNDIO needs to
be shorted on board.
10
11
10
11
10
10
11
10
11
Ground connection for VISOOUT. GND2 and GISOIN pins
can be shorted on board or connected through a ferrite
bead. See the Layout Section for more information.
GND2
11
—
Ground connection for VISOIN. GND2 and GISOIN pins
can be shorted on board or connected through a ferrite
bead. See the Layout Section for more information.
GISOIN
INA
15
2
15
2
15
2
15
2
15
19
—
I
Input channel A
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NAME
SLLSFK1B – SEPTEMBER 2021 – REVISED JANUARY 2022
PIN
NO.
I/O
DESCRIPTION
ISOW7740
ISOW7741
ISOW7742
ISOW7743
ISOW7744
INB
INC
3
4
3
3
18
18
I
I
Input channel B
Input channel C
4
17
17
17
IND
5
16
19
18
16
19
18
16
19
3
16
2
I
Input channel D
Output channel A
Output channel B
OUTA
OUTB
19
18
O
O
3
OUTC
OUTD
17
16
17
5
4
5
4
5
4
5
O
O
Output channel C
Output channel D
Output Enable 1: When EN_IO1 is high or open then the
channel output pins on side 1 are enabled. When EN_IO1
is low then the channel output pins on side 1 are in a high
impedance state and the transmitter of the channel input
pins on side 1 are disabled.
EN_IO1
EN_IO2
7
7
7
7
7
I
I
Output Enable 2: When EN_IO2 is high or open then the
channel output pins on side 2 are enabled. When EN_IO2
is low then the channel output pins on side 2 are in a high
impedance state and the transmitter of the channel input
pins on side 2 are disabled.
14
14
14
14
14
Multi-function power converter enable input pin or fault
output pin. Can only be used as either an input pin or an
output pin.
Power converter enable input pin: enables and disables
the integrated DC-DC power converter. Connect directly
to microcontroller or through a series current limiting
resistor to use as an enable input pin. DC-DC power
converted is enabled when EN/FLT is high to the VIO
voltage level and disabled when low at GND1 voltage
level.
EN/FLT
8
8
8
8
8
I/O
Fault output pin: Alert signal if power converter is not
operating properly. This pin is active low. Connect to
microcontroller through a 5 kΩ or greater pull-up resistor
in order to use as a fault outpin pin.
See Section 9.3.3 for more information
VISOOUT selection pin. VISOOUT = 5 V when VSEL shorted
to VISOOUT. VISOOUT = 3.3 V, when VSEL shorted to
GND2. For more information see the Device Functional
Modes.
VSEL
13
13
13
13
13
I
VIO
1
9
1
9
1
9
1
9
1
9
—
—
Side 1 logic supply.
VDD
Side 1 DC-DC converter power supply.
Side 2 supply voltage for isolation channels. VISOIN
and VISOOUT pins can be shorted on board or
connected through a ferrite bead. See Application and
Implementation for more information.
VISOIN
20
12
20
12
20
12
20
12
20
12
—
—
Isolated power converter output voltage. VISOIN
and VISOOUT pins can be shorted on board or
connected through a ferrite bead. See Application and
Implementation for more information.
VISOOUT
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
–0.5
–0.5
MAX
UNIT
V
VDD
Power converter supply voltage
6
6
VISOIN
Isolated supply voltage, input supply for secondary side isolation channels
V
Isolated supply voltage, Power converter output
VSEL shorted to GND2
VISOOUT
–0.5
–0.5
4
6
V
V
Isolated supply voltage, Power converter output
VSEL shorted to VISOOUT
VISOOUT
VIO
Primary side logic supply voltage
Voltage at INx, OUTx, EN_IOx(3)
Voltage at EN/FLT
–0.5
–0.5
–0.5
–0.5
–15
–40
–65
6
VSI + 0.5
VSI + 0.5
VISOOUT + 0.5
15
V
V
V
V
Voltage at VSEL
V
IO
Maximum output current through data channels
Junction temperature
mA
°C
°C
TJ
150
Tstg
Storage temperature
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) VDD, VISOIN VISOOUT, and VIO are with respect to the local ground pin (GND1 or GND2). All voltage values except differential I/O bus
voltages are peak voltage values.
(3) VSI = input side supply; Cannot exceed 6 V.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2
±3000
Electrostatic
discharge
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C6
V(ESD)
±1500
±8000
V
Contact discharge per IEC 61000-4-2(2)
Isolation barrier withstand test
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.
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SLLSFK1B – SEPTEMBER 2021 – REVISED JANUARY 2022
7.3 Recommended Operating Conditions
Over recommended operating conditions, typical values are at VDD = VIO = 3.3 V and TA =25°C, GND1 = GNDIO, GND2 =
GISOIN (unless otherwise noted)
MIN
NOM
MAX
UNIT
Power Converter
3.3 V operation
5 V operation
2.97
4.5
3.3
5
3.63
5.5
V
V
Power converter supply
voltage
VDD
Positive threshold when
power converter supply is
rising
Positive threshold when power
converter supply is rising
VDD(UVLO+)
2.7
2.95
V
Positive threshold when
power converter supply is
falling
Positive threshold when power
converter supply is falling
VDD(UVLO-)
2.40
0.15
2.55
V
V
Power converter supply
voltage hysteresis
Power converter supply voltage
hysteresis
VDD(HYS)
Channel Isolation
1.8 V operation
1.71
2.25
1.89
5.5
V
V
(3)
VIO, VISOIN
Channel logic supply voltage
2.5 V, 3.3 V, and 5 V operation
VIO(UVLO+)
VIO(UVLO-)
VIO(HYS)
Rising threshold of logic supply voltage
1.55
1.41
1.7
V
Falling threshold of logic supply voltage
Logic supply voltage hysteresis
1.0
75
–4
–2
–1
–1
V
mV
mA
mA
mA
mA
mA
mA
mA
mA
V
VISOIN = 5 V
VISOIN = 3.3 V
VISOIN = 2.5 V
VISOIN = 1.8 V
VISOIN = 5 V
IOH
High level output current(1)
Low level output current(1)
4
VISOIN = 3.3 V
VISOIN = 2.5 V
VISOIN = 1.8 V
2
IOL
1
1
VIH
VIL
DR
High-level input voltage(2)
Low-level input voltage
Data rate
0.7 × VSI
0
VSI
0.3 × VSI
100
V
Mbps
Channel isolator ready after
power up or EN/FLT high
tPWRUP
TA
VISOIN > VIO(UVLO+)
5
ms
°C
Ambient temperature
–40
125
(1) This current is for data output channel.
(2) VSI = input side supply; VSO = output side supply
(3) The channel outputs are in undetermined state when 1.89 V < VSI < 2.25 V and 1.05 V < VSI < 1.71 V
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UNIT
SLLSFK1B – SEPTEMBER 2021 – REVISED JANUARY 2022
7.4 Thermal Information
ISOW774x
DFM (SOIC)
20 PINS
68.5
THERMAL METRIC(1)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
24.6
53.7
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
17.1
ΨJB
50.9
RθJC(bot)
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Ratings
VDD = VIO = 5.5 V, IISO = 110 mA, TJ = 150°C, TA ≤ 80°C, CL = 15 pF, input a 50-MHz 50% duty-cycle square wave
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.48
0.74
0.74
UNIT
W
PD
Maximum power dissipation (both sides) VDD = 5.5 V, VIO = 5.5 V, VISOOUT
=
VISOIN, IISOOUT = 100 mA, TJ = 150°C,
TA ≤ 80°C, CL = 15 pF, input a 50-MHz
50% duty-cycle square wave
PD1
PD2
Maximum power dissipation (side-1)
Maximum power dissipation (side-2)
W
W
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7.6 Insulation Specifications
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
CLR
CPG
External clearance(1)
Shortest terminal-to-terminal distance through air
>8
>8
mm
mm
Shortest terminal-to-terminal distance across the
package surface
External creepage(1)
Minimum internal gap (internal clearance – capacitive
signal isolation)
> 17
DTI
CTI
Distance through the insulation
µm
V
Minimum internal gap (internal clearance –
transformer power isolation)
>120
Comparative tracking index
Material group
DIN EN 60112 (VDE 0303-11); IEC 60112
According to IEC 60664-1
> 600
I
Rated mains voltage ≤ 300 VRMS
I-IV
I-IV
I-III
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 600 VRMS
Rated mains voltage ≤ 1000 VRMS
DIN VDE V 0884-11:2017-01(2)
Maximum repetitive peak isolation
VIORM
AC voltage (bipolar)
1500
VPK
voltage
AC voltage; Time dependent dielectric breakdown
(TDDB) Test
1000
1500
7071
VRMS
VDC
VPK
VIOWM
Maximum working isolation voltage
DC voltage
VTEST = VIOTM; t = 60 s (qualification);
VTEST = 1.2 × VIOTM; t = 1 s (100% production)
VIOTM
VIOSM
VIOSM
Maximum transient isolation voltage
Maximum surge isolation voltage
ISOW774x(3)
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 10000 VPK(qualification)
6250
6000
VPK
VPK
Maximum surge isolation voltage
ISOW774xB(3)
Test method per IEC 62368-1, 1.2/50 µs waveform,
VTEST = 1.3 × VIOSM = 7800 VPK(qualification)
Method a, after input/output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM, tm = 10 s
≤ 5
≤ 5
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s; ISOW774x: Vpd(m) = 1.6 ×
VIORM, tm = 10 s, ISOW774xB: Vpd(m) = 1.2 × VIORM, tm
= 10 s
qpd
Apparent charge(4)
pC
Method b1, at routine test (100% production) and
preconditioning (type test),
Vini = 1.2 × VIOTM, tini = 1 s;
≤ 5
ISOW774x: Vpd(m) = 1.875 × VIORM, tm = 1
s, ISOW774xB: Vpd(m) = 1.5 × VIORM, tm = 1 s
CIO
RIO
Barrier capacitance, input to output(5)
Insulation resistance(5)
VIO = 0.4 × sin (2πft), f = 1 MHz
VIO = 500 V, TA = 25°C
~3.5
> 1012
> 1011
> 109
pF
Ω
VIO = 500 V, 100°C ≤ TA ≤ 125°C
VIO = 500 V, TS = 150°C
Pollution degree
Climatic category
2
40/125/21
UL 1577
VTEST = VISO(UL)= 5000 VRMS, t = 60 s (qualification),
VTEST = 1.2 × VISO(UL) = 6000 VRMS, t = 1 s (100%
production)
VISO(UL) Withstand isolation voltage
5000
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.
Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the
isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal
in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these
specifications.
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(2) ISOW77xx is suitable for safe electrical insulation and ISOW77xxB is suitable for basic electrical insulation only within the safety
ratings.. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device.
7.7 Safety-Related Certifications
VDE
CSA
UL
CQC
TUV
Recognized under
UL 1577 Component
Recognition Program
Certified according to
EN 61010-1:2010/A1:2019
and EN 62368-1:2014
Certified according to DIN Certified according to IEC
Certified according to
GB 4943.1-2011
VDE V 0884-11:2017-01
62368-1, and IEC 60601-1
CSA 62368-1-19 and IEC
62368-1:2018 Ed. 3 and EN
62368-1:2020. (pollution degree
2, material group I) 600
Reinforced insulation;
Maximum transient
isolation voltage, 7071
5000 VRMS Reinforced
insulation per EN 61010-
1:2010 up to working
VPK
;
VRMS (ISOW774x Reinforced),
Maximum repetitive peak 1000VRMS (ISOW774xB Basic)
Reinforced Insulation,
Altitude ≤ 5000 m,
Tropical Climate, 700
VRMS maximum working 62368-1:2014 up to
voltage;
voltage of 600 VRMS;
5000 VRMS Reinforced
insulation per EN
isolation voltage, 1500
VPK
maximum working voltage;
2 MOPP (Means of Patient
Protection) per CSA 60601-1:14
and IEC 60601-1 Ed. 3+A1,
250 VRMS maximum working
voltage. Temperature rating is
90°C for reinforced insulation
and 125°C for basic insulation;
see certificate for details.
Single protection, 5000
VRMS
;
Maximum surge
isolation voltage, 6250
working voltage of
600 VRMS (ISOW774x
Reinforced), 1000
V
PK for ISOW774x
(Reinforced), 6000
VPK for ISOW774xB
(Basic).
VRMS (ISOW774xB Basic)
Certificate #: Reinforced:
40040142.
Basic: Pending
Certificate #:
CQC21001297517
Master Contract#: 220991
File #: E181974
Client ID: 77311
7.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RθJA = 68.5°C/W, VI = 5.5 V, TJ = 150°C,
TA = 25°C
332
IS
Safety input, output, or supply current(1)
mA
RθJA = 68.5°C/W, VI = 3.6 V, TJ = 150°C,
TA = 25°C
507
PS
TS
Safety input, output, or total power(1)
Maximum safety temperature(1)
RθJA = 68.5°C/W, TJ = 150°C, TA = 25°C
1825
150
mW
°C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The
IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use the following equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
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7.9 Electrical Characteristics - Power Converter
VDD = 5 V ±10% or 3.3 V ±10% and VISOIN power externally, GND1 = GNDIO, GND2 = GISOIN (over recommended
operating conditions, unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 5 V, VISOOUT = 5 V, VSEL = VISOOUT
VISOOUT
VISOOUT
Isolated supply voltage
Isolated supply voltage
External IISOOUT = 0 to 55 mA
External IISOOUT = 0 to 110 mA
4.75
4.5
5
5
5.25
5.25
V
V
VISOOUT(LINE
DC line regulation
DC load regulation
IISOOUT = 55 mA, VDD = 4.5 V to 5.5 V
IISOOUT = 0 to 110 mA
2
mV/V
)
VISOOUT(LOA
1%
D)
IISOOUT = 110 mA, CLOAD = 0.01 µF || 10 µF;
VI = VDD (ISOW774x); VI =0 V (ISOW774x
with F suffix).
Efficiency at maximum load
current (1)
EFF
46%
Output ripple on isolated supply 20-MHz bandwidth, CLOAD = 0.01 µF || 20 µF,
VISOOUT(RIP)
24
mV
mA
(pk-pk)
IISOOUT = 110 mA
DC current from VDD supply
under short circuit on VISOOUT
IISOOUT_SC
VISOOUT shorted to GND2
250
VDD = 5 V, VISOOUT = 3.3 V, VSEL = GND2
VISOOUT
VISOOUT
Isolated supply voltage
Isolated supply voltage
External IISOOUT = 0 to 70 mA
External IISOOUT = 0 to 140 mA
3.135
3.135
3.3
3.3
3.465
3.465
V
V
VISOOUT(LINE
DC line regulation
DC load regulation
IISOOUT = 70 mA, VDD = 4.5 V to 5.5 V
IISOOUT = 0 to 140 mA
2
mV/V
)
VISOOUT(LOA
1%
D)
IISOOUT = 140 mA, CLOAD = 0.01 µF || 10 µF;
VI = VDD (ISOW774x); VI =0 V (ISOW774x
with F suffix).
Efficiency at maximum load
current (1)
EFF
36%
Output ripple on isolated supply 20-MHz bandwidth , CLOAD = 0.01 µF || 20 µF,
VISOOUT(RIP)
30
mV
mA
(pk-pk)
IISOOUT = 110 mA
DC current from VDD supply
under short circuit on VISOOUT
IISOOUT_SC
VISOOUT shorted to GND2
250
VDD = 3.3 V, VISOOUT = 3.3 V, VSEL = GND2
VISOOUT
VISOOUT
Isolated supply voltage
Isolated supply voltage
External IISOOUT = 0 to 30 mA
External IISOOUT = 0 to 60 mA
3.135
3.135
3.3
3.3
3.465
3.465
V
V
VISOOUT(LINE
DC line regulation
DC load regulation
IISOOUT = 30 mA, VDD = 3.0 V to 3.6 V
IISOOUT = 0 to 60 mA
2
mV/V
)
VISOOUT(LOA
1%
D)
IISOOUT = 60 mA, CLOAD = 0.01 µF || 10 µF;
VI = VDD (ISOW774x); VI =0 V (ISOW774x
with F suffix).
Efficiency at maximum load
current (1)
EFF
43%
Output ripple on isolated supply 20-MHz bandwidth, CLOAD = 0.01 µF || 20 µF,
VISOOUT(RIP)
14
mV
mA
(pk-pk)
IISOOUT = 60 mA
DC current from VDD supply
under short circuit on VISOOUT
IISOOUT_SC
VISOOUT shorted to GND2
185
(1) Power converter ILOAD = current required to power the secondary side. ILOAD does not take into account the channel isolator current.
See Supply Current Characteristics Channel Isolator section for details.
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7.10 Supply Current Characteristics - Power Converter
VDD = 5 V ±10% or 3.3 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions unless otherwise
noted).
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Power Converter Disabled
Power converter supply
current
EN/FLT = GND1, VISOOUT = No ILOAD
EN/FLT = GND1
IDD
0.28
0.27
0.45
0.57
mA
mA
Logic supply current
IIO
Power Converter Enabled
VDD = 5 V, VSEL = VISOOUT
VDD = 5 V, VSEL = VISOOUT
VDD = 5 V, VSEL = GND2
VDD = 5 V, VSEL = GND2
VDD = 3.3 V, VSEL = GND2
VDD = 3.3 V, VSEL = GND2
VDD = 5 V
ILOAD = 55 mA
ILOAD = 110 mA
ILOAD = 70 mA
ILOAD = 140 mA
ILOAD = 30 mA
ILOAD = 60 mA
VSEL = VISOOUT
VSEL = GND2
VSEL = GND2
115
225
127
250
74
171
316
169
310
112
216
mA
mA
mA
mA
mA
mA
mA
mA
mA
Power converter supply
current input
IDD
143
110
140
60
Power converter output
current (1)
VDD = 5 V
IISOOUT
VDD = 3.3 V
(1) ILOAD does not take into account the channel isolator current. See Supply Current Characteristics Channel Isolator section for details.
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7.11 Electrical Characteristics Channel Isolator - VIO, VISOIN = 5-V
VIO, VISOIN = 5 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
PARAMETER
Channel Isolation
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VITH
VITL
Input pin rising threshold
Input pin falling threshold
0.7 x VSI
V
V
0.3 x VSI
0.1 x VSI
–25
Input pin threshold hysteresis
(INx)
VI(HYS)
V
IIL
Low level input current
High level input current
VIL = 0 at INx
µA
µA
IIH
VIH = VSI (1) at INx
25
(1)
IO = –4 mA, see Switching Characteristics
Test Circuit and Voltage Waveforms
VSO
–
VOH
VOL
High level output voltage
Low level output voltage
V
V
0.4
IO = 4 mA, see Switching Characteristics Test
Circuit and Voltage Waveforms
0.4
Common mode transient
immunity
VI = VSI or 0 V, VCM = 1000 V; see Common-
Mode Transient Immunity Test Circuit
CMTI
85
100
kV/us
(1) VSI = input side supply; VSO = output side supply
7.12 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 5-V
VIO, VISOIN = 5 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ISOW7740 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7740);
VI = 0 V (ISOW7740 with F suffix)
IDD_IO
2.5
4.6
2.5
4.6
2.5
4.6
6.9
4.8
4.7
4.8
4.9
7.3
6.5
31
3.6
6.9
3.6
6.9
3.6
6.9
9.2
7.2
6.4
7
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
Supply current - Disable
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7740);
VI = VCCI (ISOW7740 with F suffix)
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7740);
VI = 0 V (ISOW7740 with F suffix)
Channel Supply current -
DC signal
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7740);
VI = VCCI (ISOW7740 with F suffix)
1 Mbps
6.7
9.7
8.4
35
Channel Supply current -
AC signal
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
100 Mbps
ISOW7741 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7741);
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
2.8
4.3
2.8
4.3
2.8
4.3
6.1
5.5
4.1
6.3
4.1
6.3
4.1
6.3
8.4
7.9
mA
mA
mA
mA
mA
mA
mA
mA
VI = 0 V (ISOW7741 with F suffix)
Supply current - Disable
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7741);
VI = VCCI (ISOW7741 with F suffix)
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7741);
VI = 0 V (ISOW7741 with F suffix)
Channel Supply current -
DC signal
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7741);
VI = VCCI (ISOW7741 with F suffix)
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VIO, VISOIN = 5 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
IDD_IO
4.4
4.9
5
6.3
7.1
7
mA
mA
mA
mA
mA
mA
1 Mbps
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
Channel Supply current -
AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
6.3
12.2
25
8.9
14.2
32
ISOW7742 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7742);
VI = 0 V (ISOW7742 with F suffix)
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
3.1
3.9
4.7
5.6
4.7
5.6
4.7
5.6
7.7
8.5
6.3
7.2
7.6
8.3
20
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Supply current - Disable
3.1
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7742);
VI = VCCI (ISOW7742 with F suffix)
3.9
3.1
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7742);
VI = 0 V (ISOW7742 with F suffix)
3.9
Channel Supply current -
DC signal
5.4
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7742);
VI = VCCI (ISOW7742 with F suffix)
6.2
4.2
1 Mbps
5.1
5.5
Channel Supply current -
AC signal
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
6.3
16.7
17.33
100 Mbps
22
ISOW7743 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7743);
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
3.5
3.6
3.5
3.6
3.5
3.6
4.7
7
5.2
5.1
5.2
5.1
5.2
5.1
6.9
9.4
6.2
7.2
8.2
8
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
VI = 0 V (ISOW7743 with F suffix)
Supply current - Disable
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7743);
VI = VCCI (ISOW7743 with F suffix)
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7743);
VI = 0 V (ISOW7743 with F suffix)
Channel Supply current -
DC signal
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7743);
VI = VCCI (ISOW7743 with F suffix)
4
1 Mbps
5.3
6
Channel Supply current -
AC signal
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
6.2
24
14
27
100 Mbps
17
ISOW7744 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7744);
IDD_IO
IISOIN
IDD_IO
IISOIN
3.8
3.3
3.8
3.3
5.8
4.6
5.8
4.6
mA
mA
mA
mA
VI = 0 V (ISOW7744 with F suffix)
Supply current - Disable
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7744);
VI = VCCI (ISOW7744 with F suffix)
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VIO, VISOIN = 5 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
IDD_IO
3.8
3.3
4
5.8
4.6
6.2
10.2
6.1
7.3
8.6
7.3
34
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7744);
VI = 0 V (ISOW7744 with F suffix)
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
Channel Supply current -
DC signal
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7744);
VI = VCCI (ISOW7744 with F suffix)
7.7
3.8
5.5
6.4
5.6
30
1 Mbps
Channel Supply current -
AC signal
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
100 Mbps
7.4
9
(1) VCCI = VIO or VISOIN
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7.13 Electrical Characteristics Channel Isolator - VIO, VISOIN = 3.3-V
VIO, VISOIN = 3.3 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
PARAMETER
Channel Isolation
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VITH
VITL
Input pin rising threshold
Input pin falling threshold
0.7 x VSI
V
V
0.3 x VSI
0.1 x VSI
-25
Input pin threshold hysteresis
(INx)
VI(HYS)
V
IIL
Low level input current
High level input current
VIL = 0 at INx
µA
µA
IIH
VIH = VSI (1) at INx
25
(1)
IO = –2 mA, see Switching Characteristics
Test Circuit and Voltage Waveforms
VSO
–
VOH
VOL
High level output voltage
Low level output voltage
V
V
0.3
IO = 2 mA, see Switching Characteristics Test
Circuit and Voltage Waveforms
0.3
Common mode transient
immunity
VI = VSI or 0 V, VCM = 1000 V; see Common-
Mode Transient Immunity Test Circuit
CMTI
85
100
kV/us
(1) VSI = input side supply; VSO = output side supply
7.14 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 3.3-V
VIO, VISOIN = 3.3 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ISOW7740 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7740);
VI = 0 V (ISOW7740 with F suffix)
IDD_IO
2.4
4.6
2.4
4.5
2.4
4.5
6.8
4.8
4.6
4.7
4.7
6
3.5
6.9
3.5
6.9
3.5
6.9
9.1
7.2
6.4
7
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
Supply current - Disable
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7740);
VI = VCCI (ISOW7740 with F suffix)
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7740);
VI = 0 V (ISOW7740 with F suffix)
Channel Supply current -
DC signal
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7740);
VI = VCCI (ISOW7740 with F suffix)
1 Mbps
6.4
8.6
7.8
30
Channel Supply current -
AC signal
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
5.5
22
100 Mbps
ISOW7741 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7741);
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
2.8
4.2
2.8
4.2
2.8
4.2
6.1
5.5
4
6.3
4
mA
mA
mA
mA
mA
mA
mA
mA
VI = 0 V (ISOW7741 with F suffix)
Supply current - Disable
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7741);
VI = VCCI (ISOW7741 with F suffix)
6.3
4
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7741);
VI = 0 V (ISOW7741 with F suffix)
6.3
8.3
7.9
Channel Supply current -
DC signal
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7741);
VI = VCCI (ISOW7741 with F suffix)
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SLLSFK1B – SEPTEMBER 2021 – REVISED JANUARY 2022
VIO, VISOIN = 3.3 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
IDD_IO
4.4
4.9
6.3
7.1
6.7
8.3
12
mA
mA
mA
mA
mA
mA
1 Mbps
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
4.8
Channel Supply current -
AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
5.9
9.4
17.5
25
ISOW7742 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7742);
VI = 0 V (ISOW7742 with F suffix)
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
3.1
3.9
3.1
3.9
3.1
3.9
5.4
6.2
4.2
5.1
4.9
5.7
13
4.6
5.5
4.6
5.5
4.6
5.5
7.6
8.5
6.3
7.2
7
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Supply current - Disable
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7742);
VI = VCCI (ISOW7742 with F suffix)
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7742);
VI = 0 V (ISOW7742 with F suffix)
Channel Supply current -
DC signal
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7742);
VI = VCCI (ISOW7742 with F suffix)
1 Mbps
Channel Supply current -
AC signal
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
7.9
16.6
17.5
100 Mbps
13.7
ISOW7743 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7743);
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
3.4
3.6
3.4
3.6
3.4
3.6
4.7
6.9
4
5.1
5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
VI = 0 V (ISOW7743 with F suffix)
Supply current - Disable
5.1
5
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7743);
VI = VCCI (ISOW7743 with F suffix)
5.1
5
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7743);
VI = 0 V (ISOW7743 with F suffix)
Channel Supply current -
DC signal
6.8
9.3
6.2
7.2
7.4
7.6
23
14
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7743);
VI = VCCI (ISOW7743 with F suffix)
1 Mbps
5.3
5
Channel Supply current -
AC signal
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
5.6
17
100 Mbps
10.5
ISOW7744 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7744);
IDD_IO
IISOIN
IDD_IO
IISOIN
3.7
3.2
3.7
3.2
5.7
4.5
5.7
4.5
mA
mA
mA
mA
VI = 0 V (ISOW7744 with F suffix)
Supply current - Disable
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7744);
VI = VCCI (ISOW7744 with F suffix)
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SLLSFK1B – SEPTEMBER 2021 – REVISED JANUARY 2022
www.ti.com
VIO, VISOIN = 3.3 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
IDD_IO
3.7
3.2
4
5.7
4.5
6.1
10.1
6.1
7.3
7.8
7.3
29
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7744);
VI = 0 V (ISOW7744 with F suffix)
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
Channel Supply current -
DC signal
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7744);
VI = VCCI (ISOW7744 with F suffix)
7.6
3.8
5.5
5.5
5.5
21
1 Mbps
Channel Supply current -
AC signal
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
100 Mbps
6.3
8.3
(1) VCCI = VIO or VISOIN
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SLLSFK1B – SEPTEMBER 2021 – REVISED JANUARY 2022
7.15 Electrical Characteristics Channel Isolator - VIO, VISOIN = 2.5-V
VIO, VISOIN = 2.5 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
PARAMETER
Channel Isolation
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VITH
VITL
Input pin rising threshold
Input pin falling threshold
0.7 x VSI
V
V
0.3 x VSI
0.1 x VSI
-25
Input pin threshold hysteresis
(INx)
VI(HYS)
V
IIL
Low level input current
High level input current
VIL = 0 at INx
µA
µA
IIH
VIH = VSI (1) at INx
25
(1)
IO = –1 mA, see Switching Characteristics
Test Circuit and Voltage Waveforms
VSO
–
VOH
VOL
High level output voltage
Low level output voltage
V
V
0.1
IO = 1 mA, see Switching Characteristics Test
Circuit and Voltage Waveforms
0.1
Common mode transient
immunity
VI = VSI or 0 V, VCM = 1000 V; see Common-
Mode Transient Immunity Test Circuit
CMTI
85
100
kV/us
(1) VSI = input side supply; VSO = output side supply
7.16 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 2.5-V
VIO, VISOIN = 2.5 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ISOW7740 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7740);
VI = 0 V (ISOW7740 with F suffix)
IDD_IO
2.4
4.5
2.4
4.5
2.4
4.5
6.8
4.7
4.6
4.7
4.7
5.7
5.3
18
3.8
6.9
3.8
6.9
3.8
6.9
9
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
Supply current - Disable
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7740);
VI = VCCI (ISOW7740 with F suffix)
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7740);
VI = 0 V (ISOW7740 with F suffix)
Channel Supply current -
DC signal
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7740);
VI = VCCI (ISOW7740 with F suffix)
7.2
6.4
7
1 Mbps
6.4
8.1
7.2
24
Channel Supply current -
AC signal
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
100 Mbps
ISOW7741 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7741);
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
2.7
4.2
2.7
4.2
2.7
4.2
6.1
5.4
4.3
6.3
4.3
6.3
4.3
6.3
8.3
7.9
mA
mA
mA
mA
mA
mA
mA
mA
VI = 0 V (ISOW7741 with F suffix)
Supply current - Disable
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7741);
VI = VCCI (ISOW7741 with F suffix)
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7741);
VI = 0 V (ISOW7741 with F suffix)
Channel Supply current -
DC signal
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7741);
VI = VCCI (ISOW7741 with F suffix)
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SLLSFK1B – SEPTEMBER 2021 – REVISED JANUARY 2022
www.ti.com
VIO, VISOIN = 2.5 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
IDD_IO
4.4
4.9
6.3
7.1
mA
mA
mA
mA
mA
mA
1 Mbps
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
4.7
8.3
Channel Supply current -
AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
5.6
7.9
8.2
11.2
18.8
14.6
ISOW7742 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7742);
VI = 0 V (ISOW7742 with F suffix)
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
3.1
3.8
3.1
3.8
3.1
3.8
5.3
6.1
4.2
5.1
4.7
5.6
10.9
11.7
4.6
5.5
4.6
5.5
4.6
5.4
7.5
8.4
6.3
7.2
6.8
7.7
14.5
15.5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Supply current - Disable
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7742);
VI = VCCI (ISOW7742 with F suffix)
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7742);
VI = 0 V (ISOW7742 with F suffix)
Channel Supply current -
DC signal
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7742);
VI = VCCI (ISOW7742 with F suffix)
1 Mbps
Channel Supply current -
AC signal
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
100 Mbps
ISOW7743 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7743);
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
3.4
3.5
3.4
3.5
3.4
3.5
4.6
6.8
4
5.1
4.9
5.1
4.9
5.1
4.9
6.7
9.3
6.2
7.2
7
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
VI = 0 V (ISOW7743 with F suffix)
Supply current - Disable
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7743);
VI = VCCI (ISOW7743 with F suffix)
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7743);
VI = 0 V (ISOW7743 with F suffix)
Channel Supply current -
DC signal
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7743);
VI = VCCI (ISOW7743 with F suffix)
1 Mbps
5.3
4.8
5.6
13.8
8.3
Channel Supply current -
AC signal
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
7.5
17
100 Mbps
13
ISOW7744 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7744);
IDD_IO
IISOIN
IDD_IO
IISOIN
3.7
3.2
3.7
3.2
5.9
4.4
5.7
4.4
mA
mA
mA
mA
VI = 0 V (ISOW7744 with F suffix)
Supply current - Disable
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7744);
VI = VCCI (ISOW7744 with F suffix)
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SLLSFK1B – SEPTEMBER 2021 – REVISED JANUARY 2022
VIO, VISOIN = 2.5 V ±10% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
IDD_IO
3.7
3.2
3.9
7.5
3.8
5.5
4.8
5.5
16.5
6
5.7
4.4
6.2
10
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7744);
VI = 0 V (ISOW7744 with F suffix)
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
Channel Supply current -
DC signal
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7744);
VI = VCCI (ISOW7744 with F suffix)
6.1
7.3
7.2
7.3
22
1 Mbps
Channel Supply current -
AC signal
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
100 Mbps
8.1
(1) VCCI = VIO or VISOIN
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7.17 Electrical Characteristics Channel Isolator - VIO, VISOIN = 1.8-V
VIO, VISOIN = 1.8 V ±5% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
PARAMETER
Channel Isolation
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VITH
VITL
Input pin rising threshold
Input pin falling threshold
0.7 x VSI
V
V
0.3 x VSI
0.1 x VSI
-25
Input pin threshold hysteresis
(INx)
VI(HYS)
V
IIL
Low level input current
High level input current
VIL = 0 at INx
µA
µA
IIH
VIH = VSI (1) at INx
25
(1)
IO = –1 mA, see Switching Characteristics
Test Circuit and Voltage Waveforms
VSO
–
VOH
VOL
High level output voltage
Low level output voltage
V
V
0.1
IO = 1 mA, see Switching Characteristics Test
Circuit and Voltage Waveforms
0.1
Common mode transient
immunity
VI = VSI or 0 V, VCM = 1000 V; see Common-
Mode Transient Immunity Test Circuit
CMTI
85
100
kV/us
(1) VSI = input side supply; VSO = output side supply
7.18 Supply Current Characteristics Channel Isolator - VIO, VISOIN = 1.8-V
VIO, VISOIN = 1.8 V ±5% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ISOW7740 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7740);
VI = 0 V (ISOW7740 with F suffix)
IDD_IO
1.9
4.2
1.9
4.2
1.9
4.2
6.1
4.4
4.0
4.7
4.0
5.4
4.6
14.6
3
6.3
3
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
Supply current - Disable
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7740);
VI = VCCI (ISOW7740 with F suffix)
6.3
3
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7740);
VI = 0 V (ISOW7740 with F suffix)
6.3
8.7
6.7
6.4
7
Channel Supply current -
DC signal
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7740);
VI = VCCI (ISOW7740 with F suffix)
1 Mbps
6.4
7.7
9.5
19
Channel Supply current -
AC signal
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
100 Mbps
ISOW7741 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7741);
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
2.4
3.8
2.4
3.8
2.4
3.8
5.5
4.9
3.6
5.6
3.6
5.6
3.6
5.6
7.8
7.3
mA
mA
mA
mA
mA
mA
mA
mA
VI = 0 V (ISOW7741 with F suffix)
Supply current - Disable
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7741);
VI = VCCI (ISOW7741 with F suffix)
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7741);
VI = 0 V (ISOW7741 with F suffix)
Channel Supply current -
DC signal
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7741);
VI = VCCI (ISOW7741 with F suffix)
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Product Folder Links: ISOW7740 ISOW7741 ISOW7742 ISOW7743 ISOW7744
ISOW7740, ISOW7741, ISOW7742, ISOW7743, ISOW7744
www.ti.com
SLLSFK1B – SEPTEMBER 2021 – REVISED JANUARY 2022
VIO, VISOIN = 1.8 V ±5% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
IDD_IO
4
4.4
4.2
5.2
6.9
12
5.7
6.5
6
mA
mA
mA
mA
mA
mA
1 Mbps
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
Channel Supply current -
AC signal
All channels switching with square
wave clock input; CL = 15 pF
10 Mbps
100 Mbps
7.3
9.6
15.8
ISOW7742 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7742);
VI = 0 V (ISOW7742 with F suffix)
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
2.8
3.4
2.8
3.4
2.8
3.4
5
4.3
5.1
4.3
5.1
4.3
5.1
7.4
8.1
6.3
7.2
6.6
7.5
12.5
13.3
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Supply current - Disable
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7742);
VI = VCCI (ISOW7742 with F suffix)
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7742);
VI = 0 V (ISOW7742 with F suffix)
Channel Supply current -
DC signal
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7742);
VI = VCCI (ISOW7742 with F suffix)
5.6
4.2
4.5
4.3
5.0
9.1
9.7
1 Mbps
Channel Supply current -
AC signal
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
100 Mbps
ISOW7743 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7743);
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
3.2
3
5
4.5
5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
VI = 0 V (ISOW7743 with F suffix)
Supply current - Disable
3.2
3
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7743);
VI = VCCI (ISOW7743 with F suffix)
4.5
5
3.2
3
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7743);
VI = 0 V (ISOW7743 with F suffix)
4.5
6.6
8.9
6.2
7.2
6.7
7.4
15
Channel Supply current -
DC signal
4.4
6.2
4
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7743);
VI = VCCI (ISOW7743 with F suffix)
1 Mbps
4.6
4.6
4.9
11.4
7.8
Channel Supply current -
AC signal
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
100 Mbps
9.8
ISOW7744 Channel Supply Current
EN_IO1 = EN_IO2 = 0 V; VI = VCCI (1) (ISOW7744);
IDD_IO
IISOIN
IDD_IO
IISOIN
3.6
2.6
3.6
2.6
5.7
3.8
5.7
3.8
mA
mA
mA
mA
VI = 0 V (ISOW7744 with F suffix)
Supply current - Disable
EN_IO1 = EN_IO2 = 0 V; VI = 0 V (ISOW7744);
VI = VCCI (ISOW7744 with F suffix)
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VIO, VISOIN = 1.8 V ±5% GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions, unless otherwise
specified)
SUPPLY
CURRENT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
IDD_IO
3.6
2.6
3.8
6.7
3.8
4.7
4.5
4.7
13.8
5.2
5.7
3.8
6.1
9.6
6.1
7.3
7
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
EN_IO1 = EN_IO2 = VCCI; VI = VCCI (ISOW7744);
VI = 0 V (ISOW7744 with F suffix)
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
IDD_IO
IISOIN
Channel Supply current -
DC signal
EN_IO1 = EN_IO2 = VCCI; VI = 0 V (ISOW7744);
VI = VCCI (ISOW7744 with F suffix)
1 Mbps
Channel Supply current -
AC signal
All channels switching with square
10 Mbps
wave clock input; CL = 15 pF
7.3
16.9
7.7
100 Mbps
(1) VCCI = VIO or VISOIN
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SLLSFK1B – SEPTEMBER 2021 – REVISED JANUARY 2022
7.19 Switching Characteristics - 5-V Supply
VISOIN = 5 V ±10%, VIO = 5 V ±10%, GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions unless
otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL – tPLH
TEST CONDITIONS
MIN
TYP
10.7
0.9
MAX UNIT
tPLH, tPHL
PWD
7.6
15.7
5
ns
ns
See Switching Characteristics Test
Circuit and Voltage Waveforms
|
ENIO_tPLH
ENIO_tPHL
,
See Enable/Disable Propagation Delay
Time Test Circuit and Waveform
ENIO propagation delay time (opposite side)
210
473.8
ns
tsk(o)
tsk(pp)
tr
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
Same-direction channels
4
5.5
3.6
3.5
ns
ns
ns
ns
Output signal rise time
2.5
2.4
See Switching Characteristics Test
Circuit and Voltage Waveforms
tf
Output signal fall time
Channel disable propagation delay, high-to-high impedance
output
tPHZ
tPLZ
217
217
237
237
237
237
286
286
333
333
333
333
ns
ns
ns
ns
ns
ns
Channel disable propagation delay, low-to-high impedance
output
Channel enable propagation delay, high impedance-to-high
output for ISOW774x
See Enable/Disable Propagation Delay
Time Test Circuit and Waveform
tPZH
Channel enable propagation delay, high impedance-to-high
output for ISOW774x with F suffix
Channel enable propagation delay, high impedance-to-low
output for ISOW774x
tPZL
Channel enable propagation delay, high impedance-to-low
output for ISOW774x with F suffix
Measured from the time VIO or VISOIN
goes below 1.6 V at 10 mV/ns.
See Default Output Delay Time Test
Circuit and Voltage Waveforms
tDO
Default output delay time from input power loss
Time interval error
0.1
0.7
0.3
μs
ns
tie
216 – 1 PRBS data at 100 Mbps
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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7.20 Switching Characteristics - 3.3-V Supply
VISOIN = 3.3 V ±10%, VIO = 3.3 V ±10%, GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions unless
otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL – tPLH
TEST CONDITIONS
MIN
TYP
11
MAX UNIT
tPLH, tPHL
PWD
6
16.2
4.7
ns
ns
See Switching Characteristics Test
Circuit and Voltage Waveforms
|
0.6
ENIO_tPLH
ENIO_tPHL
,
See Enable/Disable Propagation Delay
Time Test Circuit and Waveform
ENIO propagation delay time (opposite side)
220
474
ns
tsk(o)
tsk(pp)
tr
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
Same-direction channels
4.1
4.5
2.7
2.4
ns
ns
ns
ns
Output signal rise time
1.8
1.6
See Switching Characteristics Test
Circuit and Voltage Waveforms
tf
Output signal fall time
Channel disable propagation delay, high-to-high impedance
output
tPHZ
tPLZ
230
230
226
226
225
225
300.4
299.6
318.9
319.1
317.9
317.6
ns
ns
ns
ns
ns
ns
Channel disable propagation delay, low-to-high impedance
output
Channel enable propagation delay, high impedance-to-high
output for ISOW774x
See Enable/Disable Propagation Delay
Time Test Circuit and Waveform
tPZH
Channel enable propagation delay, high impedance-to-high
output for ISOW774x with F suffix
Channel enable propagation delay, high impedance-to-low
output for ISOW774x
tPZL
Channel enable propagation delay, high impedance-to-low
output for ISOW774x with F suffix
Measured from the time VIO or VISOIN
goes below 1.6 V at 10 mV/ns.
See Default Output Delay Time Test
Circuit and Voltage Waveforms
tDO
Default output delay time from input power loss
Time interval error
0.1
0.3
μs
ns
tie
216 – 1 PRBS data at 100 Mbps
0.65
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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SLLSFK1B – SEPTEMBER 2021 – REVISED JANUARY 2022
7.21 Switching Characteristics - 2.5-V Supply
VISOIN = 2.5 V ±10%, VIO = 2.5 V ±10%, GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions unless
otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL – tPLH
TEST CONDITIONS
MIN
TYP
12
MAX UNIT
tPLH, tPHL
PWD
7.5
18
ns
ns
See Switching Characteristics Test
Circuit and Voltage Waveforms
|
0.36
5.1
ENIO_tPLH
ENIO_tPHL
,
See Enable/Disable Propagation Delay
Time Test Circuit and Waveform
ENIO propagation delay time (opposite side)
225
478
ns
tsk(o)
tsk(pp)
tr
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
Same-direction channels
4.1
6
ns
ns
ns
ns
Output signal rise time
2
3.26
3.2
See Switching Characteristics Test
Circuit and Voltage Waveforms
tf
Output signal fall time
1.8
Channel disable propagation delay, high-to-high impedance
output
tPHZ
tPLZ
237
236
228
228
227
227
326
325
360
360
350
350
ns
ns
ns
ns
ns
ns
Channel disable propagation delay, low-to-high impedance
output
Channel enable propagation delay, high impedance-to-high
output for ISOW774x
See Enable/Disable Propagation Delay
Time Test Circuit and Waveform
tPZH
Channel enable propagation delay, high impedance-to-high
output for ISOW774x with F suffix
Channel enable propagation delay, high impedance-to-low
output for ISOW774x
tPZL
Channel enable propagation delay, high impedance-to-low
output for ISOW774x with F suffix
Measured from the time VIO or VISOIN
goes below 1.6 V at 10 mV/ns.
See Default Output Delay Time Test
Circuit and Voltage Waveforms
tDO
Default output delay time from input power loss
Time interval error
0.1
0.7
0.3
μs
ns
tie
216 – 1 PRBS data at 100 Mbps
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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7.22 Switching Characteristics - 1.8-V Supply
VISOIN = 1.8 V ±5%, VIO = 1.8 V ±5%, GND1 = GNDIO, GND2 = GISOIN (over recommended operating conditions unless
otherwise noted)
PARAMETER
Propagation delay time
Pulse width distortion(1) |tPHL – tPLH
TEST CONDITIONS
MIN
TYP
15
0
MAX UNIT
tPLH, tPHL
PWD
7.5
21.5
5.8
ns
ns
See Switching Characteristics Test
Circuit and Voltage Waveforms
|
ENIO_tPLH
ENIO_tPHL
,
See Enable/Disable Propagation Delay
Time Test Circuit and Waveform
ENIO propagation delay time (opposite side)
243
475
ns
tsk(o)
tsk(pp)
tr
Channel-to-channel output skew time(2)
Part-to-part skew time(3)
Same-direction channels
4.1
8.6
3
ns
ns
ns
ns
Output signal rise time
1.9
1.8
See Switching Characteristics Test
Circuit and Voltage Waveforms
tf
Output signal fall time
3
Channel disable propagation delay, high-to-high impedance
output
tPHZ
tPLZ
260
260
240
240
237
237
410
406
444
444
439
439
ns
ns
ns
ns
ns
ns
Channel disable propagation delay, low-to-high impedance
output
Channel enable propagation delay, high impedance-to-high
output for ISOW774x
See Enable/Disable Propagation Delay
Time Test Circuit and Waveform
tPZH
Channel enable propagation delay, high impedance-to-high
output for ISOW774x with F suffix
Channel enable propagation delay, high impedance-to-low
output for ISOW774x
tPZL
Channel enable propagation delay, high impedance-to-low
output for ISOW774x with F suffix
Measured from the time VIO or VISOIN
goes below 1.6 V at 10 mV/ns.
See Default Output Delay Time Test
Circuit and Voltage Waveforms
tDO
Default output delay time from input power loss
Time interval error
0.1
0.7
0.3
μs
ns
tie
216 – 1 PRBS data at 100 Mbps
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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SLLSFK1B – SEPTEMBER 2021 – REVISED JANUARY 2022
7.23 Insulation Characteristics Curves
550
VDD = VIO = VISOIN = 3.6 V
VDD = VIO = VISOIN = 5.5 V
500
450
400
350
300
250
200
150
100
50
0
0
20
40
60
80
100
120
140
160
Ambient Temperature (C)
Figure 7-2. Thermal Derating Curve for Safety
Limiting Power for DFM-20 Package
Figure 7-1. Thermal Derating Curve for Safety
Limiting Current for DFM-20 Package
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7.24 Typical Characteristics
3.4
5.1
5.08
5.06
5.04
5.02
5
VDD = 5 V
VDD = 3.3 V
3.38
3.36
3.34
3.32
3.3
3.28
3.26
3.24
3.22
3.2
4.98
4.96
4.94
4.92
4.9
0
20
40
60
80
100
120
140
0
10 20 30 40 50 60 70 80 90 100 110 120
Load Current (mA)
Load Current (mA)
VSEL = GND2
TA = 25°C
VISOOUT = 3.3 V
VSEL = VISOOUT
TA = 25°C
VISOOUT = 5 V
Figure 7-3. Isolated Supply Voltage (VISOOUT) vs
Load Current (IISOOUT
Figure 7-4. Isolated Supply Voltage (VISOOUT) vs
Load Current (IISOOUT
)
)
270
240
210
180
150
120
90
48
45
42
39
36
33
30
27
24
21
VDD = 5 V, VISOOUT = 5 V
VDD = 3.3 V, VISOOUT = 3.3 V
VDD = 5 V, VISOOUT = 3.3 V
VDD = 5 V, VISOOUT = 5 V
VDD = 3.3 V, VISOOUT = 3.3 V
VDD = 5 V, VISOOUT = 3.3 V
60
30
0
0
20
40
60
80
100
120
140
0
20
40
60
80
100
120
140
Load Current (mA)
Load Current (mA)
TA = 25°C
TA = 25°C
Figure 7-5. Supply Current (IDD) vs Load Current
(IISOOUT
Figure 7-6. Efficiency vs Load Current (IVISOOUT
)
)
800
700
600
500
400
300
200
100
0
3.35
3.34
3.33
3.32
3.31
3.3
3.29
3.28
3.27
3.26
3.25
VDD = 5 V, VISOOUT = 5 V
VDD = 3.3 V, VISOOUT = 3.3 V
VDD = 5 V, VISOOUT = 3.3 V
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (C)
0
20
40
60
80
100
120
140
Output Load Current (mA)
VSEL = GND2
VDD = 5 V
No VISOOUT Load
TA = 25°C
Figure 7-8. 3.3-V Isolated Supply Voltage (VISOOUT
vs Free-Air Temperature
)
Figure 7-7. Power Dissipation vs Load Current
(IISOOUT
)
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SLLSFK1B – SEPTEMBER 2021 – REVISED JANUARY 2022
5.05
5.04
5.03
5.02
5.01
5
340
320
300
280
260
240
220
200
180
160
4.99
4.98
4.97
4.96
4.95
-40 -25 -10
5
20 35 50 65 80 95 110 125
3
3.25 3.5 3.75
4
4.25 4.5 4.75
5
5.25 5.5
Temperature (C)
Input Supply Voltage, VDD (mA)
VSEL = VISOOUT
VDD = 5 V
No VISOOUT Load
VSEL = VISOOUT VISOOUT = GND2 TA = 25°C = GND1
Figure 7-9. 5-V Isolated Supply Voltage (VISOOUT) vs
Free-Air Temperature
Figure 7-10. Short-Circuit Supply Current (ICC) vs
Supply Voltage (VCC)
24
20
IIO, VIO = 5 V
IISOIN, VISOIN = 5 V
IIO, VIO = 3.3 V
IISOIN, VISOIN = 3.3 V
IIO, VIO = 5 V
IISOIN, VISOIN = 5 V
IIO, VIO = 3.3 V
22
18
16
14
12
10
8
20
18
16
14
12
10
8
IISOIN, VISOIN = 3.3 V
6
6
4
4
2
2
0
10
20
30
40
50
60
70
80
90 100
0
10
20
30
40
50
60
70
80
90 100
Data Rate (Mbps)
Data Rate (Mbps)
CL = 15 pF
TA = 25°C
CL = 0 pF
TA = 25°C
Figure 7-11. ISOW7741 Channel Supply Currents
vs Data Rate For CL = 15 pF
Figure 7-12. ISOW7741 Channel Supply Currents
vs Data Rate For CL = 0 pF
3
17
tPHL, VIO = 5 V, VISOIN = 5 V
tPLH, VIO = 5 V, VISOIN = 5 V
tPHL, VIO = 5 V, VISOIN = 3.3 V
tPLH, VIO = 5 V, VISOIN = 3.3 V
tPHL, VIO = 3.3 V, VISOIN = 3.3 V
tPLH, VIO = 3.3 V, VISOIN = 3.3 V
16
15
14
13
12
11
10
9
2.75
2.5
VIO UVLO+
VIO UVLO-
VISOIN UVLO+
VISOIN UVLO-
VDD UVLO+
VDD UVLO-
2.25
2
1.75
1.5
1.25
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (C)
Temperature (C)
Figure 7-14. Propagation Delay Time vs Free-Air
Temperature
Figure 7-13. Power-Supply Undervoltage
Threshold vs Free Air Temperature
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5
0.8
0.6
0.4
0.2
0
4.5
VSO = 3.3 V
VSO = 5 V
4
3.5
3
VSO = 3.3 V
VSO = 5 V
2.5
0
3
6
9
12
15
-15
-12
-9
-6
-3
0
Low-Level Output Current (mA)
High-Level Output Current (mA)
TA = 25°C
TA = 25°C
Figure 7-16. Low-Level Output Voltage vs Low-
Level Output Current
Figure 7-15. High-Level Output Voltage vs High-
Level Output Current
VDD = 5 V VISOOUT = 3.3
V
TA = 25°C
VDD = 5 V VISOOUT = 3.3
V
10 uF
Capacitor on
VISOOUT
Figure 7-17. 10-mA to 110-mA Load Transient
Response
Figure 7-18. Soft Start at 10-mA Load For VISOOUT
3.3 V
=
VDD = 5 V VISOOUT = 3.3
V
10 uF
Capacitor on
VISOOUT
VDD = 5 V VISOOUT = 3.3
V
10 uF
Capacitor on
VISOOUT
Figure 7-19. Soft Start at 50-mA Load For VISOOUT
3.3 V
=
Figure 7-20. Soft Start at 110-mA Load For VISOOUT
= 3.3 V
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VDD = 5 V VISOOUT = 5 V
10 uF
Capacitor on
VISOOUT
VDD = 5 V VISOOUT = 5 V
10 uF
Capacitor on
VISOOUT
Figure 7-22. Soft Start at 50-mA Load For VISOOUT
5 V
=
Figure 7-21. Soft Start at 10-mA Load For VISOOUT
5 V
=
VDD = 3.3 V VISOOUT = 3.3
V
10 uF
Capacitor on
VISOOUT
VDD = 5 V VISOOUT = 5 V
10 uF
Capacitor on
VISOOUT
Figure 7-24. VISOOUT Ripple Voltage at 3.3 V with 10
uF Capacitor and 60 mA load
Figure 7-23. Soft Start at 110-mA Load For VISOOUT
= 5 V
VDD = 5 V VISOOUT = 5 V
10 uF
Capacitor on
VISOOUT
VDD = 3.3 V VISOOUT = 3.3
V
100 uF
Capacitor on
VISOOUT
Figure 7-25. VISOOUT Ripple Voltage at 5 V with 10
uF Capacitor and 110 mA load
Figure 7-26. VISOOUT Ripple Voltage at 3.3 V with
100 uF Capacitor and 60 mA load
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70
60
50
40
30
20
10
0
VDD = 5 V, VISOOUT = 5 V, 110 mA load
VDD = 5 V, VISOOUT = 3.3 V, 140 mA load
VDD = 3.3 V, VISOOUT = 3.3 V, 60 mA load
VDD = 5 V VISOOUT = 5 V
100 uF
Capacitor on
VISOOUT
10
20
30
40
50
60
70
80
90
100
VISOOUT Capacitor (F)
TA = 25°C
Figure 7-27. VISOOUT Ripple Voltage at 5 V with 100
uF Capacitor and 110 mA load
Figure 7-28. VISOOUT Ripple Voltage vs Load
Capacitor
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8 Parameter Measurement Information
In the below images, VCCI and VCCO refers to the power supplies VIO and VISOIN, respectively.
V
CCI
V
50%
I
50%
IN
OUT
0 V
V
t
t
PHL
PLH
Input Generator
(See Note A)
C
L
V
I
V
50 ꢀ
O
See Note B
OH
90%
10%
50%
50%
V
O
V
OL
t
r
t
f
Copyright © 2016, Texas Instruments Incorporated
A. CL = 15 pF and The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns,
tf ≤ 3ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in actual application.
B. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 8-1. Switching Characteristics Test Circuit and Voltage Waveforms
VCC1
VCC / 2
VCC / 2
VI
0 V
VOH
tPZH
VO
IN
OUT
0 V or 3 V
50%
0.5 V
VO
EN
0 V
RL = 1 kꢀ 1%
tPHZ
CL
See Note B
tPZL
tPLZ
Input
Generator
(See Note A)
VOH
0.5 V
VOL
VI
50 ꢀ
VO
50%
A. A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3ns, ZO
= 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in actual application.
B. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 8-2. Enable/Disable Propagation Delay Time Test Circuit and Waveform
VCCI
See Note B
V
CCI
V
1.4 V
I
0 V
default high
IN
OUT
IN = 0 V (Devices without suffix F)
IN = V (Devices with suffix F)
V
O
t
DO
CC
V
OH
C
L
50%
V
O
See Note A
V
OL
default low
Note
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
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Note
B. Power Supply Ramp Rate = 10 mV/ns.
Figure 8-3. Default Output Delay Time Test Circuit and Voltage Waveforms
5V
Connected to Visoout on PCB
VISOIN
VIO
0.01uF
1uF
10uF
10uF
1uF
0.01uF
VIO
GND1
OUT
IN
5V
GND1
VDD
C
L
10uF
1uF
0.01uF
GND1
GND2
+
–
V
CM
Note
CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Note
Pass-fail criteria: Outputs must remain stable.
Figure 8-4. Common-Mode Transient Immunity Test Circuit
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9 Detailed Description
9.1 Overview
The ISOW774x family of devices have low-noise, low-emissions isolated DC-DC converter, and four high- speed
isolated data channels. Section 9.2 shows the functional block diagram of the ISOW774x device.
9.1.1 Power Isolation
The integrated isolated DC-DC converter uses advanced circuit and on-chip layout techniques to reduce
radiated emissions and achieve upto 46% typical efficiency. The integrated transformer uses thin film polymer
as the insulation barrier. Output voltage of power converter can be controlled to 3.3 V or 5 V using VSEL
pin. The DC-DC converter can be switched off using the EN/FLT pin to save power. The output voltage,
VISOOUT , is monitored and feedback information is conveyed to the primary side through a dedicated isolation
channel. VISOOUT needs to be connected to VISOIN to ensure the feedback channel is properly powered to
regulate the DC-DC converter. This can be achieved by connecting the pins directly or through an LDO that
remains powered up at all times. A ferrite bead is recommended between Visoout and Visoin to further reduce
emissions. See the Section 10.2 section. The duty cycle of the primary switching stage is adjusted accordingly.
The fast feedback control loop of the power converter ensures low overshoots and undershoots during load
transients. Undervoltage lockout (UVLO) with hysteresis is integrated on the VIO, VDD and VISOIN supplies
which ensures robust fails-safe system performance under noisy conditions. An integrated soft-start mechanism
ensures controlled inrush current and avoids any overshoot on the output during power up.
9.1.2 Signal Isolation
The integrated signal isolation channels employ an ON-OFF keying (OOK) modulation scheme to transmit the
digital data across a silicon-dioxide based isolation barrier. The transmitter sends a high frequency carrier
across the barrier to represent one state and sends no signal to represent the other state. The receiver
demodulates the signal after signal conditioning and produces the output through a buffer stage. The signal-
isolation channels incorporate advanced circuit techniques to maximize the CMTI performance and minimize the
radiated emissions from the high frequency carrier and IO buffer switching. Figure 9-1 shows a functional block
diagram of a typical signal isolation channel. In order to keep any noise coupling from power converter away
from signal path, power supplies on side 1 for power converter (VDD) and signal path(VIO) are kept separate.
Similarly on side 2, power converter output (VISOOUT) needs to be connected to VISOIN externally on PCB.
Emissions can be further improved by placing a ferrite bead between VISOOUT and VISOIN as well as between the
GND2 pins. For more details, refer to the Layout Guidelines section.
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9.2 Functional Block Diagram
V
V
ISOIN
IO
Isolation Barrier
VISOOUT and
VISOIN needs to
be directly
connected or
through an
LDO on board
that is always
powered.
Data Channels
(4)
Data Channels
(4)
I/O Channels
I/O Channels
FB Controller
V
ref
FB Channel (Rx)
FB Channel (Tx)
Thermal
Shutdown,
UVLO, Soft-start
UVLO, Soft-start
Transformer
Driver
Power
Controller
Rectifier
V
ISOOUT
V
DD
Transformer
Figure 9-1. Block Diagram
Transmitter
Receiver
OOK
Modulation
TX IN
SiO based
2
RX OUT
TX Signal
Conditioning
RX Signal
Conditioning
Envelope
Detection
Capacitive
Isolation
Barrier
Emissions
Reduction
Techniques
Oscillator
Figure 9-2. Conceptual Block Diagram of a Capacitive Data Channel
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Figure 9-3 shows a conceptual detail of how the OOK scheme works.
TX IN
Carrier signal through
isolation barrier
RX OUT
Figure 9-3. On-Off Keying (OOK) Based Modulation Scheme
9.3 Feature Description
Table 9-1 shows an overview of the device features.
Table 9-1. Device Features
DEFAULT OUTPUT
STATE
PART NUMBER1
CHANNEL DIRECTION
MAXIMUM DATA RATE
RATED ISOLATION2
ISOW7740
ISOW7740F
ISOW7741
ISOW7741F
ISOW7742
ISOW7742F
ISOW7743
ISOW7743F
ISOW7744
ISOW7744F
High
Low
High
Low
High
Low
High
Low
High
Low
4 forward, 0 reverse
3 forward, 1 reverse
2 forward, 2 reverse
1 forward, 3 reverse
0 forward, 4 reverse
100 Mbps
5 kVRMS / 7071 VPK
1. The F suffix is part of the orderable part number. See the Section 14 section for the full orderable part
number.
2. For detailed isolation ratings, see the Section 7.7 table.
9.3.1 Electromagnetic Compatibility (EMC) Considerations
The ISOW774x devices use emissions reduction schemes for the internal oscillator and advanced internal layout
scheme to minimize radiated emissions at the system level.
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 32. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the
ISOW774x devices incorporate many chip-level design improvements for overall system robustness. Some of
these improvements include:
•
•
•
•
Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
Low-resistance connectivity of ESD cells to supply and ground pins.
Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
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•
PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
•
•
Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
Power path and signal path separated to minimize internal high frequency coupling and allowing for an
external filtering knob using ferrite beads available to further reduce emissions
Reduced power converter switching frequency to 25 Mhz to reduce strength of high frequency components in
emissions spectrum
•
9.3.2 Power-Up and Power-Down Behavior
The ISOW774x device has built-in UVLO on the VIO, VDD, and VISOIN supplies with positive-going and negative-
going thresholds and hysteresis. Both the power converter supply (VDD) and logic supply (VIO) need to be
present for the device to work. If either of them is below its UVLO, both the signal path and the power converter
are disabled.
When the VDD voltage crosses the positive-going UVLO threshold during power-up, the DC-DC converter
initializes and the power converter duty cycle is increased in a controlled manner. This soft-start scheme limits
primary peak currents drawn from the VDD supply and charges the VISOOUT output in a controlled manner,
avoiding overshoots. Outputs of the isolated data channels are in an indeterminate state until the VIO or VDD
voltage crosses the positive-going UVLO threshold. When the UVLO positive-going threshold is crossed on the
secondary side VISOOUT pin, the feedback data channel starts providing feedback to the primary controller. The
regulation loop takes over and the isolated data channels go to the normal state defined by the respective input
channels or their default states. Design should consider a sufficient time margin (typically 10 ms with 10-µF load
capacitance) to allow this power up sequence before valid data channels are accounted for system functionality.
When either VIO or VDD power is lost, the primary side DC-DC controller turns off when the UVLO lower
threshold is reached. The VISOOUT capacitor then discharges depending on the external load. The isolated data
outputs on the VISOIN side are returned to the default state for the brief time that the VISOIN voltage takes to
discharge to zero.
9.3.3 Protection Features
The ISOW774x devices have multiple protection features to create a robust system level solution.
•
The Enable DC-DC / FAULT protection feature (EN/FLT) can be used as either an input pin, to enable or
disable the integrated DC-DC power converter, or as an output pin, which works as an alert signal if the
power converter is not operating properly. In the /FAULT use case, an alert is reported if VDD > 7 V, VDD < 2.5
V, or if the junction temperature >170°C. When a fault is detected, this pin will go low, disabling the DC-DC
converter to prevent any damage.
5 kΩ
Powers Down Isolator Channels
and DC-DC Converter.
EN/FLT
MCU OUTPUT
IQ < 1 mA Typical
MCU INPUT
Fault Reported If
VDD < 2.5 V
VDD > 7 V
Junction Temp > 170° C
Figure 9-4. EN/FLT Fault Pin Diagram
•
An over-voltage clamp feature is present on VISOOUT which will clamp the voltage at 6 V, when VSEL =
VISOOUT, or 4 V, when VSEL = GND2, if there is an increase in voltage seen on VISOOUT. It is recommended
that the VISOOUT stays lower than the over-clamp voltage for device reliability.
•
•
Over-voltage lock out on VDD will occur when a voltage higher than 7 V is seen. The device will go into a low
power state and the EN/FLT pin will go low.
The device is protected against output overload and short circuit. Output voltage starts dropping when the
power converter is not able to deliver the current demanded during overload conditions. For a VISOOUT
short-circuit to ground, the duty cycle of the converter is limited to help protect against any damage.
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•
•
•
The device is protected against output overload and short circuit. Output voltage starts dropping when the
power converter is not able to deliver the current demanded during overload conditions. For a VISOOUT
short-circuit to ground, the duty cycle of the converter is limited to help protect against any damage.
The device is protected against output overload and short circuit. Output voltage starts dropping when the
power converter is not able to deliver the current demanded during overload conditions. For a VISOOUT
short-circuit to ground, the duty cycle of the converter is limited to help protect against any damage.
Thermal protection is also integrated to help prevent the device from getting damaged during overload
and short-circuit conditions on the isolated output. Under these conditions, the device temperature starts to
increase. When the temperature goes above 165°C, thermal shutdown activates and the primary controller
turns off which removes the energy supplied to the VISOOUT load, which causes the device to cool off.
When the junction temperature goes below 150°C, the device starts to function normally. If an overload or
output short-circuit condition prevails, this protection cycle is repeated. Care should be taken in the design to
prevent the device junction temperatures from reaching such high values.
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9.4 Device Functional Modes
Table 9-2 lists the supply configurations for these devices.
Table 9-2. Supply Configuration Function Table
(1)
(3)
VDD
VIO
VSEL
VISOOUT
OFF
< VDD(UVLO+)
>VDD(UVLO+)
5 V
>VIO(UVLO+)
<VIO(UVLO+)
1.71 V to 5.5 V
1.71 V to 5.5 V
X
X
OFF
High (shorted to VISOOUT
)
5 V
5 V or 3.3 V
Low (shorted to GND2)(2)
3.3 V
(1) VDD= 3.3 V, MODE shorted to VISOOUT(essentially VISOOUT = 5 V) is not the recommended mode of operation
(2) The MODE pin has a weak pulldown internally. Therefore for VISOOUT = 3.3 V, the MODE pin should be strongly connected to the
GND2 pin in noisy system scenarios.
(3) VISOOUT shorted to VISOIN on PCB and both GND2 pins are shorted to each other and EN=High
Table 9-3 lists the channel isolators functional modes for these devices.
Table 9-3. Channel Isolator Function Table
CHANNEL
OUTPUT
SUPPLY (VCCO
IO ENABLE
(EN_IOx)
CHANNEL INPUT
OUTPUT
(OUTx)
(1)
INPUT (INx)
COMMENTS
SUPPLY (VCCI
)
(1)
)
H or
Open
H
L
H
L
Normal Operation: A channel output
assumes the logic state of its input.
H or Open
Default mode(2): When INx is open, the
corresponding channel output goes to its
default logic state.
Open
X
H or Open
Default
PU
PU
A low value of output enable causes
the outputs of the same side to be high
impedance and the output of opposite
side to be fail-safe default state.
L
Z and Default
Default mode(2): When VCCI is
unpowered, a channel output assumes
the logic state based on the selected
default option. When VCCI transitions
from unpowered to powered-up, a
channel output assumes the logic state
of the input. When VCCI transitions
from powered-up to unpowered, channel
output assumes the selected default
state.
PD
PU
X
H or Open
Default
(1) VCCI = Input-side VIO or VISOIN; VCCO = Output-side VIO or VISOIN; PU = Powered up (VIO > 1.7 V, VISOIN > 1.7 V); PD = Powered down
(VIO < 1 V, VISOIN < 1 V); X = Irrelevant; H = High level; L = Low level.
(2) In the default condition, the output is high for the ISOW774x device and low with the F suffix.
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9.4.1 Device I/O Schematics
INx (Devices without F suffix)
INx (Devices with F suffix)
VCCI
VCCI
VCCI
VCCI
VCCI
VCCI
VCCI
1.5 Mꢀ
985 ꢀ
985 ꢀ
INx
INx
1.5 Mꢀ
VSEL
OUTx
VCCO
VISOOUT
VISOOUT
VISOOUT
~20 ꢀ
1970 ꢀ
OUTx
SEL
2 Mꢀ
EN_IOx
EN/FLT
VCCI
VCCI
VCCI
VIO
VIO
VIO
VCCI
VIO
550 kꢀ
550 kꢀ
INx
INx
Fault
1mA
Figure 9-5. Device I/O Schematics
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 Application Information
The device is a high-performance, quad channel digital isolator with integrated DC-DC converter. Typically digital
isolators require two power supplies isolated from each other to power up both sides of device. Due to the
integrated DC-DC converter in the device, the isolated supply is generated inside the device that can be used
to power isolated side of the device and peripherals on isolated side, thus saving board space. The device uses
single-ended CMOS-logic switching technology. When designing with digital isolators, keep in mind that because
of the single-ended design structure, digital isolators do not conform to any specific interface standard and are
only intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between
the data controller (that is Microcontroller or UART), and a data converter or a line transceiver, regardless of the
interface type or standard.
The device is suitable for applications that have limited board space and desire more integration. The device
is also suitable for very high voltage applications, where power transformers meeting the required isolation
specifications are bulky and expensive.
10.2 Typical Application
For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files,
simulation results, and test results, refer to TI Design TIDA-01333, Eight-Channel, Isolated, High-Voltage
Analog Input Module With ISOW7841 Reference Design.
Figure 10-1 shows the typical schematic for SPI isolation.
Reference
10 ꢀF
1 ꢀF 10 nF
10 nF
1 ꢀF
10 ꢀF
3.3 VIN
VIO
VISOIN
3.3VOUT
DVCC
AVDD
DVDD
REF
CS
INA
INB
OUTA
OUTB
CS
HV+ to
Chassis
HV- to
SCLK
SCLK
ADC
MCU
DVSS
SDO
SDI
INC
OUTC
IND
SDI
Chassis
OUTD
SDO
AGND DGND
ISOW7741
GNDIO
GISOIN
330 ꢁ at 100 MHz
(BLM15EX331SN
1D)
VSEL
VISOOUT
VDD
IN OUT
1 ꢀF
10 nF
10 nF
1 ꢀF
10 ꢀF
10 ꢀF
GND
GND1
GND2
330 ꢁ at 100 MHz
(BLM15EX331SN
1D)
Optional LDO
Figure 10-1. Isolated Power and SPI for ADC Sensing Application with ISOW7741
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10.2.1 Design Requirements
To design with this device, use the parameters listed in Table 10-1.
Table 10-1. Design Parameters
PARAMETER
VALUE
VDD input voltage
VIO input voltage
VISOIN input voltage
3 V to 5.5 V
1.71 V to 5.5 V
1.71 V to 5.5 V
VDD decoupling capacitors
VIO decoupling capacitors
VISOIN decoupling capacitors
VISOOUT decoupling capacitors
VISOOUT to VISOIN series inductor
GND2 to GISOIN series inductor
VIO series inductor
10 µF + 1 µF + 0.01 µF + optional additional capacitance
0.1 µF + optional additional capacitance
0.1 µF + optional additional capacitance
10 µF + 1 µF + 0.01 µF + optional additional capacitance
BLM15ELX9331SN1D
BLM15ELX9331SN1D
BLM15ELX9331SN1D
VDD series inductor
BLM15ELX9331SN1D
GND1 to GNDIO series inductor
BLM15ELX9331SN1D
Because of very-high current flowing through the ISOW7741 device device VDD and VISOOUT supplies, higher
decoupling capacitors typically provide better noise and ripple performance. Although a 10-µF capacitor is
adequate, higher decoupling capacitors (such as 47 µF) on both the VDD and VISOOUT pins to the respective
grounds are strongly recommended to achieve the best performance.
10.2.2 Detailed Design Procedure
The devices requires specific placement of external bypass capacitors and ferrite beads to operate at high
performance. These low-ESR ceramic bypass capacitors must be placed as close to the chip pads as possible.
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10
1
F
F
10
1
F
F
VIO
330 at 100 MHz
(BLM15EX331SN1D)
10 nF
10 nF
VISOIN
1
20
OUTA
OUTB
OUTC
IND
2
3
19
18
INA
INB
4
5
17
16
INC
OUTD
GNDIO
EN_IO1
GISOIN
EN_IO2
6
7
15
14
VIO
VISOIN
EN/FLT
VSEL
8
9
13
12
VISOOUT
FAULT OUT
330 at 100 MHz
(BLM15EX331SN1D)
330 at 100 MHz
(BLM15EX331SN1D)
VISOOUT
GND2
VISOIN
VDD
1
F
10 nF
1 F
10
10 nF
F
10
F
GND1
10
11
330 at 100 MHz
(BLM15EX331SN1D)
330 at 100 MHz
(BLM15EX331SN1D)
Figure 10-2. Typical ISOW7741 Circuit Hook-Up
10.2.3 Application Curve
VDD = 5 V
VISOOUT = 5 V
IISOOUT = 100 mA
Figure 10-3. ISOW7741 Radiated Emissions versus CISPR32B line (Blue)
10.2.4 Insulation Lifetime
Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown
(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal
device and high voltage applied between the two sides; See Figure 10-4 for TDDB test setup. The insulation
breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced
insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million
(ppm). Even though the expected minimum insulation lifetime is 20 years at the specified working isolation
voltage, VDE reinforced certification requires additional safety margin of 20% for working voltage and 87.5% for
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lifetime which translates into minimum required insulation lifetime of 37.5 years at a working voltage that's 20%
higher than the specified value.
Figure 10-5 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.
Based on the TDDB data, the intrinsic capability of the insulation is 1000 VRMS with a lifetime of 1184 years.
A
Vcc 1
Vcc 2
Time Counter
> 1 mA
DUT
GND 1
GND 2
V
S
Oven at 150 °C
Figure 10-4. Test Setup for Insulation Lifetime Measurement
Figure 10-5. Insulation Lifetime Projection Data
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11 Power Supply Recommendations
To help make sure that operation is reliable at data rates and supply voltages, adequate decoupling capacitors
must be located as close to supply pins as possible. VISOOUT needs to be connected to VISOIN to ensure the
feedback channel is properly powered to regulate the DC-DC converter. If VISOOUT and VISOIN are not connected,
the DC-DC converter will run open loop and the VISOOUT voltage will drift until the over-voltage clamp clamps at 6
V. There are two ways to connect VISOOUTand VISOIN
:
1) connect VISOOUT and VISOIN directly with a ferrite bead. A ferrite bead is recommended between VISOOUTand
VISOIN to further reduce emissions.
2) connect VISOOUT and VISOIN with a ferrite bead through an LDO that remains powered up at all times. If the
LDO has an EN pin then keep the EN high at all times.
The input supply (VIO and VDD) must have an appropriate current rating to support output load and switching at
the maximum data rate required by the end application. For more information, refer to the Section 10.2 section.
For an output load current of 110 mA, it is recommended to have >600 mA of input current limit and for lower
output load currents, the input current limit can be proportionally lower.
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12 Layout
12.1 Layout Guidelines
A low cost two layer PCB should be sufficient to achieve good EMC performance:
•
Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their
inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits
of the data link.
•
•
•
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for
transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of
approximately 100 pF/in2.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links
usually have margin to tolerate discontinuities such as vias.
If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system
to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping.
Also the power and ground plane of each power system can be placed closer together, thus increasing the
high-frequency bypass capacitance significantly.
Because the device has no thermal pad to dissipate heat, the device dissipates heat through the respective GND
pins. Ensure that enough copper is present on both GND pins to prevent the internal junction temperature of the
device from rising to unacceptable levels.
Figure 12-1 shows the recommended placement and routing of device bypass capacitors. Below guidelines must
be followed to meet application EMC requirements:
•
High frequency bypass capacitors 10 nF must be placed close to VDD and VISOOUT pins, less than 1 mm
distance away from device pins. This is very essential for optimised radiated emissions performance. Ensure
that these capacitors are 0402 size so that they offer least inductance (ESL).
Bulk capacitors of atleast 10 μF must be placed on power converter input (VDD) and output (VISOOUT) supply
pins.
Traces on VDD and GND1 must be symmetric till bypass capacitors. Similarly traces on VISOOUT and GND2
must be symmetric.
Place two 0402 size Ferrite beads (Part number: BLM15EX331SN1) on VISOOUT and GND2 path so that any
high frequency noise from power converter output sees a high impedance before it goes to other components
on PCB.
•
•
•
•
•
Do not have any metal traces or ground pour within 4 mm of power converter output terminals VISOOUT pin12
and GND2 pin11. VSEL pin is also in VISOOUT domain and should be shorted to either pin 11 or pin 12 for
output voltage selection.
Following the layout guidelines of EVM as much as possible is highly recommended for a low radiated
emissions design.
12.1.1 PCB Material
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace
lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper
alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength
and stiffness, and the self-extinguishing flammability-characteristics.
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12.2 Layout Example
Ground plane on
side 2
Ground plane on
side 1
<2mm
<2mm
C
C
C
C
C
C
FB
5
VISOIN
Input Supply 1
VIO
20
19
1
10 F
10 nF
1 F
10
F
1
F
10 nF
INA
OUTA
2
INB
INC
OUTB
OUTC
3
4
18
17
16
15
14
13
OUTD
GNDIO
5
IND
GISOIN
Ground plane on side 1
6
EN_IO1
EN/FLT
VDD
7
EN_IO2
VSEL
Ground
plane on
side 2
8
10
F
1
F
10 nF
10 nF
1 F
10 F
FB
4
FB
1
Input Supply 2
9
12 VISOOUT
C
C
C
C
C
C
FB
3
FB
2
GND1
GND2
11
Ground plane
on side 2
10
<1mm
2-4mm
Keep-out zone for any metal
2-4mm
<1mm
Figure 12-1. Layout Example
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SLLSFK1B – SEPTEMBER 2021 – REVISED JANUARY 2022
13 Device and Documentation Support
13.1 Device Support
13.1.1 Development Support
For development support, refer to:
•
•
•
8-ch Isolated High Voltage Analog Input Module with ISOW7841 Reference Design
Isolated RS-485 With Integrated Signal and Power Reference Design
Isolated RS-232 With Integrated Signal and Power Reference Design
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
•
•
Texas Instruments, Digital Isolator Design Guide
Texas Instruments, Isolation Glossary
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Mar-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISOW7741BDFMR
ISOW7741DFMR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
DFM
DFM
DFM
DFM
DFM
DFM
DFM
DFM
DFM
20
20
20
20
20
20
20
20
20
850
850
850
850
850
850
850
850
850
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
TBD
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
ISOW7741
NIPDAU
NIPDAU
NIPDAU
Call TI
ISOW7741
ISOW7741F
ISOW7741F
ISOW7741FBDFMR
ISOW7741FDFMR
XISOW7740DFMR
XISOW7742FDFMR
XISOW7743DFMR
XISOW7743FDFMR
XISOW7744DFMR
TBD
Call TI
Call TI
TBD
Call TI
Call TI
TBD
Call TI
Call TI
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
3-Mar-2022
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISOW7741BDFMR
ISOW7741DFMR
ISOW7741FBDFMR
ISOW7741FDFMR
SOIC
SOIC
SOIC
SOIC
DFM
DFM
DFM
DFM
20
20
20
20
850
850
850
850
330.0
330.0
330.0
330.0
24.4
24.4
24.4
24.4
10.85 13.4
10.85 13.4
10.85 13.4
10.85 13.4
4.0
4.0
4.0
4.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISOW7741BDFMR
ISOW7741DFMR
ISOW7741FBDFMR
ISOW7741FDFMR
SOIC
SOIC
SOIC
SOIC
DFM
DFM
DFM
DFM
20
20
20
20
850
850
850
850
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
43.0
43.0
43.0
43.0
Pack Materials-Page 2
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Copyright © 2022, Texas Instruments Incorporated
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