XLMG2610RRGT [TI]

具有集成驱动器、保护和电流检测功能且适用于 ACF 的 650V 170/248mΩ GaN 半桥 | RRG | 40 | -40 to 125;


型号：	XLMG2610RRGT
厂家：	TEXAS INSTRUMENTS
描述：	具有集成驱动器、保护和电流检测功能且适用于 ACF 的 650V 170/248mΩ GaN 半桥 \| RRG \| 40 \| -40 to 125 驱动驱动器
文件：	总44页 (文件大小：1625K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMG2610

ZHCSNW8A –OCTOBER 2022 –REVISED DECEMBER 2022

LMG2610 用于有源钳位反激式转换器的集成650V GaN 半桥

1 特性

3 说明

• 650V GaN 功率FET 半桥

LMG2610 是一款 650V GaN 功率 FET 半桥，适用于

开关模式电源应用中 < 75W 的有源钳位反激式 (ACF)

转换器。LMG2610 通过在 9mm x 7mm QFN 封装中

集成半桥功率 FET、栅极驱动器、自举二极管和高侧

栅极驱动电平转换器，简化了设计、减少了元件数量并

减小了布板空间。

• 170mΩ 低侧和248mΩ 高侧GaN FET

• 具有低传播延迟和可调节导通压摆率控制的集成栅

极驱动器

• 具有高带宽和高精度的电流检测仿真

• 低侧/高侧栅极驱动互锁

• 高侧栅极驱动信号电平转换器

• 智能开关自举二极管功能

• 高侧启动：< 8us

非对称 GaN FET 电阻针对 ACF 工作条件进行了优

化。可编程导通压摆率可提供 EMI 和振铃控制。与传

统的电流检测电阻相比，低侧电流检测仿真可降低功

耗，并允许将低侧散热焊盘连接到冷却 PCB 电源接

地。

• 低侧/高侧逐周期过流保护

• 通过FLT 引脚报告实现过热保护

• AUX 空闲静态电流：240μA

• AUX 待机静态电流：50μA

• BST 空闲静态电流：60μA

• 最大电源和输入逻辑引脚电压：26V

• 具有双散热焊盘的9mm x 7mm QFN 封装

高侧栅极驱动信号电平转换器消除了外部解决方案中出

现的噪声和突发模式功率耗散问题。智能开关 GaN 自

举 FET 没有二极管正向压降，可避免高侧电源过充，

并且反向恢复电荷为零。

LMG2610 具有低静态电流和快速启动时间，支持转换

器轻负载效率要求和突发模式运行。保护特性包括

FET 导通互锁、欠压锁定 (UVLO)、逐周期电流限制和

过热关断。

2 应用

• 有源钳位反激式电源转换器

• 交流/直流适配器和充电器

• 交流/直流USB 墙壁插座电源

• 交流/直流辅助电源

器件信息

器件型号

封装⁽¹⁾

封装尺寸（标称值）

LMG2610

QFN

9.00 mm x 7.00 mm

BST

GaN

Level

Shift RX

Driver

RDRVH

AUX

Level

Shift TX

INH

Control

FLT

GaN

INL

Driver

RDRVL

Current

Emulation

AGND

简化版方框图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNOSDE2

LMG2610

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ZHCSNW8A –OCTOBER 2022 –REVISED DECEMBER 2022

Table of Contents

8.2 Functional Block Diagram.........................................20

8.3 Feature Description...................................................21

8.4 Device Functional Modes..........................................28

9 Application and Implementation..................................29

9.1 Application Information............................................. 29

9.2 Typical Application.................................................... 30

9.3 Power Supply Recommendations.............................32

9.4 Layout....................................................................... 33

10 Device and Documentation Support..........................36

10.1 Documentation Support.......................................... 36

10.2 接收文档更新通知................................................... 36

10.3 支持资源..................................................................36

10.4 Trademarks.............................................................36

10.5 Electrostatic Discharge Caution..............................36

10.6 术语表..................................................................... 36

11 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings........................................ 5

6.2 ESD Ratings............................................................... 5

6.3 Recommended Operating Conditions.........................6

6.4 Thermal Information....................................................6

6.5 Electrical Characteristics.............................................7

6.6 Switching Characteristics..........................................10

6.7 Typical Characteristics..............................................12

7 Parameter Measurement Information..........................17

7.1 GaN Power FET Switching Parameters....................17

8 Detailed Description......................................................19

8.1 Overview...................................................................19

Information.................................................................... 37

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (October 2022) to Revision A (December 2022)

Page

• 将数据表状态从“预告信息”更改为“量产数据”.............................................................................................1

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5 Pin Configuration and Functions

NC1

NC3

AGND

INL

INH

PADH

PADL

NC1

NC2

图5-1. RRG Package, 40-Pin VQFN (Top View)

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表5-1. Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

NC1

1, 13

2-12

Used to anchor QFN package to PCB. Pins must be soldered to PCB landing pads. The

PCB landing pads are non-solder mask defined pads and must not be physically

connected to any other metal on the PCB. Internally connected to DH.

High-side GaN FET drain. Internally connected to NC1.

GaN FET half-bridge switch node between the high-side GaN FET source and low-side

GaN FET drain. Internally connected to PADH.

NC2

14-16

17, 21, 37

Used to anchor QFN package to PCB. Pins must be soldered to PCB landing pads. The

PCB landing pads are non-solder mask defined pads and must not be physically

connected to any other metal on the PCB. Internally connected to AGND, SL, and PADL.

18-20, 22-27

Low-side GaN FET source. Internally connected to AGND, PADL, and NC2.

Enable. Used to toggle between active and standby modes. The standby mode has

reduced quiescent current to support converter light load efficiency targets. There is a

forward biased ESD diode from EN to AUX so avoid driving EN higher than AUX.

INH

INL

High-side gate-drive control input. Referenced to AGND. Signal is level shifted internally to

the high-side GaN FET driver. There is a forward biased ESD diode from INH to AUX so

avoid driving INH higher than AUX.

Low-side gate-drive control input. Referenced to AGND. There is a forward biased ESD

diode from INL to AUX so avoid driving INL higher than AUX.

AGND

GND

Low-side analog ground. Internally connected to SL, PADL, and NC2.

Current-sense emulation output. Outputs 1 ma/A scaled replica of the low-side GaN FET

current. Feed output current into a resistor to create a current sense voltage signal.

Reference the resistor to the power supply controller IC local ground. This function

replaces the external current-sense resistor that is used in series with the low-side FET.

NC3

Used to anchor QFN package to PCB. Pin must be soldered to a PCB landing pad. The

PCB landing pad is non-solder mask defined pad and must not be physically connected to

any other metal on the PCB. Pin not connected internally.

FLT

Active-low fault output. Open-drain output that asserts during an over-temperature shut

down.

AUX

Auxiliary voltage rail. Low-side supply voltage. Connect a local bypass capacitor between

AUX and AGND.

RDRVL

BST

Low-side drive strength control resistor. Set a resistance between RDRVL and AGND to

program the low-side GaN FET turn-on slew rate.

Bootstrap voltage rail. High-side supply voltage. The bootstrap diode function between

AUX and BST is internally provided. Connect an appropriately sized bootstrap capacitor

between BST and SW. Recommend to make the SW connection using NC4 as a pass

through connection to PADH (PADH = SW) as explained in the NC4 description.

RDRVH

NC4

High-side drive strength control resistor. Set a resistance between RDRVH and SW to

program the high-side GaN FET turn-on slew rate. Recommend to make the SW

connection using NC4 as a pass through connection to PADH (PADH = SW) as explained

in the NC4 description.

Pin is not functional. Pin is high impedance and referenced to SW. Recommend to connect

pin to PADH (PADH = SW) to use as convenient connection for the BST bypass capacitor

and the RDRVH resistor. See the example board layout in the Layout Example section.

PADH

PADL

High-side thermal pad. Internally connected to SW. All the SW current can be conducted

with PADH (PADH = SW).

Low-side thermal pad. Internally connected to SL, AGND, and NC2. All the SL current can

be conducted with PADL (PADL = SL).

(1) I = Input, O = Output, G = Ground, P = Power, NC = No Connect, TP = Thermal Pad.

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6 Specifications

6.1 Absolute Maximum Ratings

Unless otherwise noted: voltages are respect to AGND⁽¹⁾

MIN

MAX

650

UNIT

V_DS(ls)

Low-side drain-source (SW to SL) voltage, FET off

V_{DS(surge)(ls)}Low-side drain-source (SW to SL) voltage, surge condition, FET off ⁽²⁾

720

V_{DS(tr)(surge)}Low-side drain-source (SW to SL) transient ringing peak voltage, surge condition,

800

FET off ⁽²⁾

(ls)

V_DS(hs)

High-side drain source (DH to SW) voltage, FET off

650

720

V_{DS(surge)(hs)}High-side drain-source (DH to SW) voltage, surge condition, FET off ⁽²⁾

V_{DS(tr)(surge)}High-side drain-source (DH to SW) transient ringing peak voltage, surge condition,

800

FET off ⁽²⁾

(hs)

AUX

–0.3

EN, INL, INH, FLT

V_AUX+ 0.3

Pin voltage

5.5

RDRVL

BST

Pin voltage to SW

RDRVH

Internally

limited

I_D(peak)(ls)

I_S(peak)(ls)

I_D(peak)(hs)

I_S(peak)(hs)

Low-side drain (SW to SL) peak current, FET on

Low-side source (SL to SW) peak current, FET off

High-side drain (DH to SW) peak current, FET on

High-side source (SW to DH) peak current, FET off

–6.4

6.4

Internally

limited

–4

Positive sink current

Internally

limited

FLT (while asserted)

T_J

Operating junction temperature

Storage temperature

150

°C

–40

–65

T_stg

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) See GaN Power FET Switching Capability for more information on the GaN FET switching capability.

6.2 ESD Ratings

VALUE

±1000

±2000

UNIT

Pins1 through 16, Pins 38

through 40

Human body model (HBM), per

ANSI/ESDA/JEDEC JS-001⁽¹⁾

Electrostatic

discharge

Pins 17 through 37

V_(ESD)

Charged device model (CDM),

per ANSI/ESDA/JEDEC

JS-002⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

Unless otherwise noted: voltages are respect to AGND

MIN

7.5

NOM

MAX

UNIT

Supply voltage

AUX

Supply voltage to SW

Input voltage

BST

EN, INL, INH

FLT

V_AUX

Pull-up voltage on open-drain output

High-level input voltage

Low-level input voltage

V_IH

V_IL

2.5

EN, INL, INH

0.6

5.4

I_D(peak)(ls)Low-side drain (SW to SL) peak current, FET on

I_D(peak)(hs)High-side drain (DH to SW) peak current, FET on

–3.2

–2

C_AUX

AUX to AGND capacitance from external bypass capacitor

3 x C_BST

0.010

µF

C_{BST_SW}BST to SW capacitance from external bypass capacitor

RDRVL to AGND resistance from external slew-rate control resistor to configure

below low-side slew rate settings

slew rate setting 0 (slowest)

42.5

120

open

51.5

kΩ

R_RDRVL

slew rate setting 1

slew rate setting 2

slew rate setting 3 (fastest)

5.6

RDRVH to SW resistance from external slew-rate control resistor to configure below

high-side slew rate settings

slew rate setting 0 (slowest)

R_{RDRVH_}

42.5

120

open

51.5

kΩ

slew rate setting 1

slew rate setting 2

slew rate setting 3 (fastest)

5.6

6.4 Thermal Information

LMG2610

RRG (VQFN)

40 Pins

25.3

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(bot)

Junction-to-case (bottom) thermal resistance

1.22

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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6.5 Electrical Characteristics

1) Symbol definitions: V_DS(ls)= SW to SL voltage; I_DS(ls)= SW to SL current; V_DS(hs)= DH to SW voltage; I_D(hs)= DH to SW

current; 2) Unless otherwise noted: voltage, resistance, and capacitance are respect to AGND; -40 °C ≤T_J≤125 °C; 10 ≤

_AUX≤26; 7.5 ≤V_{BST_SW}≤26; V_EN= 5 V; V_INL= 0 V; V_INH= 0 V; R_RDRVL= 0 Ω; R_{RDRVH_SW}= 0 Ω; R_CS= 100 Ω

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LOW-SIDE GAN POWER FET

V_INL= 5 V, I_D(ls)= 3 A, T_J= 25°C

V_INL= 5 V, I_D(ls)= 3 A, T_J= 125°C

SL to SW current = 0.1 A

170

325

-1.9

-2.6

R_DS(on)(ls)Drain-source (SW to SL) on resistance

mΩ

Source-drain (SL to SW) third-quadrant

voltage

V_SD(ls)

SL to SW current = 1 A

V_DS(hs)= 0 V, V_DS(ls)= 650 V, T_J= 25 °C

V_DS(hs)= 0 V, V_DS(ls)= 650 V, T_J= 125 °C

I_DSS(ls)

Drain (SW to SL) leakage current

µA

Q_OSS(ls)Output (SW to SL) charge

19.7

C_OSS(ls)Output (SW to SL) capacitance

Output (SW to SL) capacitance stored

V_DS(hs)= 0 V, V_DS(ls)= 400 V

E_OSS(ls)

energy

2.32

µJ

Energy related effective output (SW to

SL) capacitance

C_OSS,er(ls)

Time related effective output (SW to SL)

capacitance

C_OSS,tr(ls)

V_DS(hs)= 0 V, V_DS(ls)= 0 V to 400 V

49.2

Q_RR(ls)

Reverse recovery charge

HIGH-SIDE GAN POWER FET

V_INH= 5 V, I_D(hs)= 1.75 A, T_J= 25°C

V_INH= 5 V, I_D(hs)= 1.75 A, T_J= 125°C

SW to DH current = 0.1 A

248

470

-2

R_DS(on)

Drain-source (DH to SW) on resistance

mΩ

(hs)

Source-drain (SW to DH) third-quadrant

voltage

V_SD(hs)

SW to DH current = 1 A

-2.7

1.4

V_DS(ls)= 0 V, V_DS(hs)= 650 V, T_J= 25 °C

V_DS(ls)= 0 V, V_DS(hs)= 650 V, T_J= 125 °C

I_DSS(hs)

Drain (DH to SW) leakage current

µA

Q_OSS(hs)Output (DH to SW) charge

15.51

22.4

C_OSS(hs)Output (DH to SW) capacitance

Output (DH to SW) capacitance stored

V_DS(ls)= 0 V, V_DS(hs)= 400 V

E_OSS(hs)

energy

2.15

26.9

µJ

C_OSS,er(hsEnergy related effective output (DH to

SW) capacitance

)

C_OSS,tr(hsTime related effective output (DH to SW)

V_DS(ls)= 0 V, V_DS(hs)= 0 V to 400 V

38.78

capacitance

)

Q_RR(hs)

LOW-SIDE OVERCURRENT PROTECTION

I_T(OC)(ls)

HIGH-SIDE OVERCURRENT PROTECTION

I_T(OC)(hs)

BOOTSTRAP RECTIFIER

Reverse recovery charge

5.4

5.9

3.5

6.4

Overcurrent fault –threshold current

V_INL= 5 V, V_{AUX_BST}= 1 V, T_J= 25°C

V_INL= 5 V, V_{AUX_BST}= 1 V, T_J= 125°C

V_INL= 5 V, V_{AUX_BST}= 7 V

R_DS(on)

AUX to BST on resistance

AUX to BST current limit

210

240

270

BST to AUX reverse current blocking

threshold

V_INL= 5 V

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1) Symbol definitions: V_DS(ls)= SW to SL voltage; I_DS(ls)= SW to SL current; V_DS(hs)= DH to SW voltage; I_D(hs)= DH to SW

current; 2) Unless otherwise noted: voltage, resistance, and capacitance are respect to AGND; -40 °C ≤T_J≤125 °C; 10 ≤

_AUX≤26; 7.5 ≤V_{BST_SW}≤26; V_EN= 5 V; V_INL= 0 V; V_INH= 0 V; R_RDRVL= 0 Ω; R_{RDRVH_SW}= 0 Ω; R_CS= 100 Ω

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_INL= 5 V, 0 A ≤I_D(ls)< I_T(OC)(ls), 0 V ≤

V_CS≤2 V

Current sense gain (I_CS(src)/ I_D(LS)

)

mA/A

V_INL= 5 V, 0 A ≤I_D(ls)< I_T(OC)(ls), 0 V ≤

V_CS≤2 V

Current sense input offset current

–50

Initial held output after overcurrent fault

occurs while INL remains high

V_INL= 5 V, 0 V ≤V_CS≤2 V

I_CS(src)

Final held output after overcurrent fault

occurs while INL remains high

15.5

(OC)(final)

V_INL= 5 V, I_D(ls)= 5 A, CS sinking 5 mA

from external source

Output clamp voltage

2.5

EN, INL, INH

V_IT+

Positive-going input threshold voltage

1.7

0.7

2.45

1.3

V_IT–

Negative-going input threshold voltage

Input threshold voltage hysteresis

Pull-down resistance

400

200

600

0 V ≤V_PIN≤3 V

kΩ

µA

Pull-down current

V_AUX= 26 V; 10 V ≤V_PIN≤26 V

OVER-TEMPERATURE PROTECTION

Temperature fault –postive-going

threshold temperature

150

130

°C

Temperature fault –negative-going

threshold temperature

Temperature fault –threshold

temperature hysteresis

FLT

Low-level output voltage

FLT sinking 1mA while asserted

V_FLT= V_AUXwhile de-asserted

200

µA

Off-state current

AUX

V_AUX,T+

8.9

8.6

9.3

9.0

9.7

9.4

UVLO –positive-going threshold voltage

(UVLO)

UVLO –negative-going threshold

voltage

250

µA

UVLO –threshold voltage hysteresis

Standby quiescent current

V_EN= 0 V

250

1370

370

Quiescent current

V_INL= 5 V, I_D(ls)= 0 A

V_INL= 0 V or 5 V, V_DS(ls)= 0 V, f_INL= 500

kHz, I_D(ls)= 0 A

Operating current

3.1

BST

V_{BST_SW,}

V_{BST_SW}UVLO for FET to turn on –

positive-going threshold voltage

6.7

4.8

7.3

T+(UVLO)

V_{BST_SW}UVLO for FET to stay on–

negative-going threshold voltage

5.1

5.4

100

Quiescent current

µA

V_INH= 5 V

330

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1) Symbol definitions: V_DS(ls)= SW to SL voltage; I_DS(ls)= SW to SL current; V_DS(hs)= DH to SW voltage; I_D(hs)= DH to SW

current; 2) Unless otherwise noted: voltage, resistance, and capacitance are respect to AGND; -40 °C ≤T_J≤125 °C; 10 ≤

_AUX≤26; 7.5 ≤V_{BST_SW}≤26; V_EN= 5 V; V_INL= 0 V; V_INH= 0 V; R_RDRVL= 0 Ω; R_{RDRVH_SW}= 0 Ω; R_CS= 100 Ω

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_INH= 0 V or 5 V, V_DS(hs)= 0 V; f_INH= 500

kHz

Operating current

1.2

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6.6 Switching Characteristics

1) Symbol definitions: V_DS(ls)= SW to SL voltage; I_DS(ls)= SW to SL current; V_DS(hs)= DH to SW voltage; I_D(hs)= DH to SW

current; 2) Unless otherwise noted: voltage, resistance, and capacitance are respect to AGND; -40 °C ≤T_J≤125 °C; 10 ≤

_AUX≤26; 7.5 ≤V_{BST_SW}≤26; V_EN= 5 V; V_INL= 0 V; V_INH= 0 V; R_RDRVL= 0 Ω; R_{RDRVH_SW}= 0 Ω; R_CS= 100 Ω

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LOW-SIDE GAN POWER FET

From V_INL> V_INL,IT+to I_D(ls)> 50 mA,

V_BUS= 400 V, L_HBcurrent = 2 A, at below

low-side slew rate settings, see GaN

Power FET Switching Parameters

t_d(on)

Drain current turn-on delay time

slew rate setting 0 (slowest)

slew rate setting 1

(Idrain)(ls)

slew rate setting 2

slew rate setting 3 (fastest)

From V_INL> V_INL,IT+to V_DS(ls)< 320 V,

V_BUS= 400 V, L_HBcurrent = 2 A, at below

low-side slew rate settings, see GaN

Power FET Switching Parameters

t_d(on)(ls)

Turn-on delay time

slew rate setting 0 (slowest)

slew rate setting 1

slew rate setting 2

slew rate setting 3 (fastest)

From V_DS(ls)< 320 V to V_DS(ls)< 80 V,

V_BUS= 400 V, L_HBcurrent = 2 A, at below

low-side slew rate settings, see GaN

Power FET Switching Parameters

t_r(on)(ls)

Turn-on rise time

slew rate setting 0 (slowest)

slew rate setting 1

14.9

5.6

3.8

1.9

slew rate setting 2

slew rate setting 3 (fastest)

From V_INL< V_INL,IT–to V_DS(ls)> 80 V,

V_BUS= 400 V, L_HBcurrent = 2 A,

(independent of slew rate

setting), see GaN Power FET Switching

Parameters

t_d(off)(ls)

Turn-off delay time

Turn-off fall time

From V_DS(ls)> 80 V to V_DS(ls)> 320 V,

V_BUS= 400 V, L_HBcurrent = 2 A,

(independent of slew rate

t_f(off)(ls)

12.5

setting), see GaN Power FET Switching

Parameters

From V_DS(ls)< 250 V to V_DS(ls)< 150 V, T_J

= 25 ℃, V_BUS= 400 V, L_HBcurrent = 2 A,

at below low-side slew rate

settings, see GaN Power FET Switching

Parameters

Turn-on slew rate

slew rate setting 0 (slowest)

slew rate setting 1

V/ns

slew rate setting 2

slew rate setting 3 (fastest)

140

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1) Symbol definitions: V_DS(ls)= SW to SL voltage; I_DS(ls)= SW to SL current; V_DS(hs)= DH to SW voltage; I_D(hs)= DH to SW

current; 2) Unless otherwise noted: voltage, resistance, and capacitance are respect to AGND; -40 °C ≤T_J≤125 °C; 10 ≤

_AUX≤26; 7.5 ≤V_{BST_SW}≤26; V_EN= 5 V; V_INL= 0 V; V_INH= 0 V; R_RDRVL= 0 Ω; R_{RDRVH_SW}= 0 Ω; R_CS= 100 Ω

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

HIGH-SIDE GAN POWER FET

From V_INH> V_INH,IT+to I_D(hs)> 50 mA,

V_BUS= 400 V, L_HBcurrent = 2 A, at below

high-side slew rate settings, see GaN

Power FET Switching Parameters

t_d(on)

Drain current turn-on delay time

slew rate setting 0 (slowest)

slew rate setting 1

(Idrain)(hs)

slew rate setting 2

slew rate setting 3 (fastest)

From V_INH> V_INH,IT+to V_DS(hs)< 320 V,

V_BUS= 400 V, L_HBcurrent = 2 A, at below

high-side slew rate settings, see GaN

Power FET Switching Parameters

t_d(on)(hs)Turn-on delay time

slew rate setting 0 (slowest)

slew rate setting 1

slew rate setting 2

slew rate setting 3 (fastest)

From V_DS(hs)< 320 V to V_DS(hs)< 80 V,

V_BUS= 400 V, L_HBcurrent = 2 A, at below

high-side slew rate settings, see GaN

Power FET Switching Parameters

t_r(on)(hs)

Turn-on rise time

slew rate setting 0 (slowest)

slew rate setting 1

13.1

4.7

3.2

1.7

slew rate setting 2

slew rate setting 3 (fastest)

From V_INH< V_INH,IT–to V_DS(hs)> 80 V,

V_BUS= 400 V, L_HBcurrent = 2 A,

(independent of slew rate

setting), see GaN Power FET Switching

Parameters

t_d(off)(hs)Turn-off delay time

From V_DS(hs)> 80 V to V_DS(hs)> 320 V,

V_BUS= 400 V, L_HBcurrent = 2 A,

(independent of slew rate

t_f(off)(hs)

Turn-off fall time

12.5

setting), see GaN Power FET Switching

Parameters

From V_DS(hs)< 250 V to V_DS(hs)< 150 V,

T_J= 25 ℃, V_BUS= 400 V, L_HBcurrent = 2

A, at below high-side slew rate

settings, see GaN Power FET Switching

Parameters

Turn-on slew rate

slew rate setting 0 (slowest)

slew rate setting 1

V/ns

slew rate setting 2

slew rate setting 3 (fastest)

165

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1) Symbol definitions: V_DS(ls)= SW to SL voltage; I_DS(ls)= SW to SL current; V_DS(hs)= DH to SW voltage; I_D(hs)= DH to SW

current; 2) Unless otherwise noted: voltage, resistance, and capacitance are respect to AGND; -40 °C ≤T_J≤125 °C; 10 ≤

_AUX≤26; 7.5 ≤V_{BST_SW}≤26; V_EN= 5 V; V_INL= 0 V; V_INH= 0 V; R_RDRVL= 0 Ω; R_{RDRVH_SW}= 0 Ω; R_CS= 100 Ω

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

From I_CS> 0.1*I_{CS(src)(final)}to I_CS

0.9*I_{CS(src)(final)}, Low-side enabled into a 2

Settling time

A load, 0 V ≤V_CS≤2 V,

V_INL= 5 V, From V_EN> V_IT+to I_D(ls)> 10

EN wake-up time

µs

BST

From V_{BST_SW}≥V_{BST_SW,T+(UVLO)}to

high-side reacts to INH rising edge with

V_{BST_SW}rising from 0 V to 10 V in 1 µs

Start-up time from deep BST to SW

discharge

µs

From V_{BST_SW}≥V_{BST_SW,T+(UVLO)}to

high-side reacts to INH rising edge with

V_{BST_SW}rising from 5 V to 10 V in 0.5 µs

Start-up time from shallow BST to SW

discharge

6.7 Typical Characteristics

1.75

1.5

1.75

1.5

1.25

0.75

0.5

0.75

0.5

-40

-20

100 120 140

-40

-20

100 120 140

Junction Temperature (°C)

图6-1. Low-Side Normalized On-Resistance vs Junction

图6-2. High-Side Normalized On-Resistance vs Junction

Temperature

4.5

3.5

2.5

1.5

0.5

50 100 150 200 250 300 350 400 450 500 550 600

Drain-Source Voltage (V)

图6-3. Low-Side Output Capacitance vs Drain-Source Voltage

图6-4. Low-Side Output Capacitance Stored Energy vs Drain-

Source Voltage

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6.7 Typical Characteristics (continued)

120

100

4.5

3.5

2.5

1.5

0.5

50 100 150 200 250 300 350 400 450 500 550 600

Drain-Source Voltage (V)

50 100 150 200 250 300 350 400 450 500 550 600

Drain-Source Voltage (V)

图6-5. High-Side Output Capacitance vs Drain-Source Voltage

图6-6. High-Side Output Capacitance Stored Energy vs Drain-

Source Voltage

100

Slew Rate 0

Slew Rate 1

Slew Rate 2

Slew Rate 3

Slew Rate 0

Slew Rate 1

Slew Rate 2

Slew Rate 3

-40

-20

100 120 140

-40

-20

100 120 140

Junction Temperature (°C)

图6-8. Low-Side Turn-On Delay Time vs Junction Temperature

图6-7. Low-Side Drain Current Turn-On Delay Time vs Junction

Temperature

250

Slew Rate 0

Slew Rate 1

Slew Rate 2

Slew Rate 3

200

Slew Rate 0

Slew Rate 1

Slew Rate 2

Slew Rate 3

150

100

-40

-20

100 120 140

-20

100 120 140

Junction Temperature (°C)

JUnction Temperature (°C)

图6-10. Low-Side Turn-On Slew Rate vs Junction Temperature

图6-9. Low-Side Turn-On Rise Time vs Junction Temperature

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6.7 Typical Characteristics (continued)

Slew Rate 0

Slew Rate 1

Slew Rate 2

Slew Rate 3

-40

-20

100 120 140

-40

-20

100 120 140

Junction Temperature (°C)

图6-11. Low-Side Turn-Off Delay Time vs Junction Temperature

图6-12. High-Side Drain Current Turn-On Delay Time vs

Junction Temperature

Slew Rate 0

Slew Rate 1

Slew Rate 2

Slew Rate 3

Slew Rate 0

Slew Rate 1

Slew Rate 2

Slew Rate 3

-40

-20

100 120 140

-40

-20

100 120 140

Junction Temperature (°C)

图6-13. High-Side Turn-On Delay Time vs Junction Temperature 图6-14. High-Side Turn-On Rise Time vs Junction Temperature

250

200

150

100

Slew Rate 0

Slew Rate 1

Slew Rate 2

Slew Rate 3

-40

-20

100 120 140

-40

-20

100 120 140

Junction Temperature (°C)

图6-15. High-Side Turn-On Slew Rate vs Junction Temperature

图6-16. High-Side Turn-Off Delay Time vs Junction Temperature

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6.7 Typical Characteristics (continued)

-40

-20

100 120 140

Junction Temperature (°C)

INL = 0 V

图6-17. AUX Standby Current vs Junction Temperature

图6-18. AUX Quiescent Current vs Junction Temperature

2000

1800

1600

1400

1200

1000

3.5

2.5

1.5

100

-40

-20

100 120 140

150

200

250

300

350

400

450

500

Junction Temperature (°C)

Frequency (kHz)

INL = 5 V

图6-20. AUX Operating Current vs Frequency

图6-19. AUX Quiescent Current vs Junction Temperature

600

550

500

450

400

350

300

250

200

-40

-20

100 120 140

-40

-20

100 120 140

Junction Temperature (°C)

INH = 5 V

INH = 0 V

图6-22. BST Quiescent Current vs Junction Temperature

图6-21. BST Quiescent Current vs Junction Temperature

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6.7 Typical Characteristics (continued)

1.4

1.2

0.8

0.6

0.4

100

150

200

250

300

350

400

450

500

Frequency (kHz)

图6-23. BST Operating Current vs Junction Temperature

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7 Parameter Measurement Information

7.1 GaN Power FET Switching Parameters

图7-1 shows the circuit used to measure the GaN power FET switching parameters. The circuit is operated as a

double-pulse tester. Consult external references for double-pulse tester details. The circuit is placed in the boost

configuration to measure the low-side GaN switching parameters. The circuit is placed in the buck configuration

to measure the high-side GaN switching parameters. The GaN FET not being measured in each configuration

(high-side in the boost and low-side in the buck) acts as the double-pulse tester diode and circulates the inductor

current in the off-state, third-quadrant conduction mode. 表7-1 shows the details for each configuration.

LMG2610

BST

C_BST

RDRVH

NC4

V_DS(hs)

PADH

C_BULK

L_HB

–

PADH

AUX

FLT

V_BUS

C_AUX

INH

INL

V_DS(ls)

–

V_AUX

–

RDRVL

–

AGND

PADL

AGND

PGND

图7-1. GaN Power FET Switching Parameters Test Circuit

表7-1. GaN Power FET Switching Parameters Test Circuit Configuration Details

Configuration

Boost

GaN FET Under

Test

GaN FET Acting S_BOOST

as Diode

S_BUCK

V_INL

V_INH

Low-side

High-side

Closed

Open

Closed

Double-pulse

0 V

waveform

0 V

Buck

High-side

Low-side

Open

Double-pulse

waveform

图7-2 shows the GaN power FET switching parameters.

The GaN power FET turn-on transition has three timing components: drain-current turn-on delay time, turn-on

delay time, and turn-on rise time. Note that the turn-on rise time is the same as the V_DS80% to 20% fall time. All

three turn-on timing components are a function of the RDRVx pin setting.

The GaN power FET turn-off transition has two timing components: turn-off delay time, and turn-off fall time.

Note that the turn-off fall time is the same as the V_DS20% to 80% rise time. The turn-off timing components are

independent of the RDRVx pin setting, but heavily dependent on the L_HBcurrent.

The turn-on slew rate is measured over a smaller voltage delta (100 V) compared to the turn-on rise time voltage

delta (240 V) to obtain a faster slew rate which is useful for EMI design. The RDRVx pin is used to program the

slew rate.

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INx

V_INx,IT+

V_INx,IT-

0 V

t_{d(on)(Idrain)}

I_D

2 A

0 A

50 mA

t_d(on)

t_d(off)

t_r(on)

t_f(off)

400 V

320 V

V_DS

250 V

150 V

80 V

Slew Rate

Calculation

Points

0 V

图7-2. GaN Power FET Switching Parameters

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8 Detailed Description

8.1 Overview

The LMG2610 is a highly-integrated 650-V GaN power-FET half bridge intended for use in active-clamp flyback

(ACF) converters. The LMG2610 combines the half-bridge power FETs, gate drivers, low-side current-sense

emulation function, high-side gate-drive level shifter, and bootstrap diode function in a 9-mm by 7-mm QFN

package.

The 650-V rated GaN power FETs support the large transformer turns ratios needed to minimize the secondary-

side synchronous-rectifier voltage requirements in flyback converter applications. The GaN half-bridge low

output-capacitive charge reduces both the time and energy needed for ACF zero-voltage switching (ZVS) and is

the key characteristic needed to create small, efficient power converters.

The GaN half-bridge consists of a 170-mΩ low-side FET and a 248-mΩ high-side FET. The asymmetric GaN

half-bridge FET sizes are a good utilization of total GaN FET size for ACF operating conditions.

The LMG2610 internal gate drivers regulate the drive voltage for optimum GaN power-FET on-resistance.

Internal drivers also reduce total gate inductance and GaN FET common-source inductance for improved

switching performance, including common-mode transient immunity (CMTI). The low-side / high-side GaN FET

turn-on slew rates can be individually programmed to one of four discrete settings for design flexibility with

respect to power loss, switching-induced ringing, and EMI.

Current-sense emulation places a scaled replica of the low-side drain current on the output of the CS pin. The

CS pin is terminated with a resistor to AGND to create the current-sense input signal to the external power

supply controller. This CS pin resistor replaces the traditional current-sense resistor, placed in series with the

low-side GaN FET source, at significant power and space savings. Furthermore, with no current-sense resistor

in series with the GaN source, the low-side GaN FET thermal pad can be connected directly to the PCB power

ground. This thermal pad connection both improves system thermal performance and provides additional device

routing flexibility since full device current can be conducted through the thermal pads.

The high-side gate-drive level-shifter reduces the capacitive coupling of the sensitive high-side gate drive path

for lower noise susceptibility and better CMTI compared to external solutions where the signal path has a much

larger PCB footprint. The level shifter also has minimal impact on device quiescent current and no impact on

device start-up time compared to external solutions with worse quiescent current and start up performance.

The bootstrap diode function between AUX and BST is implemented with a smart-switched GaN bootstrap FET.

The switched GaN bootstrap FET allows more complete charging of the BST-to-SW capacitor since the on-state

GaN bootstrap FET does not have the forward voltage drop of a traditional bootstrap diode. The smart-switched

GaN bootstrap FET also avoids the traditional bootstrap diode problem of BST-to-SW capacitor overcharging

due to off-state third-quadrant current flow in the low-side half-bridge GaN power FET. Finally, the bootstrap

function has more efficient switching due to low capacitance and no reverse-recovery charge compared to the

traditional bootstrap diode.

The AUX input supply wide voltage range is compatible with the corresponding wide range supply rail created by

power supply controllers. The BST input supply range is even wider on the low end to account for capacitive

droop in between bootstrap recharge cycles. Low AUX / BST idle quiescent currents and fast BST start-up time

support converter burst-mode operation critical for meeting government light-load efficiency mandates. Further

AUX quiescent current reduction is obtained by placing the device in standby mode with the EN pin.

The INL, INH, and EN control pins have high input impedance, low input threshold voltage and maximum input

voltage equal to the AUX voltage. This allows the pins to support both low voltage and high voltage input signals

and be driven with low-power outputs.

The LMG2610 protection features are low-side / high-side under-voltage lockout (UVLO), low-side / high-side

input gate-drive interlock, low-side / high-side cycle-by-cycle current limit, and over-temperature shut down. The

UVLO features also help achieve well-behaved converter operation. The over-temperature shut down is reported

on the open drain FLT output.

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8.2 Functional Block Diagram

BST

INH

Level-Shifter

Receiver

inh_receive

GaN

FET

bst_uvlo

hs_fet_enable

HS FET

Control

HS FET

Driver

HS Fault

Monitor

hs_slew_rate_set

hs_over_current

hs_rdrv_det

HS RDRV

Detector

RDRVH

hs_current_sense

Bootstrap

GaN

PADH

FET

Bootstrap

Control

inh_transmit

INH

Level-Shifter

Transmitter

AUX

ls_inh_transmit

FLT

INH

INL

INH_pass

INL_pass

GaN

FET

Interlock

ls_fet_on

ls_fet_enable

ls_slew_rate_set

LS FET

Driver

LS FET

Control

aux_uvlo

LS Fault

Monitor

over_temp

ls_over_current

ls_rdrv_det

LS RDRV

Detector

RDRVL

ls_current_sense

AGND

Current

Emulation

PADL

AGND

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8.3 Feature Description

8.3.1 GaN Power FET Switching Capability

Due to the silicon FET’s long reign as the dominant power-switch technology, many designers are unaware

that the nameplate drain-source voltage cannot be used as an equivalent point to compare devices across

technologies. The nameplate drain-source voltage of a silicon FET is set by the avalanche breakdown voltage.

The nameplate drain-source voltage of a GaN FET is set by the long term compliance to data sheet

specifications.

Exceeding the nameplate drain-source voltage of a silicon FET can lead to immediate and permanent damage.

Meanwhile, the breakdown voltage of a GaN FET is much higher than the nameplate drain-source voltage. For

example, the breakdown drain-source voltage of the LMG2610 GaN power FET is more than 800 V which allows

the LMG2610 to operate at conditions beyond an identically nameplate rated silicon FET.

The LMG2610 GaN power FET switching capability is explained with the assistance of 图 8-1. The figure shows

the drain-source voltage versus time for the LMG2610 GaN power FET for four distinct switch cycles in a

switching application. No claim is made about the switching frequency or duty cycle. The first two cycles show

normal operation and the second two cycles show operation during a rare input voltage surge. The LMG2610

GaN power FETs are intended to be turned on in either zero-voltage switching (ZVS) or discontinuous-

conduction mode (DCM) switching conditions.

V_{DS(tr)(surge)}= 800 V

V_DS(surge)= 720 V

V_DS(tr)= 650 V

V_DS= 520 V

t₁

Normal

ZVS Cycle

Normal

DCM Cycle

Surge

ZVS Cycle

Surge

DCM Cycle

t₀

t₂

t₀

t₂

t₀

t₂

t₀

t₂

图8-1. GaN Power FET Switching Capability

Each cycle starts before t₀with the FET in the on state. At t₀the GaN FET turns off and parasitic elements cause

the drain-source voltage to ring at a high frequency. The high frequency ringing has damped out by t₁. Between

t₁and t₂the FET drain-source voltage is set by the characteristic response of the switching application. The

characteristic is shown as a flat line (plateau), but other responses are possible. At t₂the GaN FET is turned on.

For normal operation, the transient ring voltage is limited to 650 V and the plateau voltage is limited to 520 V. For

rare surge events, the transient ring voltage is limited to 800 V and the plateau voltage is limited to 720 V.

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8.3.2 Turn-On Slew-Rate Control

The turn-on slew rate of both the low-side and high-side GaN power FETs are individually programmed to one of

four discrete settings. The low-side slew rate is programmed by the resistance between the RDRVL and AGND

pins. The high-side slew rate is programmed by the resistance between the RDRVH and SW pins. The low-side

slew-rate setting is determined one time during AUX power up when the AUX voltage goes above the AUX

Power-On Reset voltage. The high-side slew-rate setting is determined one time during BST-to-SW power up

when the BST-to-SW voltage goes above the BST Power-On Reset voltage. The slew-rate setting determination

time is not specified but is around 0.4 us.

表 8-1 shows the recommended typical resistance programming value for the four slew rate settings and the

typical turn-on slew rate at each setting. As noted in the table, an open-circuit connection is acceptable for

programming slew-rate setting 0 and a short-circuit connection (RDRVL shorted to AGND for the low-side turn-

on slew rate) (RDRVH shorted to SW for the high-side turn-on slew rate) is acceptable for programming slew-

rate setting 3.

表8-1. Slew-Rate Setting

Turn-On Slew Rate

Setting

Recommended Typical

Programming Resistance

Typical LS / HS Turn-

On Slew Rate

Comment

(V/ns)

(kΩ)

Open-circuit connection for programming

resistance is acceptable.

120

20 / 20

50 / 65

70 / 90

Short-circuit connection for programming

resistance (RDRVL shorted to AGND for low-side

slew rate) (RDRVH shorted to SW for high-side

slew rate) is acceptable.

5.6

140 / 165

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8.3.3 Current-Sense Emulation

The current-sense emulation function creates a scaled replica of the low-side GaN power FET positive drain

current at the output of the CS pin. The current-sense emulation gain, G_CSE, is 1 mA output from the CS pin, I_CS

for every 1 A passing into the drain of the low-side GaN power FET, I_D.

G_CSE= I_CS/ I_D= 1 mA / 1 A = 0.001

(1)

The CS pin is terminated with a resistor to AGND, R_CS, to create the current-sense voltage input signal to the

external power supply controller.

R_CSis determined by solving for the traditional current-sense design resistance, R_CS(trad), and multiplying by the

inverse of G_CSE. The traditional current-sense design creates the current-sense voltage, V_CS(trad), by passing the

low-side GaN power FET drain current, I_D, through R_CS(trad). The LMG2610 creates the current-sense voltage,

V_CS, by passing the CS pin output current, I_CS, through R_CS. The current-sense voltage must be the same for

both designs.

V_CS= I_CS* R_CS= V_CS(trad)= I_D* R_CS(trad)

R_CS= I_D/ I_CS* R_CS(trad)= 1 / G_CSE* R_CS(trad)

R_CS= 1000 * R_CS(trad)

(2)

(3)

(4)

The CS pin is clamped internally to a typical 2.5 V. The clamp protects vulnerable power-supply controller

current-sense input pins from over voltage if, for example, the current sense resistor on the CS pin were to

become disconnected.

图 8-2 shows the current-sense emulation operation. In both cycles, the CS pin current emulates the low-side

GaN power-FET drain current while the low-side FET is enabled. The first cycle shows normal operation where

the controller turns off the low-side GaN power FET when the controller current-sense input threshold is tripped.

The second cycle shows a fault situation where the LMG2610 Over-Current Protection turns off the low-side

GaN power FET before the controller current-sense input threshold is tripped. In this second cycle, the LMG2610

avoids a hung controller INL pulse by generating a fast-ramping artificial current-sense emulation signal to trip

the controller current-sense input threshold. The artificial signal persists until the INL pin goes to logic-low which

indicates the controller is back in control of switch operation.

Cycle without

Over-Current

Protection

Cycle with

Over-Current

Protection

INL Logic High

INL = PWM

Signal from

Controller

INL Logic Low

FET On

Low-Side

FET Enable

FET Off

I_T(OC)

Low-Side FET

Drain Current

0 A

Effective Controller

Current-Sense

Input Threshold

CS Pin

Current

0 A

Artificial Current-Sense

Emulation Signal

图8-2. Current-Sense Emulation Operation

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8.3.4 Bootstrap Diode Function

The internal bootstrap diode function is implemented with a smart-switched GaN bootstrap FET. The GaN

bootstrap FET blocks current in both directions between AUX and BST when The GaN bootstrap FET is turned

off.

The bootstrap diode function is active when the low-side GaN power FET is turned on and inactive when the

low-side GaN power FET is turned off. The GaN bootstrap FET is held off in the bootstrap diode inactive phase.

The GaN bootstrap FET is turned on a single time at the beginning of the bootstrap active phase and is

controlled as an ideal diode with diode current flowing from AUX to BST to charge the BST-to-SW capacitor. If a

small reverse current from BST to AUX is detected after the GaN bootstrap FET is turned on, the GaN bootstrap

FET is turned off for the remainder of the bootstrap active phase.

The bootstrap diode function implements a current limit to protect the GaN bootstrap FET when the BST-to-SW

capacitor is significantly discharged at the beginning of the bootstrap active phase. If there is no current limit

situation during the GaN bootstrap FET turn on, or if the bootstrap function drops out of current limit as the BST-

to-SW capacitor charges, the current limit function is disabled for the remainder of the GaN bootstrap FET turn-

on time. The current limit function is disabled to save quiescent current.

8.3.5 Input Control Pins (EN, INL, INH)

The EN pin is used to toggle the device between the active and standby modes described in Device Functional

Modes.

The INL pin is used to turn the low-side GaN power FET on and off.

The INH pin is used to turn the high-side GaN power FET on and off.

The input control pins have a typical 1-V input-voltage-threshold hysteresis for noise immunity. The pins also

have a typical 400 kΩ pull-down resistance to protect against floating inputs. The 400 kΩ saturates for typical

input voltages above 4 V to limit the maximum input pull-down current to a typical 10 uA.

The INL turn-on action is impacted by the following conditions 1) Standby Mode, 2) AUX UVLO, 3) INH in control

of Interlock, 4) Low-Side Over-Current Protection, and 5) Over-Temperature Protection.

The INH turn-on action is impacted by the following conditions 1) Standby Mode, 2) AUX UVLO, 3) INL in control

of Interlock, 4) High-Side Over-Current Protection, and 5) Over-Temperature Protection.

The Standby Mode, AUX UVLO, and Over-Temperature Protection are the universal INL / INH blocking

conditions. These conditions hold both GaN half-bridge power FETs off independent of INL and INH. 图 8-3

shows the Universal Blocking Condition Operation. Note that the high-side FET does not turn on at transistion

#4. INH only turns on the high-side FET if there is no universal blocking condition when INH goes to logic high.

This avoids an incomplete high-side FET turn-on period which can create undesired spike voltages in the

converter.

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INL Logic High

INL

INL Logic Low

INH Logic High

INH

INH Logic Low

Universal

Blocking

Condition

Blocking Condition Asserted

Blocking Condition De-Asserted

Low-Side FET On

Low-Side FET Off

High-Side FET On

Low-Side

FET Enable

High-Side

FET Enable

High-Side FET Off

图8-3. Universal INL / INH Blocking Condition Operation

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8.3.6 INL - INH Interlock

The interlock function keeps the low-side and high-side GaN power FETs from being simultaneously turned on

when the INL and INH pins are both logic-high. Either the INL or the INH pin gains control of the interlock if it is

logic high when the other pin is logic low. Once the INL or INH pin gains control of the interlock, it retains control

as long as it remains logic high. Only the INL or INH pin in control of the interlock passes a logic-high signal

through the interlock.

The interlock is disabled if any of the universal INL / INH blocking conditions defined in Input Control Pins are

asserted. When the interlock is disabled, the interlock outputs are held at logic low. If both INL and INH are logic-

high when the interlock is enabled, the INL takes priority, gains control of the interlock, and passes the INL logic-

high signal through the interlock.

8.3.7 AUX Supply Pin

The AUX pin is the input supply for the low-side internal circuits and is the power source to charge the BST-to-

SW capacitor through the internal bootstrap diode function.

8.3.7.1 AUX Power-On Reset

The AUX Power-On Reset disables all low-side functionality if the AUX voltage is below the AUX Power-On

Reset voltage. The AUX Power-On Reset voltage is not specified but is around 5 V. The AUX Power-On Reset

initates the one-time determination of the low-side slew-rate setting programmed on the RDRVL pin if the AUX

voltage goes above the AUX Power-On Reset voltage. The AUX Power-On Reset enables the over-temperature

protection function if the AUX voltage is above the AUX Power-On Reset voltage.

8.3.7.2 AUX Under-Voltage Lockout (UVLO)

The AUX UVLO holds off both the low-side and high-side GaN power FETs if the AUX voltage is below the AUX

UVLO voltage. The AUX UVLO voltage is set higher than the BST UVLO voltage so the high-side GaN power

FET can be operated when the low-side GaN power FET is operating. The voltage separation between the AUX

UVLO voltage and BST UVLO voltage accounts for operating conditions where the bootstrap charging of the

BST-to-SW capacitor from the AUX supply is incomplete. The AUX UVLO voltage hysteresis prevents on-off

chatter near the UVLO voltage trip point.

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8.3.8 BST Supply Pin

The BST pin is the input supply for the high-side internal circuits. The BST pin and corresponding high-side

circuits are referenced to the SW pin. The BST pin is powered by the low-side AUX Supply pin through the

internal bootstrap diode function. The bootstrap function is inactive when the low-side GaN FET is off and the

BST pin must rely on an external BST-to-SW capacitor for the BST power source.

Designing the BST-to-SW capacitance is a trade-off between high-side charge-up time and hold-up time. The

BST-to-SW external capacitance is recommended to be a ceramic capacitor that is at least 10 nF over operating

conditions.

8.3.8.1 BST Power-On Reset

The BST Power-On Reset voltage is with respect to the SW pin. The BST Power-On Reset disables all high-side

functionality if the BST-to-SW voltage is below the BST Power-On Reset voltage. The BST Power-On Reset

voltage is not specified but is around 5 V. The BST Power-On Reset initiates the one-time determination of the

high-side slew-rate setting programmed on the RDRVH pin if the BST-to-SW voltage goes above the BST

Power-On Reset voltage.

8.3.8.2 BST Under-Voltage Lockout (UVLO)

The BST UVLO voltage is with respect to the SW pin. The BST UVLO only controls the high-side GaN power

FET. The BST UVLO does not control the low-side GaN power FET. The BST UVLO consists of two separate

UVLO functions to create a two-level BST UVLO. The upper BST UVLO is called the BST Turn-On UVLO and

only controls if the high-side GaN power FET is turned on. The lower BST UVLO is called the BST Turn-Off

UVLO and only controls if the high-side GaN power FET is turned off after the high-side GaN power FET is

turned on. The operation of the two-level UVLO is not the same as a single UVLO with wide hysteresis.

图 8-4 shows the BST UVLO operation. The BST Turn-On UVLO prevents the high-side GaN power FET from

turning on at a INH logic-high rising edge if the BST-to-SW voltage is below the BST Turn-On UVLO voltage -

INH pulses #1, #2, and #5. After the high-side GaN power FET is successfully turned-on, the BST Turn-On

UVLO is ignored and the BST Turn-Off UVLO output is watched for the remainder of the INH logic-high pulse -

INH pulses #3, #4, and #6. The BST Turn-Off UVLO turns off the high-side GaN power FET for the remainder of

the INH logic-high pulse if the BST-to-SW voltage falls below the BST Turn-Off UVLO voltage - INH pulse #6.

BST Turn-On UVLO

BST-to-SW

BST Turn-Off UVLO

INx Logic High

Voltage

INH

INx Logic Low

FET On

High-Side

FET Enable

FET Off

图8-4. BST UVLO Operation

The effective voltage hysteresis of the two-level BST UVLO is the difference between the upper and lower BST

UVLO voltages. A single-level BST UVLO can be implemented with the same hysteresis but allows subsequent

high-side GaN power FET turn on anywhere in the hysteresis range. The two-level UVLO design prevents any

turn on in the hysteresis range. A single-level BST UVLO would allow INH pulse #5 to turn on the high-side GaN

power FET.

The two-level BST UVLO allows a wide hysteresis while making sure the BST-to-SW capacitor is adequately

charged at the beginning of every INH pulse. The wide hysteresis allows a smaller BST-to-SW capacitor to be

used which is useful for faster high-side start-up time. The adequate capacitor charge at the beginning of the

INH pulse helps make sure the high-side GaN power FET is not turned-off early in the INH pulse which can

create undesired spike voltages in the converter.

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8.3.9 Over-Current Protection

The LMG2610 implements cycle-by-cycle over-current protection for both half-bridge GaN power FETs. 图 8-5

shows the cycle-by-cycle over-current operation. Every INx logic-high cycle turns on the GaN power FET. If the

GaN power FET drain current exceeds the over-current threshold current, the over-current protection turns off

the GaN power FET for the remainder of the INx logic-high duration.

INx Logic High

INx

INx Logic Low

I_T(OC)

FET Drain Current

0 A

FET On

FET Enable

FET Off

图8-5. Cycle-by-Cycle Over-Current Protection Operation

An over-current protection event is not reported on the FLT pin. Cycle-by-cycle over-current protection minimizes

system disruption because the event is not reported and because the protection allows the GaN power FET to

turn on every INx cycle.

The low-side / high-side over-current protection threshold currents are set to different levels corresponding to the

different GaN power FET sizes. As described in Current-Sense Emulation, an artificial CS pin current is

produced after the low-side GaN power FET is turned off by the low-side over-current protection, to prevent the

controller from entering a hung state.

8.3.10 Over-Temperature Protection

The over-temperature protection holds off both the low-side and high-side GaN power FETs if the LMG2610

temperature is above the over-temperature shut-down temperature. The over-temperature shut-down hysteresis

avoids erratic thermal cycling. An over-temperature fault is reported on the FLT pin when the over-temperature

protection is asserted. This is the only fault event reported on the FLT pin. The over-temperature protection is

enabled when the AUX voltage is above the AUX Power-On Reset voltage. The low AUX Power-On Reset

voltage helps the over-temperature protection remain operational when the AUX rail droops during the cool-

down phase.

8.3.11 Fault Reporting

The LMG2610 only reports an over-temperature fault. An over-temperature fault is reported on the FLT pin when

the Over-Temperature Protection function is asserted. The FLT pin is an active low open-drain output so the pin

pulls low when there is an over-temperature fault.

8.4 Device Functional Modes

The LMG2610 has two modes of operation controlled by the EN pin. The device is in Active mode when the EN

is logic high and in Standby mode when the EN pin is logic low. In active mode, the half-bridge GaN power FETs

are controlled by the INL and INH pins. In Standby mode, the INL and INH pins are ignored, the half-bridge GaN

power FETs are held off, and the AUX quiescent current is reduced to the AUX standby quiescent current.

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9 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The LMG2610 is a GaN power-FET half bridge intended for use in off-line active-clamp flyback (ACF)

converters. The LMG2610 provides plug-and-play simplicity since it integrates the half-bridge FETs, FET gate

drivers, high-side gate-drive level shifter, bootstrap diode function, and current-sense emulation in a single

package. The typical application example shows the LMG2610 pairing seamlessly with the Texas Instruments

UCC28782 ACF controller to create a high-power-density, high-efficiency, 65-W, USB-PD charger.

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9.2 Typical Application

L_DAMPR_DAMP

V_O

Transformer

D_BG

F_AC

V_BUS

V_BULK

V_AC

Q_PD

L_K

L_O

C_X

C_BULK

R_BLEED

C_CLAMP

L_M

N_P

N_S

R_CO1

C_O1

C_REG

R_CO2

C_O2

R_OCP

Q_SEC

GND

R_DSC

LMG2610

BST

VD VG VS

V_O

SR Controller

REG

VDD

C_BST

RDRVH

R_XCD1

R_XCD2

NC4

V_P13

PADH

Q_S

Q_XCD

V_P13

C_DIFF

PADH

V_S13

C_AUX

AUX

FLT

D_SWS

R_BIAS1

FLT

R_DIFF

RUN

R_SWS

PWMH

PWML

INH

INL

V_SWS

C_SWS

V_RCS

RDRVL

R_BIAS2

AGND

PADL

AGND

PGND

C_INT

R_INT

V_BIN

D_AUX

L_B

D_B

C_BIN1

C_BIN2

C_VDD1

N_A

V_P13

V_S13

D_P13

D_BIN

C_VDD2

C_P13

R_VS1

R_VS2

XCD

BIN BGND BSW

VDD

P13

S13

SWS

V_SWS

RUN

XCD

V_REF

RUN

UCC28782

PWMH

PWML

PGND

PWML

BUR

SET

REF

FB RDM RTZ EP AGND FLT

FLT

IPC CS

R_OPP

V_RCS

V_REF

C_FB

C_REF

C_CS

AGND

R_FB

图9-1. 65-W USB-PD Charger Application

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9.2.1 Design Requirements

表9-1. Electrical Performance Specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT CHARACTERISTICS

V_IN

Input line voltage (RMS)

Input line frequency

90 115 / 230

264

f_LINE

50 / 60

V_IN= 230 V_RMS, I_O= 0 A

Input power at no-load,

V_O= 5 V

P_STBY

V_IN= 115 V_RMS, I_O= 0 A

V_IN= 230 V_RMS, P_O= 250 mW

V_IN= 115 V_RMS, P_O= 250 mW

399

359

470

Input power at 0.25-W load,

V_O= 20 V

P_0.25W

OUTPUT CHARACTERISTICS

Output voltage, 20-V setting

V_IN= 90 to 264 V_RMS, I_O= 0 A to 3.25 A

V_IN= 90 to 264 V_RMS, I_O= 0 A to 3 A

19.95

15.06

9.05

Output voltage, 15-V setting

Output voltage, 9-V setting

Output voltage, 5-V setting

V_O

5.05

Full-load rated output current,

20-V setting

3.25

I_O(FL)

V_IN= 90 to 264 V_RMS, V_O= 20 V

Full-load rated output current,

15-V, 9-V, 5-V settings

3.00

150

I_O(FL2)

V_IN= 90 to 264 V_RMS, V_O= 15 V, 9 V, 5 V

Output ripple voltage, peak to

peak

20-V setting

600 mVpp

V_IN= 90 to 264 V_RMS, I_O= 0 A to 3.25 A

V_IN= 90 to 264 V_RMS, I_O= 0 A to 3 A

Output ripple voltage, peak to

peak

15-V setting

450

300

200

V_{O_pp}

Output ripple voltage, peak to

peak

9-V setting

Output ripple voltage, peak to

peak

5-V setting

P_O(OPP)

t_OPP

Over-power protection threshold V_IN= 90 to 264 V_RMS

Over-power protection duration

V_IN= 90 to 264 V_RMS, P_O> P_O(OPP)

160

Output voltage deviation during

step-load transient

V_O= 20 V, I_Ostep between 0 A to I_O(FL)at 100

-604 /

+340

±1000 mVpp

ΔV_O

SYSTEM CHARACTERISTICS

V_IN= 230 V_RMS, I_O= 3.25 A

V_IN= 115 V_RMS, I_O= 3.25 A

V_IN= 90 V_RMS, I_O= 3.25 A

V_IN= 230 V_RMS

94%

93%

89%

79%

94.2%

93.3%

93.4%

92.4%

83.8%

89.0%

25°C

η_{FL_20}

Full-load efficiency,

V_O= 20 V

4-point average efficiency⁽¹⁾

V_O= 20 V

η_{avg_20}

V_IN= 115 V_RMS

V_IN= 230 V_RMS, I_O= 10% of I_O(FL)

V_IN= 115 V_RMS, I_O= 10% of I_O(FL)

η_{10%_20}

Efficiency at 10% load,

V_O= 20 V

T_AMB

Ambient operating temperature

range

V_IN= 90 to 264 V_RMS, V_O= 20 V, I_O= 0 to 3.25

(1) Average efficiency of four load points, I_O= 100%, 75%, 50%, and 25% of I_O(FL)

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9.2.2 Detailed Design Procedure

The 65-W USB-PD Charger Application is adapted from the typical application found in the UCC28782 High-

Density Active-Clamp Flyback Controller data sheet. The UCC28782 data sheet detailed design procedure is not

repeated here. Refer to the UCC28782 data sheet for the details in designing the active-clamp flyback primary-

side power stage and in using the UCC28782 controller. This detailed design procedure focuses on the specifics

of using the LMG2610 in the application.

9.2.2.1 Turn-On Slew-Rate Design

The LMG2610 turn-on slew rates are programmed as discussed in Turn-On Slew-Rate Control. In normal active-

clamp flyback (ACF) operation the high-side power switch operates at zero-voltage switching (ZVS), so the high-

side turn-on time does not affect the switch node slew rate. Therefore, the high-side GaN power FET is

programmed to turn on as fast as possible to minimize high-side GaN power-FET third-quadrant losses. The

fastest high-side turn-on time is programmed by setting

R_DRVH< 5.6 kΩ

(5)

In normal ACF operation, the low-side power switch operates at both ZVS and non-ZVS valley switching

depending on the load condition. The valley switching occurs at zero transformer current. Therefore, the low-side

is programmed to turn on as slow as possible to minimize EMI and circuit ringing with no additional switching

loss penalty. The slowest low-side turn-on time is programmed by setting

R_DRVL> 120 kΩ

(6)

9.2.2.2 Current-Sense Design

The UCC28782 High-Density Active-Clamp Flyback Controller data sheet shows the calculation for a traditional

current sense resistor, R_CS(UCC28782), in series with the low-side power switch current. R_CSis calculated with 方

程式4

R_CS= 1000 * R_CS(UCC28782)

(7)

The R_OPP(UCC2872)determination in the UCC28782 High-Density Active-Clamp Flyback Controller data sheet

assumes the current sense resistor is very small. R_OPPis adjusted to account for the significant R_CSvalue.

R_OPP= R_OPP(UCC2872)- R_CS

(8)

9.3 Power Supply Recommendations

The LMG2610 operates from a single input supply connected to the AUX pin. The BST pin is powered internally

by the AUX pin. The LMG2610 is intended to be operated from the same supply managed and used by the

power supply controller. The wide recommended AUX voltage range of 10 V to 26 V overlaps common-controller

supply-pin turn-on and UVLO voltage limits.

The BST-to-SW external capacitance is recommended to be a ceramic capacitor that is at least 10 nF over

operating conditions.

The AUX external capacitance is recommended to be a ceramic capacitor that is at least three-times larger than

the BST-to-SW capacitance over operating conditions.

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9.4 Layout

9.4.1 Layout Guidelines

9.4.1.1 Solder-Joint Stress Relief

Large QFN packages can experience high solder-joint stress. Several best practices are recommended to

provide solder-joint stress relief. First, the instructions for the NC1, NC2, and NC3 anchor pins found in 表 5-1

must be followed. Second, all the board solder pads must be non-solder-mask defined (NSMD) as shown in the

land pattern example in the Mechanical Data. Finally, any board trace connected to an NSMD pad must be less

than 2/3 the width of the pad on the pad side where it is connected. The trace must maintain this 2/3 width limit

for as long as it is not covered by solder mask. After the trace is under solder mask, there are no limits on the

trace dimensions. All these recommendations are followed in the Layout Example.

9.4.1.2 Signal-Ground Connection

Design the power supply with separate signal and power grounds that only connect in one location. Connect the

LMG2610 AGND pin to signal ground. Connect the LMG2610 SL pin and PADL thermal pad to power ground.

The LMG2610 serves as the single connection point between the signal and power grounds since the AGND

pin, SL pin, and PADL thermal pad are connected internally. Do not connect the signal and power grounds

anywhere else on the board except as recommended in the next sentence. To facillitate board debug with the

LMG2610 not installed, connect the AGND pad to the PADL thermal pad as shown in the Layout Example.

9.4.1.3 CS Pin Signal

As seen with 方程式 4, the current-sense signal impedance is three orders of magnitude higher than a traditional

current-sense signal. This higher impedance has implications for current-sense signal noise susceptibility.

Minimize routing the current-sense signal near any noisy traces. Place the current-sense resistor and any

filtering capacitors at the far end of the trace next to the controller current-sense input pin.

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9.4.2 Layout Example

图9-2. PCB Top Layer (First Layer)

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图9-3. PCB Inner Layer (Second Layer)

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10 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,

generate code, and develop solutions are listed below.

10.1 Documentation Support

10.1.1 Related Documentation

The LMG2610 Active-Clamp Flyback Power Stage Design Calculator is an Excel-based calculation tool for

LMG2610 design.

Using the UCC28782EVM-030 65-W USB-C PD High-Density Active-Clamp Flyback Converter is a User Guide

for the EVM

10.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

10.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

10.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

10.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

10.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OUTLINE

RRG0040A-C01

VQFN - 1.0 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

9.1

8.9

PIN 1 INDEX AREA

7.1

6.9

1.0

0.8

SEATING PLANE

0.08

0.05

0.00

1.96 0.1

(2)

(0.04)

(0.1) TYP

1.75 0.1

0.55

26X

0.45

0.55

0.45

(2)

0.1

C A B

5.02 0.1

PKG

SYMM

5.02 0.1

0.05

30X

0.5

(0.29) TYP

4X 0.625

2X 0.515

0.75

0.65

14X

PIN 1 ID

0.3

0.2

36X

2X 2.085

PKG

0.1

0.05

C A B

4226975/A 07/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RRG0040A-C01

VQFN - 1.0 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(1.3) TYP

(0.1)

(0.37)

(2.21)

CONNECTION

COVERED BY

SOLDER MASK

(1.25) TYP

PAD

SEE SOLDER MASK

DETAILS

26X (0.7)

14X (0.9)

4X (0.5)

36X (0.25)

(1.3)

TYP

(1.3)

TYP

(5.02) (6.5)

PKG SYMM

(R0.05) TYP

(5.02)

(1.96)

30X (0.5)

(1.75)

4X (0.625)

(

PKG

2X (0.515)

2X (2.085)

(2.835)

0.2) TYP

VIA

1.02

(8.7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

0.07 MAX

ALL AROUND

METAL EDGE

SOLDER MASK

OPENING

EXPOSED

METAL

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4226975/A 07/2021

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments

literature number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.

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Product Folder Links: LMG2610

LMG2610

www.ti.com.cn

ZHCSNW8A –OCTOBER 2022 –REVISED DECEMBER 2022

EXAMPLE STENCIL DESIGN

RRG0040A-C01

VQFN - 1.0 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(1.02)

(2.835)

26X (0.7)

14X (0.9)

4X (0.5)

36X (0.25)

(1.3) TYP

(0.65) TYP

PKG SYMM

(R0.05) TYP

(6.5)

8X (1.1)

4X (1.5)

30X (0.5)

4X (1.66)

4X (0.625)

2X (0.515)

(2.085)

PKG

(8.7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 10X

PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

EXPOSED PAD 41: 74%

EXPOSED PAD 42: 75%

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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Product Folder Links: LMG2610

PACKAGE OPTION ADDENDUM

www.ti.com

7-Jun-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

2000

250

(1)

(2)

(3)

(4/5)

(6)

LMG2610RRGR

LMG2610RRGT

XLMG2610RRGT

ACTIVE

VQFN

RRG

RoHS-Exempt

& Green

NIPDAU

Level-3-260C-168 HR

-40 to 150

LMG2610

NNNNC

Samples

ACTIVE

RRG

RoHS-Exempt

& Green

NIPDAU

Call TI

LMG2610

NNNNC

RRG

250

RoHS &

Non-Green

XLMG2610

NNNNC

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

7-Jun-2023

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

15-Jul-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LMG2610RRGR

LMG2610RRGT

VQFN

RRG

2000

250

330.0

180.0

16.4

9.3

7.3

1.2

12.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

15-Jul-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LMG2610RRGR

LMG2610RRGT

VQFN

RRG

2000

250

350.0

213.0

350.0

191.0

43.0

55.0

Pack Materials-Page 2

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

XLMG2610RRGT [TI]

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