bq24272YFFR [TI]
2.5A, Single Input, Single Cell Switchmode Li-Ion Battery Charger with Power Path Management; 2.5A ，单输入，单节开关模式锂离子电池充电器与电源路径管理
| 型号： | bq24272YFFR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.5A, Single Input, Single Cell Switchmode Li-Ion Battery Charger with Power Path Management |
| 文件： | 总32页 (文件大小：1222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
bq24272
www.ti.com
SLUSB09 –JUNE 2012
2.5A, Single Input, Single Cell Switchmode Li-Ion Battery Charger with Power Path
Management
Check for Samples: bq24272
1
FEATURES
–
JEITA Compatible
•
Thermal Regulation Protection for Output
Current Control
•
High-Efficiency Switch Mode Charger with
Separate Power Path Control
•
•
•
•
BAT Short-Circuit Protection
–
Instantly Startup System from a Deeply
Discharged Battery or No Battery
Soft-Start Feature to Reduce Inrush Current
Thermal Shutdown and Protection
•
20V input rating, with 10.5V Over-Voltage
Protection (OVP)
Available in Small 49-ball WCSP or QFN-24
Packages
•
•
Integrated FETs for Up to 2.5A Charge Rate
Highly Integrated Battery N-Channel MOSFET
Controller for Power Path Management
APPLICATIONS
•
Safe and Accurate Battery Management
Functions
•
•
•
•
Handheld Products
Portable Media Players
Portable Equipment
–
–
0.5% Battery Regulation Accuracy
10% Charge Current Accuracy
Tablets and Portable Internet Devices
•
Voltage-based, NTC Monitoring Input (TS)
APPLICATION SCHEMATIC
SW
IN
System
Load
PMID
BOOT
SYS
HOST
SCL
SDA
CD
INT
BAT
BYP
PGND
TS
PACK+
+
TEMP
STAT
DRV
PACK–
DESCRIPTION
The bq24272 is a highly integrated single cell Li-Ion battery charger and system power path management device
targeted for space-limited, portable applications with high capacity batteries. The single cell charger operates
from a dedicated power source such as a wall adapter or wireless power supply for a versatile solution.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
bq24272
SLUSB09 –JUNE 2012
www.ti.com
The power path management feature allows the bq24272 to power the system from a high efficiency DC to DC
converter while simultaneously and independently charging the battery. The charger monitors the battery current
at all times and reduces the charge current when the system load requires current above the input current limit.
This allows for proper charge termination and timer operation. The system voltage is regulated to the battery
voltage but will not drop below 3.5V. This minimum system voltage support enables the system to run with a
defective or absent battery pack and enables instant system turn-on even with a totally discharged battery or no
battery. The power-path management architecture also permits the battery to supplement the system current
requirements when the adapter cannot deliver the peak system currents. This enables the use of a smaller
adapter.
The battery is charged in three phases: conditioning, constant current and constant voltage. In all charge phases,
an internal control loop monitors the IC junction temperature and reduces the charge current if the internal
temperature threshold is exceeded. Additionally, the bq24272 offers a voltage-based battery pack thermistor
monitoring input (TS) that monitors battery temperature for safe charging.
2
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SLUSB09 –JUNE 2012
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
NTC MONITORING
PART NUMBER
OVP
JEITA COMPATIBLE
MINIMUM SYSTEM VOLTAGE
PACKAGE
(TS)
Yes
Yes
Yes
Yes
bq24272YFFR
bq24272YFFT
bq24272RGER
bq24272RGET
10.5 V
10.5 V
10.5 V
10.5 V
No
No
No
No
3.5 V
3.5 V
3.5 V
3.5 V
WCSP
WCSP
QFN
QFN
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–2
MAX
20
UNIT
V
IN
BYP, PMID, BOOT
–0.3
–0.7
–0.3
–0.3
20
V
Pin voltage range (with
respect to VSS)
SW
12
V
SYS, BAT, BGATE, DRV, STAT, INT, SDA, SCL, CD, TS
7
V
BOOT to SW
7
V
SW
4.5
3.5
2.75
10
A
Output Current (Continuous)
SYS
a
Input Current (Continuous)
Output Sink Current
IN
A
STAT, INT
mA
°C
°C
°C
°C
Operating free-air temperature range
Junction temperature, TJ
–40
–40
–65
85
125
150
300
Storage temperature, TSTG
Lead temperature (soldering, 10 s)
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
THERMAL INFORMATION
bq24272
THERMAL METRIC(1)
UNITS
49 PINS (YFF) 24 PINS (QFN)
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
49.8
0.2
1.1
1.1
6.6
n/a
32.6
30.5
3.3
θJCtop
θJB
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.4
ψJB
9.3
θJCbot
2.6
spacer
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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RECOMMENDED OPERATING CONDITIONS
MIN
4.2
MAX UNITS
IN voltage range
VIN
18(1)
V
IN operating range
4.2
10
IIN
Input current
2.5
3
A
A
ISYS
Output current from SW, DC
Charging
2.5
2.5
125
IBAT
TJ
A
Discharging, using internal battery FET
Operating junction temperature range
0
°C
(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BOOT or SW pins. A tight
layout minimizes switching noise.
ELECTRICAL CHARACTERISTICS
Circuit of , VUVLO < VIN < VOVP AND VIN>VBAT+VSLP, TJ = 0°C – 125°C and TJ = 25°C for typical values (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VUVLO < VIN < VOVP AND VIN > VBAT+VSLP
PWM switching
,
15
mA
IIN
Input quiescent current
VUVLO < VIN < VOVP AND VIN > VBAT+VSLP
PWM NOT switching
,
5
0°C< TJ < 85°C, High-Z Mode
175
5
μA
μA
IBATLEAK
IBAT_HIZ
Leakage current from BAT to the supply
0°C< TJ < 85°C, VBAT = 4.2V, VIN = 0V
Battery discharge current in high impedance mode,
(BAT, SW, SYS)
0°C< TJ < 85°C, VBAT = 4.2 V, VIN = 0 V or 5 V, High-Z
mode
55
μA
POWER PATH MANAGEMENT
VSYS(REG)
VBAT < VMINSYS
3.6
3.7
3.82
V
System regulation voltage
VBATREG
+1.5%
VBATREG
+3.0%
VBATREG
+4.17%
VSYSREGFETOFF
VMINSYS
Battery FET turned off, Charge disable or termination
VBAT < VMINSYS, Input current limit or VINDPM active
VBAT > 2.5 V
Minimum system regulation voltage
Enter supplement mode threshold
3.4
3.5
3.62
V
V
VBAT
–30mV
VBSUP1
VBAT
–10mV
VBSUP2
Exit supplement mode threshold
VBAT > 2.5 V
V
A
ILIM(Discharge)
Current limit, discharge or supplement mode
Current monitored in internal FET only
7
Measured from
(VBAT -VSYS) = 300 mV to
VBGATE = (VBAT - 600 mV)
Deglitch Time, OUT short circuit during discharge or
supplement mode
tDGL(SC1)
250
μs
Recovery time, OUT short circuit during discharge or
supplement mode
tREC(SC1)
60
ms
V
Battery range for BGATE operation
2.5
4.5
BATTERY CHARGER
YFF pkg
RGE pkg
37
50
57
70
Measured from BAT to SYS,
VBAT = 4.2V
RON(BAT-CS+) Internal battery charger MOSFET on-resistance
mΩ
Battery regulation voltage
3.5
–0.5%
–1%
4.44
0.5%
1%
V
VBATREG
TA = 25°C
Battery regulation voltage accuracy
Over temperature
VBATSHRT < VBAT < VBATREG
0°C to 125°C
Charge current programmable range
Fast charge current accuracy
550
2000
10%
3.1
mA
ICHARGE
–10%
2.9
VBATSHRT
IBATSHRT
Battery short threshold
VBAT Rising, 100 mV Hysteresis
VBAT < VBATSHRT
3.0
50.0
32
V
Battery short current
mA
ms
tDGL(BATSHRT)
Deglitch time for battery short to fast charge transition
ICHARGE = 50 mA
ICHARGE > 50 mA
–35%
–15%
35%
15%
ITERM
Termination charge current accuracy
Deglitch time for charge termination
Both rising and falling, 2-mV over-drive,
tRISE, tFALL = 100 ns
tDGL(TERM)
32
ms
VRCH
Recharge threshold voltage
Deglitch time
Below VBATREG
120
32
mV
ms
tDGL(RCH)
VBAT falling below VRCH, tFALL = 100ns
During battery detection source cycle
During battery detection sink cycle
3.3
3.0
VDETECT
Battery detection voltage threshold
V
4
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ELECTRICAL CHARACTERISTICS (continued)
Circuit of , VUVLO < VIN < VOVP AND VIN>VBAT+VSLP, TJ = 0°C – 125°C and TJ = 25°C for typical values (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Battery detection current before charge done (sink
current)
IDETECT
2.5
mA
tDETECT
VIH(CD)
VIL(CD)
Battery detection time
CD input high logic level
CD input low logic level
250
ms
V
1.3
0.4
V
INPUT PROTECTION
IINLIM = 1.5 A
IINLIM = 2.5 A
1.35
2.3
4.2
–2%
5
1.5
2.5
1.65
2.8
IINLIM
Input current limit
VIN=5V, DC current pulled from SW
A
V
Input DPM threshold
4.76
2%
VIN_DPM
Input DPM accuracy
VDRV
Internal bias regulator voltage
DRV Output current
5.2
5.45
V
IDRV
10
mA
mV
V
VDO_DRV
VUVLO
VSLP
DRV Dropout voltage (VIN – VDRV
)
IIN = 1A, VIN = 5V, IDRV = 10mA
VIN rising, 150 mV hysteresis
2.0 V ≤ VBAT ≤ VOREG, VIN falling
2.0 V ≤ VBAT ≤ VOREG
450
4.0
IC active threshold voltage
3.6
0
3.8
40
Sleep-mode entry threshold, VIN-VBAT
Sleep-mode exit hysteresis
100
160
mV
mV
ms
V
VSLP_EXIT
40
100
30
Deglitch time for supply rising above VSLP+VSLP_EXIT
Input supply OVP threshold voltage
Rising voltage, 2-mV over drive, tRISE=100ns
IN, VIN Rising, 100 mV hysteresis
VOVP
10.3
10.5
10.7
1.025 ×
VBATREG
1.05 ×
VBATREG
1.075 ×
VBATREG
VBOVP
Battery OVP threshold voltage
VBAT threshold over VOREG to turn off charger during charge
Lower limit for VBAT falling from above VBOVP
V
% of
VBATREG
VBOVP hysteresis
1
VBATUVLO
Battery UVLO threshold voltage
Bad source detection threshold
2.5
V
V
VIN_DPM
–
VBAT_SOURCE
80mV
Bad source detection deglitch
Cycle by cycle current limit
Thermal shutdown
32
ms
A
ILIMIT
4.1
4.9
5.6
TSHUTDWN
TREG
10°C Hysteresis
165
120
C
Thermal regulation threshold
Safety timer accuracy
C
–20%
20%
STAT, INT
IIH
High-level leakage current
V/CHG = V/PG = 5 V
1
µA
V
VOL
Low-level output saturation voltage
IO = 10 mA, sink current
0.4
PWM CONVERTER
Internal top reverse blocking MOSFET on-resistance
IIN_LIMIT = 1.5 A, Measured from VIN to PMIDU
Measured from PMID to SW
45
65
80
mΩ
mΩ
Internal top N-channel Switching MOSFET on-
resistance
110
Internal bottom N-channel MOSFET on-resistance
Oscillator frequency
Measured from SW to PGND
65
1.50
95%
115
mΩ
fOSC
1.35
0
1.65
MHz
DMAX
DMIN
Maximum duty cycle
Minimum duty cycle
BATTERY-PACK NTC MONITOR
VHOT
High temperature threshold
VTS falling, 1%VDRV Hysteresis
VTS rising, 1%VDRV Hysteresis
VTS rising, 2%VDRV Hysteresis
29.7
59.5
70
30
60
30.5
60.4
73
%VDRV
%VDRV
%VDRV
ms
VCOLD
TSOFF
tDGL(TS)
Low temperature threshold
TS Disable threshold
Deglitch time on TS change
50
VIH
Input high threshold
VPULLUP = 1.8 V, SDA and SCL
VPULLUP = 1.8 V, SDA and SCL
ISDA = 10 mA, sink current
1.3
30
V
V
VIL
Input low threshold
0.4
0.4
VOL
Output low threshold
Input high leakage current
Watchdog timer timeout
V
IIH
VPULLUP = 1.8 V, SDA and SCL
1
µA
s
tWATCHDOG
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PIN CONFIGURATION
49-Ball WCSP (Top View)
1
2
3
4
5
6
7
IN
IN
IN
IN
AGND
AGND
AGND
A
B
C
D
E
PMIDI
PMIDI
PMIDI
PMIDI
BYP
SW
BYP
SW
BYP
SW
SW
SW
SW
SW
PGND
AGND
PGND
N.C.
PGND
N.C.
PGND
PGND
PGND
PGND
BOOT
CD
SDA
SCL
SYS
BAT
SYS
BAT
SYS
BAT
SYS
BAT
BGATE
INT
DRV
F
TS
STAT
AGND
G
24-PIN QFN (Top View)
N.C.
1
18 SW
N.C.
SCL
2
3
17 PGND
16 PGND
bq24272
SDA
AGND
DRV
4
5
6
15 PGND
14 SYS
13 SYS
(Contact the factory for the latest pinout)
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PIN FUNCTIONS
PIN NO. bq24272
PIN NAME
I/O
DESCRIPTION
YFF
RGE
Input power supply. IN is connected to the external DC supply (AC adapter or alternate power source). Bypass
IN to PGND with at least a 1μF ceramic capacitor.
IN
A1–A4
B1–B4
21
I
Reverse Blocking MOSFET and High Side MOSFET Connection Point for High Power Input. Bypass PMID to
GND with at least a 4.7μF ceramic capacitor. Use caution when connecting an external load to PMID. The
PMID output is not current limited. Any short on PMID will result in damage to the IC.
PMID
20
O
Bypass for internal circuits. Bypass BYP to GND with at least 0.1µF of capacitance. Do not connect any
external load to BYP.
BYP
SW
B5–B7
C1–C7
23
O
O
18
Inductor Connection. Connect to the switched side of the external inductor.
Ground terminal.
A5–A7,
E1, G7
AGND
5, 22
—
PGND
N.C.
D1–D7
E2, E3
15, 16, 17
1, 2
—
I
Ground terminal. Connect to the thermal pad (for QFN only) and the ground plane of the circuit.
No connection. Leave N.C. unconnected.
IC Hardware Disable Input. Drive CD high to place the bq24272 in High-Z mode. Drive CD low for normal
operation.
CD
E4
24
I
SDA
SCL
E5
E6
4
3
I/O
I
I2C Interface Data. Connect SDA to the logic rail through a 10kΩ resistor.
I2C Interface Clock. Connect SCL to the logic rail through a 10kΩ resistor.
High Side MOSFET Gate Driver Supply. Connect a 0.01µF ceramic capacitor (voltage rating > 10V) from
BOOT to SW to supply the gate drive for the high side MOSFETs.
BOOT
SYS
E7
19
I
I
System Voltage Sense and Charger FET Connection. Connect SYS to the system output at the output bulk
capacitors. Bypass SYS locally with 10μF.
F1–F4
13, 14
External Discharge MOSFET Gate Connection. BGATE drives an external P-Channel MOSFET to provide a
very low resistance discharge path. Connect BGATE to the gate of the external MOSFET. BGATE is low during
supplement mode and when no input is connected.
BGATE
INT
F5
F6
10
7
O
O
Status Output. INT is an open-drain output that signals charging status and fault interrupts. INT pulls low during
charging. INT is high impedance when charging is complete or the charger is disabled. When a fault occurs, a
128μs pulse is sent out as an interrupt for the host. INT is enabled /disabled using the EN_STAT bit in the
control register. Connect INT to a logic rail through a 100kΩ resistor to communicate with the host processor.
Gate Drive Supply. DRV is the bias supply for the gate drive of the internal MOSFETs. Bypass DRV to PGND
DRV
BAT
F7
6
O
with a 1μF ceramic capacitor. DRV may be used to drive external loads up to 10mA. DRV is active whenever
the input is connected and VIN > VUVLO and VSUPPLY > (VBAT + VSLP
)
Battery Connection. Connect to the positive terminal of the battery. Additionally, bypass BAT to GND with a
1μF capacitor.
G1–G4
11, 12
I/O
Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from DRV to GND. The NTC is
connected from TS to GND. The TS function provides 4 thresholds for JEITA compatibility. TS faults are
reported by the I2C interface. See the NTC Monitor section for more details on operation and selecting the
resistor values.
TS
G5
9
I
Status Output. STAT is an open-drain output that signals charging status and fault interrupts. STAT pulls low
during charging. STAT is high impedance when charging is complete or the charger is disabled. When a fault
occurs, a 128μs pulse is sent out as an interrupt for the host. STAT is enabled /disabled using the EN_STAT
bit in the control register. Connect STAT to a logic rail using an LED for visual indication or through a 10kΩ
resistor to communicate with the host processor.
STAT
G6
—
8
O
There is an internal electrical connection between the exposed thermal pad and the VSS pin of the device. The
thermal pad must be connected to the same potential as the VSS pin on the printed circuit board. Do not use
the thermal pad as the primary ground input for the device. VSS pin must be connected to ground at all times.
Thermal
PAD
Pad
—
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TYPICAL APPLICATION CIRCUIT
ADAPTER
1.5 mH
IN
SW
PMID
0.01 mF
System
Load
1 mF
4.7 mF
BOOT
SYS
10 mF
BYP
DRV
PGND
BGATE
BAT
1 mF
VDRV
1 mF
1 mF
PACK+
STAT
TEMP
TS
V
SYS
(1.8 V)
PACK-
HOST
bq24272
INT
SDA
SCL
GPIO1
SDA
SCL
Figure 1. bq24272 Application Circuit, External Discharge FET Connected
8
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DETAILED DESCRIPTION
The bq24272 is a highly integrated single cell Li-Ion battery charger and system power path management
devices targeted for space-limited, portable applications with high capacity batteries. The single-input, single cell
charger operates from a dedicated power source (i.e. wall adapter or wireless power input).
The power path management feature allows the bq24272 to power the system from a high efficiency DC to DC
converter while simultaneously and independently charging the battery. The charger monitors the battery current
at all times and reduces the charge current when the system load requires current above the input current limit.
This allows for proper charge termination and enables the system to run with a defective or absent battery pack.
Additionally, this enables instant system turn-on even with a totally discharged battery or no battery. The power-
path management architecture also permits the battery to supplement the system current requirements when the
adapter cannot deliver the peak system currents. This enables the use of a smaller adapter. The charge
parameters are programmable using the I2C interface.
The battery is charged in three phases: conditioning, constant current and constant voltage. In all charge phases,
an internal control loop monitors the IC junction temperature and reduces the charge current if the internal
temperature threshold is exceeded.
Charge Mode Operation
Charge Profile
The internal battery MOSFET is used to charge the battery. When the battery is above the MINSYS voltage, the
internal FET is on to maximize efficiency and the PWM converter regulates the charge current into the battery.
When battery is less than MINSYS, the SYS is regulated to VSYS(REG) and battery is charged using the battery
FET to regulate the charge current. There are 5 loops that influence the charge current:
•
•
•
•
•
Constant current loop (CC)
Constant voltage loop (CV)
Thermal-regulation loop
Minimum system-voltage loop (MINSYS)
Input-voltage dynamic power-management loop (VIN-DPM)
During the charging process, all five loops are enabled and the one that is dominant takes control. The bq24272
supports a precision Li-Ion or Li-Polymer charging system for single-cell applications. The Dynamic Power Path
Management (DPPM) feature regulates the system voltage to a minimum of VMINSYS, so that startup is enabled
even for a missing or deeply discharged battery. Figure 2 shows a typical charge profile including the minimum
system output voltage feature.
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Current Regulation
Phase
Precharge
Phase
Voltage Regulation
Phase
Regulation
voltage
Charge Current
Regulation
Threshold
System Voltage
VSYS
(3.6 V)
VBATSHORT
(3.0 V)
Battery
Voltage
Charge Current
Termination
Current
Threshold
I BATSHORT
Linear Charge
to Maintain
Minimum
System
Battery
FET
is OFF
50 mA Precharge to
Close Pack Protector
Battery FET is ON
Voltage
Figure 2. Typical Charging Profile for bq24272
PWM Controller in Charge Mode
The bq24272 provides an integrated, fixed-frequency 1.5MHz voltage-mode controller to power the system and
supply the charge current. The voltage loop is internally compensated and provides enough phase margin for
stable operation, allowing the use of small ceramic capacitors with very low ESR. The input scheme for the
bq24272 prevents battery discharge when the supply voltages are lower than VBAT. The high-side N-MOSFET
(Q1) switches to control the power delivered to the output. The DRV LDO provides a supply for the gate drive for
the low side MOSFET, while a bootstrap circuit (BST) with an external bootstrap capacitor is used to boost up
the gate drive voltage for Q1.
The input is protected by a cycle-by-cycle current limit that is sensed through the internal sense MOSFETs for
Q1. The threshold for the current limit is set to a nominal 5-A peak current. The input also utilizes an input
current limit that limits the current from the power source.
Battery Charging Process
When the battery is deeply discharged or shorted (VBAT<VBATSHRT), the bq24272 applies IBATSHRT for tDETECT to
close the pack protector switch and bring the battery voltage up to acceptable charging levels. During this time,
the battery FET is linearly regulated and the system output is regulated to VSYS(REG). Once the battery rises
above VBATSHRT, the charge current is regulated to the value set in the I2C register. The battery FET is linearly
regulated to maintain the system voltage. Under normal conditions, the time spent in this region is a very short
percentage of the total charging time, so the linear regulation of the charge current does not affect the overall
charging efficiency for very long. If the die temperature does heat up, the thermal regulation circuit reduces the
charge current to maintain a die temperature less than 125°C. If the current limit for the SYS output is reached
(limited by the input current limit, or VIN_DPM), the SYS output drops to the VMINSYS output voltage. When this
happens, the current is reduced to provide the system with all the current that is needed while maintaining the
minimum system voltage. If the charge current is reduced to 0mA, pulling further current from SYS causes the
output to fall to the battery voltage and enter supplement mode (see the “Dynamic Power Path Management”
section for more details).
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Once the battery is charged enough to where the system voltage begins to rise above VSYS(REG) (approximately
3.5V), the battery FET is turned on fully and the battery is charged with the full programmed charge current set
by the I2C interface, ICHARGE. The slew rate for fast charge current is controlled to minimize the current and
voltage over-shoot during transient. The charge current is regulated to ICHARGE until the battery is charged to the
regulation voltage. Once the battery voltage is close to the regulation voltage, VBATREG, the charge current is
tapered down as shown in Figure 1 while the SYS output remains connected to the battery. The voltage
regulation feedback occurs by monitoring the battery-pack voltage between the BAT and PGND pins. The
VBATREG is targeted for single-cell voltage batteries and has an adjustable regulation voltage (3.5V to 4.44V)
programmed using the I2C interface.
The bq24272 monitors the charging current during the voltage regulation phase. Once the termination threshold,
ITERM, is detected and the battery voltage is above the recharge threshold, the bq24272 terminates charge and
turns off the battery charging FET and enters battery detection. If a battery is detected (See Battery Detection
section), the bq24272 enters charge done. The system output is regulated to the VSYS(REG) and supports the full
current available from the input and the battery supplement mode is available (see the “Dynamic Power Path
Management” section for more details). The termination current level is programmable. To disable the charge
current termination, the host sets the charge termination bit (TE) of charge control register to 0, refer to I2C
section for details.
A new charge cycle is initiated when one of the following conditions is detected:
1. The battery voltage falls below the VBATREG-VRCH threshold.
2. VIN toggle
3. CE bit toggle or RESET bit is set
4. HI-Z bit toggle
Battery Detection
When termination conditions are met, a battery detection cycle is started. During battery detection, IDETECT is
pulled from VBAT for tDETECT to verify there is a battery. If the battery voltage remains above VDETECT for the full
duration of tDETECT, a battery is determined to present and the IC enters “Charge Done”. If VBAT falls below
VDETECT, a “Battery Not Present” fault is signaled and battery detection continues. The next cycle of battery
detection, the bq24272 turns on IBATSHORT for tDETECT. If VBAT rises to VDETECT, the current source is turned off and
after tDETECT, the battery detection continues through another current sink cycle. Battery detection continues until
charge is disabled or a battery is detected. Once a battery is detected, the fault status clears and a new charge
cycle begins. Battery detection is not run when termination is disabled.
Dynamic Power Path Management (DPPM)
The bq24272 features a SYS output that powers the external system load connected to the battery. This output
is active whenever a source is connected to IN or BAT. The following sections discuss the behavior of SYS with
a source connected to the supply or a battery source only.
Input Source Connected
When a valid input source is connected, the buck converter turns on to power the load on SYS. The STAT/INT
show an interrupt with 128µs pulse to tell the host that something has changed. The FAULT bits read normal,
and the Supply Status register shows that a new supply is connected. The CE bit (bit 1) in the control register
(0x02) determines whether a charge cycle is initiated. By default, the bq24272 (/CE=0) enables a charge cycle
when a valid input source is connected. When the CE bit is 1 and a valid input source is connected, the battery
FET is turned off and the SYS output is regulated to the VSYS(REG) programmed by the VBATREG threshold in the
I2C register. A charge cycle is initiated when the CE bit is written to a 0.
When the CE bit is a 0 and a valid source is connected to IN, the buck converter starts up and a charge cycle is
initiated. When VBAT is high enough that VSYS is > VSYS(REG), the battery FET is turned on and the SYS output is
connected to BAT. If the SYS voltage falls to VSYS(REG), it is regulated to that point to maintain the system output
even with a deeply discharged or absent battery. In this mode, the SYS output voltage is regulated by the buck
converter and the battery FET linearly regulates the charge current into the battery. The current from the supply
is shared between charging the battery and powering the system load at SYS. The dynamic power path
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management (DPPM) circuitry of the bq24272 monitors the current limits continuously and if the SYS voltage
falls to the VMINSYS voltage, it adjusts charge current to maintain the minimum system voltage and supply the load
on SYS. If the charge current is reduced to zero and the load increases further, the bq24272 enters battery
supplement mode. During supplement mode, the battery FET is turned on and the battery supplements the
system load.
2000mA
1800 mA
ISYS
800mA
0mA
1500mA
IIN
~850 mA
0 mA
1A
IBAT
0mA
-200mA
3.75 V
3.55 V
DPPM loop active
VOUT
~3.1 V
Supplement
Mode
Figure 3. Example DPPM Response (VSupply=5V, VBAT = 3.1V, 1.5A Input current limit)
VBAT(REG) should never be programmed less than VBAT. If the battery is ever 5% above the regulation threshold,
the battery OVP circuit shuts the PWM converter off and the battery FET is turned on to discharge the battery to
safe operating levels. Battery OVP errors are shown in the I2C status registers.
Battery Only Connected
When a battery voltage > VBATUVLO is connected with no input source, the battery FET is turned on similar to
supplement mode. In this mode, the current is not regulated; however, there is a short circuit current limit. If the
short circuit limit is reached, the battery FET is turned off for the deglitch time. After the deglitch time, the battery
FET is turned on to test and see if the short has been removed. If it has not, the FET turns off and the process
repeats until the short is removed. This process is to protect the internal FET from over current. If an external
FET is used for discharge, the body diode prevents the load on SYS from being disconnected from the battery. If
the battery voltage is less than VBATUVLO, the battery FET (Q3) remains off and BAT is high-impedance. This
prevents further discharging deeply discharged batteries.
Battery Discharge FET (BGATE)
The bq24272 contains a MOSFET driver to drive an external discharge FET between the battery and the system
output. This external FET provides a low impedance path when supplying the system from the battery. Connect
BGATE to the gate of the external discharge MOSFET. BGATE is on under the following conditions:
1. No input supply connected.
2. HZ_MODE = 1
3. CD pin connected high
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DEFAULT Mode
DEFAULT mode is used when I2C communication is not available. DEFAULT mode is entered in the following
situations:
1. When the charger is enabled and VBAT<3.6V before I2C communication is established
2. When the watchdog timer expires without a reset from the I2C interface and the safety timer has not expired.
3. When the device comes out of any fault condition (sleep mode, OVP, faulty adapter mode, etc.) before I2C
communication is established
In default mode, the I2C registers are reset to the default values. The 27 min safety timer is reset and starts when
DEFAULT mode is entered. The default value for VBATREG is 3.6V, and the default value for ICHARGE is 1A. The
input current limit is 1.5A by default. DEFAULT mode is exited by programming the I2C interface. Note that if
termination is enabled and charging has terminated, a new charge cycle is NOT initiated when entering
DEFAULT mode.
Safety Timer and Watchdog Timer
At the beginning of charging process, the bq24272 starts the safety timer. This timer is active during the entire
charging process. If charging has not terminated before the safety timer expires, charging is halted and the CE
bit is written to a “1”. The length of the safety timer is selectable using the I2C interface. A single 128μs pulse is
sent on the STAT and INT outputs and the STATx bits of the status registers are updated in the I2C. The CE bit
must be toggled in order to clear the safety timer fault. The safety timer duration is selectable using the TMR_X
bits in the Safety Timer Register/NTC Monitor register. Changing the safety timer duration resets the safety timer.
If the safety timer expires, charging is disabled (CE changed to a “1”). This function prevents continuous charging
of a defective battery if the host fails to reset the safety timer.
In addition to the safety timer, the bq24272 contains a watchdog timer that monitors the host through the I2C
interface. Once a read/write is performed on the I2C interface, a 30-second timer (tWATCHDOG) is started. The 30-
second timer is reset by the host using the I2C interface. This is done by writing a “1” to the reset bit (TMR_RST)
in the control register. The TMR_RST bit is automatically set to “0” when the 30-second timer is reset. This
process continues until battery is fully charged or the safety timer expires. If the 30-second timer expires, the IC
enters DEFAULT mode where the default register values are loaded, the safety timer restarts at 27minutes and
charging continues. The I2C may be accessed again to reinitialize the desired values and restart the watchdog
timer as long as the 27 minute safety timer has not expired. The watchdog timer flow chart is shown in Figure 4.
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Start Safety Timer
Yes
Safety timer
fault
Safety timer expired?
No
Charging suspended
Enter suspended
mode
STAT = Hi
Update STAT
bits
Yes
Charge Done?
CHG <ITERM
I
Fault indicated in
STAT registers
No
I2C Read/Write
performed?
No
Yes
Start 30 second
watchdog timer
Reset 30 second
watchdog timer
STAT = Hi
Update STAT
bits
Yes
Charge Done?
ICHG <ITERM
No
Yes
Safety timer expired?
No
Safety timer
fault
Charging suspended
Fault indicated in
STAT registers
No
Yes
No
Received SW watchdog
RESET?
30 timer expired?
Yes
Reset to default
2
values in I C
register.
Restart 27 min
safety timer
Figure 4. The Watchdog Timer Flow Chart for bq24272
Hardware Chip Disable Input (CD)
The bq24272 contain a CD input pin that is used to disable the IC and place the bq24272 into high-impedance
mode. Drive CD low to enable charge and enter normal operation. Drive CD high to disable charge and place the
bq24272 into high-impedance mode. Driving CD high during DEFAULT mode resets the safety timer. Driving CD
high during HOST mode resets the safety timer.
LDO Output (DRV)
The bq24272 contains a linear regulator (DRV) that is used to supply the internal MOSFET drivers and other
circuitry. Additionally, DRV supplies up to 10mA external loads to power the STAT LED or the USB transceiver
circuitry. The maximum value of the DRV output is 5.45V so it ideal for protecting voltage sensitive USB circuits
from high voltage fluctuations in the supply. The LDO is on whenever a supply is connected to the IN input of the
bq24272. The DRV is disabled under the following conditions:
1. VIN < UVLO
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2. VIN < VSLP + VBAT
3. Thermal Shutdown
External NTC Monitoring (TS)
The I2C interface allows the user to easily implement the JEITA standard for systems where the battery pack
thermistor is monitored by the host. Additionally, the bq24272 provides a flexible, voltage based TS input for
monitoring the battery pack NTC thermistor. The voltage at TS is monitored to determine that the battery is at a
safe temperature during charging. The bq24272 enables the user to easily implement the JEITA. The JEITA
specification is shown in Figure 5.
1.0C
0.5C
Portion of spec not covered by TS
Implementation on bq24272
4.25V
4.15V
4.1V
T1
(0oC)
T2
(10oC)
T3
T4
T4
(60oC)
(45oC)(50oC)
Figure 5. Charge Current/Voltage During TS Conditions
The TS function is voltage based for maximum flexibility. Connect a resistor divider from DRV to GND with TS
connected to the center tap to set the threshold. The connections are shown in Figure 6. The resistor values are
calculated using the following equations:
é
ê
ë
ù
ú
û
1
1
VDRV ´RCOLD´RHOT ´
-
VCOLD VHOT
RLO =
é
ê
ë
ù
-1 - RCOLD´
é
ù
-1
ú
VDRV
VHOT
VDRV
RHOT ´
ú
ê
VCOLD
û
ë
û
(1)
(2)
VDRV
-1
VCOLD
RHI =
1
1
+
RLO RCOLD
Where:
VCOLD = 0.60 × VDRV
VHOT = 0.60 × VDRV
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Where RHOT is the NTC resistance at the hot temperature and RCOLD is the NTC resistance at cold
temperature.
VDRV
DISABLE
TS COLD
+
VDRV
TS HOT
+
RHI
TS
PACK+
TEMP
bq24272
RLO
PACK–
Figure 6. TS Circuit
If the TS function is not used, connect TS to DRV directly to disable the feature. Additionally, the TS function can
be disabled in the I2C by writing to the EN_TS bit. When the TS is disabled, the status registers always read
“Normal”.
Thermal Regulation and Protection
During the charging process, to prevent chip overheating, bq24272 monitors the junction temperature, TJ, of the
die and begins to taper down the charge current once TJ reaches the thermal regulation threshold, TREG. The
charge current is reduced to zero when the junction temperature increases about 10°C above TREG. Once the
charge current is reduced, the system current is reduced while the battery supplements the load to supply the
system. This may cause a thermal shutdown of the bq24272 if the die temperature rises too high. At any state, if
TJ exceeds TSHTDWN, bq24272 suspends charging and disables the buck converter. During thermal shutdown
mode, the PWM is turned off, all timers are suspended, and a single 128μs pulse is sent on the STAT and INT
outputs and the STATx and FAULT_x bits of the status registers are updated in the I2C. A new charging cycle
begins when TJ falls below TSHTDWN by approximately 10°C.
Input Voltage Protection in Charge Mode
Sleep Mode
The bq24272 enters the low-power sleep mode if the voltage on VIN falls below sleep-mode entry threshold,
VBAT+VSLP, and VVBUS is higher than the undervoltage lockout threshold, VUVLO. This feature prevents draining
the battery during the absence of VIN. When VIN < VBAT+ VSLP, the bq24272 turns off the PWM converter, turns
the battery FET on and drives BGATE to GND, sends a single 128μs pulse on the STAT and INT outputs and
updates the STATx and FAULT_x bits in the status registers. Once VIN > VBAT+ VSLP, the STATx and FAULT_x
bits are cleared and the device initiates a new charge cycle.
Input Voltage Based DPM
During normal charging process, if the input power source is not able to support the programmed or default
charging current, the supply voltage will decease. Once the supply drops to VIN_DPM (default 4.2V), the input
current limit is reduced down to prevent further supply droop. When the IC enters this mode, the charge current
is lower than the set value and the DPM_STATUS bit is set (Bit 5 in Register 05H). This feature ensures IC
compatibility with adapters with different current capabilities without a hardware change. Figure 7 shows the VIN-
behavior to a current limited source. In this figure the input source has a 750mA current limit and the
DPM
charging is set to 750mA. The SYS load is then increased to 1.2A.
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VIN
5 V Adapter
rated for 750 mA
IIN
VSYS
IBAT
ISYS
Figure 7. bq24272 VIN-DPM
Bad Source Detection
When a source is connected to IN, the bq24272 runs a Bad Source Detection procedure to determine if the
source is strong enough to provide some current to charge the battery. A current sink is turned on (75mA) for
32ms. If the source is valid after the 32ms (VBADSOURCE < VIN < VOVP), the buck converter starts up and normal
operation continues. If the supply voltage falls below VBAD_SOURCE during the detection, the current sink shuts off
for 2s and then retries, a single 128μs pulse is sent on the STAT and INT outputs and the STATx and FAULT_x
bits of the status registers and the battery/supply status registers are updated in the I2C. The detection circuits
retries continuously until either a new source is connected to the other input or a valid source is detected after
the detection time. If during normal operation the source falls to VBAD_SOURCE, the bq24272 turns off the PWM
converter, turns the battery FET and BGATE on, sends a single 128μs pulse is sent on the STAT and INT
outputs and the STATx and FAULT_x bits of the status registers and the battery/supply status registers are
updated in the I2C. Once a good source is detected, the STATx and FAULT_x bits are cleared and the device
returns to normal operation.
Input Over-Voltage Protection
The bq24272 provides over-voltage protection on the input that protects downstream circuitry. The built-in input
over-voltage protection to protect the device and other components against damage from overvoltage on the
input supply (Voltage from VIN to PGND). During normal operation, if VIN > VOVP, the bq24272 turns off the PWM
converter, turns the battery FET and BGATE on, sends a single 128μs pulse is sent on the STAT and INT
outputs and the STATx and FAULT_x bits of the status registers and the battery/supply status registers are
updated in the I2C. Once the OVP fault is removed, the STATx and FAULT_x bits are cleared and the device
returns to normal operation.
Charge Status Outputs (STAT, INT)
The STAT output is used to indicate operation conditions for bq24272. STAT is pulled low during charging when
EN_STAT bit in the control register (0x02h) is set to “1”. When charge is complete or disabled, STAT is high
impedance. When a fault occurs, a 128-µs pulse (interrupt) is sent out to notify the host. The status of STAT
during different operation conditions is summarized in Table 1. STAT drives an LED for visual indication or can
be connected to the logic rail for host communication. The EN_STAT bit in the control register (00H) is used to
enable/disable the charge status for STAT. The interrupt pulses are unaffected by EN_STAT and will always be
shown. The INT output is identical to STAT and is used to interface with a low voltage host processor.
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Table 1. STAT Pin Summary
CHARGE STATE
STAT AND INT BEHAVIOR
Low
Charge in progress and EN_STAT=1
Other normal conditions
High-Impedance
Status Changes: Supply Status Change (plug in or removal), safety timer fault, watchdog
expiration, sleep mode, battery temperature fault (TS), battery fault (OVP or absent),
thermal shutdown
128-µs pulse, then High Impedance
REGISTER DESCRIPTION
Status/Control Register (READ/WRITE)
Memory location: 00, Reset state: 0xxx 0xxx
BIT
NAME
Read/Write
FUNCTION
B7(MSB)
TMR_RST
Read/Write
Write: TMR_RST function, write “1” to reset the watchdog timer (auto clear)
Read: Always 0
B6
B5
B4
STAT_2
STAT_1
STAT_0
Read only
Read only
Read only
000- No Valid Source Detected
001- IN Ready
010- NA
011- Charging
100-
101- Charge Done
110- NA
111- Fault
B3
B2
B1
NA
Read/Write
Read only
Read only
NA
FAULT_2
FAULT_1
000-Normal
001- Thermal Shutdown
010- Battery Temperature Fault
011- Watchdog Timer Expired
100- Safety Timer Expired
101- Supply Fault
110- NA
111- Battery Fault
Battery/ Supply Status Register (READ/WRITE)
Memory location: 01, Reset state: xxxx 0xxx
BIT
NAME
STAT1
STAT0
Read/Write
Read Only
Read Only
FUNCTION
B7(MSB)
B6
00-Normal
01-Supply OVP
10-Weak Source Connected (No Charging)
11- VIN<VUVLO
B5
B4
B3
B2
B1
NA
Read Only
Read Only
Read/Write
Read Only
Read Only
NA
NA
NA
NA
NA
BATSTAT1
BATSTAT0
00-Battery Present and Normal
01-Battery OVP
10-Battery Not Present
11- NA
B0 (LSB)
EN_NOBATO Read/ Write
P
0-Normal Operation
1-Enables No Battery Operation when termination is disabled
(default 0)
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EN_NOBATOP (No Battery Operation with Termination Disabled)
The EN_NOBATOP bit is used to enable operation when termination is disabled and no battery is connected.
This is useful for cases where the PA is connected to the BAT pin and it desired to do a GSM calibration in the
factory. For this application, the TE bit (Bit 2 in Register 0x02h) should be set to a “0” to disable termination and
the EN_NOBATOP should be set to a “1”. This feature should not be used during normal operation as it disables
the BATOVP and the reverse boost protection circuits.
Control Register (READ/WRITE)
Memory location: 02, Reset state: 1000 1100
BIT
NAME
Read/Write
FUNCTION
B7(MSB)
RESET
Write Only
Write: 1-Reset all registers to default values
0-No effect
Read: always get “1”
B6
B5
B4
B3
NA
Read Only
Read/Write
Read/Write
Read/Write
NA
NA
NA
NA
NA
EN_STAT
1-Enable STAT output to show charge status,
0-Disable STAT output for charge status. Fault interrupts are still show even when
EN_STAT = 0. (default 1)
B2
TE
CE
Read/Write
Read/Write
1-Enable charge current termination,
0-Disable charge current termination (default 1)
B1
1-Charger is disabled
0-Charger enabled (default 0)
B0 (LSB)
HZ_MODE Read/Write
1-High impedance mode
0-Not high impedance mode (default 0)
RESET Bit
The RESET bit in the control register (0x02h) is used to reset all the charge parameters. Write “1” to RESET bit
to reset all the registers to default values and place the bq24272 into DEFAULT mode and turn off the watchdog
timer. The RESET bit is automatically cleared to zero once the bq24272 enters DEFAULT mode.
CE Bit (Charge Enable)
The CE bit in the control register (0x02h) is used to disable or enable the charge process. A low logic level (0) on
this bit enables the charge and a high logic level (1) disables the charge. When charge is disabled, the SYS
output regulates to VSYS(REG) and battery is disconnected from the SYS. Supplement mode is still available if
the system load demands cannot be met by the supply. BGATE is high impedance when CE is high.
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HZ_MODE Bit (High Impedance Mode Enable)
The HZ_MODE bit in the control register (0x02h) is used to disable or enable the high impedance mode. A low
logic level (0) on this bit enables the IC and a high logic level (1) puts the IC in a low quiescent current state
called high impedance mode. When in high impedance mode, the converter is off and the battery FET and
BGATE are on. The load on SYS is supplied by the battery.
Control/Battery Voltage Register (READ/WRITE)
Memory location: 03, Reset state: 0001 0100
BIT
B7(MSB)
B6
NAME
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
FUNCTION
VBREG5
VBREG4
VBREG3
VBREG2
VBREG1
VBREG0
IINLIMIT_IN
Battery Regulation Voltage: 640mV (default 0)
Battery Regulation Voltage: 320mV (default 0)
Battery Regulation Voltage: 160mV (default 0)
Battery Regulation Voltage: 80mV (default 1)
Battery Regulation Voltage: 40mV (default 0)
Battery Regulation Voltage: 20mV (default 1)
B5
B4
B3
B2
B1
Input Limit for IN input
0 – 1.5A
1 – 2.5A (default 0)
B0(LSB)
NA
Read/Write
NA
•
Charge voltage range is 3.5V–4.44V with the offset of 3.5V and step of 20mV (default 3.6V).
Vender/Part/Revision Register (READ only)
Memory location: 04, Reset state: 0100 0000
BIT
B7(MSB)
B6
NAME
Vender2
Vender1
Vender0
PN1
Read/Write
Read only
Read only
Read only
Read only
Read only
FUNCTION
Vender Code: bit 2 (default 0)
Vender Code: bit 1 (default 1)
Vender Code: bit 0 (default 0)
For I2C Address 6Bh:
00: bq24272
B5
B4
B3
PN0
01 – 11: Future product spins
B2
Revision2
Revision1
Revision0
Read only
Read only
Read only
000: Revision 1.0
001:Revision 1.1
B1
010: Revision 2.0
011: Revision 2.1
100: Revision 2.2
101: Revision 2.3
110-111: Future Revisions
B0(LSB)
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Battery Termination/Fast Charge Current Register (READ/WRITE)
Memory location: 05, Reset state: 0011 0010
BIT
NAME
ICHRG4
ICHRG3
ICHRG2
ICHRG1
ICHRG0
ITERM2
ITERM1
ITERM0
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
FUNCTION
B7(MSB)
B6
Charge current: 1200 mA – (default 0)
Charge current: 600 mA— (default 0)
Charge current: 300 mA—(default 1)
Charge current: 150 mA— (default 1)
Charge current: 75 mA (default 0)
B5
B4
B3
B2
Termination current sense voltage: 200 mA (default 0)
Termination current sense voltage: 100 mA (default 1)
Termination current sense voltage: 50 mA (default 0)
B1
B0(LSB)
•
•
Charge current sense offset is 550mA and default charge current is 1000mA
Termination threshold offset is 50mA and default termination current is 150mA
VIN-DPM Voltage/ DPPM Status Register
Memory location: 06, Reset state: xx00 0000
BIT
NAME
Read/Write
FUNCTION
B7(MSB) MINSYS_STATUS
Read Only
1 – Minimum System Voltage mode is active (low battery condition)
0 – Minimum System Voltage mode is not active
B6
DPM_STATUS
Read Only
1 – VIN-DPM mode is active
0 – VIN-DPM mode is not active
B5
B4
B3
B2
B1
NA
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
NA
NA
NA
NA
NA
VINDPM2
VINDPM1
IN input VIN-DPM voltage: 320 mV (default 0)
IN input VIN-DPM voltage: 160 mV (default 0)
IN input VIN-DPM voltage: 80 mV (default 0)
B0(LSB) VINDPM0
•
VIN-DPM voltage offset is 4.20 V and default VIN-DPM threshold is 4.20 V.
Safety Timer/ NTC Monitor Register (READ/WRITE)
Memory location: 07, Reset state: 1001 1xxx
BIT
NAME
Read/Write
FUNCTION
B7(MSB) 2XTMR_EN
Read/Write
1 – Timer slowed by 2x when in thermal regulation, input current limit, VIN_DPM or DPPM
0 – Timer not slowed at any time (default 0)
B6
B5
TMR_1
TMR_2
Read/Write
Read/Write
Safety Timer Time Limit
00 – 27 minute fast charge
01 – 6 hour fast charge
10 – 9 hour fast charge
11 – Disable safety timers (default 00)
B4
B3
NA
Read/Write
Read/Write
NA
TS_EN
0 – TS function disabled
1 – TS function enabled (default 1)
B2
B1
TS_FAULT1
TS_FAULT0
Read Only
Read Only
TS Fault Mode:
00 – Normal, No TS fault
01 – TS temp < TCOLD or TS temp > THOT(Charging suspended)
10 – TCOOL > TS temp > TCOLD (Charge current reduced by half)
11 – TWARM < TS temp < THOT (Charge voltage reduced by 140mV)
B0(LSB) LOW_CHG
Read/Write
0 – Charge current as programmed in Register 0x05
1 – Charge current half programmed value in Register 0x05 (default 0)
Copyright © 2012, Texas Instruments Incorporated
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bq24272
SLUSB09 –JUNE 2012
www.ti.com
LOW_CHG Bit (Low Charge Mode Enable)
The LOW_CHG bit is used to reduce the charge current from the programmed value. This feature is used by
systems where battery NTC is monitored by the host and requires a reduced charge current setting or by
systems that need a “preconditioning” current for low battery voltages. Write a “1” to this bit to charge at half of
the programmed charge. Write a “0” to this bit to charge at the programmed charge current.
22
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Product Folder Link(s) :bq24272
bq24272
www.ti.com
SLUSB09 –JUNE 2012
APPLICATION INFORMATION
Output Inductor and Capacitor Selection Guidelines
When selecting an inductor, several attributes must be examined to find the right part for the application. First,
the inductance value should be selected. The bq24272 is designed to work with 1.5µH to 2.2µH inductors. The
chosen value will have an effect on efficiency and package size. Due to the smaller current ripple, some
efficiency gain is reached using the 2.2µH inductor, however, due to the physical size of the inductor, this may
not be a viable option. The 1.5µH inductor provides a good tradeoff between size and efficiency.
Once the inductance has been selected, the peak current must be calculated in order to choose the current
rating of the inductor. Use equation 2 to calculate the peak current.
%
æ
IPEAK = ILOAD(MAX) ´ 1+
ö
RIPPPLE
ç
÷
ø
2
è
(3)
The inductor selected must have a saturation current rating less than or equal to the calculated IPEAK. Due to the
high currents possible with the bq24272, a thermal analysis must also be done for the inductor. Many inductors
have 40°C temperature rise rating. This is the DC current that will cause a 40°C temperature rise above the
ambient temperature in the inductor. For this analysis, the typical load current may be used adjusted for the duty
cycle of the load transients. For example, if the application requires a 1.5A DC load with peaks at 2.5A 20% of
the time, a Δ40°C temperature rise current must be greater than 1.7A:
ITEMPRISE = ILOAD + D´ I
(
-ILOAD = 1.5A + 0.2´ 2.5A -1.5A = 1.7A
) ( )
PEAK
(4)
The bq24272 provides internal loop compensation. Using this scheme, the bq24272 is stable with 10µF to 200µF
of local capacitance. The capacitance on the BAT rail can be higher if distributed amongst the rail. To reduce the
output voltage ripple, a ceramic capacitor with the capacitance between 10µF and 47µF is recommended for
local bypass to SYS.
PCB Layout Guidelines
It is important to pay special attention to the PCB layout. The following provides some guidelines:
•
To obtain optimal performance, the power input capacitors, connected from the PMID input to PGND, must be
placed as close as possible to the bq24272
•
Place 4.7µF input capacitor as close to PMID pin and PGND pin as possible to make high frequency current
loop area as small as possible. Place 1µF input capacitor GNDs as close to the respective PMID cap GND
and PGND pins as possible to minimize the ground difference between the input and PMID_.
•
•
•
The local bypass capacitor from SYS to GND should be connected between the SYS pin and PGND of the
IC. The intent is to minimize the current path loop area from the SW pin through the LC filter and back to the
PGND pin.
Place all decoupling capacitor close to their respective IC pin and as close as to PGND (do not place
components such that routing interrupts power stage currents). All small control signals should be routed
away from the high current paths.
The PCB should have a ground plane (return) connected directly to the return of all components through vias
(two vias per capacitor for power-stage capacitors, one via per capacitor for small-signal components). It is
also recommended to put vias inside the PGND pads for the IC, if possible. A star ground design approach is
typically used to keep circuit block currents isolated (high-power/low-power small-signal) which reduces noise-
coupling and ground-bounce issues. A single ground plane for this design gives good results. With this small
layout and a single ground plane, there is no ground-bounce issue, and having the components segregated
minimizes coupling between signals.
•
•
The high-current charge paths into IN, BAT, SYS and from the SW pins must be sized appropriately for the
maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be
connected to the ground plane to return current through the internal low-side FET.
For high-current applications, the balls for the power paths should be connected to as much copper in the
board as possible. This allows better thermal performance as the board pulls heat away from the IC.
Copyright © 2012, Texas Instruments Incorporated
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bq24272
SLUSB09 –JUNE 2012
www.ti.com
Sample Layout
QFN I2C PART
WCSP I2C PART
GND
GND
BOOT
PMID
SW
PGND
BYP
BOOT
IN
IN
PMID
BYP
SW
SW
SYS
PGND
BAT
SYS
SYS
SYS
BAT
Package Summary
1
2
3
4
5
6
7
IN
IN
IN
IN
PGND
PGND
BYP
PGND
A
PMIDI
PMIDI
SW
PMIDI
SW
PMIDI
SW
BYP
SW
BYP
SW
B
C
D
E
SW
SW
TI YMLLLLS
bq24272
PGND
PGND
PGND
N.C.
PGND
N.C.
PGND
CD
PGND
SDA
PGND
SCL
PGND
BOOT
D
SYS
BAT
SYS
BAT
SYS
BAT
SYS
BAT
BGATE
INT
DRV
F
TS
STAT
PGND
G
0-Pin A1 Marker, TI-TI Letters, YM- Year Month Date Code,
LLLL-Lot Trace Code, S-Assembly Site Code
E
CHIP SCALE PACKAGING DIMENSIONS
The bq2427x devices are available in a 49-bump chip scale package (YFF, NanoFreeTM). The package dimensions are:
D – 2.78 mm 0.05 mm
E – 2.78 mm 0.05 mm
24
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Jul-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
BQ24272RGER
BQ24272RGET
BQ24272YFFR
BQ24272YFFT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
RGE
RGE
YFF
YFF
24
24
49
49
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
SNAGCU Level-1-260C-UNLIM
SNAGCU Level-1-260C-UNLIM
DSBGA
DSBGA
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BQ24272RGER
BQ24272RGET
BQ24272YFFR
BQ24272YFFT
VQFN
VQFN
RGE
RGE
YFF
YFF
24
24
49
49
3000
250
330.0
180.0
180.0
180.0
12.4
12.4
8.4
4.25
4.25
2.93
2.93
4.25
4.25
2.93
2.93
1.15
1.15
0.81
0.81
8.0
8.0
4.0
4.0
12.0
12.0
8.0
Q2
Q2
Q1
Q1
DSBGA
DSBGA
3000
250
8.4
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
BQ24272RGER
BQ24272RGET
BQ24272YFFR
BQ24272YFFT
VQFN
VQFN
RGE
RGE
YFF
YFF
24
24
49
49
3000
250
367.0
210.0
210.0
210.0
367.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
DSBGA
DSBGA
3000
250
Pack Materials-Page 2
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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