XC61FN5612PL-G [TOREX]

Power Management Circuit;


型号：	XC61FN5612PL-G
厂家：	Torex Semiconductor
描述：	Power Management Circuit
文件：	总14页 (文件大小：593K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XC61FSeries

ETR0202_004a

Voltage Detectors, Delay Circuit Built-In

■GENERAL DESCRIPTION

The XC61F series are highly accurate, low power consumption voltage detectors, manufactured using CMOS and laser

trimming technologies. A delay circuit is built-in to each detector.

Detect voltage is extremely accurate with minimal temperature drift.

Both CMOS and N-channel open drain output configurations are available.

Since the delay circuit is built-in, peripherals are unnecessary and high density mounting is possible.

■APPLICATIONS

■FEATURES

Highly Accurate

Low Power Consumption : 1.0μA(TYP.)[ VIN=2.0V ]

Detect Voltage Range 1.6V ~ 6.0V in 0.1V increments

: ± 2%

●Microprocessor reset circuitry

●Memory battery back-up circuits

●Power-on reset circuits

Operating Voltage Range : 0.7V ~ 10.0V

Detect Voltage Temperature Characteristics

:±100ppm/℃(TYP.)

●Power failure detection

●System battery life and charge voltage monitors

●Delay circuitry

Built-In Delay Circuit

: ① 1ms ~ 50ms

② 50ms ~ 200ms

③ 80ms ~ 400ms

: N-channel open drain or CMOS

: SOT-23

Output Configuration

Packages

: SOT-89

: TO-92

Environmentally Friendly : EU RoHS Compliant, Pb Free

* No parts are available with an accuracy of ± 1%

■TYPICAL PERFORMANCE

■TYPICAL APPLICATION CIRCUITS

CHARACTERISTICS

●Release Delay Time vs. Ambient Temperature

Ambient Temperature:Ta(℃)

1/14

XC61F Series

■PIN CONFIGURATION

(SIDE VIEW)

SIDE VIEW

■PIN ASSIGNMENT

PIN NUMBER

PIN NAME

FUNCTION

SOT-23

SOT-89

TO-92 (T)

VIN

VSS

Supply Voltage Input

Ground

VOUT

Output

2/14

XC61F

Series

■PRODUCT CLASSIFICATION

●Ordering Information

(

)

XC61F ①②③④⑤⑥⑦-⑧

DESIGNATOR

ITEM

SYMBOL

DESCRIPTION

CMOS output

①

Output Configuration

Detect Voltage

N-ch open drain output

e.g. 2.5V → ②2 , ③5

e.g. 3.8V → ②3, ③8

50ms ~ 200ms

②

③

16 ~ 60

④

⑤

Release Output Delay

Detect Accuracy

80ms ~ 400ms

1ms ~ 50ms

Within ±2.0%

MR-G

SOT-23 (3,000/Reel)

SOT-89 (1,000/Reel)

PR-G

SOT-89 (1,000/Reel)

(*1)

⑥⑦-⑧

Packages (Order Unit)

TO-92 Taping Type: Paper type (2,000/Tape)

TO-92 Taping Type: Paper type (3,000/Tape)

TO-92 Taping Type: Bag (500/Bag)

TH-G

TB-G

(*1)

The “-G” suffix indicates that the products are Halogen and Antimony free as well as being fully RoHS compliant.

■BLOCK DIAGRAMS

(1) CMOS output

(2) N-channel open drain output

3/14

XC61F Series

■

ABSOLUTE MAXIMUM RATINGS

Ta = 25℃

UNITS

PARAMETER

SYMBOL

RATINGS

12.0

Input Voltage

VIN

Output Current

IOUT

VSS -0.3 ~ VIN + 0.3

VSS -0.3 ~ 9

250

CMOS

Output Voltage

VOUT

N-ch open drain

SOT-23

Power Dissipation

SOT-89

500

TO-92

300

Operating Temperature Range

Storage Temperature Range

Topr

Tstg

-30～+80

-40～+125

℃

Ta = 25℃

■ELECTRICAL CHARACTERISTICS

PARAMETER

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS CIRCUIT

VDF(T)

x 0.98

VDF

VDF(T)

x 1.02

VDF

x 0.08

2.6

Detect Voltage

VDF

①

VDF

x 0.05

0.9

1.0

1.3

1.6

2.0

Hysteresis Width

VHYS

x 0.02

VIN = 1.5V

VIN = 2.0V

3.0

Supply Current

ISS

VIN

μA

②

①

③

VIN = 3.0V

VIN = 4.0V

VIN = 5.0V

3.4

3.8

4.2

Operating Voltage

VDF= 1.6V to 6.0V

0.7

1.0

3.0

5.0

6.0

7.0

10.0

VIN = 1.0V

VIN = 2.0V

VIN = 3.0V

VIN = 4.0V

VIN = 5.0V

2.2

7.7

N-ch VDS =0.5V

10.1

11.5

13.0

Output Current

IOUT

Ileak

P-ch VDS=2.1V

(CMOS Output)

VIN = 8.0V

-10.0

0.01

-2.0

④

③

CMOS

Leak

Current

Output

Nch Open

Drain

V_IN= 10.0V，V_OUT= 10.0V

μA

0.1

Detect Voltage

Temperature

Characteristics

ΔVDF

ΔTopr･VDF

ppm/

℃

±100

200

400

Release Delay Time

(VDR → VOUT inversion)

TDLY^＊

VIN changes from 0.6V to 10V

⑤

VDF (T): Setting detect voltage value

Release Voltage: VDR = VDF + VHYS

* Release Delay Time: 1ms to 50ms & 80ms to 400ms versions are also available.

Note: The power consumption during power-start to output being stable (release operation) is 2μA greater than it is after that period

(completion of release operation) because of delay circuit through current.

4/14

XC61F

Series

■OPERATIONAL EXPLANATION

●CMOS output

①

When a voltage higher than the release voltage (VDR) is applied to the voltage input pin (VIN), the voltage will

gradually fall. When a voltage higher than the detect voltage (VDF) is applied to VIN, output (VOUT) will be equal to the

input at VIN.

Note that high impedance exists at VOUT with the N-channel open drain configuration. If the pin is pulled up, VOUT will

be equal to the pull up voltage.

②

③

④

When VIN falls below VDF, VOUT will be equal to the ground voltage (VSS) level (detect state). Note that this also

applies to N-channel open drain configurations.

When VIN falls to a level below that of the minimum operating voltage (VMIN ) output will become unstable. Because

the output pin is generally pulled up with N-channel open drain configurations, output will be equal to pull up voltage.

When VIN rises above the VSS level (excepting levels lower than minimum operating voltage), VOUT will be equal to

VSS until VIN reaches the VDR level.

⑤

⑥

Although VIN will rise to a level higher than VDR, VOUT maintains ground voltage level via the delay circuit.

Following transient delay time, VIN will be output at VOUT. Note that high impedance exists with the N-channel open

drain configuration and that voltage will be dependent on pull up.

Notes:

1. The difference between VDR and VDF represents the hysteresis range.

2. Release delay time (t_DLY) represents the time it takes for VIN to appear at VOUT once the said voltage has exceeded the

VDR level.

●Timing Chart

(t_DLY

)

5/14

XC61F Series

■DIRECTIONS FOR USE

●Notes on Use

1. Please use this IC within the stated maximum ratings. The IC is liable to malfunction should the ratings be exceeded.

2. When a resistor is connected between the VIN pin and the input with CMOS output configurations, oscillation may

occur as a result of voltage drops at RIN if load current (IOUT) exists. It is therefore recommend that no resistor be added.

(refer to Oscillation Description (1) below)

3. When a resistor is connected between the VIN pin and the input with CMOS output configurations, irrespective of N-ch

output configurations, oscillation may occur as a result of through current at the time of voltage release even if load

current (IOUT) does not exist. (refer to Oscillation Description (2) below)

4. With a resistor connected between the VIN pin and the input, detect and release voltage will rise as a result of the IC's

supply current flowing through the VIN pin.

5. If a resistor (RIN) must be used, then please use with as small a level of input impedance as possible in order to control

the occurrences of oscillation as described above.

Further, please ensure that RIN is less than 10kΩ and that CIN is more than 0.1μF (Figure 1). In such cases, detect

and release voltages will rise due to voltage drops at RIN brought about by the IC's supply current.

6. Depending on circuit's operation, transient delay time of this IC can be widely changed due to upper limits or lower limits

of operational ambient temperature.

●Oscillation Description

(1) Oscillation as a result of output current with the CMOS output configuration:

When the voltage applied at IN rises, release operations commence and the detector's output voltage increases. Load

current (IOUT) will flow through RL. Because a voltage drop (RIN x IOUT) is produced at the RIN resistor, located

between the input (IN) and the VIN pin, the load current will flow via the IC's VIN pin. The voltage drop will also lead to

a fall in the voltage level at the VIN pin. When the VIN pin voltage level falls below the detect voltage level, detect

operations will commence. Following detect operations, load current flow will cease and since voltage drop at RIN will

disappear, the voltage level at the VIN pin will rise and release operations will begin over again.

Oscillation may occur with this " release - detect - release " repetition.

Further, this condition will also appear via means of a similar mechanism during detect operations.

(2) Oscillation as a result of through current:

Since the XC61F series are CMOS ICS, through current will flow when the IC's internal circuit switching operates

(during release and detect operations). Consequently, oscillation is liable to occur during release voltage operations

as a result of output current which is influenced by this through current (Figure 3).

Since hysteresis exists during detect operations, oscillation is unlikely to occur.

Figure 1. When using an input resistor

6/14

XC61F

Series

■DIRECTIONS FOR USE (Continued)

●Oscillation Description (Continued)

7/14

XC61F Series

■TEST CIRCUITS

測定回路１

測定回路２

●Circuit ②

●Circuit ①

220KΩ^*

測定回路３

測定回路４

●Circuit ④

●Circuit ③

測定回路５

●Circuit ⑤

220KΩ

* CMOS出力品の場合は不要です。

*Not necessary with CMOS output products.

8/14

XC61F

Series

■TYPICAL PERFORMANCE CHARACTERISTICS

9/14

XC61F Series

■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)

(7) Release Delay Time vs. Ambient Temperature

10/14

XC61F

Series

■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)

(8) Release Delay Time vs. Input Voltage

11/14

XC61F Series

■PACKAGING INFORMATION

●SOT-23

●SOT-89

●TO-92

12/14

XC61F

Series

■MARKING RULE

●SOT-23, SOT-89

① represents integer of detect voltage and output configuration

CMOS output (XC61FC series)

MARK

CONFIGURATION

CMOS

VOLTAGE (V)

0.x

1.x

2.x

3.x

4.x

5.x

6.x

CMOS

①

②

③

④

CMOS

N-channel open drain (XC61FN series)

MARK

CONFIGURATION

VOLTAGE (V)

N-ch

0.x

1.x

2.x

3.x

4.x

5.x

6.x

② represents decimal number of detect voltage

MARK

VOLTAGE (V)

MARK

VOLTAGE (V)

x.0

x.1

x.2

x.3

x.4

x.5

x.6

x.7

x.8

x.9

③ represents delay time

VOLTAGE (V)

DELAY TIME

50 ~ 200ms

80 ~ 400ms

1 ~ 50ms

④ represents assembly lot number (Based on internal standards)

●TO-92

① represents output configuration

MARK

OUTPUT CONFIGURATION

CMOS

N-ch

①

⑤

⑦

②

③

④

⑥

②, ③ represents detect voltage

MARK

VOLTAGE (V)

②

③

3.3

5.0

④ represents delay time

MARK

DELAY TIME

50ms ~ 200ms

80ms ~ 400ms

1ms ~ 50ms

TO-92 (T Type)

（TOP VIEW）

⑤ represents detect voltage accuracy

MARK

DETECT VOLTAGE ACCURACY

Within +2%

⑥ represents a least significant digit of the production year (ex.)

MARK

PRODUCTION YEAR

2003

2004

⑦ represents production lot number

0 to 9, A to Z repeated (G, I, J, O, Q, W excluded)

13/14

XC61F Series

1. The products and product specifications contained herein are subject to change without

notice to improve performance characteristics. Consult us, or our representatives

before use, to confirm that the information in this datasheet is up to date.

2. We assume no responsibility for any infringement of patents, patent rights, or other

rights arising from the use of any information and circuitry in this datasheet.

3. Please ensure suitable shipping controls (including fail-safe designs and aging

protection) are in force for equipment employing products listed in this datasheet.

4. The products in this datasheet are not developed, designed, or approved for use with

such equipment whose failure of malfunction can be reasonably expected to directly

endanger the life of, or cause significant injury to, the user.

(e.g. Atomic energy; aerospace; transport; combustion and associated safety

equipment thereof.)

5. Please use the products listed in this datasheet within the specified ranges.

Should you wish to use the products under conditions exceeding the specifications,

please consult us or our representatives.

6. We assume no responsibility for damage or loss due to abnormal use.

prior permission of TOREX SEMICONDUCTOR LTD.

14/14

XC61FN5612PL-G [TOREX]

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