JT6N38S [TOSHIBA]

IC SPECIALTY CONSUMER CIRCUIT, UUC20, WAFER-20, Consumer IC:Other;
JT6N38S
型号: JT6N38S
厂家: TOSHIBA    TOSHIBA
描述:

IC SPECIALTY CONSUMER CIRCUIT, UUC20, WAFER-20, Consumer IC:Other

商用集成电路
文件: 总7页 (文件大小:109K)
中文:  中文翻译
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JT6N38S  
TOSHIBA CMOS Integrated Circuit Silicon Monolithic  
J T 6 N 3 8 S  
Single-Chip System LSI for RFID Card  
The JT6N38S is a system LSI for radio frequency identification (RFID) wireless cards. The JT6N38S  
incorporates an analog circuit, a data processing circuit and data memory in a single chip.  
Features  
High-noise-resistant PSK modulation:  
binary phase-shift keying (BPSK) for both reader-to-RFID and RFID-to-reader transmission.  
Start-stop synchronization and half-duplex transmission: with parity, 1 stop bit  
High-efficiency power generation circuit using electromagnetic induction:  
battery less operation, full-wave rectifier circuit, shunt regulator  
Data processing logic circuit: digital PLL, security circuit  
High-reliablity E2PROM: 4 Kbits  
Maximum write time: 7 ms (16-byte batch write)  
Overwrite: 100,000 times  
Data retention: 10 years  
Selectable receive carrier frequency: 120 kHz to 500 kHz (when external antenna circuit is used)  
Serial transmitter circuit (for active PSK): long-distance communication supported  
Programmable security circuit: security level can be set  
High-speed transfer rate of 25 kbps: 1/16 of receive carrier frequency = 400 kHz  
High-speed multi-read of 32 IDs per second: when receive carrier frequency = 400 kHz (ID only read)  
Supplied as chips or on wafer  
Chip thickness: 175 µm (typ.)  
000707EDA1  
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general  
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the  
buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and  
to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or  
damage to property.  
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the  
most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling  
Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..  
The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal  
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are  
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or  
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy  
control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control  
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document  
shall be made at the customer’s own risk.  
The products described in this document are subject to the foreign exchange and foreign trade laws.  
The products described in this document contain components made in the United States and subject to export control of the U.S.  
authorities. Diversion contrary to the U.S. law is prohibited.  
The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by  
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its  
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or  
others.  
The information contained herein is subject to change without notice.  
2000-07-21 1/7  
JT6N38S  
System Block Diagram  
0.1 µF (recommended value)  
VZ  
V
DD  
ANT1  
V
DD  
Rectifier  
circuit  
Shunt  
regulator  
Voltage  
detector  
circuit  
Data processing,  
security and  
multi-read functions  
ANT2  
GND  
BGR  
2
E PROM  
(4 Kbits)  
Transmission  
circuit  
Transmission  
control  
Modulator  
circuit  
Carrier  
extraction circuit  
Demodulator  
PLL  
OSC  
2000-07-21 2/7  
JT6N38S  
Pad Allocation  
Y
X
0
2.51 mm  
Pad Coordinates  
Pad No.  
Pad Name  
X-Coordinate (µm)  
Y-Coordinate (µm)  
1
2
Test pin  
Test pin  
Test pin  
Test pin  
ANT1  
989  
849  
709  
569  
1108  
968  
1419  
1419  
1419  
1419  
1419  
1419  
1419  
1419  
1419  
1419  
1419  
1419  
1419  
1419  
1419  
1419  
1419  
1419  
1419  
1419  
3
4
5
6
ANT2  
7
Test pin  
GND  
828  
8
688  
9
V
548  
DD  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
Test pin  
Test pin  
Test pin  
Test pin  
Test pin  
Test pin  
Test pin  
Test pin  
Test pin  
Test pin  
Test pin  
408  
268  
128  
12  
152  
292  
432  
572  
712  
852  
1000  
Note: Values for X-and Y-coordinates are pad center values.  
2000-07-21 3/7  
JT6N38S  
Pin Functions  
Pin No.  
Symbol  
Function  
Rectifier diode input, antenna connection pin 1  
5
ANT1  
ANT2  
VZ  
6
Rectifier diode input (carrier extraction input side), antenna connection pin 2  
Bridge diode output for rectification  
7
8
GND  
GND-internal circuit voltage reference  
9
V
Power supply for regulator voltage and internal circuits  
LSI test pins  
DD  
1~4, 10~20  
LSI External Specifications  
Parameter  
Specifications  
Power supply  
Battery less-externally supplied by electromagnetic induction  
Electromagnetic induction  
Coupling type  
Power feed frequency  
120 kHz~500 kHz  
Note: External devices such as antenna and capacitors must be selected.  
Receive: PSK, Transmission: PSK  
(carrier frequency is half the power feeding frequency)  
Communications method  
Transfer speed  
Transfer method  
Memory size  
Write time  
1/16 of power feeding frequency  
Half-duplex start-stop synchronization transmission (with parity, 1 stop bit)  
2
4-Kbit E PROM (512 bits are used as security area.)  
7 ms max (for batch write of 16 bytes)  
Key checking and access level control by hardware  
Incorporates six access keys (6-byte key and 2-byte status).  
Using access keys, read-only or write/read privilege can be set independently for each 64-byte  
area (programmable security).  
Control circuit  
Block write or read in units of 16 bytes using an access key and physical address.  
Controls multi-read using Multi-Read command.  
Multi-read  
32 reads/s (typical value with power feed frequency of 400 kHz)  
Operating temperature  
20°C~+85°C  
2000-07-21 4/7  
JT6N38S  
Functions and Specifications of the Core Block  
The JT6N38S is comprised of the following: an RF analog block for power generation, carrier extraction and  
regulation, and a digital block for data modulation, demodulation and  
2
data processing an E PROM for data storage.  
1. Analog Block  
(1) Rectifier circuit  
Receives radio wave via the (external) antenna circuit and generates DC power for operating internal  
circuits with full-wave rectification.  
(2) Shunt regulator  
Maintains the voltage generated by the rectifier circuit at a fixed voltage, 3.1 V (typ.).  
2
The digital circuits and E PROM operate using the voltage supplied by the shunt regulator.  
The shunt regulator also protects internal circuits from the effects of strong electric fields.  
(3) Carrier extraction circuit  
Shapes the PSK-processed received carrier in to a square wave which is then input to the logic  
circuits for demodulation.  
(4) Oscillation circuit (OSC)  
Generates a clock for the digital PLL in the logic block.  
(Oscillation frequency range: 8 MHz~12 MHz)  
(5) Transmitter circuit (serial transmitter circuit for active PSK)  
Powerfully modulates transmission by switching the line between the rectifier circuit and the shunt  
regulator. The switching is performed at half the received carrier frequency. That is, the transmission  
carrier frequency is half the received carrier frequency.  
Note that when the rectifier circuit and the shunt regulator are left open, protection is performed for  
the bridge rectifier circuit so that the voltage at the bridge rectifier circuit is up to three times the  
remaining voltage of the shunt regulator.  
(6) Voltage detector  
Supports three types of voltage detector circuit for initializing the system and enabling/disabling  
2
E PROM writing. As a result, operation is always stable.  
2. Digital Block  
(1) Demodulator  
Converts the PSK signal shaped by the carrier extraction circuit of the analog block into binary data.  
(2) Digital PLL  
Compares the frequency of the oscillator circuit in the analog block with the signal shaped by the  
carrier extraction circuit and generates a clock with a fixed frequency for operation of the entire  
digital block. Using the clock the internal LSI operates in synchronize with the carrier.  
(3) Data processing  
2
Processes data according to the commands received. Processes include parity check, E PROM write  
and read, and reset of the entire LSI.  
(4) Security logic  
2
Six keys can be set simultaneously using the security area allocated to the E PROM. Using the keys,  
2
write/read, read or no access can be set in units of 64-byte blocks (obtained by dividing E PROM  
memory area by four). (For example, with key A, read/write for a particular block can be set, while  
with key B, read/write for all block can be set.)  
(5) Status reply  
Replies to a command from the R/W consist of the status followed by data. The status represents, the  
internal status of the LSI to the R/W. If the LSI status is normal, status data 00H is inserted at the  
beginning (without any parity, start or end bits) followed by the data. If the LSI status is abnormal,  
no data follows and only the status indicating the abnormality is sent. The bit corresponding to each  
abnormality condition which has occurred is set to 1 in the status field.  
(6) Multi-read  
Multi-read is a function used for reading multiple RFIDs in the communications area using the same  
reader/writer (R/W). An RFID (LSI) generates a random number internally using the Multi-Read  
command transmitted by the R/W. The RFID replies using the response timing determined by the  
corresponding time slot. Thus, replies from the different RFIDs will not conflict, enabling data to be  
received properly by the R/W.  
Note: Depending on the reading environment, the ability to read all the data may fluctuate . In some  
cases, some data may be left unread (since it cannot be undetected). Toshiba recommend the use of an  
additional chip with a detection function other than the multi-read function.  
2000-07-21 5/7  
JT6N38S  
Electrical Characteristics  
1. Ratings  
Operating Rating  
DC30  
Parameter  
Symbol  
Unit  
mA  
Input current  
I
ANT  
(between ANT1 GND ANT2)  
Operating temperature range  
Storage temperature range  
T
20~+85  
°C  
°C  
opr  
T
50~+150  
stg  
*: Unless otherwise specified, the specifications are within the above operating temperature range.  
2. DC Characteristics (Ta = −20~+85°C)  
Test  
Circuit  
Parameter  
Symbol  
Description  
Min  
Typ.  
2.0  
Max  
2.2  
Unit  
V
Minimum operating voltage  
excluding memory write  
(Voltage check pin is V .)  
Minimum operating voltage 1  
V
(min)  
DD  
DD  
Minimum operating voltage  
including memory write  
Minimum operating voltage 2  
Operating current dissipation 1  
V
(eew)  
2.7  
2.9  
V
DD  
(Voltage check pin is V .)  
DD  
Current dissipation for  
operations excluding memory  
I
I
400  
600  
µA  
µA  
DDopr1  
write (V  
= 2.5 V)  
DD  
Current dissipation for all  
operations including memory  
Operating current dissipation 2  
Reply Peak Voltage  
600  
2.5  
900  
DDopr2  
write (V  
= 2.9 V)  
DD  
Peak voltage of VZ pin at reply  
V
psk  
(V  
as reference) times  
DD  
3. Operation Characteristics (Ta = −20~+85°C)  
Test  
Circuit  
Parameter  
Symbol  
Description  
Min  
120  
Typ.  
Max  
500  
Unit  
kHz  
Carrier frequency at which  
operation is possible  
Receive carrier frequency  
f
crr  
Reply carrier frequency  
Transfer rate  
f
Carrier frequency at reply  
Transfer speed  
fcrr × 1/2  
kHz  
bps  
psk  
fcrr × 1/16  
Receiving carrier frequency per  
bit  
Receive 1-bit frequency  
16  
Cycles  
Reply 1-bit frequency  
Reply carrier frequency per bit  
8
Cycles  
ms  
2
E PROM write time  
t
7
pw  
2
5
No. of  
times  
E PROM overwrite time  
10  
2
E PROM data hold time  
10  
Years  
2000-07-21 6/7  
JT6N38S  
Memory Map  
Page No  
00H  
Page No  
16-Byte Block  
ATR data  
16-Byte Block  
01H  
03H  
05H  
07H  
09H  
0BH  
0DH  
0FH  
11H  
13H  
15H  
17H  
19H  
1BH  
1DH  
1FH  
Key 0010  
Key 0110  
Key 0011  
Key 0111  
02H  
04H  
06H  
08H  
0AH  
0CH  
0EH  
10H  
12H  
14H  
16H  
18H  
1AH  
1CH  
1EH  
Key 0100  
Key 0101  
Any data  
Any data  
Any data  
Any data  
Any data  
Any data  
Any data  
Any data  
Any data  
Any data  
Any data  
Any data  
Any data  
Any data  
Any data  
Any data  
Any data  
Any data  
Any data  
Any data  
Any data  
Any data  
Any data  
Any data  
Any data  
Any data  
Any data  
Any data  
Note 1: ATR: Answer to Reset. The LSI sends back the ATR data after receiving a reset command or self reset.  
Note 2: Using the keys at 01H to 03H, access privileges can be set for the 64-byte blocks (enclosed by bold lines)  
from 04H to 1FH. A key area consists of 8 bytes.  
2
Note 3: Write to E PROM is performed in units of 16 bytes to addresses matching the page numbers above.  
The advantage of using this LSI is that it can be supplied as a single LSI for RFID allowing the user to configure  
peripherals (e.g. antennae, and reader/writers) so as to develop the desired system. However, because the  
peripheral environment may be highly user-specific, incompatibilities between the LSI and the user-configured  
environment (communications failures) may occur. Please carry out sufficient research before using this LSI.  
2000-07-21 7/7  

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