TB62201AFG_技术文档

TB62201AFG

TOSHIBA Bi-CMOS Processor IC Silicon Monolithic

TB62201AFG

Dual-Stepping Motor Driver IC for OA Equipment Using PWM Chopper Type

The TB62201AFG is a dual-stepping motor driver driven by

chopper micro-step pseudo sine wave.

To drive two-phase stepping motors, Two pairs of 16-bit latch and

shift registers are built in the IC. The IC is optimal for driving

stepping motors at high efficiency and with low-torque ripple.

The IC supports Mixed Decay mode for switching the attenuation

ratio at chopping. The switching time for the attenuation ratio

can be switched in four stages according to the load.

Features

z Two stepping motors driven by micro-step pseudo sine wave

Weight: 0.79 g (typ.)

are controlled by a single driver IC

z Monolithic Bi-CMOS IC

z Low ON-resistance of Ron = 0.5 Ω (T = 25°C @ 1.0 A: typ.)

j

z ESD protection Exceeds 2000 V, MIL-STD-883D

z Two pairs of built-in 16-bit shift and latch registers

z Two pairs of built-in 4-bit DA converters for micro steps

z Built-in ISD, TSD, V &V power monitor (reset) circuit for protection

DD

M

z Built-in charge pump circuit (two external capacitors)

z 36-pin power flat package (HSOP36-P-450-0.65)

z Output voltage: 40 V max

z Output current: 1.5 A/phase max

z Built-in Mixed Decay mode enables specification of four-stage attenuation ratio.

(The attenuation ratio table can be overwritten externally.)

z Chopping frequency can be set by external resistors and capacitors. High-speed chopping possible at 100 kHz or

higher.

Note: When using the IC, pay attention to thermal conditions.

These devices are easy damage by high static voltage.

In regards to this, please handle with care.

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TB62201AFG

Block Diagram

1. Overview (Power lines: A/B unit (C/D unit is the same as A/B unit))

Mixed decay timing, table logic circuit

RESET

16-bit shift

Mixed decay

register

16-bit latch

timing table

selector

SETUP

Current control data logic circuit

Chopping reference

circuit

DATA

CLK

16-bit shift

register

Chopping

waveform

generator

circuit

DATA

input

16-bit latch

CR

selector

STROBE

Waveform

shaping

circuit

Current Setting

Torque

control

4-bit D/A

(angle control)

V

ref

Current feedback circuit

V

R COMP

S

circuit 1

RS

Output control circuit

R

S

circuit 1

V

RS

R COMP

S

M

circuit 2

ISD

TSD

circuit

Charge

pump

Output circuit

(H-bridge)

circuit

V

/V

DDR MR

circuit

V

M

V

DD

Protected circuit

Out X

High-Voltage Wiring (V )

M

Stepping

motor

Logic data

Analog data

IC Terminal

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TB62201AFG

2. Logic Unit A/B (C/D unit is the same as A/B unit)

Function

This circuit is used to input from the DATA pins micro-step current setting data and to transfer them to the

subsequent stage. By switching the SETUP pin, the data in the mixed decay timing table can be

overwritten.

Mixed decay timing table logic circuit

Mixed

decay

timing

table 1

Mixed

decay

timing

table 2

Mixed

decay

timing

table 3

Mixed

decay

timing

table 4

Mixed

decay

Initial

setup

circuit

timing

table selector

16-bit latch

Mixed

decay

timing

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

Output

control

circuit

0

1

2

3

16-bit shift register

Micro-step current setting data logic circuit

16-bit shift register

SETUP

DATA

CLK

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

A unit side

16-bit latch

STROBE

Data input

selector

Decay

Current

× 4 bits

B unit side

Phase

× 1 bit

B unit side

Torque

× 2 bits

B unit side

RESET

Current feedback circuit

D/A circuit

Output control circuit

Note: The RESET and SETUP pins are pulled down in the IC by 10 kΩ resistor.

When not using these pins, connect them to GND. Otherwise, malfunction may occur.

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TB62201AFG

3. Current Feedback Circuit and Current Setting Circuit

(A/B unit (C/D unit is the same as A/B unit))

Function

The current setting circuit is used to set the reference voltage of the output current using the micro-step

current setting data input from the DATA pins.

The current feedback circuit is used to output to the output control circuit the relation between the set

current value and output current. This is done by comparing the reference voltage output to the current

setting circuit with the potential difference generated when current flows through the current sense

resistor connected between RS and V .

M

The chopping waveform generator circuit to which CR is connected is used to generate clock used as

reference for the chopping frequency.

Logic

unit

TORQUE

0, 1

CURRENT

0 to 3

V

ref

15

100%

14

13

12

11

10

9

CR

85%

70%

50%

Micro-step

current

setting

TORQUE

control

circuit

8

selector

circuit

7

6

Mixed

decay

timing

circuit

5

4

Waveform shaping circuit

3

4-bit

D/A

2

1

circuit

Chopping reference circuit

0

Current setting circuit

Output stop signal (ALL OFF)

Use in Charge mode

V

circuit 1

RS

(detects

potential

Output

control

circuit

R

COMP

S

circuit 1

(Note 1)

difference

between

R

NF

(set current

reached signal)

R

V

S

and V )

S

M

V

RS

circuit 2

M

(detects

R

S

COMP

potential

difference

between

RNF

circuit 2

(Note 2)

(set current

monitor signal)

V

M

and R )

S

Use in Fast mode

Current feedback circuit

Note 1: RS COMP 1: Compares the set current with the output current and outputs a signal when the output current

reaches the set current.

Note 2: RS COMP 2: Compares the set current with the output current at the end of Fast mode during chopping.

Outputs a signal when the set current is below the output current.

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TB62201AFG

4. Output Control Circuit, Current Feedback Circuit and Current Setting Circuit

(A/B unit (C/D unit is the same as A/B unit))

Micro-step current setting

data logic circuit

Chopping

reference circuit

Decay

mode

Mixed

decay

timing

circuit

Output control circuit

Phase

NF

set current

reached signal

Current

feedback

circuit

CR

counter

Mixed

RNF

decay

timing

set current

monitor signal

CR counter

charge start

Current

setting

circuit

U

L

1

2

1

2

Output stop

signal

Output

circuit

Output control circuit

L

V

DD

V

M

Output reset signal

Power supply

for upper

RESET

output MOS

transistors

Output

circuit

ISD (current

shutdown)

circuit

Charge

pump

halt

V

H

Output pin

signal

Reset signal

V

MR

circuit

Ccp A

Ccp B

Ccp C

Charge pump

circuit

V

M

selector

circuit

V

DDR

V

DD

circuit

Thermal

shut down

(TSD)

circuit

Charge pump

circuit

Protection circuit

Micro-step

current

Mixed decay

timing table

clear signal

V

: V

power on Reset

DDR DD

setup latch clear

signal

V

MR

:

V

M

ISD: Current shutdown circuit

TSD: Thermal shutdown circuit

Logic

Note: The RESET pins is pulled down in the IC by 10-kΩ resistor.

When not using the pin, connect it to GND. Otherwise, malfunction may occur.

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TB62201AFG

5. Output Equivalent Circuit (A/B unit (C/D unit is the same as A/B unit))

To V

M

R

S A

R

RS A

Output driver

circuit

U

1

U

1

U

2

L

1

From

2

output

control

circuit

Output A

Power supply

for upper

L

1

L

2

output MOS

transistors

(V )

H

Phase A

V

M B

R

S B

R

RS B

Output driver

circuit

U

1

U

1

U

2

L

1

From

2

Output B

output

control

circuit

M

Output B

Power supply

for upper

L

1

L

2

output MOS

transistors

(V )

H

Phase B

PGND

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TB62201AFG

6. Input Equivalent Circuit

(1) Logic input circuit (CLK, DATA, STROBE)

V

27

IN

DD

To logic IC

150 Ω

30/29/31

25/26/24

GND

F

IN

(2) Input circuit (SETUP, RESET )

V

27

IN

DD

To logic IC

150 Ω

6/28

GND

F

IN

(3)

V

ref

input circuit

V

27

IN

DD

4

9/10

To D/A circuit

GND

F

IN

Note: The SETUP and RESET pins are pulled down. Do not use them open.

When not using these pins, connect them to GND.

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TB62201AFG

Pin Assignment

(Top view)

V

1

2

3

4

5

6

7

8

9

36

35

34

33

32

31

30

29

28

V

M B

M A

OUT B

OUT A

R

S A

S B

PGND

OUT B

SETUP

Ccp A

CR

PGND

OUT A

STROBE AB

CLK AB

DATA AB

RESET

V

REF AB

TB62201AFG

V

(F

)

V

(F )

IN

SS

IN

SS

DD

V

27

26

25

24

23

22

21

20

19

REF CD

NC

10

11

12

13

14

15

16

DATA CD

CLK CD

STROBE CD

OUT C

Ccp B

Ccp C

OUT D

PGND

R

S D

R

S C

OUT D

OUT C

17

18

V

MC

MD

Note: [Important] If this IC is inserted reverse, voltages exceeding the voltages of standard may be applied to some

pins, causing damage.

Please confirm the pin assignment before mounting and using the IC.

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TB62201AFG

Pin Description

Pin No.

Pin Symbol

Description

Voltage major for output B block

1

2

3

4

5

6

7

8

9

V

M B

OUT B

Output B pin

R

S B

Channel B current pin

PGND

OUT B

SETUP

Power GND pin

Output B pin

CR setup switching pin (L: normal, H: setup)

Capacitor pin for charge pump (Ccp1)

External C/R (osc) pin (sets chopping frequency)

C

cp

A

CR

V

input pin AB

ref

REF AB

F

IN

V

F (V ): Logic GND pin

IN SS

SS

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

V

Vref input pin CD

REF CD

NC

Non conection

C

B

C

Capacitor pin for charge pump (Ccp2)

Output D pin

cp

OUT D

PGND

Power GND pin

R

S D

Channel D current pin

Output D pin

OUT D

V

Voltage major for output D block

Voltage major for output C block

Output C pin

M D

M C

OUT C

R

S C

Channel C current pin

Power GND pin

PGND

OUT C

Output C pin

STROBE CD CD STROBE (latch) signal input pin (

: LATCH)

CLK CD

CD clock input pin

DATA CD

CD serial data signal input pin

Power pin for logic block

V

DD

F

IN

V

F (V ) : Logic GND pin

IN SS

SS

28

RESET

DATA AB

CLK AB

Output reset signal input pin (L: RESET)

AB serial data signal input pin

AB clock input pin

29

30

31

32

33

34

35

36

STROBE AB

OUT A

AB STROBE (latch) signal input pin (

Output A pin

: LATCH)

PGND

Power GND pin

R

S A

Channel A current pin

OUT A

Output A pin

V

Voltage major for output A block

M A

Note: How to handle GND pins

All power GND pins and FIN (V : signal GND) pins must be grounded.

SS

Since FIN also functions as a heat sink, take the heat dissipation into consideration when designing the board.

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TB62201AFG

Signal Functions

1. Serial Input Signals (for A/B. C/D is the same as A/B)

Data No.

Name

TORQUE 0

Functions

0

LSB

DATA No.0, 1 = HH: 100%, LH: 85%

HL: 70%, LL: 50%

1

TORQUE 1

2

DECAY MODE B

0

1

00: DECAY MODE 0, 01: DECAY MODE 1

10: DECAY MODE 2, 11: DECAY MODE 3

3

4

Current B

0

1

2

3

Used for setting current.

(LLLL = Output ALL OFF MODE)

4-bit current B data

5

6

(Steps can be divided into 16 by 4-bit data)

7

(Note 1)

8

PHASE B

Phase information (H: OUT A: H, OUT A: L)

9

DECAY MODE A

0

1

00: DECAY MODE 0, 01: DECAY MODE 1

10: DECAY MODE 2, 11: DECAY MODE 3

10

11

Current A

0

1

2

3

Used for setting current.

(LLLL = Output ALL OFF MODE)

4-bit current A data

12

13

(Steps can be divided into 16 by 4-bit data)

14

15 MSB

PHASE A

Phase information (H: OUT A: H, OUT A : L)

Note 1: Serial data input order

Serial data are input in the order LSB (DATA 0)

→ MSB (DATA 15)

Role of Data

Data Name

Number of Bits

2

Functions

Roughly regulates the current (four stages).

Common to A and B units.

TORQUE

Selects Decay mode.

A and B units are set separately.

DECAY MODE

CURRENT

PHASE

2 × 2 phases

4 × 2 phases

1 × 2 phases

Sets a 4−bit micro−step electrical angle.

A and B units are set separately.

Determines polarity (+ or −).

A and B units are set separately.

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TB62201AFG

2. Serial Input Signal Functions

Input

Action

VDDR

(Note 2) or

Operation of

TSD/ISD

CLK

STROBE

DATA

RESET

(Note 2)

V

MR

×

H

L

×

H

L

No change in shift register.

H

H level is input to shift register.

L level is input to shift register.

Shift register data are latched.

Qn

×

Output off, charge pump halted

(S/R DATA CLR)

×

L

×

L

Output off (S/R DATA CLR)

Charge pump halted

×

L

Mixed decay timing table cleared (only V

)

DDR

Output off (S/R DATA HOLD)

Charge pump halted

×

H

Restored when RESET goes from Low to High

×:

Qn:

Note 1: V

Don’t Care

Latched output level when STROBE is

and V

.

DDR

MR

H when the operable range (3 V typical) or higher and L when lower.

When one of V or V is operating, the system resets (OR relationship).

DDR

MR

Note 2: High when TSD is in operation.

When one of TSD or ISD is operating, the system resets (OR relationship).

Note:

Function of overcurrent protection circuit

Until the RESET signal is input after ISD is triggered, the overcurrent protection circuit remains in operation.

During ISD, the charge pump stays halted.

When TSD and ISD are operating, the charge pump halts.

3. PHASE Functions

Input

Function

H

L

Positive polarity (A: H, Α : L)

Negative polarity (A: L, Α : H)

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TB62201AFG

4. DECAY Mode X0, X1 Functions

DECAY MODE X1

DECAY MODE X0

Function

Decay mode 0

(Initial value: SLOW DECAY MODE)

L

H

L

Decay mode 1

(Initial value: MIXED DECAY MODE: 37.5%)

Decay mode 2

(Initial value: MIXED DECAY MODE: 75%)

H

Decay mode 3

(Initial value: FAST DECAY MODE)

H

5. TORQUE Functions

TORQUE 0

TORQUE 1

Comparator Reference Voltage Ratio

H

L

H

L

100%

85%

70%

50%

H

L

6. Current AX (BX) Functions

Set Angle

Step

A

B

0

3

2

1

0

3

2

1

16

15

14

13

12

11

10

9

90.0

84.4

78.8

73.1

67.5

61.2

56.3

50.6

45.0

39.4

33.8

28.1

22.5

16.9

11.3

5.6

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

8

L

H

7

H

L

H

L

H

L

H

L

6

L

H

L

5

L

H

L

H

L

4

L

H

3

L

H

L

H

L

H

L

2

L

H

1

L

H

L

H

0

0.0

L

By inputting the above current data (A: 4-bit, B: 4-bit), 17-microstep drive is possible. For 1 step fixed to 90

degrees, see the section on output current vector line (83 page).

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TB62201AFG

7. SETUP Functions

Input

Function

H

L

Decay timing data input mode

Normal operating mode

Note: The SETUP pin is pulled down in the IC by 10-kΩ resistor.

8. Serial Data Input Setting (Normal operation)

SETUP pin: L

DATA

CLK

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

STROBE

Note: Data input to the DATA pin are 16-bit serial data.

Data are transferred from DATA 0 (Torque 0) to DATA 15 (Phase A). Data are input and transferred at the

following timings.

At CLK falling edge: data input

At CLK rising edge: data transfer

After data are transferred, all data are latched on the rising edge of the STROBE signal.

As long as STROBE is not rising, the signal can be either Low or High during data transfer.

9. Serial Data Input Setting (Decay timing setup)

SETUP pin: H

DATA

CLK

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

STROBE

Note: Data input to the DATA pin are 16-bit serial data.

•

Data are transferred from DATA 0 (Current Mode 1) to DATA 15 (DECAY MODE X-4). Data are input and

transferred at the following timings.

•

At CLK falling edge: data input

At CLK rising edge: data transfer

After data are transferred, all data are latched on the rising edge of the STROBE signal.

As long as STROBE is not rising, the signal can be either Low or High during data transfer.

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TB62201AFG

10. Conditions on Overwriting MIXED DECAY TIMING Table

If the following conditions are satisfied, the table can be overwritten.

• When RESET = H (when RESET = L, the shift register is cleared, thus data cannot be input)

• When an internal reset is not triggered.

1) When the temperature is such that TSD is not triggered (or not reset by TSD).

2) Under a condition where ISD is not triggered (or not reset by ISD).

3) Both V

and V are within the operating voltage.

M

DD

Note 1: While the output transistors are operating, do not rewrite the values in the mixed decay timing

table.

Note 2: The SETUP pins is pulled down in the IC by 10-kΩ resistor

When not using the pin, connect it to GND. Otherwise, malfunction may occur.

11. Data Input Signal at Setting Mixed Decay Timing Table

Data No.

Name

Function

Initial Value

15 MSB

Current Mode 3

Selects Slow or Mixed Decay mode

1 : MIXED DECAY MODE

14

13

12

11

10

9

DECAY MODE 3-2

DECAY MODE 3-1

DECAY MODE 3-0

Current Mode 2

Sets decay 3 ratio (decay 3 raito)

1

↑

1

↑↑

1 : 100% : FAST DECAY MODE

Selects Slow or Mixed Decay mode

1 : MIXED DECAY MODE

DECAY MODE 2-2

DECAY MODE 2-1

DECAY MODE 2-0

Current Mode 1

Sets decay 2 ratio

1

↑

0

8

↑

1 : 75% MIXED DECAY

7

Selects Slow or Mixed Decay mode

1 : MIXED DECAY MODE

6

DECAY MODE 1-2

DECAY MODE 1-1

DECAY MODE 1-0

Current Mode 0

Sets decay 1 ratio

0

5

↑

1

4

↑

0 : 37.5% MIXED DECAY

3

Selects Slow or Mixed Decay mode

0 : SLOW DECAY MODE

2

DECAY MODE 0-2

DECAY MODE 0-1

DECAY MODE 0-0

Sets decay 0 ratio

0

1

↑

0

0 LSB

0 (SLOW DECAY MODE)

Note 1: Input order of serial data

When setting decay timing, first input H to the SETUP pin, the same as for ordinary data, then

input data from LSB (DATA 0) to MSB (DATA 15).

When power is first turned on, the initial values in the table above are set as defaults.

Once latched, data are not cleared except by VDDR (power-on and power-off reset).

Next, after the mode changes to SETUP, the data are retained until mixed decay timing data are input and

latched.

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TB62201AFG

12. Function of Setting Mixed Decay Timing

CURRENT

MODE X

DECAY MODE DECAY MODE

DECAY MODE

X-0

MIXED DECAY TIMING

X-2

X-1

0%

L

Don’t care

(SLOW DECAY MODE)

H

L

H

L

12.5%

25.0%

37.5%

50.0%

62.5%

75.0%

87.5%

L

H

L

H

L

H

L

H

L

H

100%

H

(FAST DECAY MODE)

Mixed decay timing means the time for switching Slow mode to Fast mode in MIXED DECAY MODE.

In Mixed Decay mode, the Fast mode time at the end of chopping Cycle (T ) is fixed by data.

chop

The IC is switched from Slow to Fast mode according to the percentage representing mode time in the table

above.

(For example, 12.5% means that 12.5% of the time is in Fast mode and the rest of the time, 87.5%, in

Charge and Slow modes.)

Only when the value is maximum (100%), the mode is Fast Decay mode.

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TB62201AFG

Maximum Ratings (Ta = 25°C)

Characteristics

Symbol

Rating

Unit

Logic supply voltage

Output voltage

V

7

V

DD

V

40

1.5

V

M

Output current

I

A/phase (Note 1)

V

OUT

Current detect pin voltage

V

4.5

+ 7.0

+ 0.4

RS

M

Charge pump pin maximum voltage

(CCP1 pin)

V

H

Logic input voltage

V

to V

DD

IN

1.4

3.2

W

(Note 2)

(Note 3)

Power dissipation

P

D

Operating temperature

Storage temperature

Junction temperature

T

−40 to 85

−50 to 150

150

°C

opr

T

stg

T

j

Note 1: Perform thermal calculations for the maximum current value under normal conditions. Use the IC at 1.2 A or

less per phase.

Note 2: Input 7 V or less as V

.

IN

Note 3: Measured for the IC only. (Ta = 25°C)

Note 4: Measured when mounted on the board. (Ta = 25°C)

Ta: IC ambient temperature

T

: IC ambient temperature when starting operation

opr

T : IC chip temperature during operation T (max) is controlled by TSD (thermal shut down circuit)

j

Recommended Operating Conditions (Ta = 0 to 85°C)

Characteristics

Power supply voltage

Symbol

Test Condition

Min

Typ.

Max

Unit

V

⎯

4.5

20

5.0

24

5.5

34

V

DD

Output voltage

V

= 5.0 V

DD

M

Ta = 25°C, per phase

I

⎯

1.1

1.3

A

OUT (1)

OUT (2)

(when one motor is driven)

Output current

Ta = 25°C, per phase

(when two motors are driven)

Logic input voltage

Clock frequency

V

⎯

GND

1.0

40

⎯

6.25

100

3.0

V

MHz

kHz

V

IN

DD

f

V

= 5.0 V

25

CLK

DD

Chopping frequency

Reference voltage

Current detect pin voltage

f

150

chop

V

= 24 V, T

orque

= 100%

2.0

0

V

ref

M

DD

V

= 5.0 V

1.0

1.5

V

RS

DD

Note: Use the Maximum Junction Temperature (T ) at 120°C or less

j

16

2005-04-04

TB62201AFG

Electrical Characteristics 1

(unless otherwise specified, Ta = 25°C, V = 5 V, V = 24 V)

DD

M

Test

Circuit

Characteristics

Symbol

Test Condition

Min

2.0

Typ.

Max

Unit

V

DD

High

Low

V

DD

IN (H)

+ 0.4

Input voltage

1

2

CLK, RESET , STROBE, DATA pins

GND

− 0.4

V

GND

0.8

IN (L)

I

⎯

1.0

IN1 (H)

Input current 1

Input current 2

CLK, STROBE, DATA pins

RESET , SETUP pins

µA

I

IN1 (L)

IN2 (H)

I

700

I

IN2 (L)

V

= 5 V (STROBE, RESET ,

DD

I

DATA = L), RESET = L,

Logic, output all off

⎯

3.0

4.0

6.0

80

DD1

DD2

Power dissipation (V

pin)

2

mA

DD

Output OPEN, f

= 6.25 MHz

DD

CLK

LOGIC ACTIVE, V

= 5 V,

Charge Pump = charged

Output OPEN (STROBE, RESET ,

DATA = L), RESET = L,

Logic, output all off

I

⎯

5.0

12

6.0

20

M1

M2

Charge Pump = no operation

3

4

5

Output OPEN, f

= 6.25 MHz

DD

CLK

LOGIC ACTIVE, V

= 5 V,

Power dissipation (V pin)

M

mA

V

= 24 V, Output off

M

Charge Pump = charged

Output OPEN, f

LOGIC ACTIVE, 100 kHz

= 6.25 MHz

CLK

I

chopping (emulation), Output OPEN,

Charge Pump = charged Ccp1 = 0.22

µF, Ccp2 = 0.01µf

⎯

30

40

M3

V

= V = 24 V, V

= 0 V,

out

Output standby

current

RS

M

Upper

I

−400

−200

⎯

OH

RESET = H, DATA = ALL L

V

= V = 24 V, V = 24 V,

RS

M

out

µA

Output bias current

Upper

Lower

I

OB

RESET = H, DATA = ALL L

V

= V = CcpA = V =24 V,

Output leakage

current

RS

M

out

I

1.0

OL

RESET = L

High

(reference)

V

= 3.0 V, V (Gain) = 1/5.0

ref

V

⎯

83

68

48

100

85

⎯

87

72

52

RS (H)

TORQUE = (H.H) = 100% set

V

= 3.0 V, V (Gain) = 1/5.0

ref

TORQUE = (H.L) = 85% set

Mid high

Mid low

Low

V

RS (MH)

Comparator

reference voltage

ratio

6

7

%

V

= 3.0 V, V (Gain) = 1/5.0

ref

TORQUE = (L.H) = 70% set

V

70

RS (ML)

V

= 3.0 V, V (Gain) = 1/5.0

ref

V

50

RS (L)

TORQUE = (L.L) = 50% set

Differences between output current

channels

Output current differential

∆I

−5

⎯

5

out1

out2

I

= 1000 mA

out

Output current setting differential

RS pin current

∆I

7

8

I

= 1000 mA

−5

⎯

5

%

out

VRS = 24 V, V = 24 V, RESET = L

(RESET status)

M

IRS

⎯

10

µA

17

2005-04-04

TB62201AFG

Test

Circuit

Characteristics

Symbol

Test Condition

Min

⎯

Typ.

0.5

0.6

Max

0.6

Unit

I

= 1.0 A, V

= 5.0 V

DD

out

T = 25°C, Drain-Source

R

ON (D-S) 1

ON (D-S) 2

j

I

= 1.0 A, V

= 5.0 V

DD

out

T = 25°C, Source-Drain

⎯

0.6

j

Output transistor drain-source

on-resistance

9

Ω

I

= 1.0 A, V

= 5 V,

DD

out

T = 105°C, Drain-Source

⎯

0.75

j

I

= 1.0 A, V

= 5 V,

DD

out

T = 105°C, Source-Drain

⎯

j

Electrical Characteristics 2

(unless otherwise specified, Ta = 25°C, V = 5 V, V = 24 V)

DD

M

Test

Circuit

Characteristics

Symbol

Test Condition

Min

Typ.

Max

Unit

V

= 24 V, V

= 5 V,

DD

M

V

input voltage

V

10

2.0

0

⎯

V

DD

ref

RESET = H, Output on

RESET = H, Output off

input current

I

ref

V

= 24 V, V

= 3.0 V

= 5 V,

⎯

100

A

M

ref

DD

V

= 24 V, V

= 5 V,

M

V

attenuation ratio

V

(GAIN)

ref

6

1/4.8

1/ 5.0

1/5.2

⎯

RESET = H, Output on,

ref

V

= 2.0 to V

− 1.0 V

ref

DD

T TSD

(Note 1)

j

TSD temperature

11

12

13

14

V

= 5 V, V = 24 V

130

⎯

170

⎯

°C

V

DD

M

T TSD

j

−35

TSD return temperature difference

∆T TSD

j

T TSD = 130 to 170°C

j

V

= 24 V, RESET = H,

M

V

return voltage

V

2.0

⎯

4.0

⎯

DD

DDR

STROBE = H

V

= 5 V, RESET = H,

DD

STROBE = H

return voltage

V

⎯

V

M

MR

Over current protected circuit

operation current

I

V

= 5 V, V = 24 V,

M

SD

DD

fchop = 100 kHz set

2.6

A

(Note 2)

Note 1: Thermal shut down (TSD) circuit

When the IC junction temperature reaches the specified value and the TSD circuit is activated, the internal

reset circuit is activated switching the outputs of both motors to off.

When the temperature is set between 130 (min) to 170°C (max), the TSD circuit operates. When the TSD

circuit is activated, the function data latched at that time are cleared. Output is halted until the reset is

released. While the TSD circuit is in operation, the charge pump is halted.

Even if the TSD circuit is activated and RESET goes H → L → H instantaneously, the IC is not reset until

the IC junction temperature drops 35°C (typ.) below the TSD operating temperature (hysteresis function).

Note 2: Overcurrent protection circuit

When current exceeding the specified value flows to the output, the internal reset circuit is activated

switching the outputs of both shafts to off.

When the ISD circuit is activated, the function data latched at that time are cleared.

Until the RESET signal is input, the overcurrent protection circuit remains activated.

During ISD, the charge pump halts.

For failsafe operation, be sure to add a fuse to the power supply.

18

2005-04-04

TB62201AFG

Electrical Characteristics 3

(Ta = 25°C, V = 5 V, V = 24 V, I

= 1.0 A)

DD

M

out

Test

Circuit

Characteristics

Symbol

Test Condition

θA = 90 (θ16)

Min

Typ.

Max

Unit

⎯

93

91

87

83

78

72

66

58

51

42

33

24

15

5

100

98

96

92

88

83

77

71

63

56

47

38

29

20

10

0

⎯

97

93

88

82

76

68

61

52

43

34

25

15

⎯

θA = 84 (θ15)

θA = 79 (θ14)

θA = 73 (θ13)

θA = 68 (θ12)

θA = 62 (θ11)

θA = 56 (θ10)

θA = 51 (θ9)

θA = 45 (θ8)

θA = 40 (θ7)

θA = 34 (θ6)

θA = 28 (θ5)

θA = 23 (θ4)

θA = 17 (θ3)

θA = 11 (θ2)

θA = 6 (θ1)

Chopper current

Vector

15

⎯

%

θA = 0 (θ0)

⎯

19

2005-04-04

TB62201AFG

AC Characteristics (Ta = 25°C, V = 24 V, V = 5 V, 6.8 mH/5.7 Ω)

M

DD

Test

Circuit

Characteristics

Clock frequency

Symbol

Test Condition

Min

Typ.

Max

Unit

f

16

⎯

1.0

40

20

40

20

⎯

25

⎯

400

MHz

CLK

t

w (CLK)

Minimum clock pulse width

16

⎯

ns

t

⎯

wp (CLK)

t

⎯

wn (CLK)

t

⎯

STROBE

Minimum STROBE pulse width

t

⎯

STROBE (H)

t

⎯

STROBE (L)

t

⎯

suSIN-CLK

Data setup time

Data hold time

16

⎯

ns

t

⎯

suST-CLK

t

⎯

Hsin-CLK

⎯

t

⎯

hCLK-ST

t

0.1

15

10

1.2

2.5

300

r

Output Load; 6.8 mH/5.7 Ω

t

⎯

f

t

⎯

pLH (ST)

pHL (ST)

pLH (CR)

pHL (CR)

Output transistor switching

characteristic

STROBE (↑) to VOUT

Output Load; 6.8 mH/5.7 Ω

18

µs

⎯

t

⎯

CR to VOUT

Output Load; 6.8 mH/5.7 Ω

⎯

Noise rejection dead band time

t

19

20

I

= 1.0 A

200

ns

BLNK

out

CR reference signal oscillation

frequency

f

C

= 560 pF, R

= 3.6 kΩ

⎯

40

⎯

736

100

⎯

150

⎯

kHz

CR

osc

= 1.0 A)

out

f

Output active (I

Step fixed, Ccp1 = 0.22 µF,

Ccp2 = 0.01 µF

chop (min)

chop (typ.)

chop (max)

Chopping frequency range

Chopping frequency

kHz

f

20

21

Output active (I = 1.0 A)

out

CR CLK = 800 kHz

f

chop

Ccp2 = 0.22 µF, Ccp = 0.01 µF

= 24 V, V = 5 V,

Charge pump rise time

t

⎯

2

4

ms

V

ONG

M

DD

RESET = L → H

20

2005-04-04

TB62201AFG

Test Waveforms (Timing waveforms and names)

t

w (CLK)

50%

CLK

t

hCLK-ST

suST-CLK

t

wp

wn

STROBE

50%

t

STROBE (H)

STROBE (L)

t

STROBE

t

hSIN-CLK

suSIN-CLK

50%

DATA15

DATA0

DATA

50%

CR waveform

(reference)

t

pHL (CR)

t

pHL (ST)

90%

50%

10%

Output

voltage A

t

pLH (CR)

pLH (ST)

90%

50%

10%

90%

50%

10%

OUTPUT

Voltage A

t

f

r

21

2005-04-04

TB62201AFG

Test Waveforms (Timing waveforms and names)

OSC-charge delay

H

OSC-fast delay

OSC (CR)

L

T chop

H

Output

voltage A

50%

L

H

Output

voltage A

50%

L

Set current

Output

current

L

Charge

Slow

Fast

22

2005-04-04

TB62201AFG

Calculation of Set Current

Determining R and V determines the set current value.

RS

ref

T

(T

=100, 85,70,50%: input serial data)

1

orque orque

I

out

(max) =

× V (V) ×

ref

R

(Ω)

V

ref

(GAIN)

RS

1/5.0 is V (gain): V attenuation ratio (typ.).

ref

For example,

to input V = 3 V and Torque = 100% and to output I

ref out

= 0.8 A,

R

RS

= 0.75 Ω (0.5 W or more) is required.

Formulas for Calculating CR Oscillation Frequency (Chopping reference frequency)

The CR oscillation frequency and f

1

can be calculated by the following formulas:

chop

f

=

[Hz]

CR

KA ×(C× R× KB×C)

KA (constant): 0.523

KB (constant): 600

f

CR

8

f

=

[Hz]

chop

Example: When Cosc = 1,000 pF and Rosc = 2.0 kΩ are connected, f

= 735 kHz.

CR

At this time, the chopping frequency f

is: f = f /8 = 92 kHz.

chop CR

chop

1

Note:

f

=

CR

t

CR

t

= t (Charge) + t (Dis- Charge)

CR

CR oscillation CR charge

cycle time

CR distance

time

At this time, t (CR − discharge) is subject to the following condition :

600 ns > t (CR − discharge) > 400 ns.

Be sure to set the CR value in accordance with this condition.

23

2005-04-04

TB62201AFG

CR Circuit Constants

OSC circuit oscillation waveform

t (CR − charge)

t (CR − dis-charge)

E1

E2

t = 0

t = 1

t = 2

The OSC circuit generates the chopping reference signal by charging and discharging the external capacitor Cosc

through current supplied from the external resistor Rosc in the OSC block.

Voltages E1 and E2 in the diagram are set by dividing the V

The actual current chopping time is 1/8 the CR frequency.

by approximately 3/5 (E1) and 2/5 (E2).

DD

[Important: Setting the cr circuit constants]

The CR oscillation waveform is converted in the IC to the CLK waveform (CR-CLK signal) and used for control.

If the CR waveform discharge time is set outside the range shown below, the operation of the IC is not guaranteed.

Be sure to set the CR waveform discharge time within the following range.

600 ns > t (CR discharge) > 400 ns

24

2005-04-04

TB62201AFG

IC Power Dissipation

IC power dissipation is classified into two: power consumed by transistors in the output block and power consumed

by the logic block and the charge pump circuit.

(1) Power consumed by the Power Transistor (calculated with R_on= 0.6 Ω)

In Charge mode, Fast Decay mode, or Slow Decay mode, power is consumed by the upper and lower transistors

of the H bridges. The following expression expresses the power consumed by the transistors of a H bridge.

P (out) = 2 (T ) × I

(A) × V (V) = 2 × I ^2 × R ......................................(1)

DS out on

r

out

The average power dissipation for output under 4−bit micro step operation (phase difference between phases A

and B is 90°) is determined by expression (1).

Thus, power dissipation for output per unit is determined as follows (2) under the conditions below.

R

= 0.6 Ω (@ 1.0 A)

(Peak: max) = 1.0 A

= 24 V

on

I

out

V

M

= 5 V

DD

P (out) = 2 (T ) × 1.0 (A)^2 × 0.60 (Ω) ................................................................. (2)

r

=1.20 (W)

(2) Power consumed by the logic block and IM

The following standard values are used as power dissipation of the logic block and IM at operation.

I (LOGIC) = 2 mA (typ.): /unit

I (IM3) = 12.5 mA (typ.): operation/unit

I (IM1) = 6.0 mA (typ.): stop/unit

The logic block is connected to V

(5 V). IM (total of current consumed by the circuits connected to V and

M

DD

current consumed by output switching) is connected to V (24 V). Power dissipation is calculated as follows :

M

P (Logic & IM) = 5 (V) × 0.002 (A) + 24 (V) × 0.0125 (A).................................... (3)

= 0.31 (W)

(3) Thus, power dissipation for 1 unit (P) is determined as follows by (2) and (3) above.

P = P (out) + P (Logic & IM) = 1.51 (W)

Power dissipation for 1 unit at standby is determined as follows:

P (standby) = 24 (V) × 0.006 (A) + 5 (V) × 0.002 (A)

= 0.154 (W)

When one motor driving = 100 %, power dissipation is determined as follows:

P (all) = 1.51 (W) + 1.664 (W) = 1.66 (W)

For thermal design on the board, evaluate by mounting the IC.

25

2005-04-04

TB62201AFG

Mixed Decay Mode Waveforms (concept of mixed decay mode)

f

chop

CR pin

input

waveform

Set current value

DECAY MODE 0

Slow

NF

SLOW

DECAY

MODE

Charge

DECAY MODE 1

Set current value

Slow

NF

37.5%

MIXED

DECAY

MODE

Charge

Fast

Monitoring

set current

value

MDT

RNF

DECAY MODE 2

Set current value

NF

Charge

75%

Fast

MIXED

DECAY

MODE

MDT

Monitoring

set current

value

RNF

DECAY MODE 3

FAST

NF

Set current value

Charge

DECAY

MODE

Fast

Monitoring

set current

value

RNF

100%

87.5%

B

75%

C

62.5%

D

50%

E

37.5%

F

25%

G

12.5%

H

0

I

A

In Decay modes 1 to 4, any point from A to H can be set using 3-bit + 1-bit serial data × 4.

(Slow Decay mode for Decay mode 0 in the above figure can be set by setting current Decay mode X to 0.)

NF is the point where the output current reaches the set current value. RNF is the timing for monitoring the set

current.

In Mixed Decay and Fast Decay modes, where the condition RNF (set current monitor signal) < (output current)

applies, Charge mode is cancelled at the next chopping cycle (charge cancel circuit). Therefore, at the next chopping

cycle, the IC enters Slow + Fast modes (Slow → Fast at MDT).

26

2005-04-04

TB62201AFG

Mixed Decay Timing which can be Set

f

chop

Internal

CR

waveform

Defaults for

NF

Decay mode 0

0%

CURRENT MODE (X) = 0

DECAY MODE (X − 2, X − 1, X − 0) = (×, ×, ×)

X: arbitrary value

CURRENT MODE (X) = 1

DECAY MODE (X − 2, X − 1, X − 0) = (0, 0, 0)

MDT

12.5%

RNF

MDT

CURRENT MODE (X) = 1

DECAY MODE (X − 2, X − 1, X − 0) = (0, 0, 1)

25%

Defaults for

Decay mode 1

MDT

37.5%

CURRENT MODE (X) = 1

DECAY MODE (X − 2, X − 1, X − 0) = (0, 1, 0)

MDT

CURRENT MODE (X) = 1

DECAY MODE (X − 2, X − 1, X − 0) = (0, 1, 1)

50%

MDT

CURRENT MODE (X) = 1

DECAY MODE (X − 2, X − 1, X − 0) = (1, 0, 0)

62.5%

Defaults for

Decay mode 2

NF

MDT

75%

CURRENT MODE (X) = 1

DECAY MODE (X − 2, X − 1, X − 0) = (1, 0, 1)

MDT

CURRENT MODE (X) = 1

DECAY MODE (X − 2, X − 1, X − 0) = (1, 1, 0)

87.5%

Defaults for

NF

Decay mode 3

FAST

CURRENT MODE (X) = 1

DECAY MODE (X − 2, X − 1, X − 0) = (1, 1, 1)

FAST MODE → RNF: CURRENT MONITOR →

(WHEN SET CURRENT VALUE > OUTPUT CURRENT)

CHARGE MODE → FAST MODE

DECAY

MODE

27

2005-04-04

TB62201AFG

Test Circuit (A/B unit only. C/D unit conforms to A/B unit.)

1. V

, V

IN (H) IN (L)

V

9

ref AB

8

CR

SGND

V

36

34

32

35

2

M A

SGND

R

RS A

R

RS A

A

27

V

DD

I

, I

DD1 DD2

A

B

5 V

0 V

31

30

29

STROBE AB

CLK AB

5 V

0 V

5

5 V

0 V

DATA AB

Vary V .

in

R

3

1

RS B

R

RS B

V

M B

I

, I

A

IN (H) IN (L)

V

SS

(F

IN

)

SGND

Ccp 2

28

RESET

0 V to 5 V

Ccp C

Ccp B

Ccp A

13

12

7

No reset at testing

RESET = 5 [V]

6

SETUP

V

P-GND

DD

Ccp 1

SGND

: PGND

: SGND (V

)

SS

Test Method

V

IN (H)

: Set RESET to High and vary the logic input voltage from 0 to 7 V.

Monitor I

and measure the change point (V = 24 V).

DD

M

V

IN (L)

: Set RESET to High and vary the logic input voltage from 5 to 0 V.

Monitor I and measure the change point.

DD

Setup Data

H

L

DATA

CLK

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

H

L

H

L

STROBE

28

2005-04-04

TB62201AFG

2. I

_,I

, I

(A/B unit only. C/D unit conforms to A/B unit.)

IN (H) IN (L) DD1 DD2

V

9

ref AB

8

CR

SGND

V

36

34

32

35

2

M A

SGND

R

RS A

R

RS A

A

27

V

DD

I

, I

DD1 DD2

A

B

5 V

0 V

31

30

29

STROBE AB

CLK AB

5 V

0 V

5

5 V

0 V

DATA AB

Vary V .

in

R

3

1

RS B

R

RS B

V

M B

I

, I

A

IN (H) IN (L)

V

SS

(F

IN

)

SGND

Ccp 2

28

RESET

0 V to 5 V

Ccp C

Ccp B

Ccp A

13

12

7

No reset at testing

RESET = 5 [V]

6

SETUP

V

P-GND

DD

SGND

Ccp 1

: PGND

: SGND (V

)

SS

Test Method

I

: Set RESET to High, set the the logic input voltage to 5 V, and measure the input current.

: Set RESET to High, set the the logic input voltage to 0 V, and measure the input current.

IN (H)

DD1

: Apply V , input RESET, and measure I

.

DD

: Input 6.25 MHz clock and measure the current when the logic is operating. Set output to OPEN.

DD2

Setup Data

H

DATA

CLK

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

L

H

L

H

L

STROBE

29

2005-04-04

TB62201AFG

3. IM1, IM2 (A/B unit only. C/D unit conforms to A/B unit.)

V

9

ref AB

8

CR AB

SGND

V

36

34

32

35

2

M A

SGND

R

RS A

A

27

V

DD

A

B

5 V

0 V

31

30

29

STROBE AB

CLK AB

5 V

0 V

5

5 V

0 V

DATA AB

R

3

1

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

A

IM

28

RESET

Ccp C

Ccp B

Ccp A

13

12

7

At IM1 testing: RESET = L (0 V)

At IM2 testing: RESET = H (5 V)

P-GND SETUP

6

Ccp 1

: PGND

V

DD

SGND

: SGND (V

)

SS

Test Method

IM1: Set the logic block to non-active (DATA = all 0), V

= 5 V, V = 24 V, and output to open. Measure

M

DD

the current input from V supply. RESET = L

M

IM2: Set the logic block only to active (CLK = 6.25 MHz), V = 24 V, and output to open. Measure the

M

current input from V supply. RESET = H

M

Setup Data

H

L

DATA

CLK

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

H

L

H

L

STROBE

30

2005-04-04

TB62201AFG

4. IM3 (A/B unit only. C/D unit conforms to A/B unit.)

V

9

ref AB

8

CR AB

SGND

V

36

34

32

35

2

M A

SGND

R

RS A

A

27

V

DD

A

B

5 V

0 V

31

30

29

STROBE AB

CLK AB

5 V

0 V

5

5 V

0 V

DATA AB

R

3

1

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

A

IM

28

RESET

Ccp C

Ccp B

Ccp A

13

12

7

No reset at testing

V

DD

SGND

RESET = 5 [V]

P-GND SETUP

6

Ccp 1

: PGND

: SGND (V

)

SS

This is the IM current when all of the circuits, including the output transistors, in the IC are operating.

The IM current includes the current dissipation in the charge pump circuit, output gate loss, and output

predriver.

Because the IM current (IM3) is input from the RS pin, which is also used for the output current, IM3

cannot be measured by the normal testing methods.

Use the method shown below.

Setup Data

The serial data PHASE signal (both A and B) switch over to high or low.

H

DATA

CLK

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

L

H

L

H

L

STROBE

Test Method

Set output to open, change phase data from 1 → 0 → 1 → 0 and perform switching. When testing, input

phase data at double the chopping frequency (if f = 100 kHz, fDATA = 200 kHz) and measure the

chop

current value of V supply.

M

fDATA = 200 kHz means that the phase switches at 200 kHz.

31

2005-04-04

TB62201AFG

Number of Switchings at Phase Switching

Number of Switchings at Actual Operation

Mode changes three times

in one chopping cycle.

One phase switching

(16-bit data input)

To V

M

Four transistors switching

Chopping cycle

U

1

U

2

U

1

U

2

OFF

ON

OFF

ON

Load

Two transistors

switching

Switches by phase data

OFF

ON

L

1

L

2

L

1

L

2

Charge

Slow

Two transistors

switching

OFF

ON

OFF

ON

OFF

ON

Four transistors switching

One phase switching

(16-bit data input)

PGND

Eight transistors switching

in one chopping cycle

OFF

ON

Four transistors are switched at one phase switching

Fast

Number of switchings at actual operation = 2 × number of switchings at phase switching.

Therefore, switching the phase at 2 × chopping cycle matches the number of switchings at actual operation

with the number of switchings at phase switching, and allows the actual current dissipation, IM3, to be

measured.

32

2005-04-04

TB62201AFG

5. I , I , I (A/B unit only. C/D unit conforms to A/B unit.)

OB OH OL

V

9

ref AB

8

CR AB

SGND

V

36

34

32

35

2

M A

SGND

R

RS A

A

27

A

V

DD

I

OB

A

B

5 V

0 V

31

30

29

STROBE AB

CLK AB

I

, I

OH OL

5 V

0 V

5

5 V

0 V

DATA AB

R

3

1

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

28

RESET

I

Ccp C

Ccp B

Ccp A

13

12

7

OL

No reset at testing

V

DD

SGND

RESET = 5 [V]

P-GND SETUP

6

Ccp 1

: PGND

: SGND (V

)

SS

Test Method

I

: With V = 24 V, V

to GND, and measure the supply current.

= 5 V, and logic input all = 0 applied, set RESET = H, connect the output pins

OH

M

DD

: With V = 24 V, V = 5 V, and logic input all = 0 applied, set RESET = H, connect the output pins

OB

OL

M

DD

to V , and measure the supply current.

M

: With V = 24 V, V

= 5 V, and logic input all = 0 applied, set RESET = L, connect the output pins

M

DD

to GND, and measure the supply current.

Setup Data

H

DATA

L

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

H

CLK

L

H

STROBE

L

33

2005-04-04

TB62201AFG

6. V (H to L), V (GAIN) (when measuring phase A) after Measurement

RS

ref

(A/B unit only. C/D unit conforms to A/B unit.)

V

9

ref AB

8

CR AB

SGND

V

36

34

32

35

2

M A

SGND

R

RS A

A

27

V

DD

A

B

5 V

0 V

V

31

30

29

STROBE AB

CLK AB

Oscilloscope

5 V

0 V

5

5 V

0 V

DATA AB

R

3

1

RS B

V

Vary between

0 and 1 V.

M B

V

SS

(F

IN

)

SGND

28

RESET

Ccp C

Ccp B

Ccp A

13

12

7

Ccp 2

Ccp 1

No reset at testing

V

DD

SGND

RESET = 5 [V]

P-GND SETUP

6

: PGND

: SGND (V

)

SS

V

Input torque data = 100% (HH) and vary the voltage between V and R pins.

M S

RS (H to L):

Measure the voltage (V ) when output changes from fixed Charge mode to another mode.

RS

Also measure V when torque data = 85% (HL), 70% (LH), or 50% (LL) as above and

RS

calculate the ratio using V value at 100% as reference.

RS

V

(*)

ref

RS

V

: V

=

((*) V : when torque data = 100%)

RS

ref (GAIN)

Setup Data

H

L

DATA

CLK

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

H

L

H

L

STROBE

34

2005-04-04

TB62201AFG

7.

∆I_out1, ∆I_out2(A/B unit only. C/D unit conforms to A/B unit.)

V

9

ref AB

8

CR

SGND

V

36

34

32

35

2

M A

SGND

R

RS A

R

RS A

A

27

V

DD

Monitors current

waveform.

A

B

5 V

0 V

31

30

29

STROBE AB

CLK AB

5 V

0 V

5

5 V

0 V

DATA AB

R

3

1

RS B

R

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

28

RESET

Ccp C

Ccp B

Ccp A

13

12

7

No reset at testing

V

DD

SGND

RESET = 5 [V]

P-GND SETUP

6

Ccp 1

: PGND

: SGND (V

)

SS

With L load, perform chopping in Mixed Decay mode. Monitor the output current waveform and measure

the various output currents at constant current operation.

Setup Data

Set to 100%

10 11 12 13 14 15

H

DATA

CLK

0

1

2

3

4

5

6

7

8

9

L

H

L

H

L

STROBE

MDT

Output current

value (set

0%

Charge

100% 0%

Fast

Current

waveform

Slow

Measurement of

peak current

Fast

current value)

Charge

35

2005-04-04

TB62201AFG

8. IRS (when measuring phase A) (A/B unit only. C/D unit conforms to A/B unit)

V

9

ref AB

8

CR AB

SGND

V

36

34

32

35

2

M A

SGND

R

RS A

A

27

V

DD

A

B

31

30

29

STROBE AB

CLK AB

5

DATA AB

R

3

1

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

28

RESET

Ccp C

Ccp B

Ccp A

13

12

7

RESET = L

V

DD

SGND

P-GND SETUP

6

Ccp 1

: PGND

: SGND (V

)

SS

With L input to RESET , connect V and R to the power supply, and measure the current input to the

M

RS

R pin. (Either drop all the input pins to GND level or input all Low data to the DATA pin, then perform

S

measurement. At that time, leave all other output pins open.)

Setup Data

H

DATA

CLK

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

L

H

L

H

L

STROBE

36

2005-04-04

TB62201AFG

9. R

_,R

when Measuring Output A

ON (D-S) ON (S-D)

(A/B unit only. C/D unit conforms to A/B unit.)

V

9

ref AB

8

CR AB

SGND

V

36

34

32

35

2

M A

SGND

R

RS A

A

27

V

DD

A

B

5 V

0 V

31

30

29

STROBE AB

CLK AB

Curve tracer

5 V

0 V

5

5 V

0 V

DATA AB

R

3

1

RS B

V

M B

Curve tracer

SGND

V

SS

(F

IN

)

28

RESET

Ccp C

Ccp B

Ccp A

13

12

7

Ccp 2

Ccp 1

No reset at testing

RESET = 5 [V]

SGND

P-GND SETUP

6

: PGND

: SGND (V

)

SS

Input the current setting data (HHHH signal) to the DATA pin and measure the voltage between V and

M

OUT when I

= 1000 mA or the voltage between OUT and GND. Then, change the phase and repeat

out

measurement. At that time, leave the output pins which are not measured open.

Setup Data (Vary the phase data during testing.)

H

DATA

CLK

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

L

H

L

H

L

STROBE

37

2005-04-04

TB62201AFG

10. V , I (A/B unit only. C/D unit conforms to A/B unit.)

ref ref

(*) When measuring I

,

ref

Oscilloscope

fix V = 3 V and

ref

Monitor

A

measure.

V

9

ref AB

8

CR AB

Vary V

ref

= 2 to V

I

(*)

ref

SGND

− 1.0 V

DD

V

36

34

32

35

2

M A

SGND

R

RS A

R

RS A

A

27

V

DD

A

B

31

30

29

STROBE AB

CLK AB

5

DATA AB

R

3

1

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

28

RESET

Ccp C

Ccp B

Ccp A

13

12

7

No reset at testing

V

DD

SGND

RESET = 5 [V]

P-GND SETUP

6

Ccp 1

: PGND

: SGND (V

)

SS

V

ref

: Vary V = 2 to V

− 1 V and confirm that output is on.

ref

DD

I

ref

: When V = 24 V and V

= 5 V, apply the specified voltage of 3 V to the V and monitor the

DD ref

M

current flow value.

38

2005-04-04

TB62201AFG

11. T TSD, ∆T TSD (Measure in an environment such as an constant temperature chamber where

j

the temperature for the IC can be freely changed) (A/B unit only. C/D unit conforms to A/B

unit.)

V

9

ref AB

8

CR AB

SGND

V

36

34

32

35

2

M A

SGND

R

RS A

A

27

V

DD

A

B

5 V

0 V

31

30

29

STROBE AB

CLK AB

Curve tracer

5 V

0 V

5

5 V

0 V

DATA AB

R

3

1

RS B

V

M B

Curve tracer

SGND

V

SS

(F

IN

)

28

RESET

Ccp C

Ccp B

Ccp A

13

12

7

Ccp 2

Ccp 1

No reset at testing

RESET = 5 [V]

SGND

P-GND SETUP

6

: PGND

: SGND (V

)

SS

T TSD : Increase the ambient temperature. Measure the temperature when output stops.

j

∆T TSD : Gradually lower the temperature from the level when the TSD circuit was operating (output off).

j

At that time, control the RESET input thus : H → L → H → L. Output will begin at a certain

temperature level.

∆T TSD is the difference between the temperature at which output begins and the temperature at

j

which TSD is triggered.

Setup Data

H

L

DATA

CLK

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

H

L

H

L

STROBE

39

2005-04-04

TB62201AFG

12. V

(A/B unit only. C/D unit conforms to A/B unit.)

DDR

Oscilloscope

V

9

ref AB

8

CR AB

SGND

V

DD

SGND

V

36

34

32

35

2

M A

SGND

R

RS A

R

RS A

A

27

V

DD

A

B

5 V

0 V

31

30

29

STROBE AB

CLK AB

5 V

0 V

5

5 V

0 V

DATA AB

R

3

1

RS B

R

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

28

RESET

Ccp C

Ccp B

Ccp A

13

12

7

V

M

No reset at testing

RESET = 5 [V]

P-GND SETUP

6

V

Ccp 1

DD

SGND

: PGND

Vary from 0 V.

: SGND (V

)

SS

Monitor the output pins. Increase the V

voltage from 0. Measure the V

value when output starts.

DD

Next, decrease the V

voltage and measure the V

value when output stops.

DD

Setup Data

H

DATA

CLK

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

L

H

L

H

L

STROBE

40

2005-04-04

TB62201AFG

13. V

(A/B unit only. C/D unit conforms to A/B unit.)

MR

Oscilloscope

V

9

ref AB

8

CR AB

SGND

V

36

34

32

35

2

M A

SGND

R

RS A

R

RS A

A

27

V

DD

A

B

5 V

0 V

31

30

29

STROBE AB

CLK AB

5 V

0 V

5

5 V

0 V

DATA AB

R

3

1

RS B

R

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

28

RESET

Ccp C

Ccp B

Ccp A

13

12

7

Vary from 0 V.

No reset at testing

RESET = 5 [V]

P-GND SETUP

6

V

Ccp 1

DD

SGND

: PGND

: SGND (V

)

SS

With the CLK signal and DATA (all High) input, increase the V voltage from 0.

M

Measure the V value when output starts.

M

Next, decrease the V voltage and measure the V value when output stops.

M

Setup data

H

DATA

CLK

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

L

H

L

H

L

STROBE

41

2005-04-04

TB62201AFG

14. Overcurrent Protector Circuit (ISD) (To measure output A: )

(A/B unit only. C/D unit conforms to A/B unit.)

V

9

ref AB

8

CR AB

SGND

V

36

34

32

35

2

M A

SGND

R

RS A

A

27

V

DD

A

B

5 V

0 V

31

30

29

STROBE AB

CLK AB

Curve tracer

5 V

0 V

5

5 V

0 V

DATA AB

R

3

1

RS B

V

M B

Curve tracer

SGND

V

SS

(F

IN

)

28

RESET

Ccp C

Ccp B

Ccp A

13

12

7

Ccp 2

Ccp 1

At measuring, non-reset

RESET = 5 [V]

SGND

P-GND SETUP

6

: PGND

: SGND (V

)

SS

Test method: To monitor operating current of the overcurrent protector circuit when output A is

short-circuited to the power supply

Input the current setting data (HHHH signal) to the DATA pin. If short-circuited to the supply, measure

the lower output transistors. If short-circuited to ground, measure the upper output transistors (see how to

measure R ).

ON

When measuring R , increase the current flow. There is a current value at which output is switched off

ON

and R

cannot be measured. This value is the set current value for the overcurrent protector circuit.

ON

Make sure to leave open the output pins not being measured.

Note that if the temperature changes, the value may fluctuate. Try to avoid applying power to the IC by

one-shot measuring.

Setup Data (Example: The phase signal must be changed depending on the pin.)

H

DATA

CLK

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

L

H

L

H

L

STROBE

42

2005-04-04

TB62201AFG

15. Current Vector (A/B unit only. C/D unit conforms to A/B unit.)

V

9

ref AB

8

CR

SGND

V

36

34

32

35

2

M A

SGND

R

RS A

R

RS A

A

27

V

DD

Monitor current

waveform

A

B

5 V

0 V

31

30

29

STROBE AB

CLK AB

5 V

0 V

5

5 V

0 V

DATA AB

R

3

1

RS B

R

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

28

RESET

Ccp C

Ccp B

Ccp A

13

12

7

At measuring, non-reset

V

DD

SGND

RESET = 5 [V]

P-GND SETUP

6

Ccp 1

: PGND

: SGND (V

)

SS

Perform chopping in Mixed Decay mode with load L. Monitor the output current waveform and measure

the output current at constant current operation. At this time, vary the 4-bit data for current setting and

measure the current values. Using the set output current as 100%, calculate the output current ratio.

100%

Output current

(example)

71%

100%

0%

43

2005-04-04

TB62201AFG

16. f

t

, t

_,t

, t

, t_{STROBE (H)}, t

(A/B unit only. C/D unit conforms to A / B unit.)

,

CLK w (CLK) wp (CLK) wn (CLK) STROBE

STOBE (L)

, t

suSIN-CLK suST-CLK hSIN-CLK hCLK-ST

V

9

ref AB

8

CR AB

SGND

V

36

34

32

35

2

M A

SGND

R

RS A

R

RS A

A

27

V

DD

A

B

5 V

0 V

31

30

29

STROBE AB

CLK AB

5 V

0 V

5

5 V

0 V

DATA AB

R

3

1

RS B

R

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

28

RESET

Ccp C

Ccp B

Ccp A

13

12

7

No reset at testing

RESET = 5 [V]

P-GND SETUP

6

V

Ccp 1

DD

SGND

: PGND

: SGND (V

)

SS

Input any data at f

(max), perform chopping, and monitor the output waveform.

CLK

For the measuring points, see the timing chart below.

Setup Data

H

DATA

CLK

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

L

H

L

H

L

STROBE

Measuring Points

t

w (CLK)

CLK

50%

t

suST-CLK

t

hST-CLK

t

wn (CLK) wp (CLK)

STROBE

50%

t

STROBE (H)

STROBE (L)

t

STROBE

t

suSIN-CLK

t

hIN-CLK

DATA

50%

DATA15

50%

DATA0

44

2005-04-04

TB62201AFG

17. OSC-fast Delay, OSC-charge Delay (A/B unit only. C/D unit conforms to A / B unit.)

V

9

ref AB

8

CR AB

SGND

V

36

34

32

35

2

M A

SGND

R

RS A

R

RS A

A

27

V

DD

A

B

5 V

0 V

31

30

29

STROBE AB

CLK AB

5 V

0 V

5

5 V

0 V

DATA AB

R

3

1

RS B

R

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

28

RESET

Ccp C

Ccp B

Ccp A

13

12

7

No reset at testing

V

DD

SGND

RESET = 5 [V]

P-GND SETUP

6

Ccp 1

: PGND

: SGND (V

)

SS

Fix the output current value in Mixed Decay mode and turn the output on. Measure the time until the

output switches from the CR pin waveform and the output voltage waveform.

Setup Data

H

DATA

CLK

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

L

H

L

H

L

STROBE

Top

CR

Bottom

Osc-fast delay

Osc-charge delay

50%

V

out A

50%

(Mode)

Charge

Slow

Fast

Charge

45

2005-04-04

TB62201AFG

18. t

, t

, t , t (A/B unit only. C/D unit conforms to A/B unit.)

pHL (ST) pLH (ST)

r

f

Monitor

V

9

ref AB

8

CR AB

SGND

V

36

34

32

35

2

M A

SGND

R

RS A

R

RS A

R

L

= 5.7 Ω

A

27

V

DD

A

B

5 V

0 V

31

30

29

STROBE AB

CLK AB

5 V

0 V

5

5 V

0 V

DATA AB

R

3

1

RS B

R

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

28

RESET

Ccp C

Ccp B

Ccp A

13

12

7

No reset at testing

V

DD

RESET = 5 [V]

P-GND SETUP

6

SGND

Ccp 1

: PGND

: SGND (V

)

SS

Setup Data

H

L

DATA

CLK

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

H

L

H

L

STROBE

Switch PHASE every 130 µs and measure the output pin voltage and the STROBE signal.

[Oscilloscope Waveform (example)]

130 µs

50%

STROBE

t

pHL (ST)

Output

50%

voltage A

t

pLH (ST)

Output

90%

50%

90%

voltage A

10%

t

f

r

46

2005-04-04

TB62201AFG

19. t

(A/B unit only. C/D unit conforms to A/B unit.)

BRANK

V

9

ref AB

8

CR AB

SGND

V

36

34

32

35

2

M A

SGND

R

RS A

R

RS A

A

27

V

DD AB

A

B

5 V

0 V

31

30

29

STROBE AB

CLK AB

5 V

0 V

5

5 V

0 V

DATA AB

R

3

1

RS B

R

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

28

RESET

Ccp C

Ccp B

Ccp A

13

12

7

No reset at testing

RESET = 5 [V]

P-GND SETUP

6

SGND

Ccp 1

: PGND

: SGND (V

)

SS

t

is the dead time band for avoiding malfunction caused by noise. Apply sufficient differential

BRANK

voltage (when V = 3 V, 0.6 V or higher) to V -R and apply duty. When the pulse width reaches a certain

ref

M

S

value, triggering feedback and changing the output. Check the value.

Measure the pulse width

where output changes.

V

M

R

S

pin voltage

Apply pulse to the R pin

S

so that the R pin

S

= V voltage − 1.0 V.

M

H

Output operation

L

Setup Data

H

L

DATA

CLK

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

H

L

H

L

STROBE

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2005-04-04

TB62201AFG

c

hop

20. f

(f

(min), f

(max)) (A/B unit only. C/D unit conforms to A/B unit.)

chop chop

Oscilloscope

V

9

ref AB

8

CR AB

SGND

V

36

34

32

35

2

M A

SGND

R

RS A

R

RS A

A

27

V

DD

A

B

31

30

29

STROBE AB

CLK AB

5

DATA AB

R

3

1

RS B

R

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

28

RESET

Ccp C

Ccp B

Ccp A

13

12

7

V

DD

SGND

P-GND SETUP

6

Ccp 1

: PGND

: SGND (V

)

SS

Change the R

and C

values and measure the frequency on the CR pin using the oscilloscope.

osc

At this time, 1/8 of the frequency of the measured CR waveform is f

.

chop

Oscilloscope Waveform (example)

1/8 f

(SYNC) = f

CR

chop

t = 0

t = 1

48

2005-04-04

TB62201AFG

21. t

(A/B unit only. C/D unit conforms to A/B unit.)

ONG

V

9

ref AB

8

CR AB

SGND

V

36

34

32

35

2

M A

SGND

R

RS A

R

RS A

A

27

V

DD

A

B

5 V

0 V

31

30

29

STROBE AB

CLK AB

5 V

0 V

5

5 V

0 V

DATA AB

R

3

1

RS B

R

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

28

RESET

Ccp C

Ccp B

Ccp A

13

12

7

At measuring, change

V

DD

SGND

from reset to non-reset.

P-GND SETUP

6

Ccp 1

: PGND

: SGND (V

)

SS

Apply V and V

and change RESET from L to H.

M

DD

Measure the time until the CcpA pin becomes V + V

× 90%.

M

DD

V

+ V

M

DD

(V + V ) × 90%

M

DD

V

M

5 V

0 V

RESET

50%

t

ONG

49

2005-04-04

TB62201AFG

22. Mixed Decay Timing (A/B unit only. C/D unit conforms to A/B unit.)

V

9

ref AB

8

CR

SGND

V

36

34

32

35

2

M A

SGND

R

RS A

R

RS A

A

27

V

DD

A

B

5 V

0 V

31

30

29

STROBE AB

CLK AB

5 V

0 V

5

5 V

0 V

DATA AB

R

3

1

RS B

R

RS B

V

M B

V

SS

(F

)

IN

SGND

Ccp 2

28

RESET

Ccp C

Ccp B

Ccp A

13

12

7

At measuring, non-reset

RESET = 5 [V]

V

DD

SGND

P-GND

6

SETUP

Ccp 1

: PGND

When overwriting the

mixed decay timing

table, set to 5 V.

When the motors are

operating, set to

GND level.

: SGND (V

)

SS

With V = 24 V, V

= 5 V, RESET = H, change the SETUP pin from L to H and overwrite the MIXED

M

DD

DECAY TIMING TABLE.

Then change the SETUP pin from H to L. With load L, perform chopping and monitor the output current

waveform at that time. Confirm that the switching timing from Slow Decay Mode to Fast Decay Mode

within an fchop cycle is the specified MIXED DECAY TIMING.

(Depending on the load L value and the test environment, chopping may be performed every two cycles or

there may be no Slow Decay Mode. If so, conditions, for example, load condition, may need to be changed.

MDT

Output current value

(set current value)

0%

MDT

100% 0%

MDT

Slow

Fast

Slow

Fast

Charge

Current waveform

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2005-04-04

TB62201AFG

Waveforms in Various Current Modes (Ideal waveform)

Normal MIXED DECAY MODE Waveform

NF is the point at which the output current

reaches the set current value.

f

chop

CR CLK

signal

I

out

NF

Set current value

NF

Set current

value

12.5% MIXED

DECAY MODE

RNF

MDT (MIXED DECAY TIMING) point

When NF is after MIXED DECAY TIMING

Fast Decay mode after Charge mode.

Set current value

MDT (MIXED DECAY TIMING) point

I

out

NF

Set current

value

RNF

37.5% MIXED

DECAY MODE

STROBE signal input

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2005-04-04

TB62201AFG

In MIXED DECAY MODE, when the Output Current > the Set Current Value

f

chop

Set

current

value

NF

CHARGE MODE for one f

chop

cycle after STROBE signal input

Because the set current value >

the output current, no CHARGE

MODE in the next cycle.

RNF

NF

I

out

12.5%

MIXED

DECAY

MODE

RNF

NF

Set current value

RNF

MDT (MIXED DECAY TIMING) point

STROBE signal input

FAST DECAY MODE Waveform

NF is the point at which the output

current reaches the set current value.

f

chop

Set current

value

I

out

FAST DECAY

MODE

Because the set current value > the output current,

FAST DECAY MODE in the next cycle, too

(0% MIXED

DECAY MODE)

Set current value

NF

RNF

Because the set current value > the output current, CHARGE

MODE → NF → FAST DECAY MODE in the next cycle, too

RNF

STROBE signal input

Response delay time

52

2005-04-04

TB62201AFG

STROBE Signal, Internal CR CLK, and Output Current Waveform

(When STROBE signal is input in SLOW DECAY MODE)

f

chop

f

chop

37.5% MIXED DECAY MODE

Set current

value

MDT

I

out

NF

Set current

value

MDT

RNF

Momentarily enters

CHARGE MODE

STROBE signal input

Reset CR-CLK

counter here

When STROBE signal is input, the chopping counter (CR-CLK counter) is forced to reset at the next

CR-CLK timing.

Because of this, compared with a method in which the counter is not reset, response to the input data is

faster.

(The delay time, the theoretical value in the logic portion, is expected to be a one-cycle CR waveform:

1.25 µs @ 100 kHz CHOPPING.)

When the C-CLK counter is reset due to STROBE signal input, CHARGE MODE is entered momentarily

due to current comparison.

Note: In FAST DECAY MODE, too, CHARGE MODE is entered momentarily due to current comparison.

53

2005-04-04

TB62201AFG

STROBE Signal, Internal CR CLK, and Output Current Waveform

(When STROBE signal is input in CHARGE MODE)

f

chop

f

chop

Set current

value

MDT

37.5% MIXED DECAY MODE

I

out

NF

Set current

value

MDT

RNF

Momentarily enters

CHARGE MODE

STROBE signal input

54

2005-04-04

TB62201AFG

(When STROBE signal is input in FAST DECAY MODE)

f

chop

f

chop

37.5% MIXED DECAY MODE

NF

Set

current

value

MDT

I

out

NF

Set current

value

MDT

RNF

Momentarily enters

CHARGE MODE

STROBE signal input

55

2005-04-04

TB62201AFG

(When PHASE signal is input)

37.5% MIXED DECAY MODE

f

chop

f

chop

Set current

value

I

out

0

RNF

MDT

Set current

value

NF

STROBE signal input

56

2005-04-04

TB62201AFG

(When current point 0 control is included)

37.5% MIXED DECAY MODE

f

chop

f

chop

Set current

value

I

out

(1)

(2)

(1)

0

(2)

(1)

Set current

value

STROBE signal input

Reset CR-CLK

counter here

Reset CR-CLK

counter here

57

2005-04-04

TB62201AFG

(When Fast DECAY MODE is included during the sequence)

f

chop

Set current

value

37.5% MIXED DECAY MODE

FAST DECAY MODE

Set current

value

58

2005-04-04

TB62201AFG

(When SLOW DECAY MODE is included during the sequence)

f

chop

Set current

value

SLOW DECAY MODE

37.5% MIXED DECAY MODE

f

chop

Set current

value

In SLOW DECAY MODE, depending on the load,

the set current cannot be accurately traced.

Therefore, do not use SLOW DECAY MODE.

37.5% MIXED DECAY MODE

STROBE

59

2005-04-04

TB62201AFG

Current Modes (mixed (= SLOW + FAST) Decay Mode Effect)

• Sine wave in increasing (Slow Decay Mode (Charge + Slow + Fast) normally used)

Set current

value

Slow

Charge

Fast

Charge

Slow

Fast

Set current

value

Charge

Fast

Charge

• Sine wave in decreasing (When using MIXED DECAY Mode with large attenuation ratio (MDT%) at

attenuation)

Slow

Set current

value

Because current attenuates so quickly, the current

immediately follows the set current value.

Charge

Fast

Charge

Fast

Slow

Set current

value

Fast

Charge

• Sine wave in decreasing (When using MIXED DECAY Mode with small attenuation ratio (MDT%) at

attenuation)

Because current attenuates slowly, it

takes a long time for the current to follow

the set current value (or the current does

not follow).

Slow

Set current

value

Fast

Charge

Fast

Set current

value

Fast

Note: The above charts are schematics. The actual current transient responses are curves.

60

2005-04-04

TB62201AFG

Output Transistor Operating Mode

To V

M

R

S

R

S

R pin

S

U

1

U

2

U

1

U

2

U

1

U

2

(Note)

L

1

Load

L

2

L

1

Load

L

2

L

1

Load

L

2

PGND

Charge mode

Slow mode

Fast mode

(Charges coil power)

(Slightly attenuates

coil power)

(Drastically attenuates

coil power)

Output Transistor Operation Functions

CLK

U

1

U

2

L

1

L

2

CHARGE

SLOW

ON

OFF

ON

OFF

ON

FAST

ON

OFF

Note: The above table is an example where current flows in the direction of the arrows in the above figures.

When the current flows in the opposite direction of the arrows, see the table below.

CLK

U

1

U

2

L

1

L

2

CHARGE

SLOW

OFF

ON

OFF

ON

OFF

ON

FAST

OFF

ON

61

2005-04-04

TB62201AFG

Output Transistor Operating Mode 2 (Sequence of MIXED DECAY MODE)

To V

M

U

1

U

1

U

2

U

1

U

2

U

2

Out

A

Out

A

Out A

L

1

L

1

L

2

L

1

L

2

L

2

PGND

H

Output

voltage A

50%

L

H

Output

50%

voltage A

L

Set current

Ouput

current

L

Charge mode

Slow mode

Fast mode

The constant current is controlled by changing mode from Charge → Slow → Fast.

62

2005-04-04

TB62201AFG

Current Discharge Path when Current Data = 0000 are Input during Operation

In Slow Decay Mode, when all output transistors are forced to switch off, coil energy is discharged in the following

MODES :

Note: Parasitic diodes are located on dotted lines. In normal MIXED DECAY MODE, the current does not flow to the

parasitic diodes. However, when signal 0000 is input during operation, the current flows to them.

To V

To V power supply

M

R

S

R

S

R pin

S

U

1

U

2

U

1

U

2

U

1

U

2

(Note)

OFF

ON

OFF

Input Current DATA

= 0000

L

1

Load

L

2

L

1

Load

L

2

L

1

Load

L

2

OFF

ON

OFF

PGND

Charge mode

Slow Decay mode

Forced OFF mode

As shown in the figure at right, an output transistor has parasitic diodes.

To discharge energy from the coil, each transistor is switched on allowing current to flow in the reverse direction to

that in normal operation. As a result, the parasitic diodes are not used. If all the output transistors are forced to

switch off, the energy of the coil is discharged via the parasitic diodes.

63

2005-04-04

TB62201AFG

PD − Ta (Package power dissipation)

P

– Ta

D

3.5

(2)

(1) R

th (j-a)

IC Only (96°C/W)

(2) When mounted on the board

3.0

2.5

2.0

(38°C/W)

Board size

(100 mm × 200 mm × 1.6 mm)

* R

th (j-c)

: 8.5°C/W

1.5

(1)

1.0

0.5

0

25

50

75

100

125

150

Ambient temperature Ta (°C)

64

2005-04-04

TB62201AFG

Power Supply Sequence (Recommended)

V

DD (max)

DD (min)

DDR

V

DD

GND

V

M

V

M (min)

MR

V

M

GND

Non-

reset

Internal

reset

RESET

H

L

RESET

input

…..*

RESET

Takes up to t

until operable.

Non-operable area

ONG

t

Note 1: If the V

drops to the level of the V or below while the specified voltage is input to the V pin, the IC is

DDR M

DD

internally reset. This is a protective measure against malfunction. Likewise, if the V drops to the level of

M

the V

or below while regulation voltage is input to the V , the IC is internally reset as a protective

DD

MR

measure against malfunction. To avoid malfunction, when turning on V or V , we recommend you input

M

DD

the RESET signal at the above timing.

It takes time for the output control charge pump circuit to stabilize. Wait up to t

before driving the motors.

time after power on

ONG

Note 2: When the V value is between 3.3 to 5.5 V, the internal reset is released, thus output may be on. In such a

M

case, the charge pump cannot drive stably because of insufficient voltage. We recommend the RESET state

be maintained until V reaches 20 V or more.

M

Note 3: Since V

= 0 V and V = voltage within the rating are applied, output is turned off by internal reset. At that

M

DD

time, a current of several mA flows due to the Pass between V and V

.

M

DD

65

2005-04-04

TB62201AFG

Relationship between V and V

M

H

V

H

is the voltage of the CcpA pin. It is the highest voltage in this IC (power supply for driving the upper gate of the

H bridge).

V

– V (& V

)

charge up

M

H

50

40

30

20

10

0

V

voltage

H

Charge up voltage

voltage

V

= 5 V

DD

V

M

Ccp1 = 0.22 µF

Ccp2 = 0.02 µF

V

= V

+ V (CcpA)

DD M

H

Input RESET ( RESET = 0 V)

VMR

Maximum

Usable area

Recommended operation area

0

5

10

15

20

25

30

35

40

Supply voltage

V

M

(V)

z Vcharge Up is the voltage to boost V to V . Usually equivalent to V .

DD

M

H

66

2005-04-04

TB62201AFG

Operation of Charge Pump Circuit

R

RS

V

= 24 V

M

V

= 5 V

R

S

V

M

DD

3/16/21/34

1/18/19/36

27

CcpA

V

H

7

i1

i2

Di2

Di1

(2)

CcpB

12

T

r2

(1)

Comparator

&

Output

V

Z

(2)

Controller

Output

H switch

13

CcpC

Di3

R

1

T

r1

V

= V + V

= charge pump voltage

DD

H

M

i1 = charge pump current

i2 = gate block power dissipation

z Initial charging

(1) When RESET is released, T is turned ON and T turned OFF. Ccp2 is charged from Ccp2 via Di1

r1

r2

(This is the same as when TSD and ISD are operating and the IC is restored from Reset state.)

(2) T is turned OFF, T is turned ON, and Ccp1 is charged from Ccp2 via Di2.

r1

r2

(3) When the voltage difference between V and V (CcpA pin voltage = charge pump voltage) reaches V or

DD

M

H

higher, operation halts (Steady state: Because the capacitor is naturally discharged, the IC is continually

charging to the capacitor).

z Actual operation

(4) Ccp1 charge is used at fchop switching and the VH potential drops.

(5) Charges up by (1) and (2) above.

Output switching

Normal state

Initial charging

V

H

M

(1)

(2)

(3)

(4)

(5)

(4)

(5)

t

67

2005-04-04

TB62201AFG

External Capacitors for Charge Pumps

When V

= 5V, fchop = 100 kHz, and L = 10 mH is driven with V = 24 V, I

= 1100 mA, the theoretical values

DD

M

out

for Ccp1 and Ccp2 are as shown below:

Ccp1 – Ccp2

0.05

0.04

0.03

0.02

Usable area

Ccp1 = (NG)

Ccp2 = (OK)

Recommended area

Recommended value

0.01

0

0.1

0.2

0.3

0.4

0.5

Ccp1 capacitance (µF)

Combine Ccp1 and Ccp2 as shown in the shaded area in the above graph.

Select values 10: 1 or more for Ccp1: Ccp2.

When making a setting, evaluate properly and set values with a margin.

68

2005-04-04

TB62201AFG

Charge Pump Rise Time

V

+ V

M

DD

(V + V ) × 90%

M

DD

V

M

5 V

0 V

RESET

50%

t

ONG

t

: Time taken for capacitor Ccp2 (charging capacitor) to fill up Ccp1 (capacitor used to save charge) to V

+

ONG

M

V

DD

after a reset is released.

The internal IC cannot drive the gates correctly until the voltage of Ccp1 reaches V + V . Be sure to

M

DD

wait for t

or longer before driving the motors.

ONG

Basically, the larger the Ccp1 capacitance, the longer the initial charge-up time but the smaller the

voltage fluctuation.

The smaller the Ccp1 capacitance, the shorter the initial charge-up time but the larger the voltage

fluctuation.

Depending on the combination of capacitors (especially with small capacitance), voltage may not be

sufficiently boosted. Thus, use the capacitors under the capacitor combination conditions (Ccp1 = 0.22 µF,

Ccp2 = 0.01 µF) recommended by Toshiba.

69

2005-04-04

TB62201AFG

Operating Time for Overcurrent Protector Circuit

(ISD non-sensitivity time and ISD operating time)

Output halts (Reset status)

CR oscillation

(basic chopping

waveform)

min

max

min

max

(Non-sensitivity time)

ISD BLANK time

ISD operating time

Point where overcurrent flows to output transistors (overcurrent status start)

A non-sensitivity time is set for the overcurrent protector circuit to avoid misdetection of overcurrent due to spike

current at irr or switching.

The non-sensitivity time synchronizes with the frequency of the CR for setting the chopping frequency. The

non-sensitivity time is set as follows :

Non-sensitivity time = 4 × CR cycle

The time required for the ISD to actually operate after the no-sensitivity time is as follows :

Minimum: 5 × CR cycle

Maximum: 8 × CR cycle

Therefore, from the time overcurrent flows to the output transistors to the time output halts is as follows.

Note that ideally, the operating time is the operating time when overcurrent flows. Depending on the output control

mode timing, the overcurrent protector circuit may not be triggered.

Therefore, to ensure safe operation, add a fuse to the V power supply for protection.

M

The fuse capacity would vary according to the use conditions. However, select a fuse whose capacity avoids any

operating problems and does not exceed the power dissipation for the IC.

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2005-04-04

TB62201AFG

Application Operation Input Data (Example: 2-Phase Excitation mode)

TORQUE TORQUE DECAY DECAY

PHASE DECAY DECAY

PHASE

B

A

3

0

1

2

3

0

1

2

0

1

B

A

0

A

0

1

Bit

1

0

1

2

3

4

5

6

7

8

9

10

0

11 12 13 14

15

1

0

1

0

1

0

2

0

3

0

4

0

Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.

For the input conditions, see page 9, Functions.

We recommend Mixed Decay mode (37.5%) as Decay mode. Set torque to 100%.

Output Current Waveform of 2-phase Excitation Sine Wave

(%)

100

Phase B

0

Phase A

−100

Note: We recommended 2-phase excitation drive in 37.5% Mixed Decay mode.

Please refer to the caution of 2-phase excitation mode on next page.

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2005-04-04

TB62201AFG

Application Operation Input Data (Example: 1-2 Phase Excitation mode Typ. A)

TORQUE TORQUE DECAY DECAY

PHASE DECAY DECAY

PHASE

A

B

A

3

0

1

2

3

0

1

2

0

1

B

A

1

0

1

0

Bit

1

0

1

2

3

4

5

6

7

8

9

10

0

11 12 13 14

15

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

2

0

1

3

0

1

4

0

5

0

6

0

7

0

8

0

1

Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.

For the input conditions, see page 10, Functions.

We recommend Mixed Decay Mode (37.5%) as Decay Mode.

Set torque to 100%.

When using this excitation mode, high efficiency can be achieved by setting the phase data to 10% (−10%). Set

current values in the order +100% → −10% → −100% → +10%.

Output Current Waveform of 1-2 Phase Excitation Sine Wave (Type. A)

(%)

100

Phase A

10

0

−10

−100

(%)

100

Phase B

10

0

−10

−100

72

2005-04-04

TB62201AFG

Points for Control that Includes Current of 0%

In modes other than 2-Phase Excitation mode (from 1-2 Phase Excitation mode to 4W1-2 Phase Excitation mode),

when the current is controlled to 0%, the TB62201AFG’s output transistors are all turned off.

At the time, the coil's energy returns to the power supply through the parasitic diodes. If the same current is

applied several times and is within the rated current, then : the power consumed by the on-resistance when current

flows to the output MOS will be less than the power consumed when current is applied to the parasitic diodes.

Therefore, when controlling the current, rather than setting 0%, set the current to the next step beyond 0% (the

minimum step in the reverse direction) for better power dissipation results.

However, if the 0% (actually 10%) current cycle is long, the power dissipation may be greater than in Off mode

because of the need for constant-current control.

Therefore, Toshiba recommend setting the current according to the actual operating pattern. (1-2 Phase Excitation

mode is the most effective.)

Flyback Diode Mode

Charge

To V power supply

M

[%]

100

Constant-

current

The coil’s energy returns through

the parasitic diodes.

control

R pin

S

U

2

OFF

U

1

Output off

period

OFF

Because V < V , the power

DS

F

dissipation is large.

10

0

−10

Load

L

1

L

2

OFF

Constant-

current

control

Forced Off mode

−100

Diode parasite

PGND

Non-flyback Diode Mode

The coil’s energy returns through

the MOS, which is turned on.

Then the coil is charged to a level

of 10%.

Charge

[%]

To V

M

100

Constant-

current

control

R

S

The power dissipation is smaller

than when the energy is returned

via the parasitic diode.

U

OFF

U

2

1

ON

10

0

(However, the longer the 10%

rated current control time, the

longer the period of current

dissipation.)

−10

Constant-

current

control

Load

ON

OFF

L

1

L

2

Constant-

current

control

Charge mode

PGND

−100

Charge

Specifies a level of 10%,

either side of 0.

73

2005-04-04

TB62201AFG

Application Operation Input Data (Example: 1-2 Phase Excitation mode Typ.B)

TORQUE TORQUE

DECAY

B

PHASE

B

DECAY

A

PHASE

A

MDMB

B

MDM A

A

3

0

1

2

3

0

1

2

0

1

Bit

1

0

1

2

1

3

0

4

5

6

7

8

1

0

9

1

10

0

11 12 13 14

15

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

0

1

3

0

1

4

0

1

5

0

6

0

7

0

Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.

For the input conditions, see page 10, Functions.

We recommend Mixed Decay Mode (37.5%) as Decay Mode.

Set torque to 100%. Same as 1-2 phase excitation (typ. A) in the previous section, power dissipation can be reduced

by changing 0% level to 10% or −10%.

Output Current Waveform of 1-2 Phase Excitation Sine Wave (Typ. B)

(%)

100

71

Phase A

0

Phase B

−71

−100

74

2005-04-04

TB62201AFG

Application Operation Input Data (Example: 4-bit micro steps)

(2 bit micro steps = W1-2 phase excitation drive)

TORQUE TORQUE DECAY DECAY

PHASE DECAY DECAY

PHASE

B

A

3

0

1

2

3

0

1

2

0

1

B

A

1

A

0

1

0

Bit

1

0

1

2

3

4

5

6

7

8

9

10

0

1

0

11 12 13 14

15

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.

For the input conditions, see page 9, Functions.

We recommend Slow Decay Mode in the ascending direction of the sine wave; Mixed Decay Mode (37.5%) in the

descending direction. Set torque to 100%.

75

2005-04-04

TB62201AFG

Output Current Waveform of Pseudo Sine Wave (2-bit micro steps)

(%)

100

92

71

Phase A

38

0

Phase B

−38

−71

−92

−100

Step

5 micro-step from 0 to 90° drive is possible by combining Current DATA (AB & CD) and phase data.

For input Current DATA at that time, see section on Current X in the list of the Functions.

Depending on the load, the optimum condition changes for selecting MIXED DECAY MODE when the sine wave

rises and falls. Select the appropriate MIXED DECAY TIMING according to the load.

76

2005-04-04

TB62201AFG

Application Operation Input Data (Example: 3-bit micro steps)

(3 bit micro steps = 2W1-2 phase excitation drive)

TORQUE TORQUE DECAY DECAY

PHASE DECAY DECAY

PHASE

B

A

3

0

1

2

3

0

1

2

0

1

B

8

1

A

1

A

15

1

0

1

0

Bit

1

2

3

4

5

6

7

9

10

0

11 12 13 14

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

2

1

0

1

0

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

0

1

0

Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.

For the input conditions, see page 10, Functions.

We recommend Slow Decay Mode in the ascending direction of the sine wave; Mixed Decay Mode (37.5%) in the

descending direction. Set torque to 100%.

77

2005-04-04

TB62201AFG

Output Current Waveform of Pseudo Sine Wave (3-bit micro steps)

[%]

100

98

92

83

71

Phase A

56

38

20

0

−20

Phase B

−38

−56

−71

−83

−92

−98

−100

STEP

9 micro-step from 0 to 90° drive is possible by combining Current DATA (AB & CD) and phase data.

For input Current DATA at that time, see section on Current X in the list of the Functions.

Depending on the load, the optimum condition changes for selecting MIXED DECAY MODE when the sine wave

rises and falls. Select the appropriate MIXED DECAY TIMING according to the load.

78

2005-04-04

TB62201AFG

Application Operation Input Data (Example: 4-bit micro steps)

TORQUE TORQUE DECAY DECAY

PHASE DECAY DECAY

PHASE

B

A

3

0

1

2

3

0

1

2

0

1

B

8

1

A

1

A

15

1

0

1

0

Bit

1

2

3

4

5

6

7

9

10

0

11 12 13 14

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

2

1

0

1

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

0

79

2005-04-04

TB62201AFG

TORQUE TORQUE DECAY DECAY

PHASE DECAY DECAY

PHASE

B

A

3

0

1

2

3

0

1

2

0

1

B

8

0

A

1

A

15

0

1

0

Bit

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

2

3

4

5

6

7

9

10

1

11 12 13 14

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

0

Data are input on the rising edge of CLK. Every input of a data string (16-bit) requires input of the Strobe signal.

For the input conditions, see page 10, Functions. In the above input data example, Decay mode has a Mixed Decay

mode (37.5%) setting for both the rising and falling directions of the sine wave, and a torque setting of 100%.

80

2005-04-04

TB62201AFG

Output Current Vector Line

4W-1-2 phase excitation (4-bit micro steps)

X = 16

X = 15

100

98

X = 14

X = 13

96

92

X = 12

X = 11

88

83

X = 10

X = 9

77

71

63

X = 8

X = 7

X = 6

56

47

X = 5

X = 4

38

29

20

X = 3

X = 2

θ

X

10

X = 1

θ

X

X = 0

92 96 98 100

0

10

20

29

38

47

56

63

71

77

83

88

I

(%)

B

For data to be input, see the function of Current AX (BX) in the list of Functions (10 page).

82

2005-04-04

TB62201AFG

Output Current Vector Line 2 (Each mode: except 4W1-2 phase)

1-2 phase excitation (Typ. A)

1-2 phase excitation (Typ. B)

100

0

100

0

71

100

I

(%)

I

(%)

B

W 1-2 phase excitation

2W 1-2 phase excitation

100

92

100

92

98

83

71

38

56

38

20

0

38

71

92 100

0

20

38

56

71

83 92 100

98

I

(%)

I

(%)

B

83

2005-04-04

TB62201AFG

Temperature Characteristics Depending on Voltages between Output Transistor

Drain and Source (V = 24 V, V = 5 V)

M

DD

1200

1100

1000

900

800

700

600

500

400

300

200

100

0

105°C

85°C

Reference values

105°C (max)

25°C

0°C

25°C (max)

−40°C

105°C

85°C

25°C

0°C

−40°C

25°C max

105°C max

Maximum rating

0

100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000

Output current

I

(mA)

out

84

2005-04-04

TB62201AFG

Resistance Characteristics Depending on Voltages Output Transistor Drain and

Source (V = 24 V, V = 5 V) (Forward, reverse)

M

DD

1600

1400

1200

Reference values

1000

800

600

400

200

0

25°C (reference values)

25°C (max)

25°C

25°C max

Maximum rating

−200

−400

−600

−800

−1000

−1200

Output current

I

(mA)

out

The IC’s maximum rating is 1.5 A and recommended current is 1.2 A max.

Use the IC within this range.

The on-resistance value fluctuates according to temperature. Pay particular attention to the temperature

conditions when using.

85

2005-04-04

TB62201AFG

Recommended Application Circuit

The values for the devices are all recommended values. For values under each input condition, see the

above-mentioned recommended operating conditions.

(Example: f

= 96 kHz, CR: I

= 0.7 (A), LF: I

= 1.1 (A) )

chop

out

V

ref AB

CR

V

ref AB

SGND

V

M A

V

DD

R

RS A

5 V

0 V

R

RS A

0.75 Ω

STEPUP

A

5 V

0 V

CLK AB

A

B

5 V

0 V

Stepping

motor 1

DATA AB

M

(CR: 6.8 mH/5.7 Ω)

5 V

0 V

STROBE AB

R

RS B

R

RS B

0.75 Ω

V

M B

P-GND

V

SS

(F

IN

)

5 V

0 V

SGND

CLK CD

V

MC

5 V

0 V

DATA CD

STROBE CD

RESET

R

RS C

R

RS C

0.75 Ω

5 V

0 V

C

D

5 V

0 V

Stepping

motor 2

M

D

(LF: 6.8 mH/5.7 Ω)

RS D

R

RS D

0.75 Ω

V

M D

V

ref CD

Ccp A Ccp B

Ccp C

SGND

Ccp 2

0.015 µF

SGND

Note: We recommend the user add bypass capacitors as required.

Make sure as much as possible that GND wiring has only one contact point.

Also, make sure that the VM pins are connected.

For the data to be input, see the section on the recommended input data.

Because there may be shorts between outputs, shorts to supply, or shorts to ground, be careful when designing

output lines, V (V ) lines, and GND lines.

DD

M

86

2005-04-04

TB62201AFG

Example of 1-2 Phase Drive Current (actual) Waveform

∆: 170 Hz

@: 218 Hz

Test conditions

V

= 34 V

M

= 5 V

DD

ref

= 3.75 V

= 0.5 Ω

R

RS

Cosc = 1000 pF

Rosc = 2.2 kΩ

f

= 95 kHz

chop

T

37.5% MIXED DECAY mode

Ta = 25°C

4→

Using 6.8 mH/5.7 Ω, 1.8-degree,

200-step motor

Using Toshiba test board100

500 mA

M1.00 ms

Ch4 ∫

8.0 mV

Ch4

10.0 mVΩ

Example of 4W 1-2 Phase Drive Current (actual) Waveform

∆: 102 Hz

@: 99 Hz

Test conditions

V

= 24 V

M

500 mA

V

= 5 V

DD

ref

= 2.8 V

= 0.5 Ω

R

RS

Cosc = 1000 pF

Rosc = 2.2 kΩ

f

= 95 kHz

chop

37.5% MIXED DECAY mode

T

Ta = 25°C

4→

Using 6.8 mH/5.7 Ω, 1.8-degree,

200-step motor

Using Toshiba test board

M2.00 ms

Ch4 ∫

4.4 mV

Ch4

10.0 mVΩ

87

2005-04-04

TB62201AFG

Package Dimensions

HSOP36-P-450-0.65

Unit: mm

Weight: 0.79 g (typ.)

88

2005-04-04

TB62201AFG

About solderability, following conditions were confirmed

•

Solderability

(1) Use of Sn-63Pb solder Bath

· solder bath temperature = 230°C

· dipping time = 5 seconds

· the number of times = once

· use of R-type flux

(2) Use of Sn-3.0Ag-0.5Cu solder Bath

· solder bath temperature = 245°C

· dipping time = 5 seconds

· the number of times = once

· use of R-type flux

RESTRICTIONS ON PRODUCT USE

030619EBA

• The information contained herein is subject to change without notice.

• The information contained herein is presented only as a guide for the applications of our products. No

responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which

may result from its use. No license is granted by implication or otherwise under any patent or patent rights of

TOSHIBA or others.

• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor

devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical

stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of

safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of

such TOSHIBA products could cause loss of human life, bodily injury or damage to property.

In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as

set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and

conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability

Handbook” etc..

• The TOSHIBA products listed in this document are intended for usage in general electronics applications

(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,

etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires

extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or

bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or

spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,

medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this

document shall be made at the customer’s own risk.

• The products described in this document are subject to the foreign exchange and foreign trade laws.

• TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced

and sold, under any law and regulations.

89

2005-04-04


型号：	TB62201AFG
厂家：	TOSHIBA
描述：	Dual-Stepping Motor Driver IC for OA Equipment Using PWM Chopper Type 双步进电机驱动器IC，用于办公自动化设备使用PWM斩波型驱动器电机
文件：	总89页 (文件大小：1398K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TB62201AFG [TOSHIBA]

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