TC58DAM72F1FT00 [TOSHIBA]
128-MBIT (16M x 8 BITS/8M x 16BITS) CMOS NAND E2PROM; 128兆位（ 16M ×8位/ 8M X 16位） CMOS NAND E2PROM
| 型号： | TC58DAM72F1FT00 |
| 厂家： | 
TOSHIBA |
| 描述： | 128-MBIT (16M x 8 BITS/8M x 16BITS) CMOS NAND E2PROM |
| 文件： | 总34页 (文件大小：366K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TC58DVM72A1FT00/ TC58DVM72F1FT00
TC58DAM72A1FT00/ TC58DAM72F1FT00
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
128-MBIT (16M u 8 BITS/8M x 16BITS) CMOS NAND E2PROM
DESCRIPTION
The TC58DxM72x1xxxx is a 128-Mbit (138,412,032) bit NAND Electrically Erasable and Programmable
2
Read-Only Memory (NAND E PROM) organized as 528 bytes/264 words u 32 pages u 1024 blocks. The device uses
dual power supplies (2.7 V to 3.6 V for V
and 1.65 V to 1.95 V for V
). The device has a 528-byte/264-words
CC
CCQ
static register which allows program and read data to be transferred between the register and the memory cell array
in 528-byte/256-words increments. The Erase operation is implemented in a single block unit (16 Kbytes ꢀ 512 bytes:
528 bytes u 32 pages/8k words + 256 words:264 words x 32 pages).
The TC58DxM72x1xxxx is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEOArMTgaUenmRizoaErytSiocenll allay 528 u 32K u 8
xꢁ
TC58DxM72A1xxxx
TC58DxM72F1xxxx
264 x 32k x 16
264 x 16
Register
528 u 8
Page size
Block size
528 bytes
264 words
(16K ꢀ 512) bytes
(8k + 256) words
xꢁ Modes
Read, Reset, Auto Page Program
Auto Block Erase, Status Read
xꢁ Mode control
Serial input/output
Command control
xꢁ Power supplyꢀ ꢀ ꢀ ꢀ TC58DVM72x1xxxx
TC58DAM72x1xxxx
2.7V to 3.6V
Vcc:
2.7V to 3.6V
2.7V to 3.6V
Vccq:
1.65V to 1.95V
xꢁ Program/Erase Cycles 1E5 cycle (with ECC)
xꢁ Access time
Cell array to register 25 Ps max
Serial Read Cycle
50 ns min
xꢁ Operating current
Read (50 ns cycle) 10 mA typ.
Program (avg.)
Erase (avg.)
Standby
10 mA typ.
10 mA typ.
50 PA max.
xꢁ Package
TSOP I 48-P-1220-0.50 (Weight:0.53g typ)
000707EBA1
xꢁTOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid
situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide
for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
xꢁThe TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document
shall be made at the customer’s own risk.
xꢁThe products described in this document are subject to the foreign exchange and foreign trade laws.
xꢁThe information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or
others.
xꢁThe information contained herein is subject to change without notice.
2003-01-24 1/34
TC58DVM72A1FT00/ TC58DVM72F1FT00
TC58DAM72A1FT00/ TC58DAM72F1FT00
PIN ASSIGNMENT (TOP VIEW)
TC58DVM72F1FT00 / TC58DAM72F1FT00
TC58DVM72A1FT00 / TC58DAM72A1FT00
x16
x16
x8
x8
V
NC
NC
NC
NC
NC
NC
I/O8
I/O7
I/O6
I/O5
NC
NC
NC
V
NC
NC
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SS
I/O16
I/O8
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
NC
2
NC
NC
3
NC
NC
NC
NC
4
5
GND
RY/BY
RE
GND
RY/BY
RE
6
7
8
CE
CE
9
NC
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NC
NC
NC
V
V
V
CCQ
CC
SS
CCQ
CC
SS
NC
V
V
SS
V
NC
NC
NC
NC
NC
NC
NC
NC
I/O12
I/O4
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
CLE
ALE
WE
WP
NC
NC
CLE
ALE
WE
WP
NC
I/O4
I/O3
I/O2
I/O1
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
NC
NC
NC
SS
PINNAMES
I/O1 to I/O8
I/O9 to I/O16
CE
I/O port
I/O port (x16)
Chip enable
WE
Write enable
RE
Read enable
CLE
Command latch enable
Address latch enable
Write protect
ALE
WP
RY/BY
GND
Ready/Busy
Ground input
Power supply
I/O port Power supply
Ground
V
CC
V
CCQ
V
SS
2003-01-24 2/34
TC58DVM72A1FT00/ TC58DVM72F1FT00
TC58DAM72A1FT00/ TC58DAM72F1FT00
BLOCK DIAGRAM
V
V
V
CC SS
CCQ
Status register
Address register
Column buffer
Column decoder
Data register
Sense amp
I/O1
to
I/O Control circuit
I/O8
or
I/O16
Command register
CE
CLE
ALE
WE
RE
Logic control
Control
Memory cell array
WP
RY/BY
RY/BY
HV generator
ABSOLUTE MAXIMUM RATINGS
VALUE
SYMBOL
RATING
TC58DVxxxxx
TC58DAxxxx
unit
V
V
V
V
P
Power Supply Voltage
ꢂ0.6~4.6
ꢂ0.6~4.6
ꢂ0.6~4.6
ꢂ0.6~4.6
ꢂ0.6~2.6
ꢂ0.6~2.6
V
V
V
CC
CCQ
IN
I/O port Power Supply Voltage
Input Voltage for Control pins
Input/Output Voltage for I/O pins
Power Dissipation
ꢂ0.6 V~V
ꢀ 0.3 V ( 4.6 V)
ꢂ0.6 V~V
ꢀ 0.3 V ( 2.6 V)
≦
CCQ
≦
I/O
CCQ
0.3
0.3
W
°C
°C
°C
D
T
T
T
Soldering Temperature(10s)
Storage Temperature
260
260
solder
stg
ꢂ55~150
ꢂ55~150
Operating Temperature
0~70
0~70
opr
CAPACITANCE *(Ta =25°C, f= 1 MHz)
SYMB0L
PARAMETER
CONDITION
MIN
MAX
UNIT
C
C
*
Input
V
V
0 V
10
10
pF
pF
IN
IN
Output
0 V
ꢁ
OUT
OUT
This parameter is periodically sampled and is not tested for every device.
2003-01-24 3/34
TC58DVM72A1FT00/ TC58DVM72F1FT00
TC58DAM72A1FT00/ TC58DAM72F1FT00
VALID BLOCKS (1)
SYMBOL
PARAMETER
Number of Valid Blocks
MIN
TYP.
MAX
1024
UNIT
N
1004
ꢁ
Blocks
VB
(1) The device occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document.
(2) The first block (block address #00) is guaranteed to be a valid block at the time of shipment.
RECOMMENDED DC OPERATING CONDITIONS
TC58DVM72A1xxxx,TC58DVM72F1xxxx
SYMBOL
PARAMETER
MIN
TYP.
MAX
UNIT
V
V
V
V
*
Power Supply Voltage
2.7
2.7
3.3
ꢃꢄꢃꢁ
ꢁ
ꢁ
3.6
3.6
V
V
V
V
CC
I/O Port Power Supply Voltage
High Level input Voltage
Low Level Input Voltage
CCQ
IH
2.0
V
ꢀ 0.3
CCQ
ꢂ0.3*
0.8
IL
ꢂ2 V (pulse width lower than 20 ns)
TC58DAM72A1xxxx,TC58DAM72F1xxxx
SYMBOL
PARAMETER
MIN
TYP.
MAX
UNIT
V
V
V
V
*
Power Supply Voltage
2.7
3.3
1.8ꢁ
ꢁ
3.6
V
V
V
V
CC
CCQ
IH
I/O Port Power Supply Voltage
High Level input Voltage
Low Level Input Voltage
1.65
1.95
V
X 0.78
V
ꢀ 0.3
CCQ
CCQ
V X 0.22
CCQ
ꢂ0.3*
ꢁ
IL
ꢂ2 V (pulse width lower than 20 ns)
DC CHARACTERISTICS (Ta = 0° to 70°C, VCC 2.7 V to 3.6 V)
SYMBOL
PARAMETER
CONDITION
MIN
TYP.
MAX
UNIT
I
I
I
Input Leakage Current
Output Leakage Current
V
V
0 V to V
CCQ
ꢁ
10
r10
r10
30
PA
PA
IL
IN
0 V to V
CCQ
LO
OUT
Operating Current (Serial Read) CE V , I
IL OUT
0 mA, t
50 ns
mA
CCO1
cycle
Operating Current
(Command Input)
I
I
I
t
t
t
50 ns
50 ns
50 ns
10
10
10
30
30
30
mA
mA
mA
CCO3
CCO4
CCO5
cycle
cycle
cycle
Operating Current (Data Input)
Operating Current
(Address Input)
I
I
I
I
Programming Current
Erasing Current
ꢁ
ꢁ
10
10
10
30
30
1
mA
mA
mA
PA
CCO7
CCO8
CCS1
CCS2
Standby Current
Standby Current
CE V
CE V
WP 0 V/V
IH,
CCQ
ꢂ 0.2 V, WP 0 V/V
50
CCQ
CCQ
V
CCQ
-0.5
V
V
High Level Output Voltage
Low Level Output Voltage
I
I
ꢂꢅꢄꢆ mA
2.1 mA
V
OH
OL
OH
OL
0.4
V
I
( RY/BY ) Output Current of RY/BY pin
V
0.4 V
OL
8
mA
OL
2003-01-24 4/34
TC58DVM72A1FT00/ TC58DVM72F1FT00
TC58DAM72A1FT00/ TC58DAM72F1FT00
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta 0° to 70°C, V 2.7 V to 3.6 V)
CC
SYMBOL
PARAMETER
MIN
MAX
UNIT
NOTES
t
CLE Setup Time
CLE Hold Time
0
10
0
ꢁ
35
45
ꢇꢆꢁ
35
30
20
35
45
25
200
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Ps
ns
ns
nsꢁ
CLS
t
CLH
t
CE Setup Time
CE Hold Time
CS
t
10
25
0
CH
t
Write Pulse Width
ALE Setup Time
WP
t
ALS
t
ALE Hold Time
10
20
10
50
15
100
20
35
50
ꢁ
ꢈꢅꢅꢁ
10
15
0
ALH
t
Data Setup Time
Data Hold Time
DS
t
DH
t
t
Write Cycle Time
WE High Hold Time
WP High to WE Low
Ready to RE Falling Edge
Read Pulse Width
Read Cycle Time
WC
WH
t
WW
t
RR
t
RP
t
RC
t
t
RE Access Time (Serial Data Access)
CE Access Time (Serial Data Access,ID Read)
ALE Access Time (ID Read)
REA
CEA
t
ALEA
t
CE High Time for Last Address in Serial Read Cycle
RE Access Time (ID Read)
(2)
CEH
t
REAID
t
Data Output Hold Time
OH
t
RE High to Output High Impedance
CE High to Output High Impedance
RE High Hold Time
RHZ
CHZ
REH
t
t
t
Output-High-impedance-to- RE Falling Edge
RE Access Time (Status Read)
CE Access Time (Status Read)
RE High to WE Low
IR
t
0
RSTO
CSTO
t
t
RHW
WHC
WHR
t
WE High to CE Low
30
30
50
ꢁ
t
WE High to RE Low
t
Memory Cell Array to Starting Address
WE High to Busy
R
t
WB
t
ALE Low to RE Low (Read Cycle)
RE Last Clock Rising Edge to Busy(in Sequential Read)
AR2
t
RB
1+
t
CE High to Ready(When interrupted by CE in Read Mode)
Device Reset Time (Read/Program/Erase)
ꢁ
Psꢁ
Ps
(1)(2)
CRY
tr( RY/BY )
t
6/10/500
RST
AC TEST CONDITIONS
CONDITION
PARAMETER
TC58DVxxxxx
TC58DAxxxx
Input level
2.4 V, 0.4 V
3 ns
V
CCQ
-0.2 V, 0.2 V
3 ns
Input pulse rise and fall time
Input comparison level
Output data comparison level
Output load
1.5 V, 1.5 V
1.5 V, 1.5 V
(100 pF) ꢀ 1 TTL
0.9 V, 0.9 V
0.9 V, 0.9 V
C
L
C (30 pF)
L
2003-01-24 5/34
TC58DVM72A1FT00/ TC58DVM72F1FT00
TC58DAM72A1FT00/ TC58DAM72F1FT00
Note: (1) CE High to Ready time depends on the pull-up resistor tied to the RY/BY pin.
(Refer to Application Note (9) toward the end of this document.)
(2) Sequential Read is terminated when t is greater than or equal to 100 ns. If the RE to CE delay
CEH
is less than 30 ns, RY/BY signal stays Ready.
t
t 100 ns
CEH
*
*: V or V
IH IL
CE
RE
A : 0 to 30 ns oꢁBusy signal is not output.
525
526
527
A
RY/BY
Busy
PROGRAMMING AND ERASING CHARACTERISTICS
(Ta =0° to 70°C, VCC 2.7 V to 3.6 V)
SYMBOL
PARAMETER
MIN
TYP.
200
MAX
1000
UNIT
NOTES
(1)
t
Programming Time
Ps
PROG
Number of Programming Cycles on Same
Page
N
3
t
Block Erasing Time
2
10
ms
BERASE
(1): Refer to Application Note (12) toward the end of this document.
2003-01-24 6/34
TC58DVM72A1FT00/ TC58DVM72F1FT00
TC58DAM72A1FT00/ TC58DAM72F1FT00
TIMING DIAGRAMS
Latch Timing Diagram for Command/Address/Data
CLE
ALE
CE
RE
Setup Time
Hold Time
WE
t
t
DH
DS
I/O1
to I/O8
: V or V
IH IL
Command Input Cycle Timing Diagram
CLE
t
t
CLH
CLS
t
t
CH
CS
CE
WE
t
WP
t
t
ALH
ALS
ALE
t
t
DH
DS
I/O1
to I/O8
: V or V
IH IL
2003-01-24 7/34
TC58DVM72A1FT00/ TC58DVM72F1FT00
TC58DAM72A1FT00/ TC58DAM72F1FT00
Address Input Cycle Timing Diagram
t
CLS
CLE
CE
t
t
t
t
CS
CS
WC
CH
t
WP
t
t
WP
t
t
WP
WH
WH
WE
ALE
t
t
ALH
ALS
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
I/O1
to I/O8
A0 to A7
A9 to A16
A17 to A23
: V or V
IH IL
Data Input Cycle Timing Diagram
t
CLH
CLE
t
CH
t
t
CS
CH
t
CS
CE
ALE
WE
t
t
ALS
WC
t
t
t
WP
t
WP
WP
WH
t
t
DH
t
t
t
t
DH
DS
DS
DH
DS
I/O1
to I/O8
D 0
IN
D 1
IN
D
IN
527
: V or V
IH IL
2003-01-24 8/34
TC58DVM72A1FT00/ TC58DVM72F1FT00
TC58DAM72A1FT00/ TC58DAM72F1FT00
Serial Read Cycle Timing Diagram
t
RC
CE
RE
t
t
t
t
t
CHZ
RP
REH
RP
RP
t
CH
t
t
t
OH
OH
OH
t
t
t
t
t
t
RHZ
REA
RHZ
REA
RHZ
REA
I/O1
to I/O8
t
RR
t
CEA
RY/BY
Status Read Cycle Timing Diagram
t
CLS
CLE
t
t
CLH
CLS
t
CS
CE
WE
RE
t
t
CH
WP
t
t
t
CHZ
WHC
CSTO
t
WHR
t
OH
t
t
t
IR
DS
DH
t
t
RHZ
RSTO
Status
output
I/O1
to I/O8
70H*
RY/BY
* 70H represents the hexadecimal number
: V or V
IH IL
2003-01-24 9/34
TC58DVM72A1FT00/ TC58DVM72F1FT00
TC58DAM72A1FT00/ TC58DAM72F1FT00
Read Cycle (1) Timing Diagram
CLE
t
t
t
CLS
CLH
t
CS
CH
CE
WE
ALE
RE
t
WC
t
t
t
t
AR2
ALH
ALS
ALH
t
R
t
t
RC
RR
t
WB
t
t
t
t
t
t
t
t
t
DS DH
DS DH
DS DH
DS DH
REA
D
OUT
N
D
OUT
N ꢀ 1
D
OUT
N ꢀ 2
D
OUT
527
I/O1
to I/O8
00H
A0 toA7
A9 toA16
A17toA23
Column address
N*
RY/BY
* Read Operation using 00H Command N: 0 to 255
: V or V
IH IL
Read Cycle (1) Timing Diagram: When Interrupted by
CE
CLE
t
t
t
CLS
CLH
t
CS
CH
CE
WE
ALE
RE
t
t
CHZ
WC
t
t
t
t
AR2
ALH
ALS
ALH
t
R
t
t
RC
RR
t
WB
t
OH
t
t
t
t
t
t
t
t
t
t
DS DH
DS DH
DS DH
DS DH
REA
RHZ
D
OUT
N
D
OUT
N ꢀ 1
D
N ꢀ 2
I/O1
to I/O8
OUT
00H
A0 toA7
A9 toA16
A17toA23
Column address
N*
RY/BY
* Read Operation using 00H Command N: 0 to 255
: V or V
IH IL
2003-01-24 10/34
TC58DVM72A1FT00/ TC58DVM72F1FT00
TC58DAM72A1FT00/ TC58DAM72F1FT00
Read Cycle (2) Timing Diagram
CLE
t
t
CLH
CLS
t
t
CH
CS
CE
WE
ALE
RE
t
t
t
ALH
t
AR2
ALH
ALS
t
R
t
RR
t
RC
t
WB
t
t
t
t
t
REA
DS DH
DS DH
I/O1
to I/O8
01H
A0 toA7 A9 toA16 A17toA23
D
OUT
D
OUT
D
OUT
256 ꢀ M 256 ꢀ M ꢀ 1
527
Column address
N*
RY/BY
* Read Operation using 01H Command N: 0 to 255
: V or V
IH IL
Read Cycle (3) Timing Diagram
CLE
t
t
CLH
CLS
t
t
CH
CS
CE
WE
ALE
RE
t
t
t
ALH
t
AR2
ALH
ALS
t
R
t
RR
t
RC
t
WB
t
t
t
t
t
REA
DS DH
DS DH
I/O1
to I/O8
50H
A0 toA7 A9 toA16 A17toA23
D
OUT
D
OUT
D
OUT
512 ꢀ M 512 ꢀ M ꢀ 1
527
Column address
N*
RY/BY
* Read Operation using 50H Command N: 0 to15
: V or V
IH IL
2003-01-24 11/34
TC58DVM72A1FT00/ TC58DVM72F1FT00
TC58DAM72A1FT00/ TC58DAM72F1FT00
Sequential Read (1) Timing Diagram
CLE
CE
WE
ALE
RE
00H
A0 toA7 A9 toA16 A17toA23
Column Page
N
N ꢀ 1 N ꢀ 2
527
0
1
2
527
t
R
t
R
address address
N
M
RY/BY
Page M
access
Page M ꢀ 1
access
: V or V
IH
IL
Sequential Read (2) Timing Diagram
CLE
CE
WE
ALE
RE
I/O1
to I/O8
01H
A0 toA7 A9 toA16 A17toA23
Column Page
527
0
1
2
527
t
R
t
R
256 ꢀꢁ 256 ꢀ
N ꢀ 1
address address
N
N
M
RY/BY
Page M
access
Page M ꢀ 1
access
: V or V
20I0H3-0I1L-24 12/34
TC58DVM72A1FT00/ TC58DVM72F1FT00
TC58DAM72A1FT00/ TC58DAM72F1FT00
Sequential Read (3) Timing Diagram
CLE
CE
WE
ALE
RE
I/O1
to I/O8
50H
A0 toA7 A9 toA16 A17toA23
Column Page
527
512 513
527
t
R
t
R
512 ꢀꢁ 512 ꢀ 512 ꢀ
N ꢀ 1 N ꢀ 2
address address
N
N
M
RY/BY
Page M
access
Page M ꢀ 1
access
: V or V
IH IL
2003-01-24 13/34
TC58DVM72A1FT00/ TC58DVM72F1FT00
TC58DAM72A1FT00/ TC58DAM72F1FT00
Auto-Program Operation Timing Diagram
t
CLS
CLE
CE
t
t
CLH
CLS
t
CS
t
t
CH
CS
WE
ALE
RE
t
t
ALH
ALH
t
t
t
PROG
ALS
ALS
t
WB
t
DS
t
t
t
t
t
t
t
DS DH
DS DH
DH
DS DH
D
IN
527
I/O1
to I/O8
80H
A0 toA7 A9 toA16 A17toA23
D 0
IN
D 1
IN
10H
70H
Status
output
RY/BY
: V or V
IH IL
: Do not input data while data is being output.
Auto Block Erase Timing Diagram
CLE
t
CLS
t
CLH
t
t
CLS
CS
CE
WE
ALE
RE
t
t
t
t
BERASE
ALS
ALH
WB
t
t
DS DH
Status
output
I/O1
to I/O8
60H A9 toA16 A17toA23
D0H
70H
Auto Block Erase
Setup command
Erase Start
command
Status Read
command
RY/BY
Busy
: V or V
IH IL
: Do not input data while data is being output.
2003-01-24 14/34
TC58DVM72A1FT00/ TC58DVM72F1FT00
TC58DAM72A1FT00/ TC58DAM72F1FT00
ID Read Operation Timing Diagram
CLE
t
CLS
t
CLS
t
t
t
CS
CS
CH
CE
WE
ALE
RE
t
CH
t
CEA
t
t
ALS
t
ALH
ALH
t
ALEA
t
t
t
REAID
DS DH
t
REAID
I/O1
to I/O8
90H
00
98H
73H
Device code
Address
input
Maker code
: V or V
IH IL
2003-01-24 15/34
TC58DVM72A1FT00/ TC58DVM72F1FT00
TC58DAM72A1FT00/ TC58DAM72F1FT00
PIN FUNCTIONS
The device is a serial access memory which utilizes time-sharing input of address information. The device pin-outs
are configured as shown in Figure 1.
NC
NC
1
48 Vss
47 I/O16
46 I/O8
45 I/O15
44 I/O7
43 I/O14
42 I/O6
41 I/O13
40 I/O5
39 NC
2
Command Latch Enable: CLE
NC
3
NC
NC
GND
RY/BY
RE
4
The CLE input signal is used to control loading of the
operation mode command into the internal command
register. The command is latched into the command
register from the I/O port on the rising edge of the WE
signal while CLE is High.
5
6
7
8
9
CE
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NC
38 NC
V
37
V
CCQ
CC
SS
V
36 NC
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
35 NC
34 NC
Address Latch Enable: ALE
The ALE signal is used to control loading of either
address information or input data into the internal
address/data register.
33 I/O12
32 I/O4
31 I/O11
30 I/O3
29 I/O10
28 I/O2
27 I/O9
26 I/O1
25 Vss
Address information is latched on the rising edge of
WE if ALE is High.
Input data is latched if ALE is Low.
Figure 1 pinout
Chip Enable:
CE
The device goes into a low-power Standby mode when
CE goes High during a Read operation. The CE signal is ignored when device is in Busy state ( RY/BY L),
such as during a Program or Erase operation, and will not enter Standby mode even if the CE input goes High.
The CE signal must stay Low during the Read mode Busy state to ensure that memory array data is correctly
transferred to the data register.
Write Enable:
WE
The WE signal is used to control the acquisition of data from the I/O port.
Read Enable:
RE
The RE signal controls serial data output. Data is available t
after the falling edge of RE .
REA
The internal column address counter is also incremented (Address ꢁAddress ꢀ l) on this falling edge.
I/O Port: I/O1 to 8
The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from the
device.
I/O Port: I/O9 to 16
The I/O9 to 16 pins are used as a port for input/output data to and from the device. The I/O9 to 16 pins are low
level(VIL) when address and command are asserted.
Write Protect:
WP
The WP signal is used to protect the device from accidental programming or erasing. The internal voltage
regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off
sequence when input signals are invalid.
Ready/Busy:
RY/BY
The RY/BY output signal is used to indicate the operating condition of the device. The RY/BY signal is in
Busy state ( RY/BY L) during the Program, Erase and Read operations and will return to Ready state
( RY/BY H) after completion of the operation. The output buffer for this signal is an open drain.
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TC58DAM72A1FT00/ TC58DAM72F1FT00
Schematic Cell Layout and Address Assignment
The Program operation works on page units while the Erase operation works on block units.
I/O1
I/O8
A page consists of 528 bytes in which 512 bytes are used
for main memory storage and 16 bytes are for redundancy
or for other uses.
512
16
32 pages
1 block
1 page 528 bytes
1 block 528 bytes u 32 pages (16K ꢀ 512) bytes
Capacity 528 bytes u 32 pages u 1024 blocks
32768 pages
1024 blocks
8I/O
528
Figure 2. Schematic Cell Layout
I/O1
A page consists of 264 words in which 256 words are
used for main memory storage and 8 words are for
redundancy or for other uses.
I/O16
256
8
1 page 264 words
32 pages
1 block
1 block 264 words u 32 pages (8K ꢀ 256) words
Capacity 264 words u 32 pages u 1024 blocks
32768 pages
1024 blocks
An address is read in via the I/O port over three
consecutive clock cycles, as shown in Table 1.
16I/O
264
Figure 2-2. x16 Schematic Cell Layout
Table 1. Addressing
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
A0~A7: Column address
A9~A23: Page address
A14~A23: Block address
First cycle
A7
A16
*L
A6
A5
A4
A3
A2
A1
A0
A9
Second cycle
Third cycle
A15
A23
A14
A22
A13
A21
A12
A20
A11
A19
A10
A18
A9~A13: NAND address in block
A17
*: A8 is automatically set to Low or High by a 00H command or a 01H command.
I/O9-16 should be low when address is input.
*
I/O8 must be set to Low in the third cycle.
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TC58DAM72A1FT00/ TC58DAM72F1FT00
Operation Mode: Logic and Command Tables
The operation modes such as Program, Erase, Read and Reset are controlled by the ten different command
operations shown in Table 3. Address input, command input and data input/output are controlled by the CLE,
ALE, CE , WE , RE and WP signals, as shown in Table 2.
Table 2. Logic table
*1
CLE
ALE
CE
WE
RE
WP
Command Input
Address Input
Data Input
H
L
L
L
*
*
*
*
*
*
L
H
L
L
*
*
*
*
*
*
L
L
L
L
L
H
*
H
H
H
*
*
H
Serial Data Output
H
H
*
*
H
*
*
*
*
*
*
During Read (Busy)
*
During Programming (Busy)
During Erasing (Busy)
Program, Erase Inhibit
Standby
*
H
*
*
H
L
*
*
H
*
0 V/Vcc
H: V , L: V , *: V or V
IH IL IH IL
*1: Refer to Application Note (10) toward the end of this document regarding the WP signal when Program or Erase Inhibit
Table 3. Command table (HEX)
First Cycle
Second Cycle Acceptable while Busy
HEX data bit assignment
(Example)
Serial Data Input
Read Mode (1)
Read Mode (2)
Read Mode (3)
Reset
80
00
01
50
FF
10
60
70
90
ꢁ
Serial data input: 80H
ꢁ
1
0
7
0
6
0
5
0
4
0
3
0
2
0
D0
c
c
I/O8
I/O1
Auto Program
Auto Block Erase
Status Read
ID Read
0
0
0
0
0
0
0
0
I/O16 15 14 13 12 11 10 I/O9
ꢀ ꢀ 01 command isn’t implemented by x16.
Table 4 shows the operation states for Read mode.
Table 4. Read mode operation states
CLE
ALE
CE
WE
RE
I/O1~I/O16
Power
Output Select
L
L
L
L
L
L
H
H
L
Data output
Active
Active
Output Deselect
H
High impedance
H: V , L: V , *: V or V
IH IL IH IL
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TC58DAM72A1FT00/ TC58DAM72F1FT00
DEVICE OPERATION
Read Mode (1)
Read mode (1) is set when a 00H command is issued to the Command register. Refer to Figure 3 below for
timing details and the block diagram.
CLE
CE
WE
ALE
RE
RY/BY
Busy
N
M
I/O
00H
M
Start-address input
m
A data transfer operation from the cell array to the register
starts on the rising edge of WE in the third cycle (after the
address information has been latched). The device will be in
Busy state during this transfer period. The CE signal must stay
Low after the third address input and during Busy state.
Select page
N
Cell array
After the transfer period the device returns to Ready state.
Serial data can be output synchronously with the RE clock
from the start pointer designated in the address input cycle.
Figure 3. Read mode (1) operation
X8 : m=527
X16 : m=263
Read Mode (2) x8 only
CLE
CE
WE
ALE
RE
RY/BY
Busy
N
M
I/O
01H
Start-address input
256
M
527
The operation of the device after input of the 01H command is
the same as that of Read mode (1). If the start pointer is to be set
after column address 256, use Read mode (2).
Select page
N
Cell array
Figure 4. Read mode (2) operation
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TC58DAM72A1FT00/ TC58DAM72F1FT00
Read Mode (3)
Read mode (3) has the same timing as Read modes (1) and (2) but is used to access information in the extra
16-byte redundancy area of the page. The start pointer is therefore set to a value between byte 512 and byte 527.
CLE
CE
WE
ALE
RE
RY/BY
Busy
50H
Addresses bits A0~A3 are used to set the start pointer for the
redundant memory cells, while A4~A7 are ignored.
A0~A3
512
527
Once a 50H command has been issued, the pointer moves to
the redundant cell locations and only those 16 cells can be
addressed, regardless of the value of the A4-to-A7 address. (An
00H command is necessary to move the pointer back to the
0-to-511 main memory cell location.)
Figure 5. Read mode (3) operation
X8 : m=527 , n=512
X16 : m=263 , n=256
Sequential Read(1)(2)(3)
This mode allows the sequential reading of pages without additional address input.
00H
01H
Address input
Data output
Data output
t
R
t
R
t
R
RY/BY
Busy
Busy
Busy
(00H)
0
m
(01H)
(50H)
n
m
n/2
A
A
A
Sequential Read (1)
Sequential Read (2)
Sequential Read (3)
Sequential Read modes (1) and (2) output the contents of addresses 0~m as shown above, while Sequential Read
mode (3) outputs the contents of the redundant address locations only. When the pointer reaches the last address,
the device continues to output the data from this address ** on each RE clock signal.
X8 : m=527,n=512
X16 : m=263,n=256
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TC58DAM72A1FT00/ TC58DAM72F1FT00
Status Read
The device automatically implements the execution and verification of the Program and Erase operations. The
Status Read function is used to monitor the Ready/Busy status of the device, determine the result (pass/fail) of a
Program or Erase operation, and determine whether the device is in Protect mode. The device status is output
via the I/O port on the RE clock after a 70H command input. The resulting information is outlined in Table 5.
Table 5. Status output table
STATUS
OUTPUT
Fail: 1
I/O1
Pass/Fail
Not Used
Not Used
Not Used
Not Used
Not Used
Ready/Busy
Write Protect
Not Used
Pass: 0
I/O2
0
I/O3
0
The Pass/Fail status on I/O1 is only
valid when the device is in the Ready
state.
I/O4
0
I/O5
0
I/O6
0
I/O7
Ready: 1
Protect: 0
0
Busy: 0
I/O8
Not Protected: 1
I/O9 to I/O16
An application example with multiple devices is shown in Figure 6.
CE1
CE2
CE3
CEN
CEN ꢀ 1
CLE
ALE
WE
RE
Device
1
Device
2
Device
3
Device
N
Device
N ꢀ 1
I/O1
~I/O8
RY/BY
RY/BY
CLE
ALE
WE
Busy
CE1
CEN
RE
I/O
70H
70H
Status on
Device 1
Status on
Device N
Figure 6. Status Read timing application example
System Design Note: If the RY/BY pin signals from multiple devices are wired together as shown in the
diagram, the Status Read function can be used to determine the status of each individual device.
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TC58DAM72A1FT00/ TC58DAM72F1FT00
Auto Page Program
The device carries out an Automatic Page Program operation when it receives a “10H” Program command after
the address and data have been input. The sequence of command, address and data input is shown below.
(Refer to the detailed timing chart.)
Pass
80
10
70
I/O
Data input Address Data input Program
Status Read
command
Fail
command input
0 to 527 command
RY/BY
RY/BY automatically returns to Ready after
completion of the operation.
Data input
Program
Reading & verification
Selected
page
The data is transferred (programmed) from the register to the selected
page on the rising edge of WE following input of the “10H” command.
After programming, the programmed data is transferred back to the
register to be automatically verified by the device. If the programming
does not succeed, the Program/Verify operation is repeated by the device
until success is achieved or until the maximum loop number set in the
device is reached.
Figure 7. Auto Page Program operation
Auto Block Erase
The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command “D0H”
which follows the Erase Setup command “60H”. This two-cycle process for Erase operations acts as an ertra layer
of protection from aceidental erasure of data due to external noise. The device automatically executes the Erase
and Verify operations.
Pass
60
D0
70
I/O
Fail
Block Address Erase Start
input: 2 cycles command
Status Read
command
RY/BY
Busy
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TC58DAM72A1FT00/ TC58DAM72F1FT00
Reset
The Reset mode stops all operations. For example, in the case of a Program or Erase operation the internally
generated voltage is discharged to 0 volts and the device enters Wait state.
The response to an “FFH” Reset command input during the various device operations is as follows:
When a Reset (FFH) command is input during programming
Figure 8.
80
10
FF
00
Internal V
PP
RY/BY
t
(max 10 Ps)
RST
When a Reset (FFH) command is input during erasing
Figure 9.
00
D0
FF
Internal erase
voltage
RY/BY
t
(max 500 Ps)
RST
When a Reset (FFH) command is input during Read operation
Figure 10.
00
00
FF
RY/BY
t
(max 6 Ps)
RST
When a Status Read command (70H) is input after a Reset
Figure 11.
FF
70
I/O status: Pass/Fail o Pass
Ready/Busy o Ready
RY/BY
FF
70
I/O status: Ready/Busy o Busy
RY/BY
When two or more Reset commands are input in succession
Figure 12.
(1)
FF
(2)
FF
(3)
FF
RY/BY
The second
FF
command is invalid, but the third
FF
command is valid.
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TC58DAM72A1FT00/ TC58DAM72F1FT00
ID Read
The device contains ID codes which identify the device type and the manufacturer.
The ID codes can be read out under the following timing conditions:
CLE
t
CEA
CE
WE
ALE
RE
t
ALEA
t
REAID
I/O
90H
00
98H
73H
ID Read command
Address
00
Maker code
Device code
For the specifications of the access times t
, t
REAID CR
and t refer to the AC Characteristics.
AR1
Figure 13. ID Read timing
Table 6. ID Codes read out by ID read command 90H
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
Hex Data
Maker code
1
0
0
1
0
1
1
1
1
0
0
0
0
1
0
1
98H
73H
Device code
ꢀ ꢀ I/O9 to I/O16 are “0” .
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TC58DAM72A1FT00/ TC58DAM72F1FT00
APPLICATION NOTES AND COMMENTS
(1)
Power-on/off sequence:
The WP signal is useful for protecting against data corruption at power-on/off. The following timing
sequence is necessary.
The WP signal may be negated any time after the V
reaches 2.5 V and CE signal is kept high in
CC
power up sequence.
2.7 V
V
CC
1.65 V
1.5 V
0 V
0 V
V
CCQ
Don’t
care
Don’t
care
CE , WE , RE
CLE, ALE
V
IH
V
V
IL
IL
WP
Operation
Figure 15. Power-on/off Sequence
In order to operate this device stably, after V
becomes 2.5 V and VCCQ becomes 1.5V, it recommends
CC
starting access after about 200 Ps.
(2)
(3)
Status after power-on
The following sequence is necessary because some input signals may not be stable at power-on.
Power on
FF
Reset
Figure 16.
Prohibition of unspecified commands
The operation commands are listed in Table 3. Input of a command other than those specified in Table 3 is
prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle.
(4)
(5)
Restriction of command while Busy state
During Busy state, do not input any command except 70H and FFH.
Acceptable commands after Serial Input command “80H”
Once the Serial Input command “80H” has been input, do not input any command other than the Program
Execution command “10H” or the Reset command “FFH”.
If a command other than “10H” or “FFH” is input, the Program operation is not performed.
80
XX
10
For this operation the “FFH” command is needed.
Command other than
“10H” or “FFH”
Programming cannot be executed.
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TC58DAM72A1FT00/ TC58DAM72F1FT00
(6)
Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of
the block to MSB (most significant bit) page of the block. Random page address programming is prohibited.
From the LSB page to MSB page
Ex.) Random page program (Prohibition)
DATA IN: Data (1)
Data (32)
DATA IN: Data (1)
Data (32)
Data register
Data register
Page 0
Page 1
Page 2
Page 0
Page 1
Page 2
(1)
(2)
(3)
(2)
(16)
(3)
Page 15
Page 31
Page 15
(16)
(32)
(1)
Page 31
(32)
Figure 17. page programming within a block
(7)
Status Read during a Read operation
00
[A]
command
CE
00
70
WE
RY/BY
RE
Status Read
Address N
command input
Status Read
Status output
Figure 18.
The device status can be read out by inputting the Status Read command “70H” in Read mode.
Once the device has been set to Status Read mode by a “70H” command, the device will not return to Read
mode.
Therefore, a Status Read during a Read operation is prohibited.
However, when the Read command “00H” is input during [A], Status mode is reset and the device returns
to Read mode. In this case, data output starts automatically from address N and address input is unnecessary
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TC58DAM72A1FT00/ TC58DAM72F1FT00
(8)
Pointer control for “00H”, “01H” and “50H”
The device has three Read modes which set the destination of the pointer. Table 8 shows the destination of
the pointer, and Figure 19 is a block diagram of their operations.
Table 8. Pointer Destination
Pointer
0
n/2-1 n/2
n-1 n
m
Read Mode Command
A
B
C
(x8)
(x16)
(1)
(2)
(3)
00H
01H
50H
0~255
0~255
－－－
256~511
512~527
(1) 00H
(2) 01H
(3) 50H
256~263
Pointer control
Figure 19 Pointer control
The pointer is set to region A by the “00H” command, to region B by the “01H” command, and to region C by
the “50H” command.
(Example)
The “00H” command must be input to set the pointer back to region A when the pointer is pointing to region
C.
00H
50H
01H
50H
Add
Add
Add
Start point
A area
Add
Add
Add
Start point
A area
Add
Add
Start point
C area
00H
Start point
C area
Start point
C area
Start point
A area
Start point
B area
Start point
A area
To program region C only, set the start point to region C using the 50H command.
50H
80H
10H
Add
Add
DIN
Start point
C Area
Programming region C only
Programming region B and C
01H
80H
10H
Start point
B Area
Figure 20. Example of How to Set the Pointer
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TC58DAM72A1FT00/ TC58DAM72F1FT00
(9)
RY/BY : termination for the Ready/Busy pin (RY/BY )
A pull-up resistor needs to be used for termination because the RY/BY buffer consists of an open drain
DIN
circuit.
V
CCQ
Ready
V
CCQ
R
Device
Busy
RY/BY
C
L
t
f
t
r
V
SS
V
1.8 V
CCQ
Ta 25°C
30 pF
1.5 Ps
1.0 Ps
0.5 Ps
15 ns
10 ns
5 ns
Figure 21.
C
L
t
f
t
r
t
f
t
r
This data may vary from device to device.
We recommend that you use this data as a reference
when selecting a resistor value.
0
1 K:
2 K:
3 K:
4 K:
R
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TC58DAM72A1FT00/ TC58DAM72F1FT00
(10)
Note regarding the WP signal
The Erase and Program operations are automatically reset when WP goes Low. The operations are
enabled and disabled as follows:
Enable Programming
WE
DIN
WP
80
10
10
D0
D0
RY/BY
t
(100 ns min)
WW
Disable Programming
WE
DIN
80
WP
RY/BY
t
(100 ns min)
WW
Enable Erasing
WE
DIN
60
WP
RY/BY
t
(100 ns min)
WW
Disable Erasing
WE
DIN
60
WP
RY/BY
t
(100 ns min)
WW
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TC58DVM72A1FT00/ TC58DVM72F1FT00
TC58DAM72A1FT00/ TC58DAM72F1FT00
(11)
When four address cycles are input
Although the device may read in a fourth address, it is ignored inside the chip.
Read operation
CLE
CE
WE
ALE
I/O
00H, 01H, 50H
Address input
Ignored
RY/BY
Internal read operation starts when WE goes High in the third cycle.
Figure 22.
Program operation
CLE
CE
WE
ALE
I/O
80H
Address input
Data input
Ignored
Figure 23.
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TC58DVM72A1FT00/ TC58DVM72F1FT00
TC58DAM72A1FT00/ TC58DAM72F1FT00
(12)
Several programming cycles on the same page (Partial Page Program)
A page can be divided into up to 3 segments. Each segment can be programmed individually as follows:
1st programming
2nd programming
3rd programming
Result
All 1s
Data Pattern 1
All 1s
All 1s
Data Pattern 2
All 1s
Data Pattern 3
Data Pattern 3
Data Pattern 1
Data Pattern 2
Figure 24.
Note: The input data for unprogrammed or previously programmed page segments must be “1”
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TC58DVM72A1FT00/ TC58DVM72F1FT00
TC58DAM72A1FT00/ TC58DAM72F1FT00
(13)
Invalid blocks (bad blocks)
The device contains unusable blocks. Therefore, at the time of use, please check whether a block is bad and
do not use these bad blocks.
At the time of shipment, all data bytes in a Valid Block are FFh(x8) or
FFFFh(x16). For Bad Block, all bytes are not in the FFh state(x8) or FFFFh
state(x16). Please don’t perform erase operation to Bad Block.
Bad Block
Check if the device has any bad blocks after installation into the system.
Figure 27 shows the test flow for bad block detection. Bad blocks which are
detected by the test flow must be managed as unusable blocks by the
system.
A bad block does not affect the performance of good blocks because it is
isolated from the Bit line by the Select gate
Bad Block
Figure 26.
The number of valid blocks at the time of shipment is as follows:
MIN
TYP.
MAX
UNIT
Block
Valid (Good) Block Number
1004
ꢁ
1024
Bad Block Test Flowꢀ
Read Check :to verify the column address 517
bytes(x8) or 256 and 261
Start
words(x16) of the first page in the
block with FFh(x8) or FFFFh(x16)
Block No 1
Fail
Read Check
Pass
Bad Block *1
Block No. Block No. ꢀ 1
No
Block No. 1024
Yes
End
*1: No erase operation is allowed to detected bad blocks
Figure 27
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TC58DVM72A1FT00/ TC58DVM72F1FT00
TC58DAM72A1FT00/ TC58DAM72F1FT00
(14)
Failure phenomena for Program and Erase operations
The device may fail during a Program or Erase operation.
The following possible failure modes should be considered when implementing a highly reliable system.
FAILURE MODE
Erase Failure
DETECTION AND COUNTERMEASURE SEQUENCE
Status Read after Erase o Block Replacement
Block
Page
Programming
Failure
Status Read after Program o Block Replacement
Programming
Failure
1 o 0
(1) Block Verify after Program o Retry
Single Bit
(2) ECC
xꢁ ECC: Error Correction Code
xꢁ Block Replacement
Program
Error occurs
When an error happens in Block A, try to
reprogram the data into another Block (Block B)
by loading from an external buffer. Then,
prevent further system accesses to Block A (by
creating a bad block table or by using an
another appropriate scheme).
Buffer
memory
Block A
Block B
Figure 28.
Erase
When an error occurs in an Erase operation, prevent future accesses to this bad block
(again by creating a table within the system or by using another appropriate scheme).
(15) Do not turn off the power before write/erase operation is complete. Avoid using the device when the battery is
low. Power shoetage and/or power failure before write/erase operation is complete will cause loss of data and/or
damage to data.
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TC58DVM72A1FT00/ TC58DVM72F1FT00
TC58DAM72A1FT00/ TC58DAM72F1FT00
Package Dimensions
Unit : mm
Weight:
0.53g (typ.)
2003-01-24 34/34
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