TC58NYG0S3EBAI4 [TOSHIBA]
IC 128M X 8 FLASH 1.8V PROM, PBGA63, 9 X 11 MM, 0.80 MM PITCH, PLASTIC, TFBGA-63, Programmable ROM;
| 型号： | TC58NYG0S3EBAI4 |
| 厂家： | 
TOSHIBA |
| 描述： | IC 128M X 8 FLASH 1.8V PROM, PBGA63, 9 X 11 MM, 0.80 MM PITCH, PLASTIC, TFBGA-63, Programmable ROM 可编程只读存储器 内存集成电路 |
| 文件： | 总65页 (文件大小：481K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TC58NYG0S3EBAI4
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
2
1 GBIT (128M × 8 BIT) CMOS NAND E PROM
DESCRIPTION
The TC58NYG0S3E is a single 1.8V 1 Gbit (1,107,296,256 bits) NAND Electrically Erasable and Programmable
Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes × 64 pages × 1024blocks.
The device has two 2112-byte static registers which allow program and read data to be transferred between the
register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single block
unit (128 Kbytes + 4 Kbytes: 2112 bytes × 64 pages).
The TC58NYG0S3E is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
•
Organization
x8
Memory cell array 2112 × 64K × 8
Register
2112 × 8
Page size
Block size
2112 bytes
(128K + 4K) bytes
•
•
•
Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,
Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read
Mode control
Serial input/output
Command control
Number of valid blocks
Min 1004 blocks
Max 1024 blocks
•
•
Power supply
V
CC
= 1.7V to 1.95V
Access time
Cell array to register 25 µs max
Serial Read Cycle
25 ns min (CL=30pF)
•
•
Program/Erase time
Auto Page Program
Auto Block Erase
300 µs/page typ.
2.5 ms/block typ.
Operating current
Read (25 ns cycle)
Program (avg.)
Erase (avg.)
30 mA max.
30 mA max
30 mA max
50 µA max
Standby
•
Package
P-TFBGA63-0911-0.80CZ (Weight: 0.15 g typ.)
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2011-03-01C
TC58NYG0S3EBAI4
PIN ASSIGNMENT (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
A
B
C
D
E
F
NC
NC
NC
NC
NC
NC
NC
WP ALE
V
CE
WE RY/BY
SS
NC
NC
NC
NC
RE CLE NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
G
H
J
NC I/O1 NC
NC I/O2 NC
V
CC
V
CC
I/O6 I/O8
K
L
V
I/O3 I/O4 I/O5 I/O7
V
SS
SS
NC
NC
NC
NC
NC
NC
NC
NC
M
PIN NAMES
I/O1 to I/O8
CE
I/O port
Chip enable
WE
Write enable
RE
Read enable
CLE
Command latch enable
Address latch enable
Write protect
ALE
WP
RY/BY
Ready/Busy
V
Power supply
Ground
CC
V
SS
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2011-03-01C
TC58NYG0S3EBAI4
BLOCK DIAGRAM
V
V
CC SS
Status register
Address register
Column buffer
Column decoder
Data register
Sense amp
I/O1
to
I/O
Control circuit
I/O8
Command register
CE
CLE
ALE
WE
RE
Logic control
Control circuit
Memory cell array
WP
RY /BY
RY /BY
HV generator
ABSOLUTE MAXIMUM RATINGS
SYMBOL
RATING
VALUE
UNIT
V
V
V
P
Power Supply Voltage
Input Voltage
−0.6 to 2.5
−0.6 to 2.5
V
V
CC
IN
Input /Output Voltage
Power Dissipation
−0.6 to VCC + 0.3 (≤ 2.5 V)
V
I/O
0.3
260
W
°C
°C
°C
D
T
T
T
Soldering Temperature (10 s)
Storage Temperature
SOLDER
STG
OPR
−55 to 125
-40 to 85
Operating Temperature
CAPACITANCE *(Ta = 25°C, f = 1 MHz)
SYMB0L
PARAMETER
CONDITION
MIN
MAX
UNIT
C
C
*
Input
V
V
= 0 V
⎯
⎯
10
10
pF
pF
IN
IN
Output
= 0 V
OUT
OUT
This parameter is periodically sampled and is not tested for every device.
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2011-03-01C
TC58NYG0S3EBAI4
VALID BLOCKS
SYMBOL
PARAMETER
Number of Valid Blocks
MIN
TYP.
MAX
1024
UNIT
N
1004
⎯
Blocks
VB
NOTE: The device occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document.
The first block (Block 0) is guaranteed to be a valid block at the time of shipment.
The specification for the minimum number of valid blocks is applicable over lifetime
The number of valid blocks is on the basis of single plane operations, and this may be decreased with two plane
operations.
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN
1.7
TYP.
MAX
1.95
UNIT
V
V
Power Supply Voltage
⎯
CC
IH
IL
V
High Level input Voltage
Low Level Input Voltage
1.7V ≤ V
1.7V ≤ V
≤ 1.95V
≤ 1.95V
Vcc x 0.8
⎯
⎯
V
+ 0.3
V
V
CC
CC
V
−0.3*
Vcc x 0.2
CC
*
−2 V (pulse width lower than 20 ns)
DC CHARACTERISTICS (Ta = -40 to 85℃, V = 1.7 to 1.95V)
CC
SYMBOL
PARAMETER
CONDITION
CC
MIN
TYP.
MAX
UNIT
I
I
I
I
I
I
Input Leakage Current
Output Leakage Current
Serial Read Current
Programming Current
Erasing Current
V
V
= 0 V to V
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
±10
±10
30
µA
µA
IL
IN
= 0 V to V
LO
OUT
CC
= 0 mA, tcycle = 25 ns
CE = V , I
IL OUT
mA
mA
mA
µA
CCO1
CCO2
CCO3
CCS
⎯
30
⎯
30
Standby Current
CE = V
− 0.2 V, WP = 0 V/V
50
CC
CC
V
V
High Level Output Voltage
Low Level Output Voltage
I
I
= −0.1 mA
= 0.1 mA
Vcc – 0.2
⎯
⎯
4
⎯
0.2
⎯
V
V
OH
OH
OL
⎯
⎯
OL
I
Output current of RY /BY
pin
OL
( RY /BY )
V
= 0.2 V
mA
OL
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2011-03-01C
TC58NYG0S3EBAI4
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta = -40 to 85℃, V = 1.7 to 1.95V)
CC
SYMBOL
PARAMETER
MIN
MAX
UNIT
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CLE Setup Time
CLE Hold Time
CE Setup Time
CE Hold Time
Write Pulse Width
ALE Setup Time
ALE Hold Time
12
5
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
20
25
⎯
⎯
⎯
⎯
60
20
⎯
⎯
⎯
⎯
⎯
⎯
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLS
CLH
CS
20
5
CH
12
12
5
WP
ALS
ALH
DS
Data Setup Time
Data Hold Time
Write Cycle Time
WE High Hold Time
12
5
DH
25
10
100
20
20
12
25
⎯
⎯
10
10
22
5
WC
WH
WW
RR
WP High to WE Low
Ready to RE Falling Edge
Ready to WE Falling Edge
Read Pulse Width
RW
RP
Read Cycle Time
RC
RE Access Time
REA
CE Access Time
tCEA
t
t
t
t
t
t
t
t
t
t
t
t
CLE Low to RE Low
CLR
AR
ALE Low to RE Low
RE High to Output Hold Time
RE Low to Output Hold Time
RE High to Output High Impedance
CE High to Output High Impedance
CE High to ALE or CLE Don’t Care
RE High Hold Time
RHOH
RLOH
RHZ
CHZ
CSD
REH
IR
⎯
⎯
0
10
0
Output-High-impedance-to- RE Falling Edge
RE High to WE Low
30
30
60
RHW
WHC
WHR
WE High to CE Low
WE High to RE Low
t
Memory Cell Array to Starting Address
⎯
⎯
25
30
µs
µs
R
Data Cache Busy in Read Cache (following 31h and
3Fh)
t
DCBSYR1
t
Data Cache Busy in Page Copy (following 3Ah)
⎯
35
µs
DCBSYR2
t
t
WE High to Busy
⎯
⎯
100
ns
WB
Device Reset Time (Ready/Read/Program/Erase)
6/6/10/500
µs
RST
*1: tCLS and tALS can not be shorter than tWP
*2: tCS should be longer than tWP + 8ns.
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2011-03-01C
TC58NYG0S3EBAI4
AC TEST CONDITIONS
CONDITION
PARAMETER
V
: 1.7 to 1.95V
− 0.2 V, 0.2 V
3 ns
CC
Input level
V
CC
Input pulse rise and fall time
Input comparison level
Output data comparison level
Output load
Vcc / 2
Vcc / 2
See Figure below
R1
Dout
R1 = 14 kΩ
R2 = 14 kΩ
R2
30 pF
Note: Busy to ready time depends on the pull-up resistor tied to the RY /BY pin.
(Refer to Application Note (9) toward the end of this document.)
PROGRAMMING AND ERASING CHARACTERISTICS
(Ta = -40 to 85℃, V = 1.7 to 1.95V)
CC
SYMBOL
PARAMETER
MIN
TYP.
300
MAX
700
UNIT
NOTES
t
Average Programming Time
⎯
µs
PROG
t
t
Data Cache Busy Time in Write Cache (following 11h)
Data Cache Busy Time in Write Cache (following 15h)
⎯
⎯
⎯
⎯
10
µs
µs
DCBSYW1
700
(2)
(1)
DCBSYW2
N
Number of Partial Program Cycles in the Same Page
Block Erasing Time
⎯
⎯
⎯
4
t
2.5
10
ms
BERASE
(1) Refer to Application Note (12) toward the end of this document.
(2) t depends on the timing between internal programming time and data in time.
DCBSYW2
Data Output
When tREH is long, output buffers are disabled by /RE=High, and the hold time of data output depend on tRHOH
(25ns MIN). On this condition, waveforms look like normal serial read mode.
When tREH is short, output buffers are not disabled by /RE=High, and the hold time of data output depend on
tRLOH (5ns MIN). On this condition, output buffers are disabled by the rising edge of CLE,ALE,/CE or falling
edge of /WE, and waveforms look like Extended Data Output Mode.
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2011-03-01C
TC58NYG0S3EBAI4
TIMING DIAGRAMS
Latch Timing Diagram for Command/Address/Data
CLE
ALE
CE
RE
Setup Time
Hold Time
WE
t
t
DH
DS
I/O
: V or V
IH IL
Command Input Cycle Timing Diagram
CLE
t
t
CLH
CLS
t
t
CH
CS
CE
WE
ALE
I/O
t
WP
t
t
ALH
ALS
t
t
DH
DS
: V or V
IH IL
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2011-03-01C
TC58NYG0S3EBAI4
Address Input Cycle Timing Diagram
t
t
CLH
CLS
CLE
CE
t
t
t
t
CH
CH
CS
WC
t
CS
t
t
t
t
t
t
t
WP
WH
WP
WH
WP
WH
WP
WE
ALE
I/O
t
t
ALH
ALS
t
t
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
DH
DS
CA0 to 7
CA8 to 11
PA0 to 7
PA8 to 15
: V or V
IH
IL
Data Input Cycle Timing Diagram
t
t
CLH
CLS
CLE
CE
t
t
CS
t
CS
t
CH
CH
t
t
ALH
ALS
t
WC
ALE
WE
I/O
t
t
t
t
WP
WP
WH
WP
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
D
IN
0
D 1
IN
D 2111
IN
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2011-03-01C
TC58NYG0S3EBAI4
Serial Read Cycle Timing Diagram
t
RC
CE
RE
t
CHZ
t
t
t
t
RP
REH
RP
RP
t
RHZ
t
t
t
RHZ
RHZ
t
t
t
REA
REA
REA
t
t
RHOH
RHOH
RHOH
t
t
CEA
CEA
I/O
t
RR
RY /BY
: V or V
IH
IL
Status Read Cycle Timing Diagram
t
CLR
CLE
t
t
CLH
CLS
t
CS
CE
WE
t
t
t
CEA
WP
CH
t
CHZ
t
WHC
t
WHR
RE
t
RHOH
t
t
t
IR
DS
DH
t
t
RHZ
REA
Status
output
I/O
70h*
RY /BY
: V or V
IH IL
*: 70h represents the hexadecimal number
9
2011-03-01C
TC58NYG0S3EBAI4
Read Cycle Timing Diagram
t
CLR
CLE
t
t
t
t
t
t
CLS CLH
CLS
CLH
t
t
CS
CS
CH
CH
CE
WE
ALE
RE
t
WC
t
t
t
t
ALH ALS
ALH ALS
t
R
t
RC
t
WB
t
CEA
t
t
t
t
t
t
t
t
t
t
t
t
DS DH
DS DH DS DH DS DH DS DH
DS DH
t
RR
t
REA
CA0
to 7
CA8
to 11
PA0
to 7
PA8
to 15
D
OUT
N
D
OUT
N + 1
I/O
00h
30h
Data out from
Col. Add. N
Col. Add. N
RY /BY
Read Cycle Timing Diagram: When Interrupted by CE
t
CLR
CLE
t
t
t
t
t
t
CLS
CLH
CLS
CLH
t
t
CS
CH
CS
CH
CE
WE
t
t
CSD
WC
t
t
t t
ALH ALS
ALH
ALS
ALE
t
R
t
RC
t
CHZ
t
WB
RE
t
RHZ
t
t
t
t
t
t
t
t
t
t
t
t
t
CEA
DS DH
DS DH DS DH DS DH DS DH
DS DH
t
t
RHOH
RR
t
REA
CA0
to 7
CA8
to 11
PA0
to 7
PA8
to 15
D
OUT
N
D
OUT
N + 1
I/O
00h
30h
Col. Add. N
Col. Add. N
RY /BY
10
2011-03-01C
TC58NYG0S3EBAI4
Read Cycle with Data Cache Timing Diagram (1/2)
t
t
CLR
CLR
CLE
t
t
t
t
CLH
CLH
CLH
CLH
t
t
t
t
CLS
CLS
CLS
CLS
t
t
t
t
CH
CH
CH
CH
t
t
t
t
CS
CS
CS
CS
CE
WE
t
WC
t
t
t
t
t
RW
ALH ALS
ALH ALS
tCEA
tCEA
ALE
t
R
t
t
t
DCBSYR1
DCBSYR1
RC
t
t
t
WB
WB
WB
RE
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
RR
DS DH
DS DH DS DH DS DH DS DH
DS DH
DS DH
RR
DS DH
t
t
REA
REA
CA0
to 7
CA8
to 11
PA0
to 7
PA8
to 15
D
OUT
0
D
OUT
1
D
OUT
0
I/O
00h
30h
31h
D
OUT
31h
Column address
Page address
M
Page address
Page address M
Col. Add. 0
N *
M + 1
RY /BY
Col. Add. 0
*
The column address will be reset to 0 by the 31h command input.
1
1
Continues to
of next page
11
2011-03-01C
TC58NYG0S3EBAI4
Read Cycle with Data Cache Timing Diagram (2/2)
t
t
t
CLR
CLR
CLR
CLE
t
t
t
CLH
CLH
CLH
t
t
t
CLS
CLS
CLS
t
t
CH
t
CH
CH
t
t
t
CS
CS
CS
CE
WE
tCEA
tCEA
tCEA
ALE
t
DCBSYR1
t
t
DCBSYR1
t
t
DCBSYR1
t
RC
RC
RC
t
t
t
WB
WB
WB
RE
I/O
t
t
t
t
t
t
DS DH
DS DH
DS DH
t
t
RR
t
RR
t
t
t
REA
RR
REA
REA
D
D
OUT
1
D
D
OUT
1
D
OUT
0
D
OUT
1
OUT
0
OUT
0
D
OUT
31h
31h
3Fh
D
OUT
D
OUT
D
OUT
Page address
Page address M + x
Page address M + 1
M + 2
RY /BY
Col. Add. 0
Col. Add. 0
of last page
Col. Add. 0
1
Make sure to terminate the operation with 3Fh command.
Continues from
1
12
2011-03-01C
TC58NYG0S3EBAI4
Column Address Change in Read Cycle Timing Diagram (1/2)
t
CLR
CLE
t
t
t
t
CLS CLH
CLS CLH
t
t
CH
CS
t
t
CH
CS
CE
t
WC
tCEA
WE
t
t
ALH ALS
t
t
ALH ALS
ALE
RE
t
t
R
RC
t
WB
t
t
t
t
t
t
t
t
t
t
t
t
t
RR
DS DH
DS DH
DS DH
DS DH
DS DH
DS DH
t
REA
CA0
to 7
CA8
to 11
PA0
to 7
PA8
to 15
D
OUT
A
D
OUT
A + 1
D
OUT
A + N
I/O
00h
30h
Page address
P
Page address
P
RY /BY
Column address
A
1
Continues from
1
of next page
13
2011-03-01C
TC58NYG0S3EBAI4
Column Address Change in Read Cycle Timing Diagram (2/2)
t
CLR
CLE
CE
t
t
t
t
CLH
CLS
CLH
CLS
t
t
t
t
CH
CS
CH
CS
t
RHW
tCEA
t
WC
WE
t
t
t
t
ALH ALS
ALH ALS
ALE
RE
t
t
WHR
RC
t
t
t
t
t
t
t
t
DS DH
DS DH
DS DH
DS DH
t
REA
t
IR
D
OUT
A + N
D
OUT
B
D
B + 1
D
OUT
B + N’
CA0
to 7
CA8
to 11
OUT
I/O
05h
E0h
Page address
P
Column address
B
RY /BY
Column address
B
1
Continues from
1
of last page
14
2011-03-01C
TC58NYG0S3EBAI4
Data Output Timing Diagram
CLE
CE
t
t
CLH
CLS
t
t
CH
CS
WE
t
ALH
ALE
t
RC
t
CHZ
t
t
t
t
t
RHZ
RP
REH
RP
RP
RE
I/O
t
t
REA
REA
t
t
CEA
t
DH
DS
t
t
RLOH
RLOH
t
REA
Command
Dout
Dout
t
RR
t
t
RHOH
RHOH
RY /BY
15
2011-03-01C
TC58NYG0S3EBAI4
Auto-Program Operation Timing Diagram
t
CLS
CLE
CE
t
t
CLS CLH
t
t
CS
CS
t
CH
WE
t
t
ALH
ALH
t
t
PROG
ALS
t
ALS
t
WB
ALE
RE
t
DS
t
DS
t
t
DH
DS
t
t
t
t
DH
DH
DS DH
D
IN
N+1
CA0 CA8 PA0 PA8
to 7 to 11 to 7 to 15
Status
output
80h
D N
IN
10h
70h
D M
IN
I/O
Column address
N
RY /BY
: Do not input data while data is being output.
: V or V
IH IL
*) M: up to 2112 (byte input data for ×8 device).
16
2011-03-01C
TC58NYG0S3EBAI4
Auto-Program Operation with Data Cache Timing Diagram (1/3)
t
CLS
CLE
CE
t
t
CLS CLH
t
t
CS
CS
t
CH
WE
t
t
ALH
ALH
t
t
DCBSYW2
ALS
t
WB
t
ALS
ALE
RE
t
t
DS
DS
t
DS
t
t
t
t
DH
t
DH
DS DH
DH
D
IN
N+1
CA0 CA8 PA0 PA8
to 7 to 11 to 7 to 15
D N
IN
15h
80h
I/O
80h
D 2111
IN
RY /BY
: Do not input data while data is being output.
: V or V
IH IL
1
CA0 to CA11 is 0 in this diagram.
Continues to
1
of next page
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Auto-Program Operation with Data Cache Timing Diagram (2/3)
t
CLS
CLE
CE
t
t
CLS CLH
t
CS
t
CS
t
CH
WE
t
t
ALH
ALH
t
t
DCBSYW2
t
ALS
ALS
t
WB
ALE
RE
t
DS
t
DS
t
DS
t
t
t
t
t
DH
DS DH
DH
DH
D
IN
N+1
CA0 CA8 PA0 PA8
to 7 to 11 to 7 to 15
CA0
to 7
I/O
80h
D N
IN
15h
80h
D 2111
IN
RY /BY
Repeat a max of 62 times (in order to program pages 1 to 62 of a block).
2
1
Continued from
1
of last page
: Do not input data while data is being output.
: V or V
IH IL
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Auto-Program Operation with Data Cache Timing Diagram (3/3)
t
CLS
CLE
t
CLH
t
CLS
t
t
CS
CS
CE
t
CH
WE
t
ALH
t
ALH
t
t
t
PROG (*1)
ALS
ALS
t
WB
ALE
RE
t
t
DS
DS
t
t
DS
t
t
t
DH
t
DH
DS DH
DH
D
IN
CA0
to 7
CA8
to 11
PA0
to 7
PA8
to 15
I/O
80h
D N
IN
10h
70h
Status
D 2111
IN
RY /BY
: Do not input data while data is being output.
: V or V
IH IL
2
(*1) t
: Since the last page programming by 10h command is initiated after the previous cache
during cache programming is given by the following equation.
PROG
program, the t
PROG
Continued from
2
of last page
t
= t
PROG
of the last page + t
of the previous page − A
PROG
PROG
A = (command input cycle + address input cycle + data input cycle time of the last page)
If “A” exceeds the t
PROG
of previous page, t
PROG
of the last page is t
max.
PROG
(Note) Make sure to terminate the operation with 80h-10h- command sequence.
If the operation is terminated by 80h-15h command sequence, monitor I/O 6 (Ready / Busy) by
issuing Status Read command (70h) and make sure the previous page program operation is
completed. If the page program operation is completed issue FFh reset before next operation.
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Multi-Page Program Operation with Data Cache Timing Diagram (1/4)
t
CLS
CLE
CE
t
t
CLS CLH
t
t
CS
CS
t
CH
WE
t
t
ALH
ALH
t
t
t
DCBSYW1
ALS
ALS
t
WB
ALE
RE
t
DS
t
DS
t
DS
t
t
t
t
DH
t
DH
DS DH
DH
D
IN
N+1
CA0 CA8 PA0 PA8
to 7 to 11 to 7 to 15
D N
IN
11h
81h
I/O
80h
Page Address M
District-0
D 2111
IN
RY /BY
: Do not input data while data is being output.
: V or V
IH IL
1
Continues to
1
of next page
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Multi-Page Program Operation with Data Cache Timing Diagram (2/4)
t
CLS
CLE
CE
t
t
CLS CLH
t
CS
t
CS
t
CH
WE
t
t
ALH
ALH
t
t
DCBSYW2
ALS
t
WB
t
ALS
ALE
RE
t
t
DS
DS
t
DS
t
t
t
t
DH
t
DH
DS DH
DH
D
IN
N+1
CA0 CA8 PA0 PA8
to 7 to 11 to 7 to 15
CA0
to 7
I/O
81h
D N
IN
15h
80h
Page Address M
District-1
D 2111
IN
RY /BY
Repeat a max of 63 times (in order to program pages 0 to 62 of a block).
2
1
Continued from
1
of last page
: Do not input data while data is being output.
: V or V
IH IL
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Multi-Page Program Operation with Data Cache Timing Diagram (3/4)
t
CLS
CLE
CE
t
t
CLS CLH
t
t
CS
CS
t
CH
WE
t
t
ALH
ALH
t
t
DCBSYW1
t
ALS
ALS
t
WB
ALE
RE
t
DS
t
DS
t
DS
t
t
t
t
DH
t
DH
DS DH
DH
D
IN
N+1
CA0 CA8 PA0 PA8
to 7 to 11 to 7 to 15
D N
IN
11h
81h
I/O
80h
Page Address M+n
District-0
D 2111
IN
RY /BY
: Do not input data while data is being output.
: V or V
IH IL
3
2
Continues to
3
of next page
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Multi-Page Program Operation with Data Cache Timing Diagram (4/4)
t
CLS
CLE
t
CLH
t
CLS
t
CS
t
CS
CE
t
CH
WE
t
ALH
t
ALH
t
PROG (*1)
t
t
ALS
ALS
t
WB
ALE
RE
t
t
DS
DS
t
t
DS
t
t
t
t
DH
DH
DH
DS DH
D
IN
CA0
to 7
CA8
to 11
PA0
to 7
PA8
to 15
I/O
81h
D N
IN
10h
71h
Page Address M+n
District-1
D 2111
IN
RY /BY
: Do not input data while data is being output.
: V or V
IH IL
3
Continued from
3
of last page
(*1) t
: Since the last page programming by 10h command is initiated after the previous cache
during cache programming is given by the following equation.
PROG
program, the t
PROG
t
= t
PROG
of the last page + t
of the previous page − A
PROG
PROG
A = (command input cycle + address input cycle + data input cycle time of the last page)
If “A” exceeds the t
PROG
of previous page, t
PROG
of the last page is t
max.
PROG
(Note)
Make sure to terminate the operation with 80h-10h- command sequence.
If the operation is terminated by 81h-15h command sequence, monitor I/O 6 (Ready / Busy) by issuing Status
Read command (70h) and make sure the previous page program operation is completed. If the page program
operation is completed issue FFh reset before next operation.
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Auto Block Erase Timing Diagram
CLE
t
CLS
t
CLH
t
CS
t
CLS
CE
WE
ALE
RE
t
ALH
t
t
t
ALS
BERASE
WB
t
t
DS DH
Status
output
PA0
to 7
PA8
to 15
60h
D0h
70h
I/O
Busy
Auto Block
Erase Setup
command
Erase Start
command
Status Read
command
RY /BY
: V or V
IH IL
: Do not input data while data is being output.
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Multi Block Erase Timing Diagram
CLE
t
CLS
t
CLH
t
CS
t
CLS
CE
WE
ALE
RE
t
t
t
BERASE
t
ALH
WB
ALS
t
t
DS DH
I/O1
to
PA0
to 7
PA8
to 15
60h
D0h
71h
Status
output
Auto Block
Erase Setup
command
Status Read
command
RY/BY
Busy
Repeat 2 times (District-0,1)
: V or V
IH IL
: Do not input data while data is being output.
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ID Read Operation Timing Diagram
t
CLS
CLE
CE
t
CLS
t
t
t
t
CEA
CS
CS
CH
t
CH
WE
t
t
ALH
ALS
t
t
AR
ALH
ALE
RE
I/O
t
DH
t
DS
t
t
t
t
REA
t
REA
REA
REA
REA
See
Table 5
See
Table 5
See
Table 5
90h
00h
98h
A1h
ID Read
command
Address
00
Maker code
Device code
: V or V
IH IL
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PIN FUNCTIONS
The device is a serial access memory which utilizes time-sharing input of address information.
Command Latch Enable: CLE
The CLE input signal is used to control loading of the operation mode command into the internal command
register. The command is latched into the command register from the I/O port on the rising edge of the WE
signal while CLE is High.
Address Latch Enable: ALE
The ALE signal is used to control loading address information into the internal address register. Address
information is latched into the address register from the I/O port on the rising edge of WE while ALE is High.
Chip Enable: CE
The device goes into a low-power Standby mode when CE goes High during the device is in Ready state. The
CE signal is ignored when device is in Busy state ( RY / BY = L), such as during a Program or Erase or Read
operation, and will not enter Standby mode even if the CE input goes High.
Write Enable:
WE
The WE signal is used to control the acquisition of data from the I/O port.
Read Enable:
RE
The RE signal controls serial data output. Data is available t
after the falling edge of RE .
REA
The internal column address counter is also incremented (Address = Address + l) on this falling edge.
I/O Port: I/O1 to 8
The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from
the device.
Write Protect:
WP
The WP signal is used to protect the device from accidental programming or erasing. The internal voltage
regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off
sequence when input signals are invalid.
Ready/Busy:
RY /BY
The RY / BY output signal is used to indicate the operating condition of the device. The RY / BY signal is
in Busy state ( RY / BY = L) during the Program, Erase and Read operations and will return to Ready state
( RY / BY = H) after completion of the operation. The output buffer for this signal is an open drain and has to be
pulled-up to Vccq with an appropriate resister.
If RY / BY signal is not pulled-up to Vccq( “Open” state ), device operation can not guarantee.
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TC58NYG0S3EBAI4
Schematic Cell Layout and Address Assignment
The Program operation works on page units while the Erase operation works on block units.
I/O1
I/O8
Data Cache
Page Buffer
2048
2048
64
64
A page consists of 2112 bytes in which 2048 bytes are
used for main memory storage and 64 bytes are for
redundancy or for other uses.
1 page = 2112 bytes
1 block = 2112 bytes × 64 pages = (128K + 4K) bytes
Capacity = 2112 bytes × 64pages × 1024 blocks
64 Pages=1 block
65536
pages
1024 blocks
8I/O
2112
An address is read in via the I/O port over four
consecutive clock cycles, as shown in Table 1.
Table 1. Addressing
I/O8
I/O7
I/O6
I/O5
I/O4
CA3
I/O3
CA2
I/O2
CA1
I/O1
CA0 to CA11: Column address
PA0 to PA15: Page address
First cycle
CA7
L
CA6
L
CA5
L
CA4
L
CA0
CA8
PA0
PA8
PA6 to PA15: Block address
Second cycle
Third cycle
Fourth cycle
CA11 CA10 CA9
PA3 PA2 PA1
PA0 to PA5: NAND address in block
PA7
PA6
PA5
PA4
PA15 PA14 PA13 PA12 PA11 PA10 PA9
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Operation Mode: Logic and Command Tables
The operation modes such as Program, Erase, Read and Reset are controlled by command operations shown
in Table 3. Address input, command input and data input/output are controlled by the CLE, ALE, CE , WE ,
RE and WP signals, as shown in Table 2.
Table 2. Logic Table
*1
CLE
ALE
CE
WE
RE
WP
Command Input
Data Input
H
L
L
L
*
*
*
*
*
*
L
L
H
L
*
*
*
*
*
*
L
L
L
L
*
H
H
H
*
H
Address input
*
Serial Data Output
During Program (Busy)
During Erase (Busy)
H
*
*
*
H
*
*
*
H
H
L
*
*
*
*
*
During Read (Busy)
H (*2)
H (*2)
Program, Erase Inhibit
Standby
*
*
*
*
L
H
0 V/V
CC
H: V , L: V , *: V or V
IH IL IH IL
*1: Refer to Application Note (10) toward the end of this document regarding the WP signal when Program or Erase Inhibit
*2: If CE is low during read busy, WE and RE must be held High to avoid unintended command/address input to the device or
read to device. Reset or Status Read command can be input during Read Busy.
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TC58NYG0S3EBAI4
Table 3. Command table (HEX)
First Cycle
Second Cycle
Acceptable while Busy
Serial Data Input
80
00
05
31
3F
80
85
80
80
81
81
00
8C
8C
60
90
70
71
FF
⎯
30
E0
⎯
⎯
10
⎯
15
11
15
10
3A
15
10
D0
⎯
⎯
⎯
⎯
Read
Column Address Change in Serial Data Output
Read with Data Cache
Read Start for Last Page in Read Cycle with Data Cache
Auto Page Program
Column Address Change in Serial Data Input
Auto Program with Data Cache
Multi Page Program
Read for Page Copy (2) with Data Out
Auto Program with Data Cache during Page Copy (2)
Auto Program for last page during Page Copy (2)
Auto Block Erase
ID Read
Status Read
{
{
{
Status Read for Multi-Page Program or Multi Block Erase
Reset
HEX data bit assignment
(Example)
Serial Data Input: 80h
1
8
0
7
0
6
0
5
0
4
0
3
0
2
0
I/O1
Table 4. Read mode operation states
CLE
ALE
CE
WE
RE
I/O1 to I/O8
Power
Output select
L
L
L
L
L
L
H
H
L
Data output
Active
Active
Output Deselect
H
High impedance
H: V , L: V
IH IL
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DEVICE OPERATION
Read Mode
Read mode is set when the "00h" and “30h” commands are issued to the Command register. Between the two
commands, a start address for the Read mode needs to be issued. Refer to the figures below for the sequence and
the block diagram (Refer to the detailed timing chart.).
CLE
CE
WE
ALE
RE
Busy
t
R
RY /BY
I/O
Column Address M
Page Address N
M+1
Page Address N
00h
M
30h
M
M+2
Start-address input
A data transfer operation from the cell array to the Data
Cache via Page Buffer starts on the rising edge of WE in the
30h command input cycle (after the address information has
been latched). The device will be in the Busy state during this
transfer period.
m
Data Cache
Page Buffer
Select page
N
After the transfer period, the device returns to Ready state.
Serial data can be output synchronously with the RE clock
from the start address designated in the address input cycle.
Cell array
I/O1 to 8: m = 2111
Random Column Address Change in Read Cycle
CLE
CE
WE
ALE
RE
RY /BY
Busy
t
R
Col. M
E0h
M
30h
Page N
05h
00h
M+1 M+2 M+3
M’ M’+1 M’+2 M’+3 M’+4
I/O
Col. M
Col. M’
Page N
Start from Col. M
Page N
Start from Col. M’
Start-address input
M
During the serial data output from the Data Cache, the column
address can be changed by inputting a new column address
using the 05h and E0h commands. The data is read out in serial
starting at the new column address. Random Column Address
Change operation can be done multiple times within the same
page.
M’
Select page
N
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Read Operation with Read Cache
The device has a Read operation with Data Cache that enables the high speed read operation shown below. When the block address changes, this sequence has to be
started from the beginning.
CLE
CE
WE
ALE
RE
RY /BY
t
R
t
t
t
DCBSYR1
DCBSYR1
DCBSYR1
3
5
7
1
2
4
6
1
0
0
1
0
31h
31h
3Fh
2111
2
3
2111
2
3
2111
1
00h
30h
2
3
I/O
Page Address N
Page N
Page Address N + 1
Page N + 1
Page Address N + 2
Page N + 2
Col. M
Page N
Column 0
Data Cache
Page N + 2
Page N + 1
Page Buffer
1
2
Page N
3
5
7
4
6
Page N
Page N + 1
Cell Array
1
3
Page N + 2
5
3Fh & RE clock
30h
31h & RE clock
31h & RE clock
If the 31h command is issued to the device, the data content of the next page is transferred to the Page Buffer during serial data out from the Data Cache, and therefore the tR (Data transfer from memory
cell to data register) will be reduced.
1
2
Normal read. Data is transferred from Page N to Data Cache through Page Buffer. During this time period, the device outputs Busy state for tR max.
After the Ready/Busy returns to Ready, 31h command is issued and data is transferred to Data Cache from Page Buffer again. This data transfer takes tDCBSYR1 max and the completion of this time
period can be detected by Ready/Busy signal.
3
4
Data of Page N + 1 is transferred to Page Buffer from cell while the data of Page N in Data cache can be read out by /RE clock simultaneously.
The 31h command makes data of Page N + 1 transfer to Data Cache from Page Buffer after the completion of the transfer from cell to Page Buffer. The device outputs Busy state for tDCBSYR1 max..
This Busy period depends on the combination of the internal data transfer time from cell to Page buffer and the serial data out time.
5
6
Data of Page N + 2 is transferred to Page Buffer from cell while the data of Page N + 1 in Data cache can be read out by /RE clock simultaneously
The 3Fh command makes the data of Page N + 2 transfer to the Data Cache from the Page Buffer after the completion of the transfer from cell to Page Buffer. The device outputs Busy state for
tDCBSYR1 max.. This Busy period depends on the combination of the internal data transfer time from cell to Page buffer and the serial data out time.
Data of Page N + 2 in Data Cache can be read out, but since the 3Fh command does not transfer the data from the memory cell to Page Buffer, the device can accept new command input immediately
after the completion of serial data out.
7
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Multi Page Read Operation
The device has a Multi Page Read operation and Multi Page Read with Data Cache operation.
(1) Multi Page Read without Data Cache
The sequence of command and address input is shown below.
Same page address (PA0 to PA5) within each district has to be selected.
Command
input
(2 cycle)
(2 cycle)
Address input
Address input
60
60
30
A
A
Page Address
PA0 to PA15
(District 0)
Page Address
PA0 to PA15
(District 1)
tR
RY/BY
Command
input
(4 cycle)
(2 cycle)
Address input
Address input
00
05
E0
Data output
(District 0)
B
B
A
A
Column + Page Address
Column Address
CA0 to CA11
(District 0)
CA0 to CA11, PA0 to PA15
(District 0)
RY/BY
Command
input
(2 cycle)
(4 cycle)
Address input
Address input
00
05
E0
Data output
(District 1)
B
B
Column + Page Address
Column Address
CA0 to CA11
(District 1)
CA0 to CA11, PA0 to PA15
(District 1)
RY/BY
District 0
District 1
Reading
Selected
page
Selected
page
The data transfer operation from the cell array to the Data Cache via Page Buffer starts on the rising
edge of WE in the 30h command input cycle (after the 2 Districts address information has been
latched). The device will be in the Busy state during this transfer period.
After the transfer period, the device returns to Ready state. Serial data can be output synchronously
with the RE clock from the start address designated in the address input cycle.
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(2) Multi Page Read with Data Cache
When the block address changes (increments) this sequenced has to be started from the beginning.
The sequence of command and address input is shown below.
Same page address (PA0 to PA5) within each district has to be selected.
Command
input
Address input
Address input
60
60
30
A
A
Page Address
PA0 to PA15
(Page m0 ; District 0)
Page Address
PA0 to PA15
(Page n0 ; District 1)
tR
RY/BY
Command
input
Address input
Address input
31
00
05
E0
Data output
(District 0)
B
B
A
A
Column + Page Address
CA0 to CA11, PA0 to PA15
(Page m0 ; District 0)
Column Address
CA0 to CA11
(District 0)
tDCBSYR1
RY/BY
Command
input
Address input
Address input
00
05
E0
Data output
(District 1)
B
B
C
C
Column + Page Address
CA0 to CA11, PA0 to PA15
(Page n0 ; District 1)
Column Address
CA0 to CA11
(District 1)
RY/BY
Return to A
Repeat a max of 63 times
Command
input
Address input
Address input
3F
00
05
E0
Data output
D
D
C
C
Column + Page Address
Column Address
CA0 to CA11
(District 0)
(District 0)
CA0 to CA11, PA0 to PA15
(Page m63 ; District 0)
tDCBSYR1
RY/BY
Command
input
Address input
Address input
00
05
E0
Data output
(District 1)
D
D
Column + Page Address
CA0 to CA11, PA0 to PA15
(Page n63 ; District 1)
Column Address
CA0 to CA11
(District 1)
RY/BY
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(3) Notes
(a) Internal addressing in relation with the Districts
To use Multi Page Read operation, the internal addressing should be considered in relation with the District.
The device consists from 2 Districts.
Each District consists from 512 erase blocks.
•
•
•
The allocation rule is follows.
District 0: Block 0, Block 2, Block 4, Block 6,···, Block 1022
District 1: Block 1, Block 3, Block 5, Block 7,···, Block 1023
(b) Address input restriction for the Multi Page Read operation
There are following restrictions in using Multi Page Read;
(Restriction)
Maximum one block should be selected from each District.
Same page address (PA0 to PA5) within two districts has to be selected.
For example;
(60) [District 0, Page Address 0x0000] (60) [District 1, Page Address 0x0040] (30)
(60) [District 0, Page Address 0x0001] (60) [District 1, Page Address 0x0041] (30)
(Acceptance)
There is no order limitation of the District for the address input.
For example, following operation is accepted;
(60) [District 0] (60) [District 1] (30)
(60) [District 1] (60) [District 0] (30)
It requires no mutual address relation between the selected blocks from each District.
(c) WP signal
Make sure WP is held to High level when Multi Page Read operation is performed
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Auto Page Program Operation
The device carries out an Automatic Page Program operation when it receives a "10h" Program command
after the address and data have been input. The sequence of command, address and data input is shown below.
(Refer to the detailed timing chart.)
CLE
CE
WE
ALE
RE
RY/BY
Status
Out
Din
70h
80h
Din Din Din
Data
10h
I/O
Col. M
Page P
Data input
The data is transferred (programmed) from the Data Cache via
the Page Buffer to the selected page on the rising edge of WE
following input of the “10h” command. After programming, the
programmed data is transferred back to the Page Buffer to be
automatically verified by the device. If the programming does not
succeed, the Program/Verify operation is repeated by the device
until success is achieved or until the maximum loop number set in
the device is reached.
Program
Read& verification
Selected
page
Random Column Address Change in Auto Page Program Operation
The column address can be changed by the 85h command during the data input sequence of the Auto Page Program
operation.
Two address input cycles after the 85h command are recognized as a new column address for the data input. After
the new data is input to the new column address, the 10h command initiates the actual data program into the
selected page automatically. The Random Column Address Change operation can be repeated multiple times within
the same page.
80h
Din Din Din
Din
85h
Din Din Din
Din
10h
70h
Status
Col. M’
Col. M
Page N
Col. M
Col. M’
Data input
Program
Reading & verification
Selected
page
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Multi Page Program
The device has a Multi Page Program, which enables even higher speed program operation compared to Auto Page Program. The sequence of command, address and data
input is shown bellow. (Refer to the detailed timing chart.)
Although two planes are programmed simultaneously, pass/fail is not available for each page when the program operation completes. Status bit of I/O 0 is set to “1” when
any of the pages fails. Limitation in addressing with Multi Page Program is shown below.
Multi Page Program
tDCBSYW1
tPROG
R/ B
”0”
I/O0~7
80h
Address & Data Input
CA0~CA11 : Valid
11h
81h
Address & Data Input
CA0~CA11 : Valid
10h
70h
I/O0
Pass
Note
”1”
Fail
PA0~PA5
PA6
: Valid’
: District0’
PA0~PA5
PA6
: Valid
: District1
PA7~PA15 : Valid’
PA7~PA15 : Valid
NOTE: Any command between 11h and 81h is prohibited except 70h and FFh.
80h
11h
81h
10h
Data
Input
Plane 0
Plane 1
(512 Block)
(512 Block)
Block 0
Block 2
Block 1
Block 3
Block 1020
Block 1022
Block 1021
Block 1023
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Auto Page Program Operation with Data Cache
The device has an Auto Page Program with Data Cache operation enabling the high speed program operation shown below. When the block address changes this
sequenced has to be started from the beginning.
CLE
CE
WE
ALE
RE
RY /BY
t
t
t
DCBSYW2
PROG (NOTE)
DCBSYW2
I/O
Add
Add
15h
70h
15h
70h
10h
70h
Add
Add
Add Add Add
Add Add Add
Add
80h
Din Din
Din
80h
Din Din
Din
80h
Din Din
Din
Page N
Status Output
Page N + 1
Status Output
Page N + P
Status Output
5
6
1
2
3
4
3
5
Data for Page N + P
Data for Page N + 1
Data for Page N
2
Data Cache
Page Buffer
4
Data for Page N + 1
1
Data for Page N
3
Page N
Cell Array
5
6
Page N + 1
Page N + P
Page N + P − 1
Issuing the 15h command to the device after serial data input initiates the program operation with Data Cache
1
2
3
4
Data for Page N is input to Data Cache.
Data is transferred to the Page Buffer by the 15h command. During the transfer the Ready/Busy outputs Busy State (t
Data is programmed to the selected page while the data for page N + 1 is input to the Data Cache.
By the 15h command, the data in the Data Cache is transferred to the Page Buffer after the programming of page N is completed. The device output busy state from the 15h command
).
DCBSYW2
until the Data Cache becomes empty. The duration of this period depends on timing between the internal programming of page N and serial data input for Page N + 1 (t
).
DCBSYW2
5
6
Data for Page N + P is input to the Data Cache while the data of the Page N + P − 1 is being programmed.
The programming with Data Cache is terminated by the 10h command. When the device becomes Ready, it shows that the internal programming of the Page N + P is completed.
NOTE: Since the last page programming by the 10h command is initiated after the previous cache program, the tPROG during cache programming is given by the following;
t
= t
PROG
for the last page + t
PROG
of the previous page − ( command input cycle + address input cycle + data input cycle time of the previous page)
PROG
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Pass/fail status for each page programmed by the Auto Page Programming with Data Cache operation can be detected by the Status Read operation.
z
z
I/O1 : Pass/fail of the current page program operation.
I/O2 : Pass/fail of the previous page program operation.
The Pass/Fail status on I/O1 and I/O2 are valid under the following conditions.
z
z
Status on I/O1: Page Buffer Ready/Busy is Ready State.
The Page Buffer Ready/Busy is output on I/O6 by Status Read operation or RY / BY pin after the 10h command
Status on I/O2: Data Cache Read/Busy is Ready State.
The Data Cache Ready/Busy is output on I/O7 by Status Read operation or RY / BY pin after the 15h command.
Example)
I/O2 =>
I/O1 =>
Invalid
Invalid
Page 1
Invalid
Page 1
Page 2
Page N − 2
invalid
invalid
Page N − 1
Invalid
Page N
Status
Out
Status
Out
Status
Out
Status
Out
Status
Out
Status
Out
80h…15h
70h
70h
70h
70h
70h
80h…15h
Page 1
80h…15h
Page 2
80h…10h
Page N
70h
Page N − 1
RY/BY pin
Data Cache Busy
Page 1
Page Buffer Busy
Page 2
Page N − 1
Page N
If the Page Buffer Busy returns to Ready before the next 80h command input, and if Status Read is done during
this Ready period, the Status Read provides pass/fail for Page 2 on I/O1 and pass/fail result for Page1 on I/O2
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Multi Page Program with Data Cache
The device has a Multi Page Program with Data Cache operation, which enables even higher speed program
operation compared to Auto Page Program with Data Cache as shown below. When the block address changes
(increments) this sequenced has to be started from the beginning.
The sequence of command, address and data input is shown below. (Refer to the detailed timing chart.)
Data input
command
Data input
command
Dummy
Program
command
Program with
Data Cache
command
Dummy
Program
command
Auto Page
Program
for multi-page
program
for multi-page
program
Data input
command
Data input
command
command
80
11
81
15
80
11
81
10
Address Data input
Address Data input
input
0 to 2111
(District 0)
Address Data input
Address Data input
input
0 to 2111
input
0 to 2111
input
0 to 2111
(District1)
(District 1)
(District 0)
RY/BY
After “15h” or “10h” Program command is input to device, physical programing starts as follows. For details
of Auto Program with Data Cache, refer to “Auto Page Program with Data Cache”.
District 0
District 1
Program
Selected
page
Reading & verification
The data is transferred (programmed) from the page buffer to the selected page on the rising edge of
/WE following input of the “15h” or “10h” command. After programming, the programmed data is
transferred back to the register to be automatically verified by the device. If the programming does not
succeed, the Program/Verify operation is repeated by the device until success is achieved or until the
maximum loop number set in the device is reached.
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Starting the above operation from 1st page of the selected erase blocks, and then repeating the operation
total 64 times with incrementing the page address in the blocks, and then input the last page data of the
blocks, “10h” command executes final programming. Make sure to terminate with 81h-10h- command
sequence.
In this full sequence, the command sequence is following.
1st
80
80
11
11
81
81
15
15
63th
64th
80
80
11
11
81
81
15
10
After the “15h” or “10h” command, the results of the above operation is shown through the “71h”Status Read
command.
Pass
10 or15
71
I/O
Status Read
command
Fail
RY/BY
The 71h command Status description is as below.
STATUS
OUTPUT
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
Chip Status1 : Pass/Fail
District 0 Chip Status1 : Pass/Fail
District 1 Chip Status1 : Pass/Fail
District 0 Chip Status2 : Pass/Fail
District 1 Chip Status2 : Pass/Fail
Ready/Busy
Pass: 0
Pass: 0
Pass: 0
Pass: 0
Pass: 0
Ready: 1
Ready: 1
Protect: 0
Fail: 1
I/O1 describes Pass/Fail condition of
district 0 and 1(OR data of I/O2 and I/O3).
If one of the districts fails during multi
page program operation, it shows “Fail”.
Fail: 1
Fail: 1
Fail: 1
Fail: 1
I/O2 to 5 shows the Pass/Fail condition of
each district. For details on “Chip Status1”
and “Chip Status2”, refer to section
“Status Read”.
Busy: 0
Busy: 0
Data Cache Ready/Busy
Write Protect
Not Protect: 1
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Internal addressing in relation with the Districts
To use Multi Page Program operation, the internal addressing should be considered in relation with the
District.
•
•
•
The device consists from 2 Districts.
Each District consists from 512 erase blocks.
The allocation rule is follows.
District 0: Block 0, Block 2, Block 4, Block 6,···, Block 1022
District 1: Block 1, Block 3, Block 5, Block 7,···, Block 1023
Address input restriction for the Multi Page Program with Data Cache operation
There are following restrictions in using Multi Page Program with Data Cache;
(Restriction)
Maximum one block should be selected from each District.
Same page address (PA0 to PA5) within two districts has to be selected.
For example;
(80) [District 0, Page Address 0x0000] (11) (81) [District 1, Page Address 0x0040] (15 or 10)
(80) [District 0, Page Address 0x0001] (11) (81) [District 1, Page Address 0x0041] (15 or 10)
(Acceptance)
There is no order limitation of the District for the address input.
For example, following operation is accepted;
(80) [District 0] (11) (81) [District 1] (15 or 10)
(80) [District 1] (11) (81) [District 0] (15 or 10)
It requires no mutual address relation between the selected blocks from each District.
Operating restriction during the Multi Page Program with Data Cache operation
(Restriction)
The operation has to be terminated with “10h” command.
Once the operation is started, no commands other than the commands shown in the timing diagram is allowed
to be input except for Status Read command and reset command.
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Page Copy (2)
By using Page Copy (2), data in a page can be copied to another page after the data has been read out.
When the block address changes (increments) this sequenced has to be started from the beginning.
Command
input
2
3
Address input
Address
Address input
Address
Address input
Address
00
30
Data output
Col = 0 start
8C
Data input
15
00
3A
Data output
Col = 0 start
A
A
When changing data,
CA0 to CA11, PA0 to PA15
(Page N)
CA0 to CA11, PA0 to PA15
(Page M)
CA0 to CA11, PA0 to PA15
(Page N+P1)
changed data is input.
1
4
5
RY/BY
t
t
t
DCBSYR2
R
DCBSYW2
1
2
3
4
5
Data for Page N + P1
Data for Page N
Data for Page N
Data for Page M
Data Cache
Page Buffer
Cell Array
Page M
Page N + P1
Page N
Page Copy (2) operation is as following.
1
2
3
4
5
Data for Page N is transferred to the Data Cache.
Data for Page N is read out.
Copy Page address M is input and if the data needs to be changed, changed data is input.
Data Cache for Page M is transferred to the Page Buffer.
After the Ready state, Data for Page N + P1 is output from the Data Cache while the data of Page M is being programmed.
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Command
input
6
Address input
Address
Address input
Address
Address input
Address
A
A
8C
Data input
15
00
3A
Data output
Col = 0 start
00
3A
Data output
Col = 0 start
B
B
When changing data,
changed data is input.
CA0 to CA11, PA0 to PA15
(Page M+R1)
CA0 to CA11, PA0 to PA15
(Page N+P2)
CA0 to CA11, PA0 to PA15
(Page N+Pn)
9
8
7
RY /BY
t
t
t
DCBSYR2
DCBSYW2
DCBSYR2
7
9
6
8
Data for Page M + R1
Data for Page M + R1
Data for Page N + P2
Data for Page N + Pn
Data Cache
Page Buffer
Page M + Rn − 1
Page M + Rn − 1
Cell Array
Page M + R1
Page M
Page N + Pn
Page N + P2
Page N + P1
6
Copy Page address (M + R1) is input and if the data needs to be changed, changed data is input.
After programming of page M is completed, Data Cache for Page M + R1 is transferred to the Page Buffer.
By the 15h command, the data in the Page Buffer is programmed to Page M + R1. Data for Page N + P2 is transferred to the Data cache.
The data in the Page Buffer is programmed to Page M + Rn − 1. Data for Page N + Pn is transferred to the Data Cache.
7
8
9
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Command
input
10
Address input
Address
B
B
8C
Data input
10
70
Status output
CA0 to CA11, PA0 to PA15
(Page M+Rn)
11
RY /BY
t
(*1)
PROG
Data for Page M + Rn
Data for Page M + Rn
10
11
Data Cache
Page Buffer
Page N + Pn
Page M + Rn − 1
Cell Array
10 Copy Page address (M + Rn) is input and if the data needs to be changed, changed data is input.
11 By issuing the 10h command, the data in the Page Buffer is programmed to Page M + Rn.
(*1) Since the last page programming by the 10h command is initiated after the previous cache program, the t
here will be expected as the following,
PROG
t
= t of the last page + tPROG of the previous page − ( command input cycle + address input cycle + data output/input cycle time of the last page)
PROG
PROG
NOTE) This operation needs to be executed within District-0 or District-1.
Data input is required only if previous data output needs to be altered.
If the data has to be changed, locate the desired address with the column and page address input after the 8Ch command, and change only the data that needs be changed.
If the data does not have to be changed, data input cycles are not required.
Make sure WP is held to High level when Page Copy (2) operation is performed.
Also make sure the Page Copy operation is terminated with 8Ch-10h command sequence
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Multi Page Copy (2)
By using Multi Page Copy (2), data in two pages can be copied to another pages after the data has been read out.
When the each block address changes (increments) this sequenced has to be started from the beginning.
Same page address (PA0 to PA5) within two districts has to be selected.
Command
input
Address input
Address input
Address input
Address input
60
60
30
00
05
E0
Data output
A
Address
CA0 to CA11, PA0 to PA15
(Page m0)
Address
PA0 to PA15
(Page m0 ; District 0)
Address
PA0 to PA15
(Page n0 ; District 1)
Address
CA0 to CA11
(Col = 0)
A
B
RY/BY
t
R
Address input
Address
Address input
Data output
Address input
Address
Data input
00
05
E0
8C
11
A
Address
CA0 to CA11
(Col = 0)
CA0 to CA11, PA0 to PA15
(Page n0)
CA0 to CA11, PA0 to PA15
(Page M0 ; District 0)
A
B
B
C
RY/BY
t
DCBSYW1
Address input
Address
Data input
Address input
Address input
8C
15
60
60
3A
Address
PA0 to PA15
Address
PA0 to PA15
CA0 to CA11, PA0 to PA15
(Page N0 ; District 1)
(Page m1 ; District 0)
(Page n1 ; District 1)
B
C
C
C
D
RY/BY
t
t
DCBSYR2
DCBSYW2
Address input
Address input
Data output
Address input
Address
Address input
Data output
00
05
E0
00
05
E0
Address
CA0 to CA11, PA0 to PA15
(Page m1)
Address
CA0 to CA11
(Col = 0)
Address
CA0 to CA11
(Col = 0)
CA0 to CA11, PA0 to PA15
(Page n1)
D
RY/BY
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D
D
E
Address input
Address
Data input
Address input
Address
Data input
E
8C
11
8C
15
CA0 to CA11, PA0 to PA15
(Page M1 ; District 0)
CA0 to CA11, PA0 to PA15
(Page N1 ; District 1)
E
RY/BY
t
t
DCBSYW2
DCBSYW1
Address input
Address input
Address input
Address input
60
60
3A
00
05
E0
Data output
F
Address
CA0 to CA11, PA0 to PA15
(Page m63)
Address
PA0 to PA15
Address
PA0 to PA15
Address
CA0 to CA11
(Col = 0)
(Page m63 ; District 0)
(Page n63 ; District 1)
E
F
F
G
G
RY/BY
RY/BY
RY/BY
t
DCBSYR2
Address input
Address input
Data output
Address input
Address
Data input
00
05
E0
8C
11
Address
CA0 to CA11, PA0 to PA15
(Page n63)
Address
CA0 to CA11
(Col = 0)
CA0 to CA11, PA0 to PA15
(Page M63 ; District 0)
F
t
DCBSYW1
Address input
Address
Data input
G
8C
10
Note)
This operation needs to be executed within each District.
CA0 to CA11, PA0 to PA15
(Page N63 ; District 1)
Data input is required only if previous data output needs to be altered.
G
If the data has to be changed, locate the desired address with the column and page address input after
the 8Ch command, and change only the data that needs be changed.
tPROG (*1)
(*1) t : Since the last page programming by 10h command is initiated after the previous cache
PROG
If the data does not have to be changed, data input cycles are not required.
program, the t
during cache programming is given by the following equation.
= t of the last page + t of the previous page-A
PROG PROG
PROG*
Make sure WP is held to High level when Multi Page Copy (2) operation is performed.
t
Also make sure the Multi Page Copy operation is terminated with 8Ch-10h command sequence
PROG
A = (command input cycle + address input cycle + data output/input cycle time of the last page)
If “A” exceeds the t of previous page, t of the last page is t max.
PROG PROG
PROG
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Auto Block Erase
The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command “D0h” which
follows the Erase Setup command “60h”. This two-cycle process for Erase operations acts as an extra layer of
protection from accidental erasure of data due to external noise. The device automatically executes the Erase
and Verify operations.
Pass
60
D0
70
I/O
Fail
Block Address
input: 2 cycles
Status Read
command
Erase Start
command
RY /BY
Busy
Multi Block Erase
The Multi Block Erase operation starts by selecting two block addresses before D0h command as in below
diagram. The device automatically executes the Erase and Verify operations and the result can be monitored by
checking the status by 71h status read command. For details on 71h status read command, refer to section
“Multi Page Program with Data Cache”.
Pass
D0
60
Block Address
60
Block Address
71
I/O
Fail
Status Read
command
Erase Start
command
input: 2 cycles
District 0
input: 2 cycles
District 1
RY /BY
Busy
Internal addressing in relation with the Districts
To use Multi Block Erase operation, the internal addressing should be considered in relation with the District.
The device consists from 2 Districts.
Each District consists from 512 erase blocks.
•
•
•
The allocation rule is follows.
District 0: Block 0, Block 2, Block 4, Block 6,···, Block 1022
District 1: Block 1, Block 3, Block 5, Block 7,···, Block 1023
Address input restriction for the Multi Block Erase
There are following restrictions in using Multi Block Erase
(Restriction)
Maximum one block should be selected from each District.
For example;
(60) [District 0] (60) [District 1] (D0)
(Acceptance)
There is no order limitation of the District for the address input.
For example, following operation is accepted;
(60) [District 1] (60) [District 0] (D0)
It requires no mutual address relation between the selected blocks from each District.
Make sure to terminate the operation with D0h command. If the operation needs to be terminated before D0h
command input, input the FFh reset command to terminate the operation.
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ID Read
The device contains ID codes which can be used to identify the device type, the manufacturer, and features of
the device. The ID codes can be read out under the following timing conditions:
CLE
t
CEA
CE
WE
ALE
RE
t
AR
t
REA
See
table 5
See
table 5
See
table 5
I/O
00h
98h
A1h
ID Read
Address 00
Maker code Device code
command
Table 5. Code table
Description
I/O8
1
I/O7
0
I/O6
0
I/O5
1
I/O4
1
I/O3
0
I/O2
0
I/O1
0
Hex Data
98h
1st Data
2nd Data
3rd Data
4th Data
5th Data
Maker Code
Device Code
1
0
1
0
0
0
0
1
A1h
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
See table
Chip Number, Cell Type
Page Size, Block Size,
Plane Number
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
See table
See table
3rd Data
Description
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
1
2
4
8
0
0
1
1
0
1
0
1
Internal Chip Number
Cell Type
2 level cell
4 level cell
8 level cell
16 level cell
0
0
1
1
0
1
0
1
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4th Data
Description
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
1 KB
2 KB
4 KB
8 KB
0
0
1
1
0
1
0
1
Page Size
(without redundant area)
64 KB
128 KB
256 KB
512 KB
0
0
1
1
0
1
0
1
Block Size
(without redundant area)
5th Data
Description
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
1 Plane
2 Plane
4 Plane
8 Plane
0
0
1
1
0
1
0
1
Plane Number
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Status Read
The device automatically implements the execution and verification of the Program and Erase operations.
The Status Read function is used to monitor the Ready/Busy status of the device, determine the result (pass
/fail) of a Program or Erase operation, and determine whether the device is in Protect mode. The device status is
output via the I/O port using RE after a “70h” command input. The Status Read can also be used during a
Read operation to find out the Ready/Busy status.
The resulting information is outlined in Table 6.
Table 6. Status output table
Page Program
Block Erase
Read
Definition
Cache Program
Cache Read
Chip Status1
I/O1
I/O2
Pass/Fail
Pass/Fail
Invalid
Pass: 0
Fail: 1
Fail: 1
Chip Status 2
Pass: 0
Invalid
Pass/Fail
Invalid
I/O3
I/O4
I/O5
Not Used
Not Used
Not Used
0
0
0
0
0
0
0
0
0
Page Buffer Ready/Busy
I/O6
I/O7
I/O8
Ready/Busy
Ready/Busy
Write Protect
Ready/Busy
Ready/Busy
Write Protect
Ready/Busy
Ready/Busy
Write Protect
Ready: 1
Busy: 0
Data Cache Ready/Busy
Ready: 1
Busy: 0
Write Protect
Not Protected :1 Protected: 0
The Pass/Fail status on I/O1 and I/O2 is only valid during a Program/Erase operation when the device is in the Ready state.
Chip Status 1:
During a Auto Page Program or Auto Block Erase operation this bit indicates the pass/fail result.
During a Auto Page Programming with Data Cache operation, this bit shows the pass/fail results of the
current page program operation, and therefore this bit is only valid when I/O6 shows the Ready state.
Chip Status 2:
This bit shows the pass/fail result of the previous page program operation during Auto Page Programming
with Data Cache. This status is valid when I/O7 shows the Ready State.
The status output on the I/O6 is the same as that of I/O7 if the command input just before the 70h is not
15h or 31h.
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An application example with multiple devices is shown in the figure below.
CE1
CE2
CE3
CEN
CEN + 1
CLE
ALE
WE
RE
Device
Device
Device
Device
N
Device
N + 1
1
2
3
I/O1
to I/O8
RY /BY
RY /BY
CLE
ALE
WE
Busy
CE1
CEN
RE
I/O
70h
70h
Status on Device 1
Status on Device N
System Design Note: If the RY / BY pin signals from multiple devices are wired together as shown in the
diagram, the Status Read function can be used to determine the status of each individual device.
Reset
The Reset mode stops all operations. For example, in case of a Program or Erase operation, the internally
generated voltage is discharged to 0 volt and the device enters the Wait state.
Reset during a Cache Program/Page Copy may not just stop the most recent page program but it may also
stop the previous program to a page depending on when the FF reset is input.
The response to a “FFh” Reset command input during the various device operations is as follows:
When a Reset (FFh) command is input during programming
80
10
FF
00
Internal V
RY /BY
PP
t
(max 10 µs)
RST
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When a Reset (FFh) command is input during erasing
D0
FF
00
Internal erase
voltage
RY /BY
t
(max 500 µs)
RST
When a Reset (FFh) command is input during Read operation
00
30
FF
00
RY /BY
t
(max 6 µs)
RST
When a Reset (FFh) command is input during Ready
FF
00
RY /BY
t
(max 6 µs)
RST
When a Status Read command (70h) is input after a Reset
FF
70
I/O status: Pass/Fail → Pass
: Ready/Busy → Ready
RY /BY
When two or more Reset commands are input in succession
(1)
(2)
FF
(3)
FF
10
FF
RY /BY
The second
FF
command is invalid, but the third
FF
command is valid.
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APPLICATION NOTES AND COMMENTS
(1)
Power-on/off sequence:
The timing sequence shown in the figure below is necessary for the power-on/off sequence.
The device internal initialization starts after the power supply reaches an appropriate level in the power on
sequence. During the initialization the device Ready/Busy signal indicates the Busy state as shown in the
figure below. In this time period, the acceptable commands are FFh or 70h.
The WP signal is useful for protecting against data corruption at power-on/off.
1.7V
1.5V
V
CC
0 V
Don’t
care
Don’t
care
CE , WE , RE
CLE, ALE
V
IH
V
IL
V
IL
WP
1 ms max
Operation
100 µs max
Don’t
care
Invalid
Ready/Busy
(2)
Power-on Reset
The following sequence is necessary because some input signals may not be stable at power-on.
Power on
FF
Reset
(3)
(4)
Prohibition of unspecified commands
The operation commands are listed in Table 3. Input of a command other than those specified in Table 3 is
prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle.
Restriction of commands while in the Busy state
During the Busy state, do not input any command except 70h(71h) and FFh.
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(5)
Acceptable commands after Serial Input command “80h”
Once the Serial Input command “80h” has been input, do not input any command other than the Column
Address Change in Serial Data Input command “85h”, Auto Program command “10h”, Multi Page Program
command “11h”, Auto Program with Data Cache Command “15h”, or the Reset command “FFh”.
80
FF
WE
Address input
RY /BY
If a command other than “85h” , “10h” , “11h” , “15h” or “FFh” is input, the Program operation is not
performed and the device operation is set to the mode which the input command specifies.
80
XX
10
Mode specified by the command.
Programming cannot be executed.
Command other than
“85h”, “10h”, “11h”, “15h” or “FFh”
(6)
Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of
the block to MSB (most significant bit) page of the block. Random page address programming is prohibited.
From the LSB page to MSB page
Ex.) Random page program (Prohibition)
DATA IN: Data (1)
Data (64)
DATA IN: Data (1)
Data (64)
Data register
Data register
Page 0
Page 1
Page 2
Page 0
Page 1
Page 2
(1)
(2)
(3)
(2)
(32)
(3)
Page 31
Page 63
Page 31
Page 63
(32)
(64)
(1)
(64)
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(7)
Status Read during a Read operation
00
[A]
Command
CE
00
30
70
WE
RY/BY
RE
Address N
Status Read
command input
Status output
Status Read
.
The device status can be read out by inputting the Status Read command “70h” in Read mode. Once the
device has been set to Status Read mode by a “70h” command, the device will not return to Read mode
unless the Read command “00h” is inputted during [A]. If the Read command “00h” is inputted during [A],
Status Read mode is reset, and the device returns to Read mode. In this case, data output starts
automatically from address N and address input is unnecessary
(8)
Auto programming failure
Fail
80
80
10
10
70
I/O
80
10
Address Data
input
Address Data
input
M
N
If the programming result for page address M is Fail, do not try to program the
page to address N in another block without the data input sequence.
Because the previous input data has been lost, the same input sequence of 80h
command, address and data is necessary.
M
N
(9)
RY / BY : termination for the Ready/Busy pin ( RY / BY )
A pull-up resistor needs to be used for termination because the RY / BY buffer consists of an open drain
circuit.
V
CC
Ready
V
CC
V
CC
R
Busy
Device
RY /BY
t
r
C
L
t
f
V
= 1.8 V
CC
Ta = 25°C
= 30 pF
V
SS
1.5 µs
1.0 µs
0.5 µs
15 ns
10 ns
5 ns
C
L
t
f
t
r
t
f
t
r
This data may vary from device to device.
We recommend that you use this data as a
reference when selecting a resistor value.
0
1 KΩ
2 KΩ
3 KΩ
4 KΩ
R
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(10)
Note regarding the WP signal
The Erase and Program operations are automatically reset when WP goes Low. The operations are
enabled and disabled as follows:
Enable Programming
WE
DIN
WP
80
10
10
D0
D0
RY /BY
t
(100 ns MIN)
WW
Disable Programming
WE
DIN
80
WP
RY /BY
t
(100 ns MIN)
WW
Enable Erasing
WE
DIN
60
WP
RY /BY
t
(100 ns MIN)
WW
Disable Erasing
WE
DIN
60
WP
RY /BY
t
(100 ns MIN)
WW
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(11)
When five address cycles are input
Although the device may read in a fifth address, it is ignored inside the chip.
Read operation
CLE
CE
WE
ALE
I/O
00h
30h
Ignored
Address input
RY /BY
Program operation
CLE
CE
WE
ALE
I/O
80h
Ignored
Data input
Address input
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(12)
Several programming cycles on the same page (Partial Page Program)
Each segment can be programmed individually as follows:
1st programming
All 1 s
Data Pattern 1
All 1 s
2nd programming
All 1 s
Data Pattern 2
4th programming
Result
All 1 s
Data Pattern 4
Data Pattern 4
Data Pattern 1
Data Pattern 2
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(13)
Invalid blocks (bad blocks)
The device occasionally contains unusable blocks. Therefore, the following issues must be recognized:
Please do not perform an erase operation to bad blocks. It may be
impossible to recover the bad block information if the information is
erased.
Bad Block
Check if the device has any bad blocks after installation into the system.
Refer to the test flow for bad block detection. Bad blocks which are
detected by the test flow must be managed as unusable blocks by the
system.
A bad block does not affect the performance of good blocks because it is
isolated from the bit lines by select gates.
Bad Block
The number of valid blocks over the device lifetime is as follows:
MIN
TYP.
MAX
1024
UNIT
Block
Valid (Good) Block Number
1004
⎯
Bad Block Test Flow
Regarding invalid blocks, bad block mark is in either the 1st or the 2nd page.
Read Check :
Read either column 0 or 2048 of the 1st page or the
2nd page of each block. If the data of the column is not
FF (Hex), define the block as a bad block.
Start
Block No = 1
Fail
Read Check
Pass
Block No. = Block No. + 1
Bad Block *1
No
Last Block
Yes
End
*1:
No erase operation is allowed to detected bad blocks
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(14)
Failure phenomena for Program and Erase operations
The device may fail during a Program or Erase operation.
The following possible failure modes should be considered when implementing a highly reliable system.
FAILURE MODE
DETECTION AND COUNTERMEASURE SEQUENCE
Status Read after Erase → Block Replacement
Block
Page
Erase Failure
Programming Failure
Status Read after Program → Block Replacement
Programming Failure
“1 to 0”
Single Bit
ECC
•
•
ECC: Error Correction Code. 1 bit correction per 512 Bytes is necessary.
Block Replacement
Program
Error occurs
When an error happens in Block A, try to reprogram the
data into another Block (Block B) by loading from an
external buffer. Then, prevent further system accesses
to Block A ( by creating a bad block table or by using
another appropriate scheme).
Buffer
memory
Block A
Block B
Erase
When an error occurs during an Erase operation, prevent future accesses to this bad block
(again by creating a table within the system or by using another appropriate scheme).
(15)
(16)
Do not turn off the power before write/erase operation is complete. Avoid using the device when the battery
is low. Power shortage and/or power failure before write/erase operation is complete will cause loss of data
and/or damage to data.
The number of valid blocks is on the basis of single plane operations, and this may be decreased with two
plane operations.
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(17)
Reliability Guidance
This reliability guidance is intended to notify some guidance related to using NAND flash with
1 bit ECC for each 512 bytes. For detailed reliability data, please refer to TOSHIBA’s reliability note.
Although random bit errors may occur during use, it does not necessarily mean that a block is bad.
Generally, a block should be marked as bad when a program status failure or erase status failure is detected.
The other failure modes may be recovered by a block erase.
ECC treatment for read data is mandatory due to the following Data Retention and Read Disturb failures.
•
•
Write/Erase Endurance
Write/Erase endurance failures may occur in a cell, page, or block, and are detected by doing a status read
after either an auto program or auto block erase operation. The cumulative bad block count will increase
along with the number of write/erase cycles.
Data Retention
The data in memory may change after a certain amount of storage time. This is due to charge loss or charge
gain. After block erasure and reprogramming, the block may become usable again.
Here is the combined characteristics image of Write/Erase Endurance and Data Retention.
Data
Retention
[Years]
Write/Erase Endurance [Cycles]
•
Read Disturb
A read operation may disturb the data in memory. The data may change due to charge gain. Usually, bit
errors occur on other pages in the block, not the page being read. After a large number of read cycles
(between block erases), a tiny charge may build up and can cause a cell to be soft programmed to another
state. After block erasure and reprogramming, the block may become usable again.
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Package Dimensions
P-TFBGA63-0911-0.80CZ
Unit: mm
11.00
S B
0.20
INDEX
4
0.15
S
0.10
S
S
0.10
B
0.46 0.05
S AB
A B C D E F G H J K L M
0.08
1
2
3
4
A
5
6
7
8
9
10
0.80
0.40
1.10
Weight: 0.15 g (typ.)
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Revision History
Date
2009-07-01
2009-07-09
Rev.
1.00
1.10
Description
Original version based on TC58NVG0S3EBAJ5_E090629C.pdf
Changed part number and description of “RESTRICTIONS ON PRODUCT USE”.
Modified “FEATURES”.
Revised “APPLICATION NOTES AND COMMENTS ” (14).
Specified weight.
2009-07-15
2009-07-16
1.20
1.30
Corrected Device code.
tRST is changed.
Corrected output load.
Corrected typo.
2010-01-25
1.40
Deleted an invalid description at Page 30.
Deleted Confidential notation.
Changed “RESTRICTIONS ON PRODUCT USE”.
Corrected TIMING DIAGRAM of ID Read.
Changed package drawing.
Deleted TENTATIVE notation.
tR is changed.
2010-05-21
2010-06-22
2010-07-13
2011-03-01
1.50
1.60
1.70
1.80
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RESTRICTIONS ON PRODUCT USE
•
•
•
Toshiba Corporation, and its subsidiaries and affiliates (collectively “TOSHIBA”), reserve the right to make changes to the information
in this document, and related hardware, software and systems (collectively “Product”) without notice.
This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with
TOSHIBA’s written permission, reproduction is permissible only if reproduction is without alteration/omission.
Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are
responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and
systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily
injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the
Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of
all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes
for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the
instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their
own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such
design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts,
diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating
parameters for such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR
APPLICATIONS.
•
Product is intended for use in general electronics applications (e.g., computers, personal equipment, office equipment, measuring
equipment, industrial robots and home electronics appliances) or for specific applications as expressly stated in this document.
Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or
reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious
public impact (“Unintended Use”). Unintended Use includes, without limitation, equipment used in nuclear facilities, equipment used
in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling
equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric
power, and equipment used in finance-related fields. Do not use Product for Unintended Use unless specifically permitted in this
document.
•
•
Do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy Product, whether in whole or in part.
Product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any
applicable laws or regulations.
•
•
The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA for any
infringement of patents or any other intellectual property rights of third parties that may result from the use of Product. No license to
any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise.
ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF SALE
FOR PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA (1) ASSUMES NO LIABILITY
WHATSOEVER, INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES OR
LOSS, INCLUDING WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND
LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS RELATED TO
SALE, USE OF PRODUCT, OR INFORMATION, INCLUDING WARRANTIES OR CONDITIONS OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE, ACCURACY OF INFORMATION, OR NONINFRINGEMENT.
•
Do not use or otherwise make available Product or related software or technology for any military purposes, including without
limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile
technology products (mass destruction weapons). Product and related software and technology may be controlled under the
Japanese Foreign Exchange and Foreign Trade Law and the U.S. Export Administration Regulations. Export and re-export of Product
or related software or technology are strictly prohibited except in compliance with all applicable export laws and regulations.
•
•
Product is subject to foreign exchange and foreign trade control laws.
Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product.
Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances,
including without limitation, the EU RoHS Directive. TOSHIBA assumes no liability for damages or losses occurring as a result of
noncompliance with applicable laws and regulations.
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