TC59LM813AMG-55 [TOSHIBA]
IC,DRAM,FCRAM(DDR),4X8MX16,CMOS,BGA,60PIN,PLASTIC;
| 型号： | TC59LM813AMG-55 |
| 厂家： | 
TOSHIBA |
| 描述： | IC,DRAM,FCRAM(DDR),4X8MX16,CMOS,BGA,60PIN,PLASTIC 时钟 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总49页 (文件大小：382K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TC59LM913/05AMG-50,-55,-60
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
8,388,608-WORDS ´ 4 BANKS ´ 16-BITS DOUBLE DATA RATE FAST CYCLE RAM
16,777,216-WORDS ´ 4 BANKS ´ 8-BITS DOUBLE DATA RATE FAST CYCLE RAM
DESCRIPTION
TC59LM913/05AMG is a CMOS Double Data Rate Fast Cycle Random Access Memory (DDR-FCRAMTM
)
containing 536,870,912 memory cells. TC59LM913AMG is organized as 8,388,608-words ´ 4 banks ´ 16 bits,
TC59LM905AMG is organized as 16,777,216-words ´ 4 banks ´ 8 bits. TC59LM913/05AMG feature a fully
synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence. TC59LM913/05AMG can operate fast core cycle
compared with regular DDR SDRAM.
TC59LM913/05AMG is suitable for Server, Network and other applications where large memory density and low
power consumption are required. The Output Driver for FCRAMTM is capable of high quality fast data transfer
under light loading condition.
FEATURES
TC59LM913/05
PARAMETER
-50
5.5 ns
5.0 ns
25.0 ns
22.0 ns
TBD
-55
6.0 ns
5.5 ns
27.5 ns
24.0 ns
TBD
-60
6.5 ns
6.0 ns
30.0 ns
26.0 ns
TBD
CL = 3
CL = 4
t
Clock Cycle Time (min)
CK
t
t
Random Read/Write Cycle Time (min)
Random Access Time (max)
RC
RAC
I
Operating Current (single bank) (max)
Power Down Current (max)
DD1S
l
TBD
TBD
TBD
DD2P
l
Self-Refresh Current (max)
TBD
TBD
TBD
DD6
·
·
Fully Synchronous Operation
Double Data Rate (DDR)
·
·
Data input/output are synchronized with both edges of DQS.
Differential Clock (CLK and CLK ) inputs
CS , FN and all address input signals are sampled on the positive edge of CLK.
Output data (DQs and DQS) is aligned to the crossings of CLK and CLK .
Fast clock cycle time of 5 ns minimum
Clock: 200 MHz maximum
Data: 400 Mbps/pin maximum
Fast cycle and Short Latency
Distributed Auto-Refresh cycle in 7.8 ms
Self-Refresh
Power Down Mode
Variable Write Length Control
Write Latency = CAS Latency-1
Programable CAS Latency and Burst Length
CAS Latency = 3, 4
·
·
·
·
·
·
·
Burst Length = 2, 4
·
·
Organization: TC59LM813AMG : 8,388,608 words ´ 4 banks ´ 16 bits
TC59LM805AMG : 16,777,216 words ´ 4 banks ´ 8 bits
Power Supply Voltage
V
V
:
2.5 V ± 0.15V
DD
: 2.5 V ± 0.15 V
DDQ
·
·
2.5 V CMOS I/O comply with SSTL-2 (half strength driver)
Package: 60Ball BGA, 1mm ´ 1mm Ball pitch
Notice : FCRAM is trademark of Fujitsu Limited, Japan.
2002-05-16 1/49
TC59LM913/05AMG-50,-55,-60
TC59LM905AMG
PIN NAMES
PIN ASSIGNMENT (TOP VIEW)
ball pitch=1.0 x 1.0mm
PIN
NAME
Address Input
x8
A0~A14
BA0, BA1
DQ0~DQ7
CS
1
2
3
4
5
6
Bank Address
Data Input/Output
Chip Select
Index
A
B
V
DQ7
DQ0
V
DD
SS
FN
Function Control
Power Down Control
Clock Input
NC
DQ6
NC
V
Q
V Q
DD
NC
DQ1
NC
PD
SS
CLK, CLK
DQS
V
Q
V
Q
SS
C
D
DD
Write/Read Data Strobe
Power (+2.5 V)
Ground
DQ5
DQ2
V
V
DD
SS
NC
V
Q
V
Q
NC
E
F
G
H
J
SS
DD
Power (+2.5 V)
(for I/O buffer)
V
DDQ
DQ4
NC
V
Q
Q
V
Q
Q
DQ3
NC
Ground
(for I/O buffer)
V
V
SSQ
REF
V
V
DD
SS
Reference Voltage
Not Connected
NC
DQS
NC
NC
NC
VREF
CLK
A12
A11
A8
V
V
DD
A14
A13
NC
SS
CLK
FN
K
L
PD
A9
A7
A6
A4
CS
BA1
A0
BA0
A10
A1
M
N
A5
A2
P
R
V
A3
V
DD
SS
2002-05-16 2/49
TC59LM913/05AMG-50,-55,-60
TC59LM913AMG
PIN NAMES
PIN ASSIGNMENT (TOP VIEW)
ball pitch=1.0 x 1.0mm
PIN
NAME
Address Input
X16
A0~A14
BA0, BA1
DQ0~DQ15
CS
1
2
3
4
5
6
Bank Address
Data Input/Output
Chip Select
Index
A
B
V
DQ15
DQ0
V
DD
SS
FN
Function Control
Power Down Control
Clock Input
DQ14
DQ13
V
V
Q
Q
V Q
DD
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
NC
PD
SS
CLK, CLK
UDQS / LDQS
V
Q
SS
C
D
DD
Write/Read Data Strobe
Power (+2.5 V)
Ground
DQ12 DQ11
DQ4
V
V
DD
SS
DQ10
DQ9
DQ8
NC
V
V
Q
Q
Q
V
Q
E
F
G
H
J
SS
DD
Power (+2.5 V)
(for I/O buffer)
V
DDQ
V
Q
Q
Ground
(for I/O buffer)
V
V
SSQ
REF
V
V
DD
SS
Reference Voltage
Not Connected
UDQS
LDQS
NC
VREF
CLK
A12
A11
A8
V
V
DD
A14
A13
NC
SS
CLK
FN
K
L
PD
A9
A7
A6
A4
CS
BA1
BA0
A10
A1
M
N
A0
A2
A3
A5
P
R
V
V
DD
SS
2002-05-16 3/49
TC59LM913/05AMG-50,-55,-60
BLOCK DIAGRAM
CLK
CLK
PD
DLL
CLOCK
To each block
BUFFER
CONTROL
SIGNAL
GENERATOR
CS
FN
COMMAND
DECODER
BANK #3
BANK #2
BANK #1
BANK #0
MODE
REGISTER
MEMORY
A0~A14
CELL ARRAY
ADDRESS
BUFFER
UPPER ADDRESS
LATCH
BA0, BA1
LOWER ADDRESS
LATCH
COLUMN DECODER
READ
DATA
WRITE
DATA
WRITE ADDRESS
REFRESH
COUNTER
LATCH/
ADDRESS
BUFFER
BUFFER
COMPARATOR
BURST
COUNTER
DQS
DQ BUFFER
DQ0~DQn
Note: The TC59LM905AMG configuration is 4 Bank of 32768 ´ 512 ´ 8 of cell array with the DQ pins numbered DQ0~DQ7.
The TC59LM913AMG configuration is 4 Bank of 32768 ´ 256 ´ 16 of cell array with the DQ pins numbered DQ0~DQ15.
2002-05-16 4/49
TC59LM913/05AMG-50,-55,-60
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
Power Supply Voltage
RATING
UNIT
NOTES
V
V
V
V
V
- 0.3~ 3.3
V
V
DD
Power Supply Voltage (for I/O buffer)
Input Voltage
- 0.3~V + 0.3
DD
DDQ
IN
- 0.3~V + 0.3
V
DD
Output and I/O pin Voltage
Input Reference Voltage
Operating Temperature
Storage Temperature
- 0.3~V
+ 0.3
DDQ
V
OUT
REF
- 0.3~V + 0.3
V
DD
T
opr
0~70
- 55~150
260
°C
°C
°C
W
mA
T
stg
T
solder
Soldering Temperature (10 s)
Power Dissipation
P
D
2
I
Short Circuit Output Current
±50
OUT
Caution: Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device.
The device is not meant to be operated under conditions outside the limits described in the operational section of this
specification.
Exposure to “ABSOLUTE MAXIMUM RATINGS” conditions for extended periods may affect device reliability.
RECOMMENDED DC, AC OPERATING CONDITIONS (Notes: 1)(Ta= 0~70°C)
SYMBOL
PARAMETER
Power Supply Voltage
MIN
TYP.
2.5
MAX
2.65
UNIT NOTES
V
V
V
V
V
V
2.35
2.35
V
V
DD
Power Supply Voltage (for I/O buffer)
Input Reference Voltage
V
V
DD
DDQ
REF
DD
V
/2 ´ 96%
DDQ
V
/2
DDQ
V /2 ´ 104%
DDQ
V
V
V
V
2
5
(DC)
Input DC High Voltage
V
+ 0.2
¾
V
V
V
+ 0.2
- 0.2
+ 0.1
IH
IL
REF
DDQ
REF
(DC)
(DC)
Input DC Low Voltage
- 0.1
¾
¾
5
Differential Clock DC Input Voltage
- 0.1
10
ICK
DDQ
Input Differential Voltage.
CLK and CLK inputs (DC)
V
(DC)
0.4
¾
V
V
+ 0.2
+ 0.2
V
7, 10
ID
DDQ
DDQ
V
V
(AC)
Input AC High Voltage
Input AC Low Voltage
V
+ 0.35
REF
¾
¾
V
V
3, 6
4, 6
IH
IL
(AC)
(AC)
- 0.1
V
- 0.35
REF
Input Differential Voltage.
CLK and CLK inputs (AC)
V
0.7
¾
V
+ 0.2
DDQ
V
7, 10
ID
V (AC)
Differential ACInput Cross Point Voltage
Differential Clock AC Middle Level
V
/2 - 0.2
¾
¾
V
/2 + 0.2
/2 + 0.2
V
V
8, 10
9, 10
X
DDQ
DDQ
V
(AC)
V
/2 - 0.2
DDQ
V
ISO
DDQ
2002-05-16 5/49
TC59LM913/05AMG-50,-55,-60
Note:
(1) All voltages referenced to V , V
SS SSQ
.
(2) V
is expected to track variations in V
DC level of the transmitting device.
REF
Peak to peak AC noise on V
DDQ
may not exceed ±2% V
(DC).
REF
REF
(3) Overshoot limit: V
= V
+ 0.9 V with a pulse width £ 5 ns.
IH (max)
DDQ
= - 0.9 V with a pulse width £ 5 ns.
(4) Undershoot limit: V
IL (min)
(5) V (DC) and V (DC) are levels to maintain the current logic state.
IH IL
(6) V (AC) and V (AC) are levels to change to the new logic state.
IH IL
(7) V is magnitude of the difference between CLK input level and CLK input level.
ID
(8) The value of V (AC) is expected to equal V
/2 of the transmitting device.
X
DDQ
(9) V
means {V
(CLK) + V
ICK ICK
(CLK )} /2
ISO
(10) Refer to the figure below.
CLK
V
V
V
V
V
V (AC)
ID
x
x
x
x
x
CLK
V
V
V
V
ICK
ICK
ICK
ICK
V
SS
|V (AC)|
ID
0 V Differential
V
ISO
V
V
ISO (max)
ISO (min)
V
SS
(11) In the case of external termination, VTT (termination voltage) should be gone in the range of V
0.04 V.
(DC) ±
REF
CAPACITANCE (V = 2.5V, V
= 2.5 V, f = 1 MHz, Ta = 25°C)
DD
DDQ
SYMBOL
PARAMETER
MIN
MAX
Delta
UNIT
C
Input pin Capacitance
TBD
TBD
TBD
¾
TBD
TBD
TBD
TBD
TBD
TBD
TBD
¾
pF
pF
pF
pF
IN
C
INC
Clock pin (CLK, CLK ) Capacitance
DQ, DQS, UDQS, LDQS Capacitance
NC pin Capacitance
C
I/O
C
NC
Note: These parameters are periodically sampled and not 100% tested.
2002-05-16 6/49
TC59LM913/05AMG-50,-55,-60
RECOMMENDED DC OPERATING CONDITIONS
(V =2.5V ± 0.15V, V
=2.5V ± 0.15V, Ta = 0~70°C)
DDQ
DD
MAX
SYMBOL
PARAMETER
UNIT
NOTES
1, 2
-50
-55
-60
Operating Current
= min; I = min,
t
CK
RC
Read/Write command cycling,
0 V £ V £ V (AC) (max), V (AC) (min) £ V £ V ,
DDQ
I
TBD
TBD
TBD
DD1S
IN
IL
IH
IN
1 bank operation, Burst length = 4,
Address change up to 2 times during minimum I
.
RC
Standby Current
= min, CS = V , PD = V ,
IH
t
CK
IH
I
0 V £ V £ V (AC) (max), V (AC) (min) £ V £ V ,
TBD
TBD
TBD
TBD
TBD
TBD
1
1
1
DD2N
IN
IL
IH
IN
DDQ
All banks: inactive state,
Other input signals are changed one time during 4 ´ t
.
CK
mA
Standby (power down) Current
t
= min, CS = V , PD = V (power down),
CK
IH
IL
I
DD2P
0 V £ V £ V
,
IN
DDQ
All banks: inactive state
Auto-Refresh Current
t
= min; I
= min, t = min,
REFI
CK
REFC
I
Auto-Refresh command cycling,
0 V £ V £ V (AC) (max), V (AC) (min) £ V £ V ,
DDQ
TBD
TBD
TBD
TBD
TBD
TBD
DD5
IN
IL
IH
IN
REFC
Address change up to 2 times during minimum I
.
Self-Refresh Current
Self-Refresh mode
I
DD6
PD = 0.2 V, 0 V £ V £ V
IN
DDQ
SYMBOL
PARAMETER
MIN
MAX
5
UNIT
NOTES
Input Leakage Current
I
LI
- 5
mA
( 0 V£ V £ V
, all other pins not under test = 0 V)
IN
DDQ
Output Leakage Current
(Output disabled, 0 V £ V
I
- 5
- 5
5
5
mA
mA
LO
£ V
)
DDQ
OUT
I
V
Current
REF
REF
Output Source DC Current
= V - 0.4V
I
(DC)
(DC)
(DC)
(DC)
(DC)
(DC)
(DC)
(DC)
- 10
¾
3
3
3
3
3
3
3
3
OH
V
OH
DDQ
Normal
Output Driver
Output Sink DC Current
= 0.4V
I
OL
10
- 11
11
- 8
8
¾
¾
¾
¾
¾
¾
¾
V
OL
Output Source DC Current
= V - 0.4V
I
OH
V
OH
DDQ
Strong Output
Driver
Output Sink DC Current
= 0.4V
I
OL
V
OL
mA
Output Source DC Current
= V - 0.4V
I
OH
V
OH
DDQ
Weaker
Output Driver
Output Sink DC Current
= 0.4V
I
OL
V
OL
Output Source DC Current
= V - 0.4V
I
- 7
7
OH
V
OH
DDQ
Weakest
Output Driver
Output Sink DC Current
= 0.4V
I
OL
V
OL
Notes: 1. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of
, t and I
t
.
RC
CK RC
2. These parameters depend on the output loading. The specified values are obtained with the output open.
3. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Register.
2002-05-16 7/49
TC59LM913/05AMG-50,-55,-60
AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2)
-50
-55
-60
SYMBOL
PARAMETER
Random Cycle Time
UNIT NOTES
MIN
25
MAX
¾
MIN
27.5
6.0
MAX
¾
MIN
30
MAX
¾
t
t
3
3
3
RC
CK
C = 3
5.5
5.0
8.5
8.5
12.0
12.0
6.5
6.0
12.0
12.0
L
Clock Cycle Time
C = 4
L
5.5
t
t
t
t
t
t
t
Random Access Time
Clock High Time
¾
22.0
¾
¾
24.0
¾
¾
26.0
¾
3
3
RAC
0.45 ´ t
0.45 ´ t
0.45 ´ t
0.45 ´ t
0.45 ´ t
0.45 ´ t
CH
CK
CK
CK
Clock Low Time
¾
¾
¾
3
CL
CK
CK
CK
QS Access Time from CLK
Data Output Skew from QS
Data Access Time from CLK
Data Output Hold Time from CLK
- 0.65
¾
0.65
0.4
0.65
0.65
- 0.75
¾
0.75
0.45
0.75
0.75
- 0.85
¾
0.85
0.55
0.85
0.85
3, 8
4
CKQS
QSQ
AC
- 0.65
- 0.65
- 0.75
- 0.75
- 0.85
- 0.85
3, 8
3, 8
OH
0.9 ´ t
- 0.2
1.1 ´ t
+ 0.2
0.9 ´ t
- 0.2
1.1 ´ t
+ 0.2
0.9 ´ t
1.1 ´ t
+ 0.2
CK
CK
CK
CK
CK CK
t
t
t
t
QS (read) Preamble Pulse Width
3, 8
3
QSPRE
- 0.2
min(t
CH
CLK half period (minimum of
min(t
,
min(t
,
,
CH
)
CH
)
¾
¾
¾
HP
Actual t
,
t )
CL
t
t
t )
CL
CH
CL
CL
t
t
-
t
t
-
t
t
-
HP
QHS
HP
QHS
HP
QHS
QS (read) Pulse Width
¾
¾
¾
4, 8
QSP
t
t
-
t
t
-
t -
HP
HP
HP
Data Output Valid Time from QS
DQ, QS Hold Skew factor
¾
¾
¾
4, 8
ns
QSQV
t
QHS
QHS
QHS
t
t
t
t
t
t
¾
0.55
¾
0.6
¾
0.65
QHS
DS (write) Low to High Setup Time 0.75 ´ t
1.25 ´ t
0.75 ´ t
1.25 ´ t
0.75 ´ t
1.25 ´ t
3
4
3
3
4
DQSS
CK
CK
CK
CK
CK
CK
DS (write) Preamble Pulse Width
DS First Input Setup Time
0.4 ´ t
¾
¾
0.4 ´ t
¾
¾
0.4 ´ t
¾
¾
DSPRE
DSPRES
DSPREH
DSP
CK
CK
CK
0
0
0
DS First Low Input Hold Time
0.25 ´ t
¾
0.25 ´ t
¾
0.25 ´ t
¾
CK
CK
CK
CK
CK
DS High or Low Input Pulse Width 0.45 ´ t
0.55 ´ t
0.45 ´ t
0.55 ´ t
0.45 ´ t
0.55 ´ t
CK
CK
CK
CK
C = 3
1.3
1.3
¾
¾
1.4
1.4
¾
¾
1.5
1.5
¾
¾
3, 4
3, 4
L
DS Input Falling Edge
to Clock Setup Time
t
DSS
C = 4
L
t
t
DS (write) Postamble Pulse Width
0.45 ´ t
1.3
¾
¾
¾
¾
¾
0.45 ´ t
1.4
¾
¾
¾
¾
¾
0.45 ´ t
1.5
¾
¾
¾
¾
¾
4
3, 4
3, 4
4
DSPST
CK
CK
CK
C = 3
L
DS (write) Postamble
Hold Time
DSPSTH
C = 4
L
1.3
1.4
1.5
t
t
Data Input Setup Time from DS
Data Input Hold Time from DS
0.5
0.5
0.6
DS
0.5
0.5
0.6
4
DH
Command/Address Input Setup
Time
t
0.9
0.9
¾
¾
0.9
0.9
¾
¾
1.0
1.0
¾
¾
3
3
IS
IH
Command/Address Input Hold
Time
t
2002-05-16 8/49
TC59LM913/05AMG-50,-55,-60
AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2) (continued)
-50
-55
-60
SYMBOL
PARAMETER
UNIT NOTES
3,6,8
MIN
MAX
MIN
MAX
MIN
MAX
Data-out Low Impedance Time
from CLK
t
LZ
- 0.65
¾
- 0.75
¾
- 0.85
¾
Data-out High Impedance Time
from CLK
t
t
¾
0.65
¾
0.75
¾
0.85
3,7,8
3,6,8
HZ
QS-out Low Impedance Time from
CLK
- 0.65
¾
- 0.75
¾
- 0.85
¾
QSLZ
QS-out High Impedance Time from
CLK
t
t
- 0.65
0.65
- 0.75
0.75
- 0.85
0.85
3,7,8
QSHZ
QPDH
Last output to PD High Hold
Time
0
¾
0
¾
0
¾
ns
t
t
Power Down Exit Time
Input Transition Time
0.9
0.1
¾
0.9
0.1
¾
1.0
0.1
¾
3
PDEX
1
1
1
T
PD Low Input Window for
Self-Refresh Entry
t
- 0.5 ´ t
5
- 0.5 ´ t
5
- 0.5 ´ t
CK
5
3
FPDL
CK
CK
t
t
Auto-Refresh Average Interval
Pause Time after Power-up
0.4
7.8
0.4
7.8
0.4
7.8
5
REFI
ms
200
¾
200
¾
200
¾
PAUSE
C = 3
5
5
¾
¾
5
5
¾
¾
5
5
¾
¾
Random Read/Write
Cycle Time
(applicable to same bank)
L
I
RC
C = 4
L
RDA/WRA to LAL Command Input
Delay
I
1
1
1
1
1
1
RCD
(applicable to same bank)
C = 3
4
4
¾
¾
4
4
¾
¾
4
4
¾
¾
LAL to RDA/WRA
Command Input Delay
(applicable to same bank)
L
I
RAS
C = 4
L
Random Bank Access Delay
(applicable to other bank)
I
2
¾
2
¾
2
¾
RBD
B = 2
2
3
¾
¾
2
3
¾
¾
2
3
¾
¾
LAL following RDA to
WRA Delay
(applicable to other bank)
L
I
RWD
B = 4
L
LAL following WRA to RDA Delay
(applicable to other bank)
I
1
¾
1
¾
1
¾
WRD
cycle
C = 3
5
5
¾
¾
5
5
¾
¾
5
5
¾
¾
L
Mode Register Set Cycle
Time
I
RSC
C = 4
L
PD Low to Inactive State of Input
Buffer
I
¾
¾
1
1
¾
¾
1
1
¾
¾
1
1
PD
PD High to Active State of Input
Buffer
I
PDA
C = 3
15
18
15
18
¾
¾
¾
¾
15
18
15
18
¾
¾
¾
¾
15
18
15
18
¾
¾
¾
¾
L
Power down mode valid
from REF command
I
PDV
C = 4
L
C = 3
L
I
Auto-Refresh Cycle Time
REFC
C = 4
L
REF Command to Clock Input
Disable at Self-Refresh Entry
I
16
¾
¾
16
¾
¾
16
¾
¾
CKD
DLL Lock-on Time (applicable to
RDA command)
I
200
200
200
LOCK
2002-05-16 9/49
TC59LM913/05AMG-50,-55,-60
AC TEST CONDITIONS
SYMBOL
PARAMETER
Input High Voltage (minimum)
VALUE
UNIT
NOTES
V
V
V
V
V
V
V
+ 0.35
V
V
IH (min)
IL (max)
REF
REF
REF
Input Low Voltage (maximum)
Input Reference Voltage
- 0.35
/2
V
V
DDQ
Termination Voltage
V
V
TT
REF
Input Signal Peak to Peak Swing
Differential Clock Input Reference Level
Input Differential Voltage
1.0
V
SWING
Vr
V (AC)
X
V
V
(AC)
1.5
1.0
V
ID
SLEW
Input Signal Minimum Slew Rate
Output Timing Measurement Reference Voltage
V/ns
V
V
V
/2
DDQ
9
OTR
V
DDQ
V
TT
R =50 W
T
V
V
(AC)
(AC)
Measurement point
IH min
REF
V
SWING
Output
Z = 50 W
V
IL max
V
REF
CL=30pF
V
SS
DT
DT
(AC))/DT
AC Test Load
SLEW = (V
(AC) - V
IL max
IH min
Note:
(1)
Transition times are measured between V
(DC) and V
(DC).
IL max
IH min
Transition (rise and fall) of input signals have a fixed slope.
(2)
If the result of nominal calculation with regard to t
rounded up to the nearest decimal place.
contains more than one decimal place, the result is
CK
(i.e., t
= 0.75 ´ t , t = 5 ns, 0.75 ´ 5 ns = 3.75 ns is rounded up to 3.8 ns.)
CK CK
DQSS
(3)
(4)
(5)
There parameters are measured from the differential clock (CLK and CLK ) AC cross point.
These parameters are measured from signal transition point of DS crossing V level.
REF
The t
The t
applies to equally distributed refresh method.
applies to both burst refresh method and distributed refresh method.
REFI (max)
REFI (min)
In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400 ns
always. In other words, the number of Auto-Refresh cycles which can be performed within 3.2 ms (8 ´ 400 ns)
is to 8 times in the maximum.
(6)
(7)
(8)
(9)
Low Impedance State is specified at V
/2 ± 0.2 V from steady state.
DDQ
High Impedance State is specified where output buffer is no longer driven.
These parameters depend on the clock jitter. These parameters are measured at stable clock.
Output timing is measured by using Normal driver strength.
2002-05-16 10/49
TC59LM913/05AMG-50,-55,-60
POWER UP SEQUENCE
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
As for PD , being maintained by the low state (£ 0.2 V ) is desirable before a power-supply injection.
Apply V
Apply V
before or at the same time as V
.
DD
DDQ
before or at the same time as V
.
REF
DDQ
Start clock (CLK, CLK ) and maintain stable condition for 200 ms (min).
After stable power and clock, apply DESL and take PD =H.
Issue EMRS to enable DLL and to define driver strength. (Note: 1)
Issue MRS for set CAS latency (CL), Burst Type (BT), and Burst Length (BL). (Note: 1)
Issue two or more Auto-Refresh commands (Note: 1).
Ready for normal operation after 200 clocks from Extended Mode Register programming.
Notes:
(1)
Sequence 6, 7 and 8 can be issued in random order.
(2)
L = Logic Low, H = Logic High
2.5V(TYP)
2.5V(TYP)
V
DD
V
DDQ
1.25V(TYP)
V
REF
CLK
CLK
t
PDEX
l
l
l
l
l
REFC
200us(min)
PDA
RSC
RSC
REFC
PD
Command
Address
200clock cycle(min)
DESL RDA MRS DESL RDA MRS
DESL WRAREF DESL
WRAREF DESL
op-code
EMRS
op-code
MRS
DQ
Hi-Z
DQS
EMRS
MRS
Auto Refresh cycle
Normal Operation
2002-05-16 11/49
TC59LM913/05AMG-50,-55,-60
TIMING DIAGRAMS
Input Timing
Command and Address
t
CK
t
t
t
CL
CK
CH
CLK
CLK
t
IS
t
IS
t
IS
t
t
t
t
IS
t
IS
t
IS
t
IH
t
IH
t
IH
IH
IH
IH
1st
1st
2nd
CS
FN
2nd
LA
A0~A14
UA, BA
BA0, BA1
Data
DQS
t
t
t
t
DS DH
DS DH
DQ (input)
Refer to the Command Truth Table.
Timing of the CLK, CLK
t
t
CL
CH
V
V
CLK
IH
IH
(AC)
(AC)
V
V
IL
IL
CLK
t
T
t
T
t
CK
CLK
CLK
V
V
IH
IL
V
(AC)
ID
V
V
V
X
X
X
2002-05-16 12/49
TC59LM913/05AMG-50,-55,-60
=
Read Timing (Burst Length 4)
t
t
t
CK
CH
CL
CLK
CLK
t
t
IS IH
LAL (after RDA )
Input
(control &
DESL
addresses)
t
IPW
t
t
CKQS
CKQS
t
QSLZ
t
t
t
t
t
CKQS QSP QSP
QSHZ
CAS latency = 3
t
QSPRE
DQS
(output)
Hi-Z
Preamble
Postamble
t
t
LZ
t
QSQV
QSQ
t
t
t
QSQ QSQ QSQV
HZ
DQ
(output)
Hi-Z
Q0
Q1
Q2
Q3
t
t
t
OH
t
t
AC
AC
AC
CKQS
t
CKQS
t
QSLZ
t
CKQS
t
t
t
QSHZ
QSP QSP
t
CAS latency = 4
QSPRE
DQS
(output)
Hi-Z
Hi-Z
Preamble
t
Postamble
t
t
LZ
QSQV
QSQ
t
t
t
t
HZ
QSQ QSQ QSQV
DQ
Q0
Q1
Q2
Q3
(output)
t
t
t
OH
AC
t
AC
AC
Note: DQ0 to DQ15 are aligned with DQS or LDQS/UDQS.
The correspondence of LDQS, UDQS to DQ. (TC59LM913AMG)
LDQS
UDQS
DQ0~DQ7
DQ8~DQ15
2002-05-16 13/49
TC59LM913/05AMG-50,-55,-60
Write Timing (Burst Length = 4)
t
t
t
CK
CH
CL
CLK
CLK
t
t
IS IH
LAL (after WRA)
Input
(control &
DESL
addresses)
t
IPW
t
DSPSTH
t
DQSS
t
DSS
t
DSPRES
t
t
t t
DSP DSP DSPST
DSP
t
DSPREH
CAS latency = 3
DQS
(input)
t
Preamble
DSS
Postamble
t
DSPRE
t
t
t
DS
DS
DS
t
t
t
DH
DIPW
t
DH
DH
DQ
(input)
D0
D1
D2
D3
t
DQSS
t
t
DSS
t
DSPSTH
DSS
t
DSPRES
t
t t t
DSP DSP DSPST
CAS latency = 4
DSP
t
DSPREH
DQS
(input)
Preamble
Postamble
t
DSPRE
t
t
t
DS
DS
DS
t
t
t
t
DH
DIPW
DH
DH
DQ
(input)
D0
D1
D2
D3
t
t
DQSS
DQSS
Note: DQ0 to DQ15 are sampled at both edges of DQS or LDQS / UDQS.
The correspondence of LDQS, UDQS to DQ. (TC59LM913AMG)
LDQS
UDQS
DQ0~DQ7
DQ8~DQ15
2002-05-16 14/49
TC59LM913/05AMG-50,-55,-60
t
, t
, Ixxxx Timing
REFI PAUSE
CLK
CLK
t
, t
, I
REFI PAUSE XXXX
t
t
t
t
IS IH
IS IH
Input
(control &
addresses )
Command
Note: “I ” means “I ”, “I
Command
”, “I ”, etc.
RAS
XXXX
RC
RCD
2002-05-16 15/49
TC59LM913/05AMG-50,-55,-60
Write Timing (x16 device) (Burst Length =4)
CLK
CLK
Input
(control &
WRA
LAL
(DESL)
addresses )
t
t
t
t
DSSK DSSK DSSK DSSK
CAS latency = 3
LDQS
Preamble
Postamble
t
t
DS
t
t
DS
DS
DS
t
t
DH
t
DH
t
DH
DH
DQ0~DQ7
UDQS
D0
D1
D2
D3
Preamble
Postamble
t
t
t
t
DS
DS
DS
DS
t
t
t
t
DH
DH
DH
DH
D0
D1
D2
D3
DQ8~DQ15
t
t
t
t
DSSK DSSK DSSK DSSK
CAS latency = 4
LDQS
Preamble
t
Postamble
t
t
t
t
DS
DS
DS
DS
t
t
t
DH
DH
DH
DH
DQ0~DQ7
UDQS
D0
D1
D2
D3
Preamble
Postamble
t
t
t
t
DS
DS
DS
DS
t
t
t
DH
DH
DH
D0
D1
D2
D3
DQ8~DQ15
2002-05-16 16/49
TC59LM913/05AMG-50,-55,-60
FUNCTION TRUTH TABLE (Notes: 1, 2, 3)
Command Truth Table (Notes: 4)
· The First Command
SYMBOL
FUNCTION
Device Deselect
CS
FN
BA1~BA0
A14~A9
A8
A7
A6~A0
DESL
RDA
H
L
L
´
´
´
´
´
´
Read with Auto-close
Write withAuto-close
H
L
BA
BA
UA
UA
UA
UA
UA
UA
UA
UA
WRA
· The Second Command (The next clock of RDA or WRA command)
BA1~
BA0
A14,
A13
A12~
A11
SYMBOL
FUNCTION
CS
FN
A10~A 9
A8
A7
A6~A0
LAL
LAL
REF
MRS
Lower Address Latch (x16)
Lower Address Latch (x8)
Auto-Refresh
H
H
L
´
´
´
´
´
´
V
V
´
V
´
´
´
LA
´
LA
LA
´
LA
LA
´
´
´
´
´
Mode Register Set
L
V
L
L
L
L
V
V
Notes: 1. L = Logic Low, H = Logic High, ´ = either L or H, V = Valid (specified value), BA = Bank Address, UA = Upper Address,
LA = Lower Address
2. All commands are assumed to issue at a valid state.
3. All inputs for command (excluding SELFX and PDEX) are latched on the crossing point of differential clock input where
CLK goes to High.
4. Operation mode is decided by the combination of 1st command and 2nd command. Refer to “STATE DIAGRAM” and
the command table below.
Read Command Table
COMMAND (SYMBOL)
CS
FN
BA1~BA0 A14~A9
A8
A7
A6~A0
NOTES
5
RDA (1st)
LAL (2nd)
L
H
BA
UA
UA
LA
UA
LA
UA
LA
H
´
´
´
Note 5 : For x16 device, A 8 is “X” (either L or H).
Write Command Table
·
TC59LM913AMG
BA1~
BA0
A10~
A9
COMMAND(SYMBOL)
CS
FN
A14
UA
A13
A12
UA
A11
A8
A7
A6~A0
WRA (1st)
LAL (2nd)
L
L
BA
UA
UA
UA
UA
UA
LA
UA
LA
H
´
´
LVW0 LVW1 UVW0 UVW1
´
´
·
TC59LM905AMG
BA1~
BA0
A10~
A9
COMMAND(SYMBOL)
CS
FN
A14
A13
A12
A11
A8
A7
A6~A0
WRA (1st)
LAL (2nd)
L
L
BA
UA
UA
UA
UA
UA
UA
LA
UA
LA
UA
LA
H
´
´
VW0
VW1
´
´
´
Notes: 6. A14 and A11 are used for Variable Write Length (VW) control at Write Operation.
2002-05-16 17/49
TC59LM913/05AMG-50,-55,-60
FUNCTION TRUTH TABLE (continued)
VW Truth Table
Burst Length
Function
Write All Words
VW0
VW1
L
´
BL=2
Write First One Word
Reserved
H
L
´
L
L
H
H
Write All Words
H
L
BL=4
Write First Two Words
Write First One Word
H
Note 7 : For x16 device, LVW0 and LVW1 control DQ0~DQ7.
UVW0 and UVW1 control DQ8~DQ15.
Mode Register Set Command Table
COMMAND (SYMBOL)
CS
FN
BA1~BA0 A14~A9
A8
A7
A6~A0
NOTES
8
RDA (1st)
L
L
H
´
´
´
´
´
MRS (2nd)
´
V
L
L
V
V
Notes: 8. Refer to “MODE REGISTER TABLE”.
Auto-Refresh Command Table
PD
n - 1
COMMAND CURRENT
FUNCTION
CS
FN BA1~BA0 A14~A9 A8 A7 A6~A0 NOTES
(SYMBOL)
STATE
n
Active
WRA (1st)
REF (2nd)
Standby
Active
H
H
H
H
L
L
L
´
´
´
´
´
´
´
´
´
´
Auto-Refresh
´
Self-Refresh Command Table
PD
COMMAND CURRENT
FUNCTION
CS
FN BA1~BA0 A14~A9 A8 A7 A6~A0 NOTES
(SYMBOL)
STATE
n - 1
H
n
Active
WRA (1st)
REF (2nd)
¾
Standby
Active
H
L
L
L
´
L
´
´
´
´
´
´
´
´
´
´
´
´
´
´
´
´
´
´
´
´
´
Self-Refresh Entry
Self-Refresh Continue
Self-Refresh Exit
H
9, 10
11
Self-Refresh
Self-Refresh
L
L
´
SELFX
L
H
H
´
Power Down Table
PD
COMMAND CURRENT
FUNCTION
CS
FN BA1~BA0 A14~A9 A8 A7 A6~A0 NOTES
(SYMBOL)
STATE
n - 1
n
L
L
H
Power Down Entry
Power Down Continue
Power Down Exit
PDEN
¾
Standby
H
L
L
H
´
´
´
´
´
´
´
´
´
´
´
´
´
´
´
´
´
´
´
10
11
Power Down
Power Down
PDEX
H
Notes: 9. PD has to be brought to Low within t
from REF command.
FPDL
10. PD should be brought to Low after DQ’s state turned high impedance.
11. When PD is brought to High from Low, this function is executed asynchronously.
2002-05-16 18/49
TC59LM913/05AMG-50,-55,-60
FUNCTION TRUTH TABLE (continued)
PD
CURRENT STATE
CS
FN
ADDRESS COMMAND
ACTION
NOTES
12
n - 1
n
H
H
H
H
H
L
H
H
H
L
L
´
H
L
L
H
L
´
´
´
DESL
RDA
WRA
PDEN
¾
NOP
H
L
´
BA, UA
BA, UA
Row activate for Read
Row activate for Write
Power Down Entry
Illegal
Idle
´
´
´
´
´
¾
Refer to Power Down State
H
H
H
H
L
H
H
L
L
´
H
L
H
L
´
´
´
´
´
´
´
´
´
´
´
LA
LAL
Begin Read
Op-code
MRS/EMRS Access to Mode Register
PDEN Illegal
MRS/EMRS Illegal
Row Active for Read
Row Active for Write
´
´
´
¾
Invalid
H
H
H
H
L
H
H
L
L
´
H
L
H
L
´
LA
´
LAL
REF
PDEN
Begin Write
Auto-Refresh
Illegal
´
´
REF (self) Self-Refresh Entry
´
¾
Invalid
H
H
H
H
H
L
H
H
H
L
L
´
H
L
L
H
L
´
´
´
DESL
RDA
WRA
PDEN
¾
Continue Burst Read to End
H
L
´
BA, UA
Illegal
Illegal
Illegal
Illegal
Invalid
13
13
BA, UA
Read
´
´
´
´
´
¾
Data Write & Continue Burst Write to
End
H
H
H
´
´
DESL
H
H
H
H
L
H
H
L
L
´
L
L
H
L
´
H
L
´
BA, UA
RDA
WRA
PDEN
¾
Illegal
Illegal
Illegal
Illegal
Invalid
13
13
BA, UA
Write
´
´
´
´
´
¾
H
H
H
H
H
L
H
H
H
L
L
´
H
L
L
H
L
´
´
´
DESL
RDA
WRA
PDEN
¾
NOP ® Idle after I
Illegal
REFC
H
L
´
BA, UA
BA, UA
Illegal
Auto-Refreshing
´
´
´
Self-Refresh Entry
Illegal
14
´
´
¾
Refer to Self -Refreshing State
NOP ® Idle after I
H
H
H
H
H
L
H
H
H
L
L
´
H
L
L
H
L
´
´
´
DESL
RDA
WRA
PDEN
¾
RSC
H
L
´
BA, UA
Illegal
Illegal
Illegal
Illegal
Invalid
BA, UA
Mode Register
Accessing
´
´
´
´
´
¾
H
L
´
´
´
´
´
´
´
¾
¾
Invalid
L
Maintain Power Down Mode
Power Down
Exit Power Down Mode ® Idle after
L
H
H
´
´
PDEX
t
PDEX
L
H
L
L
L
H
´
L
´
´
´
´
´
´
´
´
´
´
´
¾
¾
Illegal
Invalid
L
H
H
´
¾
Maintain Self-Refresh
Exit Self-Refresh ® Idle after I
Illegal
Self-Refreshing
H
L
SELFX
¾
REFC
Notes: 12. Illegal if any bank is not idle.
13. Illegal to bank in specified states; Function may be legal in the bank inidicated by Bank Address (BA).
14. Illegal if t is not satisfied.
FPDL
2002-05-16 19/49
TC59LM913/05AMG-50,-55,-60
MODE REGISTER TABLE
Regular Mode Register (Notes: 1)
*1
*1
*3
ADDRESS
Register
BA1
BA0
A14~A8
0
A7
A6~A4
CL
A3
BT
A2~A0
BL
0
0
TE
A7
TEST MODE (TE)
A3
BURST TYPE (BT)
0
1
Regular (default)
Test Mode Entry
0
1
Sequential
Interleave
A6
A5
A4
CAS LATENCY (CL)
A2
A1
A0 BURST LENGTH (BL)
*2
*2
0
0
0
1
1
1
1
0
1
1
0
0
1
1
´
Reserved
0
0
0
0
1
0
0
1
1
´
0
1
0
1
´
Reserved
*2
0
1
0
1
0
1
Reserved
2
4
3
4
*2
Reserved
*2
Reserved
*2
Reserved
*2
Reserved
Extended Mode Register (Notes: 4)
*4
*4
*6
*5
ADDRESS
Register
BA1
BA0
A14~A 12
A11
1
A10~A 7
0
A6
DIC
A5~A2
0
A1
A0
0
1
0
DIC
DS
OUTPUT DRIVE IMPEDANCE CONTROL
(DIC)
A6 A1
0
0
1
1
0
Normal Output Driver
Strong Output Driver
Weaker Output Driver
Weakest Output Driver
1
0
1
A0
DLL SWITCH (DS)
0
1
DLL Enable
DLL Disable
Notes: 1. Regular Mode Register is chosen using the combination of BA0 = 0 and BA1 = 0.
2. “Reserved” places in Regular Mode Register should not be set.
3. A7 in Regular Mode Register must be set to “0” (low state).
Because Test Mode is specific mode for supplier.
4. Extended Mode Register is chosen using the combination of BA0 = 1 and BA1 = 0.
5. A0 in Extended Mode Register must be set to "0" to enable DLL for normal operation.
6. A11 in Extended Mode Register must be set to “1”.
2002-05-16 20/49
TC59LM913/05AMG-50,-55,-60
STATE DIAGRAM
SELF-
REFRESH
POWER
DOWN
SELFX
PDEX
( PD = H)
( PD = H)
PDEN
PD = L
( PD = L)
STANDBY
(IDLE)
PD = H
AUTO-
MODE
REFRESH
REGISTER
WRA
RDA
REF
MRS
ACTIV E
(RESTORE)
ACTIVE
LAL
LAL
WRITE
(BUFFER)
READ
Command input
Automatic return
The second command at Active state
must be issued 1 clock after RDA or
WRA command input.
2002-05-16 21/49
TC59LM913/05AMG-50,-55,-60
TIMING DIAGRAMS
SINGLE BANK READ TIMING(CL 3)
=
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 5 cycles
I
= 5 cycles
I
= 5 cycles
RC
RC
RC
RDA LAL
DESL
RDA LAL
DESL
RDA LAL
DESL
RDA
Command
I
=1 cycle
I
= 4 cycles
I
=1 cycle
I
= 4 cycles
I
=1 cycle
I
= 4 cycles
RCD
RAS
RCD
RAS
RCD
RAS
Address
UA
#0
LA
UA
#0
LA
UA
#0
LA
UA
#0
Bank Add.
BL = 2
Hi-Z
DQS
(output)
CL = 3
CL = 3
CL = 3
DQ
(output)
Hi-Z
Hi-Z
Hi-Z
Q0 Q1
Q0 Q1
Q0 Q1
BL = 4
DQS
(output)
CL = 3
CL = 3
CL = 3
DQ
(output)
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
2002-05-16 22/49
TC59LM913/05AMG-50,-55,-60
=
SINGLE BANK READ TIMING(CL 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 5 cycles
I
= 5 cycles
I
= 5 cycles
RC
RC
RC
RDA LAL
DESL
RDA LAL
DESL
RDA LAL
DESL
RDA
Command
I
=1 cycle
I
= 4 cycles
I
=1 cycle
I
= 4 cycles
I
=1 cycle
I
= 4 cycles
RCD
RAS
RCD
RAS
RCD
RAS
Address
UA
#0
LA
UA
#0
LA
UA
#0
LA
UA
#0
Bank Add.
BL = 2
Hi-Z
DQS
(output)
CL = 4
CL = 4
CL = 4
DQ
(output)
Hi-Z
Hi-Z
Hi-Z
Q0 Q1
Q0 Q1
Q0
BL = 4
DQS
(output)
CL = 4
CL = 4
CL = 4
DQ
(output)
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Q0
2002-05-16 23/49
TC59LM913/05AMG-50,-55,-60
=
SINGLE BANK WRITE TIMING (CL 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 5 cycles
I
= 5 cycles
I
= 5 cycles
RC
RC
RC
WRA LAL
DESL
WRA LAL
DESL
WRA LAL
DESL
WRA
Command
I
=1 cycle
I
= 4 cycles
I
=1 cycle
I
= 4 cycles
I
=1 cycle
I
= 4 cycles
RCD
RAS
RCD
RAS
RCD
RAS
Address
UA
#0
LA
UA
#0
LA
UA
#0
LA
UA
#0
Bank Add.
BL = 2
DQS
(input)
WL = 2
WL = 2
WL = 2
DQ
(input)
D0 D1
D0 D1
D0 D1
BL = 4
DQS
(input)
WL = 2
WL = 2
WL = 2
DQ
(input)
D0 D1 D2 D3
D0 D1 D2 D3
D0 D1 D2 D3
2002-05-16 24/49
TC59LM913/05AMG-50,-55,-60
=
SINGLE BANK WRITE TIMING (CL 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 5 cycles
I
= 5 cycles
I
= 5 cycles
RC
RC
RC
WRA LAL
DESL
WRA LAL
DESL
WRA LAL
DESL
WRA
UA
Command
Address
UA
#0
LA
UA
#0
LA
UA
#0
LA
Bank Add.
#0
BL = 2
DQS
(input)
WL = 3
WL = 3
WL = 3
DQ
(input)
D0 D1
D0 D1
D0 D1
BL = 4
DQS
(input)
WL = 3
WL = 3
WL = 3
DQ
(input)
D0 D1 D2 D3
D0 D1 D2 D3
D0 D1 D2 D3
2002-05-16 25/49
TC59LM913/05AMG-50,-55,-60
=
SINGLE BANK READ-WRITE TIMING (CL 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 5 cycles
I
= 5 cycles
I
= 5 cycles
RC
RC
RC
RDA LAL
DESL
WRA LAL
DESL
RDA LAL
DESL
WRA
UA
Command
Address
UA
#0
LA
UA
#0
LA
UA
#0
LA
Bank Add.
#0
BL = 2
Hi-Z
DQS
CL = 3
CL = 3
WL = 2
Hi-Z
Hi-Z
DQ
Q0 Q1
D0 D1
Q0 Q1
BL = 4
DQS
CL = 3
WL = 2
CL = 3
Hi-Z
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Q0 Q1 Q2 Q3
DQ
2002-05-16 26/49
TC59LM913/05AMG-50,-55,-60
=
SINGLE BANK READ-WRITE TIMING (CL 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 5 cycles
I
= 5 cycles
I
= 5 cycles
RC
RC
RC
RDA LAL
DESL
WRA LAL
DESL
RDA LAL
DESL
WRA
UA
Command
Address
UA
#0
LA
UA
#0
LA
UA
#0
LA
Bank Add.
#0
BL = 2
Hi-Z
DQS
CL = 4
WL = 3
CL = 4
Hi-Z
Hi-Z
DQ
Q0 Q1
D0 D1
Q0
BL = 4
DQS
CL = 4
WL = 3
CL = 4
Hi-Z
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Q0
DQ
2002-05-16 27/49
TC59LM913/05AMG-50,-55,-60
=
MULTIPLE BANK READ TIMING(CL 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
I
= 2 cycles I
= 2 cycles I
= 2 cycles I
= 2 cycles
RBD
RBD
RBD
RBD
RBD
RDA LAL RDA LAL DESL RDA LAL RDA LAL RDA LAL RDA LAL RDA LAL
Command
Address
RDA
UA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
Bank Add.
I
(Bank"a") = 5 cycles
RC
I
(Bank"b") = 5 cycles
RC
BL = 2
Hi-Z
DQS
(output)
CL = 3
CL = 3
DQ
(output)
Hi-Z
Hi-Z
Qa0Qa1
Qb0Qb1
Qa0Qa1
Qb0Qb1
Qc0Qc1
Qd0 Qd1
BL = 4
DQS
(output)
CL = 3
CL = 3
DQ
(output)
Hi-Z
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3Qc0Qc1Qc2Qc3Qd0Qd1
Note: l
to the same bank must be satisfied.
RC
2002-05-16 28/49
TC59LM913/05AMG-50,-55,-60
=
MULTIPLE BANK READ TIMING(CL 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
I
= 2 cycles I
= 2 cyclesI
= 2 cycles I
= 2 cycles
RBD
RBD
RBD
RBD
RBD
RDA LAL RDA LAL DESL RDA LAL RDA LAL RDA LAL RDA LAL RDA LAL
Command
Address
RDA
UA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
Bank Add.
I
(Bank"a") = 5 cycles
RC
I
(Bank"b") = 5 cycles
RC
BL = 2
Hi-Z
DQS
(output)
CL = 4
CL = 4
DQ
(output)
Hi-Z
Qa0Qa1
Qb0Qb1
Qa0Qa1
Qb0Qb1
Qc0Qc1
BL = 4
DQS
Hi-Z
Hi-Z
(output)
CL = 4
CL = 4
DQ
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3Qc0Qc1Qc2
(output)
Note: l
to the same bank must be satisfied.
RC
2002-05-16 29/49
TC59LM913/05AMG-50,-55,-60
=
MULTIPLE BANK WRITE TIMING (CL 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
I
= 2 cycles I
= 2 cycles I
= 2 cycles I
= 2 cycles
RBD
RBD
RBD
RBD
RBD
Command
Address
WRA LAL WRA LAL DESL WRA LAL WRA LAL WRA LAL WRA LAL WRA LAL WRA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
Bank Add.
I
(Bank"a") = 5 cycles
RC
I
(Bank"b") = 5 cycles
RC
BL = 2
DQS
(input)
WL = 2
WL = 2
DQ
(input)
Da0Da1
Db0Db1
Da0Da1
Db0Db1
Dc0Dc1
Dd0Dd1
BL = 4
DQS
(input)
WL = 2
WL = 2
DQ
(input)
Da0Da1Da2Da3Db0Db1Db2Db3
Da0Da1Da2Da3Db0Db1Db2Db3Dc0Dc1Dc2Dc3Dd0Dd1Dd0Dd1
Note: l
to the same bank must be satisfied.
RC
2002-05-16 30/49
TC59LM913/05AMG-50,-55,-60
=
MULTIPLE BANK WRITE TIMING (CL 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
I
= 2 cycles I
= 2 cycles I
= 2 cycles I
= 2 cycles
RBD
RBD
RBD
RBD
RBD
WRA LAL WRA LAL DESL WRA LAL WRA LAL WRA LAL WRA LAL WRA LAL WRA
Command
Address
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
Bank Add.
I
(Bank"a") = 5 cycles
RC
I
(Bank"b") = 5 cycles
RC
BL = 2
DQS
(input)
WL = 3
WL = 3
DQ
(input)
Da0Da1
Db0Db1
Da0Da1
Db0Db1
Dc0Dc1
Dd0Dd1
BL = 4
DQS
(input)
WL = 3
WL = 3
DQ
(input)
Da0Da1Da2Da3Db0Db1Db2Db3
Da0Da1Da2Da3Db0Db1Db2Db3Dc0Dc1Dc2Dc3Dd0Dd1
Note: l
to the same bank must be satisfied.
RC
2002-05-16 31/49
TC59LM913/05AMG-50,-55,-60
=
MULTIPLE BANK READ-WRITE TIMING(BL 2)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
RBD
Command
WRA LAL RDA LAL DESL WRA LAL RDA
LAL DESL WRA LAL RDA LAL DESL WRA
= 2 cycles
I
= 1 cycle
I
= 2 cycles
I
= 1 cycle
I
RWD
WRD
RWD
WRD
Address
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
Bank
"c"
Bank Add.
I
(Bank"a")
RC
I
(Bank"b")
RC
CL = 3
Hi-Z
DQS
CL = 3
WL = 2
Hi-Z
Hi-Z
DQ
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
Da0 Da1
CL = 4
DQS
CL = 4
WL = 3
Hi-Z
DQ
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
Da0 Da1
Note: l
to the same bank must be satisfied.
RC
2002-05-16 32/49
TC59LM913/05AMG-50,-55,-60
=
MULTIPLE BANK READ-WRITE TIMING(BL 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
RBD
Command
WRA LAL RDA LAL
DESL
= 3 cycles
WRA LAL RDA
LAL
LA
DESL
= 3 cycles
WRA LAL RDA LAL
I
= 1 cycle
I
I
= 1 cycle
I
I = 1 cycle
WRD
WRD
RWD
WRD
RWD
Address
UA
LA
UA
LA
UA
LA
UA
UA
LA
UA
LA
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
Bank Add.
I
(Bank"a")
RC
I
(Bank"b")
RC
CL = 3
Hi-Z
DQS
CL = 3
WL = 2
Hi-Z
Hi-Z
DQ
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
Qd0 Qd1 Qd2 Qd3
CL = 4
DQS
CL = 4
WL = 3
Hi-Z
DQ
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
Qd0 Qd1 Qd2 Qd3
Note: l
to the same bank must be satisfied.
RC
2002-05-16 33/49
TC59LM913/05AMG-50,-55,-60
=
WRITE with VARIAVLE WRITE LENGTH (VW) CONTROL(CL 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
BL = 2, SEQUENTIAL MODE
WRA LAL
DESL
WRA LAL
DESL
Command
LA=#3
LA=#1
Address
UA
UA
VW=All
VW=1
VW0 = Low
VW1 = don't care
VW0 = High
VW1 = don't care
Bank
"a"
Bank
"a"
Bank Add.
DQS
(input)
DQ
(input)
D0 D1
D0
Lower Address #3 #2
#1 (#0)
Last one data is masked.
BL = 4, SEQUENTIAL MODE
WRA LAL
DESL
WRA LAL
DESL
WRA LAL
DESL
Command
Address
LA=#3
LA=#1
LA=#2
UA
UA
UA
VW=All
VW=1
VW=2
VW0 = High
VW1 = Low
VW0 = High
VW1 = High
VW0 = Low
VW1 = High
Bank
"a"
Bank
"a"
Bank
"a"
Bank Add.
DQS
(input)
DQ
(input)
D0 D1 D2 D3
D0
D0 D1
Lower Address #3 #0 #1 #2
#1(#2)(#3)(#0)
#2 #3 (#0)(#1)
Last three data are masked.
Note: DQS input must be continued till end ofburst count even if some of laster data is masked.
Last two data are masked.
2002-05-16 34/49
TC59LM913/05AMG-50,-55,-60
=
=
POWER DOWN TIMING (CL 4, BL 4)
Read cycle to Power Down Mode
0
1
2
3
4
5
6
7
8
9
10
n-1
n
n+1
n+2
n+3
CLK
CLK
I
PDA
RDA
or
Command
Address
RDA LAL
DESL
DESL
WRA
UA
LA
UA
t
I
= 1 cycle
IS PD
t
IH
PD
t
t
PDEX
QPDH
l
, t
RC(min) REFI(max)
Hi-Z
DQS
(output)
CL = 4
DQ
Hi-Z
Hi-Z
Q0 Q1 Q2 Q3
(output)
Power Down Entry
Note: PD must be kept "High" level until end of Burst data output.
PD should be brought to "High" within t (max.) to maintain the data written into cell.
Power Down Exit
REFI
In Power Down Mode, PD "Low" and a stable clock signal must be maintained.
When PD is brought to "High", a valid executable command may be applied lPDA cycles later.
2002-05-16 35/49
TC59LM913/05AMG-50,-55,-60
=
=
POWER DOWN TIMING (CL 4, BL 4)
Write cycle to Power Down Mode
0
1
2
3
4
5
6
7
8
9
10
n-1
n
n+1
n+2
n+3
CLK
CLK
I
PDA
RDA
or
WRA
WRA LAL
DESL
Command
Address
DESL
UA
LA
UA
t
I
= 1 cycle
IS PD
t
IH
PD
WL = 3
2 clock cycles
t
PDEX
l
, t
RC(min) REFI(max)
DQS
(input)
WL = 3
DQ
D0 D1 D2 D3
(input)
Note: PD must be kept "High" level until WL+2 clock cycles from LAL command.
PD should be brought to "High" within t (max.) to maintain the data written into cell.
REFI
In Power Down Mode, PD "Low" and a stable clock signal must be maintained.
When PD is brought to "High", a valid executable command may be applied lPDA cycles later.
2002-05-16 36/49
TC59LM913/05AMG-50,-55,-60
=
=
MODE REGISTER SET TIMING(CL 4, BL 2)
From Read operation to Mode Register Set operation.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
RSC
RDA
or
Command
A14~A0
RDA LAL
DESL
RDA MRS
DESL
LAL
LA
WRA
Valid
UA
BA
LA
UA
BA
(opcode)
BA0="0"
BA1="0"
BA0, BA1
CL + BL/2
Hi-Z
DQS
(output)
DQ
(output)
Q0 Q1
Note: Minimum delay from LAL following RDA to RDA of MRS operation is CL+BL/2.
2002-05-16 37/49
TC59LM913/05AMG-50,-55,-60
=
=
MODE REGISTER SET TIMING(CL 4, BL 4)
From Write operation to Mode Register Set operation.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
RSC
RDA
or
WRA LAL
DESL
RDA MRS
DESL
LAL
LA
Command
A14~A0
WRA
Valid
UA
BA
LA
UA
BA
(opcode)
BA0="0"
BA1="0"
BA0, BA1
WL+BL/2
DQS
(input)
DQ
(input)
D0 D1 D2 D3
Note: Minimum delay from LAL following WRA to RDA of MRS operation is WL+BL/2.
2002-05-16 38/49
TC59LM913/05AMG-50,-55,-60
=
=
EXTENDED MODE REGISTER SET TIMING(CL 4, BL 2)
From Read operation to Extended Mode Register Set operation.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
RSC
RDA
or
Command
A14~A0
RDA LAL
DESL
RDA MRS
DESL
LAL
LA
WRA
Valid
UA
BA
LA
UA
BA
(opcode)
BA0="1"
BA1="0"
BA0, BA1
CL + BL/2
Hi-Z
DQS
(output)
DQ
(output)
Q0 Q1
Note: Minimum delay from LAL following RDA to RDA of EMRS operation is CL+BL/2.
DLL switch in Extended Mode Register must be set to enable mode for normal operation.
DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence.
2002-05-16 39/49
TC59LM913/05AMG-50,-55,-60
=
=
EXTENDED MODE REGISTER SET TIMING (CL 4, BL 4)
From Write operation to Extended Mode Register Set operation.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
RSC
RDA
or
WRA LAL
DESL
RDA MRS
DESL
LAL
LA
Command
A14~A0
WRA
Valid
UA
BA
LA
UA
BA
(opcode)
BA0="1"
BA1="0"
BA0, BA1
WL+BL/2
DQS
(input)
DQ
(input)
D0 D1 D2 D3
Note: DLL switch in Extended Mode Register must be set to enable mode for normal operation.
DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence.
Minimum delay from LAL following WRA to RDA of EMRS operation is WL+BL/2.
2002-05-16 40/49
TC59LM913/05AMG-50,-55,-60
=
=
AUTO-REFRESH TIMING(CL 4, BL 4)
0
1
2
3
4
5
6
7
n - 1
n
n + 1
n + 2
CLK
CLK
I
= 5 cycles
I
= 18 cycles
RC
REFC
RDA
or
LAL or
MRS or
REF
RDA
LAL
DESL
WRA
REF
DESL
Command
WRA
Bank,
UA
LA
Bank, Address
I
= 1 cycle
I
= 4 cycles
CL = 4
I = 1 cycle
RCD
RCD
RAS
DQS
(output)
Hi-Z
Hi-Z
Hi-Z
DQ
(output)
Hi-Z
Q0 Q1 Q2 Q3
Note: In case of CL = 4, I
must be meet 18 clock cycles.
REFC
When the Auto-Refresh operation is performed, the synthetic average interval of Auto-Refresh command
specified by t must be satisfied.
REFI
t
is average interval time in 8 Refresh cycles that is sampled randomly.
REFI
t
1
t
2
t
3
t
7
t
8
CLK
WRA REF
WRA REF
WRA REF
WRA REF
WRA REF
8 Refresh cycle
Total time of 8 Refresh cycle
8
t + t + t + t + t + t + t + t
1 2 3 4 5 6 7 8
t
=
=
REFI
8
t
isspecified to avoid partly concentrated current of Refresh operation that is activated larger area
REFI
than Read / Write operation.
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TC59LM913/05AMG-50,-55,-60
SELF-REFRESH ENTRY TIMING
0
1
2
3
4
5
m - 1
m
m + 1
CLK
CLK
I
= 1 cycle
I
REFC
RCD
WRA
REF
DESL
Command
PD
t
t
FPDL (min) FPDL (max)
Auto Refresh
Self Refresh Entry
*2
I
PDV
t
QPDH
I
CKD
Hi-Z
DQS
(output)
DQ
(output)
Hi-Z
Qx
Notes: 1.
is don’t care.
2. PD must be brought to "Low" within the timing between t (min) and t (max) to Self
FPDL FPDL
Refresh mode.When PD is brought to "Low" after l , FCRAM perform Auto Refresh and enter
PDV
Power down mode.
3. It is desirable that clock input is continued at least l
brought to “Low ” for Self -Refresh Entry.
from REF command even though PD is
CKD
SELF-REFRESH EXIT TIMING
0
1
2
m - 1
m
m + 1
m + 2
n - 1
n
n + 1
p - 1
p
CLK
CLK
*2
*6
Command (1st)
Command (2nd)
I
I
REFC
REFC
*6
*7
*3
*5
*5
*7
DESL
WRA
REF
DESL
RDA
LAL
Command
PD
*4
I
= 1 cycles
I
= 1 cycle
I
= 1 cycle
PDA
RCD
RCD
t
PDEX
I
LOCK
DQS
Hi-Z
(output)
DQ
(output)
Hi-Z
Self-Refresh Exit
Notes: 1.
2. Clock should be stable prior to PD = “High” if clock input is suspended in Self-Refresh mode.
3. DESL command must be asserted during I after PD is brought to “High”.
is don’t care.
REFC
4.
I
is defined from the first clock rising edge after PD is brought to “High”.
PDA
5. It is desirable that one Auto-Refresh command is issued just after Self -Refresh Exit before any
other operation.
6. Any command (except Read command) can be issued after I
.
REFC
7. Read command (RDA + LAL) can be issued after I
.
LOCK
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TC59LM913/05AMG-50,-55,-60
FUNCTIONAL DESCRIPTION
TM
DDR FCRAM
DDR FCRAMTM is an acronym of Double Data Rate Fast Cycle Random Access Memory. The DDR FCRAMTM
is competent to perform fast random core access, low latency and high-speed data transfer.
PIN FUNCTIONS
CLK
CLOCK INPUTS: CLK &
The CLK and CLK inputs are used as the reference for synchronous operation. CLK is master clock input. The
CS , FN and all address input signals are sampled on the crossing of the positive edge of CLK and the negative
edge of CLK . The DQS and DQ output are aligned to the crossing point of CLK and CLK . The timing reference
point for the differential clock is when the CLK and CLK signals cross during a transition.
PD
POWER DOWN:
The PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a Clock
Suspend function like a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into low state if
any Read or Write operation is being performed.
CS
CHIP SELECT & FUNCTION CONTROL:
& FN
The CS and FN inputs are a control signal for forming the operation commands on FCRAMTM. Each operation
mode is decided by the combination of the two consecutive operation commands using the CS and FN inputs.
BANK ADDRESSES: BA0~BA1
The BA0 to BA1 inputs are latched at the time of assertion of the RDA or WRA command and are selected the
bank to be used for the operation. BA0 and BA1 also define which mode register is loaded during the Mode Register
Set command (MRS or EMRS).
BA0
BA1
Bank #0
Bank #1
Bank #2
Bank #3
0
1
0
1
0
0
1
1
ADDRESS INPUTS: A0~A14
Address inputs are used to access the arbitrary address of the memory cell array within each bank. The Upper
Addresses with Bank addresses are latched at the RDA or WRA command and the Lower Addresses are latched at
the LAL command. The A0 to A14 inputs are also used for setting the data in the Regular or Extended Mode
Register set cycle.
UPPER ADDRESS
LOWER ADDRESS
TC59LM905AMG
TC59LM913AMG
A0~A14
A0~A14
A0~A8
A0~A7
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TC59LM913/05AMG-50,-55,-60
DATA INPUT/OUTPUT: DQ0~DQ7 or DQ15
The input data of DQ0 to DQ15 are taken in synchronizing with the both edges of DQS input signal. The
output data of DQ0 to DQ15 are outputted synchronizing with the both edges of DQS signal.
DATA STROBE: DQS, LDQS / UDQS
The DQS is bi-directional signal. Both edge of DQS are used as the reference of data input or output. In write
operation, the DQS used as an input signal is utilized for a latch of write data. In read operation, the DQS is an
output signal provides the read data strobe.
POWER SUPPLY: VDD, VDDQ, VSS, VSSQ
V
V
and V
DDQ
are power supply pins for memory core and peripheral circuits.
are power supply pins for the output buffer.
SSQ
DD
SS
and V
REFERENCE VOLTAGE: VREF
V
is reference voltage for all input signals.
REF
2002-05-16 44/49
TC59LM913/05AMG-50,-55,-60
COMMAND FUNCTIONS and OPERATIONS
TC59LM913/05AMG are introduced the two consecutive command input method. Therefore, except for Power
Down mode, each operation mode decided by the combination of the first command and the second command from
stand-by states of the bank to be accessed.
+
=
+
Read Operation (1st command 2nd command RDA LAL)
Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated
by Bank Address in a read mode. When the LAL command with Lower Addresses is issued at the next clock of the
RDA command, the data is read out sequentially synchronizing with the both edges of DQS output signal (Burst
Read Operation). The initial valid read data appears after CAS latency from the issuing of the LAL command.
The valid data is outputted for a burst length. The CAS latency, the burst length of read data and the burst type
must be set in the Mode Register beforehand. The read operated bank goes back automatically to the idle state
after l
.
RC
+
=
+
Write Operation (1st command 2nd command WRA LAL)
Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated
by Bank Address in a write mode. When the LAL command with Lower Addresses is issued at the next clock of the
WRA command, the input data is latched sequentially synchronizing with the both edges of DQS input signal
(Burst Write Operation). The data and DQS inputs have to be asserted in keeping with clock input after CAS
latency-1 from the issuing of the LAL command. The DQS has to be provided for a burst length. The CAS latency
and the burst type must be set in the Mode Register beforehand. The write operated bank goes back automatically
to the idle state after l . Write Burst Length is controlled by VW0 and VW1 inputs with LAL command. See VW
RC
truth table.
+
=
+
Auto-Refresh Operation (1st command 2nd command WRA REF)
TC59LM913/05AMG are required to refresh like a standard SDRAM. The Auto-Refresh operation is begun with
the REF command following to the WRA command. The Auto-Refresh mode can be effective only when all banks are
in the idle state and all outputs are in Hi-Z states. In a point to notice, the write mode started with the WRA
command is canceled by the REF command having gone into the next clock of the WRA command instead of the
LAL command. The minimum period between the Auto-Refresh command and the next command is specified by
l
. However, about a synthetic average interval of Auto-Refresh command, it must be careful. In case of equally
REFC
distributed refresh, Auto-Refresh command has to be issued within once for every 7.8 ms by the maximum. In case
of burst refresh or random distributed refresh, the average interval of eight consecutive Auto-Refresh commands
has to be more than 400 ns always. In other words, the number of Auto-Refresh cycles that can be performed within
3.2 ms (8 ´ 400 ns) is to 8 times in the maximum.
+
=
+
PD =
Self-Refresh Operation (1st command 2nd command WRA REF with “L”)
In case of Self-Refresh operation, refresh operation can be performed automatically by using an internal timer.
When all banks are in the idle state and all outputs are in Hi-Z states, the TC59LM913/05AMG become
Self-Refresh mode by issuing the Self-Refresh command. PD has to be brought to “Low” within t
FPDL
from the
REF command following to the WRA command for a Self-Refresh mode entry. In order to satisfy the refresh period,
the Self-Refresh entry command should be asserted within 7.8 ms after the latest Auto-Refresh command. Once the
device enters Self-Refresh mode, the DESL command must be continued for l
period. In addition, it is
REFC
period. The device is in Self-Refresh mode as long as PD held “Low”.
desirable that clock input is kept in l
CKD
During Self-Refresh mode, all input and output buffers are disabled except for PD , therefore the power dissipation
lowers. Regarding a Self-Refresh mode exit, PD has to be changed over from “Low” to “High” along with the DESL
command, and the DESL command has to be continuously issued in the number of clocks specified by l
. The
REFC
Self-Refresh exit function is asynchronous operation. It is required that one Auto-Refresh command is issued to
avoid the violation of the refresh period just after l from Self-Refresh exit.
REFC
PD =
Power Down Mode (
“L”)
When all banks are in the idle state and DQ outputs are in Hi-Z states, the TC59LM 913/05AMG become Power
Down Mode by asserting PD is “Low”. When the device enters the Power Down Mode, all input and output buffers
are disabled after specified time except for PD . Therefore, the power dissipation lowers. To exit the Power Down
Mode, PD has to be brought to “High” and the DESL command has to be issued for two clocks cycle after PD
goes high. The Power Down exit function is asynchronous operation.
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TC59LM913/05AMG-50,-55,-60
+
=
+
Mode Register Set (1st command 2nd command RDA MRS)
When all banks are in the idle state, issuing the MRS command following to the RDA command can program the
Mode Register. In a point to notice, the read mode started with the RDA command is canceled by the MRS
command having gone into the next clock of the RDA command instead of the LAL command. The data to be set in
the Mode Register is transferred using A0 to A14, BA0 to BA1 address inputs. The TC59LM 913/05AMG have two
mode registers. These are Regular and Extended Mode Register. The Regular or Extended Mode Register is chosen
by BA0 and BA1 in the MRS command. The Regular Mode Register designates the operation mode for a read or
write cycle. The Regular Mode Register has four function fields.
The four fields are as follows:
(R-1) Burst Length field to set the length of burst data
(R-2) Burst Type field to designate the lower address access sequence in a burst cycle
(R-3) CAS Latency field to set the access time in clock cycle
(R-4) Test Mode field to use for supplier only.
The Extended Mode Register has two function fields.
The two fields are as follows:
(E-1) DLL Switch field to choose either DLL enable or DLL disable
(E-2) Output Driver Impedance Control field.
(E-3) DQS enable field.
(E-4) Interface select field to use for supplier only.
Once those fields in the Mode Register are set up, the register contents are maintained until the Mode Register is
set up again by another MRS command or power supply is lost. The initial value of the Regular or Extended Mode
Register after power-up is undefined, therefore the Mode Register Set command must be issued before proper
operation.
·
Regular Mode Register/Extended Mode Register change bits (BA0, BA1)
These bits are used to choose either Regular MRS or Extended MRS
BA1
BA0
A14~A0
0
0
1
0
1
´
Regular MRS Cycle
Extended MRS Cycle
Reserved
Regular Mode Register Fields
(R-1) Burst Length field (A2 to A0)
This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length
to be 2 or 4 words.
A2
A1
A0
BURST LENGTH
0
0
0
0
1
0
0
1
1
´
0
1
0
1
´
Reserved
2 words
4 words
Reserved
Reserved
(R-2) Burst Type field (A3)
The Burst Type can be chosen Interleave mode or Sequential mode. When the A3 bit is “0”, Sequential
mode is selected. When the A3 bit is “1”, Interleave mode is selected. Both burst types support burst
length of 2 and 4 words.
A3
BURST TYPE
0
1
Sequential
Interleave
2002-05-16 46/49
TC59LM913/05AMG-50,-55,-60
·
Addressing sequence of Sequential mode (A3)
A column access is started from the inputted lower address and is performed by incrementing the lower
address input to the device.
CAS Latency = 4
CLK
CLK
Command
DQS
RDA
LAL
Data Data Data Data
DQ
0
1
2
3
Addressing sequence for Sequential mode
DATA
ACCESS ADDRESS
BURST LENGTH
Data 0
Data 1
Data 2
Data 3
n
2 words (address bits is LA0)
not carried from LA0~LA1
n + 1
n + 2
n + 3
4 words (address bits is LA1, LA0)
not carried from LA1~LA2
·
Addressing sequence of Interleave mode
A column access is started from the inputted lower address and is performed by interleaving the address
bits in the sequence shown as the following.
Addressing sequence for Interleave mode
DATA
ACCESS ADDRESS
BURST LENGTH
2 words
Data 0
Data 1
Data 2
Data 3
???A8 A7 A6 A5 A4 A3 A2 A1 A0
???A8 A7 A6 A5 A4 A3 A2 A1 A0
???A8 A7 A6 A5 A4 A3 A2 A1 A0
???A8 A7 A6 A5 A4 A3 A2 A1 A0
4 words
(R-3) CAS Latency field (A6 to A4)
This field specifies the number of clock cycles from the assertion of the LAL command following the
RDA command to the first data read. The minimum values of CAS Latency depends on the frequency of
CLK. In a write mode, the place of clock that should input write data is CAS Latency cycles - 1.
A6
A5
A4
CAS LATENCY
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
3
4
Reserved
Reserved
Reserved
(R-4) Test Mode field (A7)
This bit is used to enter Test Mode for supplier only and must be set to “0” for normal operation.
(R-5) Reserved field in the Regular Mode Register
·
Reserved bits (A8 to A14, BA1)
These bits are reserved for future operations. They must be set to “0” for normal operation.
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TC59LM913/05AMG-50,-55,-60
Extended Mode Register fields
(E-1) DLL Switch field (A0)
This bit is used to enable DLL. When the A0 bit is set “0”, DLL is enabled.
(E-2) Output Driver Impedance Control field (A1, A6)
This field is used to choose Output Driver Strength. Three types of Driver Strength are supported.
A6
A1
OUTPUT DRIVER IMPEDANCE CONTROL
0
0
1
1
0
1
0
1
Normal Output Driver
Strong Output Driver
Weaker Output Driver
Weakest Output Driver
(E-3) DQS enable (A10)
DQS is not supported. This bit must be always set “0”.
(E-4) Interface mode select (A11)
This bit must be always set “1”.
(E-5) Reserved field (A2 to A5, A7 to A9, A12 to A14)
These bits are reserved for future operations and must be set to “0” for normal operation.
2002-05-16 48/49
TC59LM913/05AMG-50,-55,-60
RESTRICTIONS ON PRODUCT USE
000707EBA
· TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system , and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
· The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
· The products described in this document are subject to the foreign exchange and foreign trade laws.
· The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
rights of the third parties which may result from its use. No license is granted by implication or otherwise under
any intellectual property or other rights of TOSHIBA CORPORATION or others.
· The information contained herein is subject to change without notice.
2002-05-16 49/49
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