TC59LM818DMGI-37 [TOSHIBA]
IC 16M X 18 DDR DRAM, 0.65 ns, PBGA60, 9 X 17 MM, 1.00 MM PITCH, LEAD FREE, PLASTIC, TFBGA-60, Dynamic RAM;
| 型号： | TC59LM818DMGI-37 |
| 厂家： | 
TOSHIBA |
| 描述： | IC 16M X 18 DDR DRAM, 0.65 ns, PBGA60, 9 X 17 MM, 1.00 MM PITCH, LEAD FREE, PLASTIC, TFBGA-60, Dynamic RAM 时钟 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总55页 (文件大小：673K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TC59LM818DMGI-37
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
Lead-Free
288Mbits Network FCRAM2 (I-version)
− 4,194,304-WORDS × 4 BANKS × 18-BITS
DESCRIPTION
Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM818DMGI is Network
FCRAMTM containing 301,989,888 memory cells. TC59LM818DMGI is organized as 4,194,304-words × 4 banks × 18
bits. TC59LM818DMGI feature a fully synchronous operation referenced to clock edge whereby all operations are
synchronized at a clock input which enables high performance and simple user interface coexistence.
TC59LM818DMGI can operate fast core cycle compared with regular DDR SDRAM.
TC59LM818DMGI is suitable for Network, Server and other applications where large memory density and low
power consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data
transfer under light loading condition. TC59LM818DMGI guarantees −40deg°C to 100deg°C operating temperature
so it is suitable for use in wide operating temperature system.
FEATURES
PARAMETER
TC59LM818DMGI37
CL = 4
CL = 5
CL = 6
5.0 ns
4.0 ns
3.75 ns
25 ns
t
Clock Cycle Time (min)
CK
t
t
I
Random Read/Write Cycle Time (min)
Random Access Time (max)
RC
25 ns
RAC
DD1S
DD2P
Operating Current (single bank) (max)
Power Down Current (max)
220 mA
65 mA
l
•
•
Fully Synchronous Operation
Double Data Rate (DDR)
•
•
Data input/output are synchronized with both edges of DS / QS.
Differential Clock (CLK and CLK ) inputs
CS , FN and all address input signals are sampled on the positive edge of CLK.
Output data (DQs and QS) is aligned to the crossings of CLK and CLK .
Fast clock cycle time of 3.75 ns minimum
Clock: 266 MHz maximum
Data: 533 Mbps/pin maximum
Operating Temperature : −40deg°C ~ 100deg°C (Case Temperature)
Quad Independent Banks operation
Fast cycle and Short Latency
Selectable Data Strobe
Distributed Auto-Refresh cycle in 1.95 µs
Power Down Mode
•
•
•
•
•
•
•
•
•
Variable Write Length Control
Write Latency = CAS Latency-1
Programable CAS Latency and Burst Length
CAS Latency = 4, 5, 6
Burst Length = 2, 4
•
•
Organization: 4,194,304 words × 4 banks × 18 bits
Power Supply Voltage
V
DD
V
:
2.5 V ± 0.125V
: 1.7 V ~ 1.9 V
DDQ
•
•
•
Low voltage CMOS I/O covered with SSTL_18 (Half strength driver)
Package:
60Ball BGA, 1mm × 1mm Ball pitch (P-BGA60-0917-1.00AZ)
Lead-Free
Notice: FCRAM is trademark of Fujitsu limited, Japan.
Rev 1.2
2005-11-08 1/55
TC59LM818DMGI-37
PIN NAMES
PIN ASSIGNMENT (TOP VIEW)
ball pitch=1.0 x 1.0mm
PIN
NAME
Address Input
x18
A0~A14
BA0, BA1
DQ0~DQ17
CS
1
2
3
4
5
6
Bank Address
Data Input/Output
Chip Select
A
B
Index
V
DQ17
DQ0
V
DD
SS
DQ16
DQ15
V
V
Q
Q
V
Q
DD
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
DQ8
A14
A13
NC
SS
FN
Function Control
Power Down Control
Clock Input
PD
V
Q
C
D
DD
SS
CLK, CLK
DS / QS
DQ14 DQ13
DQ4
Write/Read Data Strobe
Power (+2.5 V)
Ground
V
V
DD
SS
DQ12
DQ11
DQ10
DQ9
VREF
CLK
A12
V
V
Q
Q
V
Q
DD
E
F
SS
V
Q
DD
SS
Power (+1.8 V)
(for DQ buffer)
V
DDQ
V
Q
V
Q
G
H
J
SS
DD
Ground
(for DQ buffer)
V
V
SSQ
REF
DS
QS
Reference Voltage
Not Connected
NC
V
V
DD
SS
CLK
FN
K
L
PD
A9
A7
A6
A4
CS
A11
BA1
BA0
A10
A1
M
N
A8
A0
A2
A3
A5
P
R
V
V
DD
SS
: Depopulated Ball
Rev 1.2
2005-11-08 2/55
TC59LM818DMGI-37
BLOCK DIAGRAM
CLK
CLK
PD
DLL
CLOCK
BUFFER
To each block
CS
FN
CONTROL
SIGNAL
COMMAND
DECODER
BANK #3
BANK #2
BANK #1
BANK #0
GENERATOR
MODE
REGISTER
MEMORY
CELL ARRAY
A0~A14
ADDRESS
BUFFER
UPPER ADDRESS
LATCH
BA0, BA1
LOWER ADDRESS
LATCH
COLUMN DECODER
READ
DATA
WRITE
DATA
WRITE ADDRESS
REFRESH
COUNTER
LATCH/
ADDRESS
BUFFER
BUFFER
COMPARATOR
BURST
COUNTER
DS
QS
DQ BUFFER
DQ0~DQ17
Note: The TC59LM818DMGI configuration is 4 Bank of 32768 × 128 × 18 of cell array with the DQ pins numbered DQ0~DQ17.
Rev 1.2
2005-11-08 3/55
TC59LM818DMGI-37
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
Power Supply Voltage
RATING
UNIT
NOTES
V
V
V
V
V
−0.3~ 3.3
V
V
DD
Power Supply Voltage (for DQ buffer)
Input Voltage
−0.3~V + 0.3
DD
DDQ
IN
−0.3~V + 0.3
V
DD
Output and I/O pin Voltage
Input Reference Voltage
Operating Temperature (case)
Storage Temperature
−0.3~V
+ 0.3
DDQ
V
OUT
REF
opr
−0.3~V + 0.3
V
DD
T
T
T
−40~100
−55~150
260
°C
°C
°C
W
mA
stg
Soldering Temperature (10 s)
Power Dissipation
solder
P
2
D
I
Short Circuit Output Current
±50
OUT
Caution: Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device.
The device is not meant to be operated under conditions outside the limits described in the operational section of this
specification.
Exposure to “ABSOLUTE MAXIMUM RATINGS” conditions for extended periods may affect device reliability.
RECOMMENDED DC, AC OPERATING CONDITIONS (Notes: 1)(T
= -40~100°C)
CASE
SYMBOL
PARAMETER
Power Supply Voltage
MIN
TYP.
MAX
UNIT
NOTES
V
V
V
V
V
V
2.375
1.7
2.5
2.625
1.9
V
V
V
V
V
V
DD
Power Supply Voltage (for DQ buffer)
Reference Voltage
DDQ
REF
V
/2 × 95%
+ 0.125
V
/2
DDQ
V
/2 × 105%
DDQ
2
5
DDQ
(DC)
Input DC High Voltage
V
V
+ 0.2
DDQ
IH
IL
REF
(DC)
(DC)
Input DC Low Voltage
−0.1
−0.1
V
− 0.125
5
REF
Differential Clock DC Input Voltage
V
V
V
+ 0.1
+ 0.2
10
ICK
DDQ
DDQ
DDQ
Differential Input Voltage
CLK and CLK inputs (DC)
V
(DC)
0.4
V
7, 10
ID
V
V
(AC)
Input AC High Voltage
Input AC Low Voltage
V
+ 0.2
REF
+ 0.2
− 0.2
V
V
3, 6
4, 6
IH
IL
(AC)
(AC)
(AC)
−0.1
V
REF
Differential Input Voltage.
V
0.55
V
+ 0.2
V
7, 10
ID
X
DDQ
CLK and CLK inputs (AC)
V
V
Differential AC Input Cross Point Voltage
Differential Clock AC Middle Level
V
V
/2 − 0.125
/2 − 0.125
V
V
/2 + 0.125
/2 + 0.125
V
V
8, 10
9, 10
DDQ
DDQ
(AC)
ISO
DDQ
DDQ
Rev 1.2
2005-11-08 4/55
TC59LM818DMGI-37
Note:
(1) All voltages referenced to V , V
.
SS SSQ
(2) V
REF
is expected to track variations in V
DC level of the transmitting device.
DDQ
may not exceed ±2% V
Peak to peak AC noise on V
REF
(DC).
REF
+ 0.7 V with a pulse width ≤ 5 ns.
= −0.7 V with a pulse width ≤ 5 ns.
(3) Overshoot limit: V
IH (max)
= V
DDQ
(4) Undershoot limit: V
IL (min)
(5) V (DC) and V (DC) are levels to maintain the current logic state.
IH IL
(6) V (AC) and V (AC) are levels to change to the new logic state.
IH IL
(7) V is differential voltage of CLK input level and CLK input level.
ID
(8) The value of V (AC) is expected to equal V
/2 of the transmitting device.
DDQ
X
(9) V
ISO
means {V
(CLK) + V (CLK )} /2
ICK
ICK
(10) Refer to the figure below.
CLK
V
V
V
V
V
V (AC)
ID
x
x
x
x
x
CLK
V
V
V
V
ICK
ICK
ICK
ICK
V
SS
|V (AC)|
ID
0 V Differential
V
ISO
V
V
ISO (max)
ISO (min)
V
SS
(11) In the case of external termination, VTT (termination voltage) should be gone in the range of V
0.04 V.
(DC) ±
REF
CAPACITANCE (V = 2.5V, V
= 1.8 V, f = 1 MHz, Ta = 25°C)
DD
DDQ
SYMBOL
PARAMETER
MIN
MAX
Delta
UNIT
C
C
C
C
Input pin Capacitance
1.5
1.5
2.5
3.0
3.0
3.5
1.5
0.25
0.25
0.5
pF
pF
pF
pF
IN
Clock pin (CLK, CLK ) Capacitance
DQ, DS, QS Capacitance
NC pin Capacitance
INC
I/O
NC
Note: These parameters are periodically sampled and not 100% tested.
Rev 1.2
2005-11-08 5/55
TC59LM818DMGI-37
RECOMMENDED DC OPERATING CONDITIONS
(V = 2.5 V ± 0.125 V, V
= 1.7 V ~ 1.9 V, T
= −40 ~ 100°C)
DD
DDQ
CASE
SYMBOL
PARAMETER
MAX
UNIT
NOTES
Operating Current
One bank read or write operation ;
= min; I = min, I = 0mA ;
t
CK
RC
OUT
I
I
I
220
1, 2
DD1S
DD2N
DD2P
Burst Length = 4, CAS Latency = 6, Free running QS mode ;
0 V ≤ V ≤ V (AC) (max), V (AC) (min) ≤ V ≤ V
,
DDQ
IN
IL
IH
IN
Address inputs change up to 2 times during minimum I
Read data change twice per clock cycle
,
RC
Standby Current
All banks: inactive state ;
t
= min, CS = V , PD = V
;
IH
CK
IH
95
1, 2
0 V ≤ V ≤ V (AC) (max), V (AC) (min) ≤ V ≤ V ;
DDQ
IN
IL
IH
IN
Other input signals change one time during 4 × t
,
CK
DQ and DS inputs change twice per clock cycle
Standby (power down) Current
All banks: inactive state ;
t
= min, PD = V (power down) ;
IL
CK
65
1, 2
CAS Latency = 6, Free running QS mode ;
0 V ≤ V ≤ V (AC) (max), V (AC) (min) ≤ V ≤ V ;
DDQ
IN
IL
IH
IN
Other input signals change one time during 4 × t
,
CK
DQ and DS inputs are floating (V
/2)
DDQ
mA
Write Operating Current (4Banks)
4 Bank interleaved continuous burst write operation ;
= min, I = min ;
t
CK
RC
I
I
I
420
420
220
1, 2
DD4W
DD4R
DD5B
Burst Length = 4, CAS Latency = 6, Free running QS mode ;
0 V ≤ V ≤ V (AC) (max), V (AC) (min) ≤ V ≤ V
Address inputs change once per clock cycle,
;
DDQ
IN
IL
IH
IN
DQ and DS inputs change twice per clock cycle
Read Operating Current (4Banks)
4 Bank interleaved continuous burst read operation ;
t
= min, I
= min, I
= 0mA ;
OUT
CK
RC
1, 2
Burst Length = 4, CAS Latency = 6, Free running QS mode ;
0 V ≤ V ≤ V (AC) (max), V (AC) (min) ≤ V ≤ V
;
DDQ
IN
IL
IH
IN
Address inputs change once per clock cycle,
Read data change twice per clock cycle
Burst Auto Refresh Current
Refresh command at every I
interval ;
REFC
t
= min; I
= min ;
REFC
CK
1, 2, 3
CAS Latency = 6, Free running QS mode ;
0 V ≤ V ≤ V (AC) (max), V (AC) (min) ≤ V ≤ V ,
DDQ
IN
IL
IH
IN
Address inputs change up to 2 times during minimum I
DQ and DS inputs change twice per clock cycle
,
REFC
Notes: 1. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of
, t and I
t
.
RC
CK RC
2. These parameters define the current between V
and V
.
SS
DD
3.
I
is specified under burst refresh condition. Actual system should use distributed refresh that meet to t
DD5B REFI
specification.
Rev 1.2
2005-11-08 6/55
TC59LM818DMGI-37
RECOMMENDED DC OPERATING CONDITIONS (continued)
(V = 2.5 V ± 0.125 V, V
= 1.7 V ~ 1.9 V, T = −40 ~ 100°C)
DD
DDQ
CASE
SYMBOL
PARAMETER
MIN
−5
MAX
UNIT
NOTES
Input Leakage Current
( 0 V ≤ V ≤ V , all other pins not under test = 0 V)
I
I
5
5
µA
LI
IN
DDQ
Output Leakage Current
−5
µA
µA
LO
(Output disabled, 0 V ≤ V
≤ V
)
OUT
DDQ
I
I
V
Current
REF
−5
5
REF
(DC)
V
V
V
V
V
V
= 1.420 V
= 0.280 V
= 1.420 V
= 0.280 V
= 1.420 V
= 0.280 V
−5.6
OH
OL
OH
OL
OH
OL
OH
OL
OH
OL
OH
OL
Normal Output
Driver
I
I
I
I
I
(DC)
(DC)
(DC)
(DC)
(DC)
5.6
−9.8
9.8
Output DC Current
(V = 1.7V~1.9V)
Strong Output
Driver
mA
1
DDQ
−2.8
2.8
Weak
Output Driver
Notes: 1. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Register.
Rev 1.2
2005-11-08 7/55
TC59LM818DMGI-37
AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2)
(V = 2.5 V ± 0.125V, V
= 1.7V ~ 1.9V, T = −40 ~ 100°C)
DD
DDQ
CASE
MIN
MAX
SYMBOL
PARAMETER
UNIT
NOTES
25
5.0
4.0
3.75
7.5
7.5
7.5
24
3
3
C
C
C
= 4
= 5
= 6
L
L
L
t
Clock Cycle Time
3
CK
3
t
t
t
t
t
t
t
Random Access Time
Clock High Time
3
RAC
CH
0.45 × t
3
CK
Clock Low Time
0.45 × t
3
CL
CK
QS Access Time from CLK
Data Output Skew from QS
Data Access Time from CLK
−0.6
0.6
0.3
0.65
0.65
3, 8
CKQS
QSQ
AC
−0.65
−0.65
3, 8
3, 8
Data Output Hold Time from CLK
OH
CLK half period
(minimum of Actual t , t
t
min (t , t
)
3
HP
CH CL
)
CH CL
t
t
t
t
t
t
t
t
QS (read) Pulse Width
t
− t
HP QHS
4, 8
4, 8
QSP
Data Output Valid Time from QS
DQ, QS Hold Skew factor
t
− t
HP QHS
QSQV
QHS
0.055 × t + 0.17
CK
ns
DS (write) Low to High Setup Time
DS (write) Preamble Pulse Width
DS First Input Setup Time
0.8 × t
1.2 × t
3
4
3
3
4
DQSS
DSPRE
DSPRES
DSPREH
DSP
CK
CK
0.4 × t
CK
0
DS First Low Input Hold Time
DS High or Low Input Pulse Width
0.3 × t
CK
0.45 × t
0.55 × t
CK
CK
C
= 4
= 5
= 6
1.0
3, 4
3, 4
3, 4
L
L
L
DS Input Falling Edge to Clock
Setup Time
t
C
C
1.0
1.0
DSS
t
t
DS (write) Postamble Pulse Width
0.45 × t
1.0
4
3, 4
3, 4
3, 4
4
DSPST
CK
C
L
C
L
C
L
= 4
= 5
= 6
DS (write) Postamble Hold
Time
1.0
DSPSTH
1.0
t
t
t
t
Data Input Setup Time from DS
Data Input Hold Time from DS
0.4
DS
DH
IS
0.4
4
Command/Address Input Setup Time
Command/Address Input Hold Time
0.7
3
0.7
3
IH
Rev 1.2
2005-11-08 8/55
TC59LM818DMGI-37
AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2) (continued)
MIN
MAX
SYMBOL
PARAMETER
UNIT
NOTES
3,6,8
t
t
Data-out Low Impedance Time from CLK
−0.65
LZ
Data-out High Impedance Time from CLK
0.65
3,7,8
HZ
ns
t
t
t
t
t
Last output to PD High Hold Time
Power Down Exit Time
0
0.7
0.1
0.4
200
5
QPDH
PDEX
T
3
5
Input Transition Time
1
Auto-Refresh Average Interval
Pause Time after Power-up
1.95
REFI
PAUSE
µs
C
L
C
L
C
L
= 4
= 5
= 6
Random Read/Write Cycle
Time
(applicable to same bank)
I
6
RC
7
RDA/WRA to LAL Command Input Delay
(applicable to same bank)
I
I
1
1
RCD
RAS
C
L
C
L
C
L
= 4
= 5
= 6
4
5
6
LAL to RDA/WRA Command
Input Delay
(applicable to same bank)
Random Bank Access Delay
(applicable to other bank)
I
I
I
2
RBD
RWD
WRD
B
= 2
= 4
2
3
LAL following RDA to WRA
Delay
(applicable to other bank)
L
L
B
LAL following WRA to RDA Delay
(applicable to other bank)
1
cycle
C
= 4
= 5
= 6
7
2
L
L
L
I
Mode Register Set Cycle Time
C
C
7
RSC
7
I
I
PD Low to Inactive State of Input Buffer
PD High to Active State of Input Buffer
1
PD
PDA
C
L
C
L
C
L
C
L
C
L
C
L
= 4
= 5
= 6
= 4
= 5
= 6
19
23
25
19
23
25
Power down mode valid from
REF command
I
PDV
I
I
Auto-Refresh Cycle Time
REFC
LOCK
DLL Lock-on Time
(applicable to RDA command)
200
Rev 1.2
2005-11-08 9/55
TC59LM818DMGI-37
AC TEST CONDITIONS
SYMBOL
PARAMETER
Input High Voltage (minimum)
VALUE
UNIT
NOTES
V
V
V
V
V
V
V
+ 0.2
V
V
IH (min)
IL (max)
REF
REF
REF
Input Low Voltage (maximum)
Input Reference Voltage
− 0.2
/2
V
V
DDQ
Termination Voltage
V
V
TT
REF
Input Signal Peak to Peak Swing
Differential Clock Input Reference Level
Input Differential Voltage
0.8
V
SWING
Vr
V
(AC)
V
X
V
(AC)
1.0
V
ID
SLEW
Input Signal Minimum Slew Rate
Output Timing Measurement Reference Voltage
2.5
V/ns
V
V
V
/2
9
OTR
DDQ
V
DDQ
V
V
(AC)
(AC)
IH min
REF
V
TT
25 Ω
V
SWING
Output
V
IL max
Measurement point
V
SS
∆T
∆T
(AC))/∆T
AC Test Load
SLEW = (V
(AC) − V
IL max
IH min
Note:
(1) Transition times are measured between V
(DC) and V
IL max
(DC).
IH min
Transition (rise and fall) of input signals have a fixed slope.
(2) If the result of nominal calculation with regard to t
rounded up to the nearest decimal place.
contains more than one decimal place, the result is
CK
(i.e., t
DSP(min)
= 0.45 × t , t = 3.75 ns, 0.45 × 3.75 ns = 1.6875 ns is rounded up to 1.7 ns.)
CK CK
(3) These parameters are measured from the differential clock (CLK and CLK ) AC cross point.
(4) These parameters are measured from signal transition point of DS crossing V
REF
level.
(5) The t
The t
applies to equally distributed refresh method.
applies to both burst refresh method and distributed refresh method.
REFI (max)
REFI (min)
In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400 ns
always. In other words, the number of Auto-Refresh cycles which can be performed within 3.2 µs (8 × 400 ns)
is to 8 times in the maximum.
(6) Low Impedance State is specified at V /2 ± 0.1 V from steady state.
DDQ
(7) High Impedance State is specified where output buffer is no longer driven.
(8) These parameters depend on the clock jitter. These parameters are measured at stable clock.
(9) Output timing is measured by using Normal driver strength at VDDQ = 1.7 ∼ 1.9V.
Rev 1.2
2005-11-08 10/55
TC59LM818DMGI-37
POWER UP SEQUENCE
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
As for PD , being maintained by the low state (≤ 0.2 V) is desirable before a power-supply injection.
Apply V
Apply V
before or at the same time as V
.
DD
DDQ
before or at the same time as V
.
DDQ
REF
Start clock (CLK, CLK ) and maintain stable condition for 200 µs (min).
After stable power and clock, apply DESL and take PD =H.
Issue EMRS to enable DLL and to define driver strength and data strobe type. (Note: 1)
Issue MRS for set CAS latency (CL), Burst Type (BT), and Burst Length (BL). (Note: 1)
Issue two or more Auto-Refresh commands (Note: 1).
Ready for normal operation after 200 clocks from Extended Mode Register programming.
Notes:
(1)
Sequence 6, 7 and 8 can be issued in random order.
L = Logic Low, H = Logic High
(2)
(3)
DQ output is Hi-Z state during power upsequence.
2.5V(TYP)
1.8V(TYP)
V
DD
V
DDQ
1/2 V
(TYP)
DDQ
V
REF
CLK
CLK
t
PDEX
l
l
l
l
REFC
RSC
RSC
REFC
200us(min)
PD
l
= 200clock cycle(min)
LOCK
l
PDA
Command
DESLRDA MRS DESL RDA MRS
DESL WRA REF DESL
WRA REF DESL
op-code
EMRS
op-code
Address
MRS
DQ
(Input)
DS
QS
Low
(Uni-QS mode)
QS
(Free Running mode)
EMRS
MRS
Auto Refresh cycle
Normal Operation
Rev 1.2
2005-11-08 11/55
TC59LM818DMGI-37
TIMING DIAGRAMS
Input Timing
Command and Address
t
CK
t
t
t
CL
CK
CH
CLK
CLK
t
t
t
t
t
t
t
t
t
t
t
t
IS
IS
IS
IH
IH
IH
IS
IS
IS
IH
IH
IH
CS
FN
1st
1st
2nd
2nd
LA
A0~A14
UA, BA
BA0, BA1
Data
DS
t
t
t
t
DH
DH
DS
DH
DS
DQn (input)
DQm (input)
t
t
t
DH
t
DS
DS
Refer to the Command Truth Table.
Timing of the CLK,
CLK
t
t
CL
CH
V
V
IH
IH
CLK
(AC)
(AC)
V
V
IL
IL
CLK
t
t
T
T
t
CK
CLK
CLK
V
V
IH
IL
V
(AC)
ID
V
V
V
X
X
X
Rev 1.2
2005-11-08 12/55
TC59LM818DMGI-37
Read Timing (Burst Length = 4)
Unidirectional DS/QS mode
t
t
t
CK
CH
CL
CLK
CLK
t
t
IS IH
LAL (after RDA)
Input
(control &
DESL
addresses)
DS
(Input)
t
t
CKQS
CKQS
t
t
t
CKQS QSP QSP
CAS latency = 4
QS
Low
Low
(output)
t
t
t
QSQ
QSQV
LZ
t
t
t
t
HZ
QSQ QSQ QSQV
DQ
Hi-Z
Q0
Q1
Q2
Q3
(output)
t
t
t
OH
t
AC
AC
AC
t
t
CKQS
CKQS
t
t
t
CKQS
QSP QSP
CAS latency = 5
QS
Low
Low
Hi-Z
(output)
t
t
QSQV
t
LZ
QSQ
t
t
t
t
HZ
QSQ QSQ QSQV
DQ
Q0
Q1
Q2
Q3
(output)
t
t
t
OH
AC
t
AC
AC
t
t
CKQS
CKQS
t
t
t
CKQS QSP QSP
CAS latency = 6
QS
(output)
Low
Hi-Z
Low
t
t
t
QSQ
LZ
QSQV
t
t
t
t
HZ
QSQ QS
QSQV
Q2
DQ
Q0
Q1
Q3
AC
(output)
t
t
t
t
OH
AC
AC
Note: DQ0 to DQ17 are aligned with QS.
Rev 1.2
2005-11-08 13/55
TC59LM818DMGI-37
Read Timing (Burst Length = 4)
Unidirectional DS/Free Running QS mode
t
t
t
CK
CH
CL
CLK
CLK
t
t
IS IH
LAL (after RDA)
Input
(control &
DESL
addresses)
DS
(Input)
t
t
CKQS
CKQS
t
t
t
QSP QSP
CKQS
CAS latency = 4
QS
(output)
t
t
t
LZ
QSQV
QSQ
Q3
t
t
t
t
QSQ
Q0
t
QSQV
HZ
QSQ
DQ
(output)
Hi-Z
Q1
Q2
t
t
AC
t
AC
AC
OH
t
t
CKQS
CKQS
t
t
t
QSP QSP
CKQS
CAS latency = 5
QS
(output)
t
t
t
QSQ
LZ
QSQV
t
t
HZ
t
t
QSQV
QSQ QSQ
DQ
(output)
Hi-Z
Q0
Q1
Q2
Q3
t
t
t
AC
AC
AC
t
OH
t
t
CKQS
CKQS
t
t
t
QSP QSP
CKQS
CAS latency = 6
QS
(output)
t
t
t
QSQV
QSQ
LZ
t
t
HZ
t
t
QSQV
QSQ QSQ
DQ
(output)
Hi-Z
Q0
Q1
Q2
Q3
t
t
t
AC
AC
AC
t
OH
Note: DQ0 to DQ17 are aligned with QS.
QS is always asserted in Free Running QS mode.
Rev 1.2
2005-11-08 14/55
TC59LM818DMGI-37
Write Timing (Burst Length = 4)
Unidirectional DS/QS mode, Unidirectional DS/Free Running QS mode
t
t
t
CK
CH
CL
CLK
CLK
t
t
IS IH
LAL (after WRA)
Input
(control &
DESL
addresses)
t
DSPSTH
t
DQSS
t
DSS
t
DSPRES
t
t
t
t
DSP DSP DSP DSPST
t
DSPREH
CAS latency = 4
DS
(input)
t
Preamble
Postamble
DSS
t
DSPRE
t
t
DS
t
DS
DS
t
t
DH
t
DH
DH
DQ
D0
D1
D2
D3
(input)
t
DQSS
t
DSS
t
t
DSPSTH
DSS
t
DSPRES
t
t
t t
DSP DSP DSPST
CAS latency = 5
DSP
t
DSPREH
DS
(input)
Preamble
Postamble
t
DSPRE
t
t
DS
t
DS
DS
t
t
t
DH
DH
DH
DQ
D3
D0
D1
D2
(input)
t
t
DQSS
DQSS
t
DSS
t
t
DSPSTH
DSS
t
DSPRES
t
t
t
t
t
DSP DSP DSP DSPST
CAS latency = 6
t
DSPREH
DS
(input)
Preamble
Postamble
t
DSPRE
t
t
DS
DS
DS
t
t
t
DH
DH
DH
DQ
D3
D0
D1
D2
(input)
t
t
DQSS
DQSS
QS
(Uni-QS)
Low
QS
(Free Runninig)
Note: DQ0 to DQ17 are sampled at both edges of DS.
Rev 1.2
2005-11-08 15/55
TC59LM818DMGI-37
t
, t
, I
Timing
REFI PAUSE XXXX
CLK
CLK
t
, t
,
REFI PAUSE
t
t
t
t
IS IH
IS IH
Input
(control &
addresses)
Command
Command
Note: “I
” means “I ”, “I
”, “I
”, etc.
RAS
XXXX
RC
RCD
Rev 1.2
2005-11-08 16/55
TC59LM818DMGI-37
FUNCTION TRUTH TABLE (Notes: 1, 2, 3)
Command Truth Table (Notes: 4)
• The First Command
SYMBOL
FUNCTION
Device Deselect
CS
FN
BA1~BA0
A14~A9
A8
A7
A6~A0
DESL
RDA
H
L
L
×
H
L
×
×
×
×
×
Read with Auto-close
Write with Auto-close
BA
BA
UA
UA
UA
UA
UA
UA
UA
UA
WRA
• The Second Command (The next clock of RDA or WRA command)
BA1~
BA0
A14~
A13
A12~
A11
SYMBOL
FUNCTION
CS
FN
A10~A9
A8
A7
A6~A0
LAL
REF
MRS
Lower Address Latch
Auto-Refresh
H
L
L
×
×
×
×
×
V
×
L
×
×
L
×
×
L
×
×
L
×
×
LA
×
Mode Register Set
V
V
V
Notes: 1. L = Logic Low, H = Logic High, × = either L or H, V = Valid (specified value), BA = Bank Address, UA = Upper Address,
LA = Lower Address
2. All commands are assumed to issue at a valid state.
3. All inputs for command (excluding PDEX) are latched on the crossing point of differential clock input where CLK goes to
High.
4. Operation mode is decided by the combination of 1st command and 2nd command. Refer to “STATE DIAGRAM” and
the command table below.
Read Command Table
COMMAND (SYMBOL)
CS
FN
BA1~BA0
A14~A9
A8
A7
A6~A0
NOTES
RDA (1st)
LAL (2nd)
L
H
BA
UA
UA
UA
UA
LA
H
×
×
×
×
×
Write Command Table
BA1~
BA0
A10~
A9
COMMAND(SYMBOL)
CS
FN
A14
A13
A12
A11
A8
A7
A6~A0
WRA (1st)
LAL (2nd)
L
L
BA
UA
UA
UA
UA
UA
UA
UA
UA
LA
H
×
×
VW0
VW1
×
×
×
×
×
Notes: 5. A14~ A13 are used for Variable Write Length (VW) control at Write Operation.
VW Truth Table
Burst Length
Function
Write All Words
VW0
VW1
L
H
L
×
×
BL=2
Write First One Word
Reserved
L
Write All Words
H
L
L
BL=4
Write First Two Words
Write First One Word
H
H
H
Rev 1.2
2005-11-08 17/55
TC59LM818DMGI-37
FUNCTION TRUTH TABLE (continued)
Mode Register Set Command Table
COMMAND (SYMBOL)
CS
FN
BA1~BA0
A14~A9
A8
A7
A6~A0
NOTES
6
RDA (1st)
L
L
H
×
×
×
×
×
MRS (2nd)
×
V
L
L
V
V
Notes: 6. Refer to “MODE REGISTER TABLE”.
Auto-Refresh Command Table
PD
COMMAND CURRENT
FUNCTION
CS
FN BA1~BA0 A14~A9 A8
A7 A6~A0 NOTES
(SYMBOL)
STATE
n − 1
H
n
H
H
Active
WRA (1st)
REF (2nd)
Standby
Active
L
L
L
×
×
×
×
×
×
×
×
×
×
Auto-Refresh
H
×
Power Down Table
PD
COMMAND CURRENT
FUNCTION
CS
FN BA1~BA0 A14~A9 A8
A7 A6~A0 NOTES
(SYMBOL)
STATE
n − 1
n
L
Power Down Entry
Power Down Continue
Power Down Exit
PDEN
Standby
H
L
L
H
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
7
8
Power Down
Power Down
L
PDEX
H
H
Notes: 7. PD should be brought to Low after DQ’s state turned high impedance.
8. When PD is brought to High from Low, this function is executed asynchronously.
Rev 1.2
2005-11-08 18/55
TC59LM818DMGI-37
FUNCTION TRUTH TABLE (continued)
PD
CURRENT STATE
CS FN
ADDRESS COMMAND
ACTION
NOTES
n − 1
H
H
H
H
H
L
n
H
H
H
L
H
L
×
H
L
×
×
×
×
×
×
×
×
×
×
×
×
×
×
H
L
×
×
×
×
DESL
RDA
WRA
PDEN
NOP
BA, UA
Row activate for Read
Row activate for Write
Power Down Entry
Illegal
L
BA, UA
Idle
H
L
×
10
L
×
×
×
×
Refer to Power Down State
Begin Read
H
H
H
H
L
H
H
L
H
L
LA
LAL
Op-code
MRS/EMRS Access to Mode Register
PDEN Illegal
MRS/EMRS Illegal
Row Active for Read
Row Active for Write
H
L
×
L
×
×
×
×
LAL
REF
PDEN
REF
Invalid
H
H
H
H
L
H
H
L
H
L
LA
Begin Write
×
Auto-Refresh
H
L
×
Illegal
L
×
Illegal
×
×
×
Invalid
H
H
H
H
H
L
H
H
H
L
H
L
×
DESL
RDA
WRA
PDEN
Continue Burst Read to End
BA, UA
Illegal
Illegal
Illegal
Illegal
Invalid
11
11
L
BA, UA
Read
H
L
×
×
×
L
×
×
Data Write&Continue Burst Write to
End
H
H
H
×
×
DESL
H
H
H
H
L
H
H
L
L
L
H
L
×
H
L
L
H
L
×
H
L
L
H
L
×
×
×
H
L
×
×
×
×
H
L
×
×
×
×
H
L
×
×
×
×
×
BA, UA
RDA
WRA
PDEN
Illegal
Illegal
Illegal
Illegal
Invalid
11
11
BA, UA
Write
×
L
×
×
×
H
H
H
H
H
L
H
H
H
L
×
DESL
RDA
WRA
PDEN
NOP → Idle after I
Illegal
REFC
BA, UA
BA, UA
Illegal
Auto-Refreshing
×
Illegal
L
×
Illegal
×
×
Illegal
H
H
H
H
H
L
H
H
H
L
×
DESL
RDA
WRA
PDEN
NOP → Idle after I
Illegal
RSC
BA, UA
BA, UA
Illegal
Mode Register
Accessing
×
×
×
×
×
Illegal
L
Illegal
×
Invalid
H
L
×
Invalid
L
Maintain Power Down Mode
Power Down
Exit Power Down Mode → Idle after
L
L
H
H
H
L
×
×
×
×
PDEX
t
PDEX
Illegal
Notes: 10. Illegal if any bank is not idle.
11. Illegal to bank in specified states; Function may be legal in the bank inidicated by Bank Address (BA).
Rev 1.2
2005-11-08 19/55
TC59LM818DMGI-37
MODE REGISTER TABLE
Regular Mode Register (Notes: 1)
*1
*1
*3
ADDRESS
Register
BA1
BA0
A14~A8
0
A7
A6~A4
CL
A3
BT
A2~A0
BL
0
0
TE
A7
TEST MODE (TE)
A3
BURST TYPE (BT)
0
1
Regular (default)
Test Mode Entry
0
1
Sequential
Interleave
A6
A5
A4
CAS LATENCY (CL)
A2
A1
A0
BURST LENGTH (BL)
*2
*2
0
0
0
1
1
1
1
0
1
1
0
0
1
1
×
0
1
0
1
0
1
Reserved
0
0
0
0
1
0
0
1
1
×
0
1
0
1
×
Reserved
*2
Reserved
2
4
*2
Reserved
4
5
6
*2
Reserved
*2
Reserved
Extended Mode Register (Notes: 4)
*4
*4
*5
ADDRESS
Register
BA1
BA0
A14~A7
0
A6~A5
SS
A4~A3
A2~A1
A0
0
1
DIC (QS)
DIC (DQ)
DS
QS
DQ
OUTPUT DRIVE IMPEDANCE CONTROL
(DIC)
A6 A5
STROBE SELECT
A4 A3 A2 A1
*2
0
0
1
1
0
Reserved
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
Normal Output Driver
Strong Output Driver
Weak Output Driver
Reserved
*2
1
0
1
Reserved
Unidirectional DS/QS
Unidirectional DS/Free Running QS
A0
DLL SWITCH (DS)
0
1
DLL Enable
DLL Disable
Notes: 1. Regular Mode Register is chosen using the combination of BA0 = 0 and BA1 = 0.
2. “Reserved” places in Regular Mode Register should not be set.
3. A7 in Regular Mode Register must be set to “0” (low state).
Because Test Mode is specific mode for supplier.
4. Extended Mode Register is chosen using the combination of BA0 = 1 and BA1 = 0.
5. A0 in Extended Mode Register must be set to "0" to enable DLL for normal operation.
Rev 1.2
2005-11-08 20/55
TC59LM818DMGI-37
STATE DIAGRAM
POWER
DOWN
PDEX
( PD = H)
PDEN
( PD = L)
STANDBY
(IDLE)
PD = H
AUTO-
REFRESH
MODE
REGISTER
WRA
RDA
REF
MRS
ACTIVE
(RESTORE)
ACTIVE
LAL
LAL
WRITE
(BUFFER)
READ
Command input
Automatic return
The second command at Active state
must be issued 1 clock after RDA or
WRA command input.
Rev 1.2
2005-11-08 21/55
TC59LM818DMGI-37
TIMING DIAGRAMS
SINGLE BANK READ TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 5 cycles
I
= 5 cycles
RC
I
= 5 cycles
RC
RC
Command
RDA LAL
=1 cycle
DESL
RDA LAL
DESL
RDA LAL
DESL
RDA
I
I
= 4 cycles
I
=1 cycle
I
= 4 cycles
I
=1 cycle
I
= 4 cycles
RAS
RCD
RAS
RCD
RAS
RCD
Address
UA
#0
LA
UA
#0
LA
UA
#0
LA
UA
#0
Bank Add.
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
Low
(output)
CL = 4
CL = 4
CL = 4
DQ
(output)
Hi-Z
Q0 Q1
Q0 Q1
Q0
BL = 4
DS
(input)
QS
(output)
Low
Hi-Z
CL = 4
CL = 4
CL = 4
DQ
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Q0
(output)
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
CL = 4
CL = 4
CL = 4
DQ
Hi-Z
Q0 Q1
Q0 Q1
Q0
(output)
BL = 4
DS
(input)
QS
(output)
CL = 4
CL = 4
CL = 4
DQ
Hi-Z
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Q0
(output)
Rev 1.2
2005-11-08 22/55
TC59LM818DMGI-37
SINGLE BANK READ TIMING (CL = 5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 6 cycles
I
= 6 cycles
RC
RC
Command
RDA LAL
DESL
RDA LAL
DESL
RDA LAL
DESL
I
=1 cycle
I
= 5 cycles
I
=1 cycle
I
= 5 cycles
I
=1 cycle
RCD
UA
RAS
RCD
RAS
RCD
UA
Address
LA
UA
#0
LA
LA
Bank Add.
#0
#0
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
CL = 5
CL = 5
DQ
Hi-Z
Q0 Q1
Q0 Q1
(output)
BL = 4
DS
(input)
QS
Low
Hi-Z
(output)
CL = 5
CL = 5
DQ
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
(output)
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
CL = 5
CL = 5
DQ
(output)
Hi-Z
Q0 Q1
Q0 Q1
BL = 4
DS
(input)
QS
(output)
CL = 5
CL = 5
DQ
(output)
Hi-Z
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Rev 1.2
2005-11-08 23/55
TC59LM818DMGI-37
SINGLE BANK READ TIMING (CL = 6)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 7 cycles
I
= 7 cycles
RC
RC
Command
RDA LAL
DESL
= 6 cycles
RDA LAL
DESL
RDA LAL
I
=1 cycle
I
I
=1 cycle
I
= 6 cycles
I
=1 cycle
RCD
UA
RAS
RCD
RAS
RCD
UA
Address
LA
UA
#0
LA
LA
Bank Add.
#0
#0
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
CL = 6
CL = 6
DQ
Hi-Z
Q0 Q1
Q0 Q1
(output)
BL = 4
DS
(input)
QS
Low
Hi-Z
(output)
CL = 6
CL = 6
DQ
Q0 Q1 Q2 Q3
Q0 Q1 Q2
(output)
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
CL = 6
CL = 6
DQ
(output)
Hi-Z
Q0 Q1
Q0 Q1
BL = 4
DS
(input)
QS
(output)
CL = 6
CL = 6
DQ
(output)
Hi-Z
Q0 Q1 Q2 Q3
Q0 Q1 Q2
Rev 1.2
2005-11-08 24/55
TC59LM818DMGI-37
SINGLE BANK WRITE TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 5 cycles
I
= 5 cycles
RC
I
= 5 cycles
RC
RC
Command
WRA LAL
DESL
WRA LAL
DESL
WRA LAL
DESL
WRA
I
=1 cycle
I
= 4 cycles
I
=1 cycle
I
= 4 cycles
I
=1 cycle
I
= 4 cycles
RAS
RCD
UA
RAS
RCD
RAS
RCD
Address
LA
UA
#0
LA
UA
#0
LA
UA
#0
Bank Add.
#0
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
WL = 3
WL = 3
WL = 3
DQ
(input)
D0 D1
D0 D1
D0 D1
BL = 4
DS
(input)
QS
Low
(output)
WL = 3
WL = 3
WL = 3
DQ
D0 D1 D2 D3
D0 D1 D2 D3
D0 D1 D2 D3
(input)
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
WL = 3
WL = 3
WL = 3
DQ
D0 D1
D0 D1
D0 D1
(input)
BL = 4
DS
(input)
QS
(output)
WL = 3
WL = 3
WL = 3
DQ
D0 D1 D2 D3
D0 D1 D2 D3
D0 D1 D2 D3
(input)
Rev 1.2
2005-11-08 25/55
TC59LM818DMGI-37
SINGLE BANK WRITE TIMING (CL = 5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 6 cycles
I
= 6 cycles
RC
RC
Command
WRA LAL
DESL
WRA LAL
DESL
WRA LAL
DESL
I
=1 cycle
I
= 5 cycles
I
=1 cycle
I
= 5 cycles
I
=1 cycle
RCD
UA
RAS
RCD
UA
RAS
RCD
UA
Address
LA
LA
LA
Bank Add.
#0
#0
#0
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
Low
(output)
WL = 4
WL = 4
DQ
D0 D1
D0 D1
(input)
BL = 4
DS
(input)
QS
(output)
Low
WL = 4
WL = 4
DQ
D0 D1 D2 D3
D0 D1 D2 D3
(input)
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
WL = 4
WL = 4
DQ
D0 D1
D0 D1
(input)
BL = 4
DS
(input)
QS
(output)
WL = 4
WL = 4
DQ
(input)
D0 D1 D2 D3
D0 D1 D2 D3
Rev 1.2
2005-11-08 26/55
TC59LM818DMGI-37
SINGLE BANK WRITE TIMING (CL = 6)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 7 cycles
I
= 7 cycles
RC
RC
Command
WRA LAL
DESL
WRA LAL
DESL
WRA LAL
I
=1 cycle
I
= 6 cycles
I
=1 cycle
I
= 6 cycles
I =1 cycle
RCD
RCD
UA
RAS
RCD
RAS
Address
LA
UA
#0
LA
UA
#0
LA
Bank Add.
#0
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
WL = 5
WL = 5
DQ
(input)
D0 D1
D0 D1
BL = 4
DS
(input)
QS
Low
(output)
WL = 5
WL = 5
DQ
(input)
D0 D1 D2 D3
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
WL = 5
WL = 5
DQ
(input)
D0 D1
D0 D1
BL = 4
DS
(input)
QS
(output)
WL = 5
WL = 5
DQ
D0 D1 D2 D3
D0 D1 D2 D3
(input)
Rev 1.2
2005-11-08 27/55
TC59LM818DMGI-37
SINGLE BANK READ-WRITE TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 5 cycles
I
= 5 cycles
RC
I
= 5 cycles
RC
RC
Command
Address
RDA LAL
DESL
WRA LAL
DESL
RDA LAL
DESL
WRA
UA
UA
#0
LA
UA
#0
LA
UA
#0
LA
Bank Add.
#0
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
CL = 4
WL = 3
CL = 4
Hi-Z
DQ
Q0 Q1
D0 D1
Q0
BL = 4
DS
(input)
QS
Low
(output)
CL = 4
WL = 3
CL = 4
Hi-Z
DQ
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Q0
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
CL = 4
WL = 3
CL = 4
Hi-Z
DQ
Q0 Q1
D0 D1
Q0
BL = 4
DS
(input)
QS
(output)
CL = 4
WL = 3
CL = 4
Hi-Z
DQ
Q0 Q1 Q2 Q3
Read data
D0 D1 D2 D3
Write data
Q0
Rev 1.2
2005-11-08 28/55
TC59LM818DMGI-37
SINGLE BANK READ-WRITE TIMING (CL = 5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 6 cycles
I
= 6 cycles
RC
RC
Command
Address
RDA LAL
DESL
WRA LAL
DESL
RDA LAL
DESL
UA
#0
LA
UA
#0
LA
UA
#0
LA
Bank Add.
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
CL = 5
WL = 4
Hi-Z
DQ
Q0 Q1
D0 D1
BL = 4
DS
(input)
QS
Low
(output)
WL = 4
CL = 5
Hi-Z
DQ
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
CL = 5
WL = 4
Hi-Z
DQ
Q0 Q1
D0 D1
BL = 4
DS
(input)
QS
(output)
WL = 4
CL = 5
Hi-Z
DQ
Q0 Q1 Q2 Q3
Read data
D0 D1 D2 D3
Write data
Rev 1.2
2005-11-08 29/55
TC59LM818DMGI-37
SINGLE BANK READ-WRITE TIMING (CL = 6)
0
1
2
3
4
5
6
7
8
9
10
I
11
12
13
14
15
CLK
CLK
= 7 cycles
I
= 7 cycles
RC
RC
Command
Address
RDA LAL
DESL
WRA LAL
DESL
RDA LAL
UA
#0
LA
UA
#0
LA
UA
#0
LA
Bank Add.
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
CL = 6
WL = 5
Hi-Z
DQ
Q0 Q1
D0 D1
BL = 4
DS
(input)
QS
Low
(output)
WL = 5
CL = 6
Hi-Z
DQ
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
CL = 6
WL = 5
Hi-Z
DQ
Q0 Q1
D0 D1
BL = 4
DS
(input)
QS
(output)
WL = 5
CL = 6
DQ
(output)
Hi-Z
Q0 Q1 Q2 Q3
Read data
D0 D1 D2 D3
Write data
Rev 1.2
2005-11-08 30/55
TC59LM818DMGI-37
MULTIPLE BANK READ TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
I
= 2 cycles I
= 2 cyclesI
= 2 cycles I
= 2 cycles
RBD
RBD
RBD
RBD
RBD
Command
Address
RDA LAL RDA LAL DESL RDA LAL RDA LAL RDA LAL RDA LAL RDA LAL RDA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank Add.
I
(Bank"a") = 5 cycles
RC
I
(Bank"b") = 5 cycles
RC
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
Low
(output)
CL = 4
CL = 4
DQ
Hi-Z
Qa0Qa1
Qb0Qb1
Qa0Qa1
Qb0Qb1
Qc0Qc1
(output)
BL = 4
DS
(input)
QS
Low
Hi-Z
(output)
CL = 4
CL = 4
DQ
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3Qc0Qc1Qc2
(output)
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
CL = 4
CL = 4
Hi-Z
DQ
(output)
Qa0Qa1
Qb0Qb1
Qa0Qa1
Qb0Qb1
Qc0Qc1
BL = 4
DS
(input)
QS
(output)
CL = 4
CL = 4
DQ
Hi-Z
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3Qc0Qc1Qc2
(output)
Note: l
to the same bank must be satisfied.
RC
Rev 1.2
2005-11-08 31/55
TC59LM818DMGI-37
MULTIPLE BANK READ TIMING (CL = 5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
I
= 2 cycles I
= 2 cycles I
= 2 cycles I
= 2 cycles
RBD
RBD
RBD
RBD
RBD
Command
Address
RDA LAL RDA LAL
DESL
RDA LAL RDA LAL RDA LAL RDA LAL RDA LAL
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank Add.
I
(Bank"a") = 6 cycles
RC
I
(Bank"b") = 6 cycles
RC
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
CL = 5
CL = 5
DQ
(output)
Hi-Z
Qa0Qa1
Qb0Qb1
Qa0Qa1
Qb0Qb1
BL = 4
DS
(input)
QS
(output)
Low
Hi-Z
CL = 5
CL = 5
DQ
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
Qa0Qa1Qa2Qa3Qb0Qb1Qb2
(output)
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
CL = 5
CL = 5
DQ
Hi-Z
Qa0Qa1
Qb0Qb1
Qa0Qa1
Qb0Qb1
(output)
BL = 4
DS
(input)
QS
(output)
CL = 5
CL = 5
DQ
Hi-Z
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
Qa0Qa1Qa2Qa3Qb0Qb1Qb2
(output)
Note: l
to the same bank must be satisfied.
RC
Rev 1.2
2005-11-08 32/55
TC59LM818DMGI-37
MULTIPLE BANK READ TIMING (CL = 6)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
I
= 2 cycles I
= 2 cycles I
= 2 cycles I
= 2 cycles
RBD
RBD
RBD
RBD
RBD
Command
Address
RDA LAL RDA LAL
DESL
RDA LAL RDA LAL RDA LAL RDA LAL RDA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank Add.
I
(Bank"a") = 7 cycles
RC
I
(Bank"b") = 7 cycles
RC
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
CL = 6
CL = 6
DQ
Hi-Z
Qa0Qa1
Qb0Qb1
Qa0Qa1
(output)
BL = 4
DS
(input)
QS
Low
Hi-Z
(output)
CL = 6
CL = 6
DQ
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
Qa0Qa1Qa2
(output)
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
CL = 6
CL = 6
DQ
Hi-Z
Qa0Qa1
Qb0Qb1
Qa0Qa1
(output)
BL = 4
DS
(input)
QS
(output)
CL = 6
CL = 6
DQ
(output)
Hi-Z
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
Qa0Qa1Qa2
Rev 1.2
2005-11-08 33/55
TC59LM818DMGI-37
MULTIPLE BANK WRITE TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
I
= 2 cycles I
= 2 cycles I
= 2 cycles I
= 2 cycles
RBD
RBD
RBD
RBD
RBD
Command
Address
WRA LAL WRA LAL DESL WRA LAL WRA LAL WRA LAL WRA LAL WRA LAL WRA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
Bank Add.
I
(Bank"a") = 5 cycles
(Bank"b") = 5 cycles
RC
I
RC
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
WL = 3
WL = 3
DQ
Da0Da1
Db0Db1
Da0Da1
Db0Db1
Dc0Dc1
Dd0Dd1
(input)
BL = 4
DS
(input)
QS
Low
(output)
WL = 3
WL = 3
DQ
Da0Da1Da2Da3Db0Db1Db2Db3
Da0Da1Da2Da3Db0Db1Db2Db3Dc0Dc1Dc2Dc3Dd0Dd1
(input)
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
WL = 3
WL = 3
DQ
(input)
Da0Da1
Db0Db1
Da0Da1
Db0Db1
Dc0Dc1
Dd0Dd1
BL = 4
DS
(input)
QS
(output)
WL = 3
WL = 3
DQ
Da0Da1Da2Da3Db0Db1Db2Db3
Da0Da1Da2Da3Db0Db1Db2Db3Dc0Dc1Dc2Dc3Dd0Dd1
(input)
Note: l
to the same bank must be satisfied.
RC
Rev 1.2
2005-11-08 34/55
TC59LM818DMGI-37
MULTIPLE BANK WRITE TIMING (CL = 5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
I
= 2 cycles I
= 2 cycles I
= 2 cycles I
= 2 cycles
RBD
RBD
RBD
RBD
RBD
LAL
LA
Command
Address
WRA LAL WRA LAL
DESL
WRA LAL WRA LAL WRA LAL WRA LAL WRA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank Add.
I
(Bank"a") = 6 cycles
RC
I
(Bank"b") = 6 cycles
RC
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
Low
(output)
WL = 4
WL = 4
DQ
(input)
Da0Da1
Db0Db1
Da0Da1
Db0Db1
Dc0Dc1
BL = 4
DS
(input)
QS
Low
(output)
WL = 4
WL = 4
DQ
Da0Da1Da2Da3Db0Db1Db2Db3
Da0Da1Da2Da3Db0Db1Db2Db3Dc0Dc1
(input)
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
WL = 4
WL = 4
DQ
Da0Da1
Db0Db1
Da0Da1
Db0Db1
Dc0Dc1
(input)
BL = 4
DS
(input)
QS
(output)
WL = 4
WL = 4
DQ
Da0Da1Da2Da3Db0Db1Db2Db3
Da0Da1Da2Da3Db0Db1Db2Db3Dc0Dc1
(input)
Note: l
to the same bank must be satisfied.
RC
Rev 1.2
2005-11-08 35/55
TC59LM818DMGI-37
MULTIPLE BANK WRITE TIMING (CL = 6)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
I
= 2 cycles I
= 2 cycles I
= 2 cycles I
= 2 cycles
RBD
RBD
RBD
RBD
RBD
Command
Address
WRA LAL WRA LAL
DESL
WRA LAL WRA LAL WRA LAL WRA LAL WRA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank Add.
I
(Bank"a") = 7 cycles
RC
I
(Bank"b") = 7 cycles
RC
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
Low
(output)
WL = 5
WL = 5
DQ
Da0Da1
Db0Db1
Da0Da1
Db0Db1
(input)
BL = 4
DS
(input)
QS
Low
(output)
WL = 5
WL = 5
DQ
Da0Da1Da2Da3Db0Db1Db2Db3
Da0Da1Da2Da3Db0Db1
(input)
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
WL = 5
WL = 5
DQ
Da0Da1
Db0Db1
Da0Da1
Db0Db1
(input)
BL = 4
DS
(input)
QS
(output)
WL = 5
WL = 5
DQ
(input)
Da0Da1Da2Da3Db0Db1Db2Db3
Da0Da1Da2Da3Db0Db1
Note: l
to the same bank must be satisfied.
RC
Rev 1.2
2005-11-08 36/55
TC59LM818DMGI-37
MULTIPLE BANK READ-WRITE TIMING (BL = 2)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
RBD
Command
WRA LAL RDA LAL DESL WRA LAL RDA LAL DESL WRA LAL RDA LAL DESL WRA
I
= 1 cycle
I
= 2 cycles
I
= 1 cycle
I
= 2 cycles
WRD
RWD
WRD
RWD
Address
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
Bank
"c"
Bank Add.
I
(Bank"a")
RC
I
(Bank"b")
RC
Unidirectional DS/QS mode
CL = 4
DS
(input)
QS
(output)
DQ
Low
Hi-Z
CL = 4
WL = 3
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
Da0 Da1
CL = 5
DS
(input)
QS
(output)
Low
Hi-Z
CL = 5
WL = 4
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
Da0 Da1
DQ
CL = 6
DS
(input)
QS
(output)
Low
Hi-Z
CL = 6
WL = 5
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
DQ
Unidirectional DS/Free Running QS mode
CL = 4
DS
(input)
QS
(output)
CL = 4
WL = 3
Hi-Z
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
Da0 Da1
DQ
DS
CL = 5
(input)
QS
(output)
CL = 5
WL = 4
Hi-Z
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
Da0 Da1
DQ
CL = 6
DS
(input)
QS
(output)
CL = 6
WL = 5
Hi-Z
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
DQ
Note: l
to the same bank must be satisfied.
RC
Rev 1.2
2005-11-08 37/55
TC59LM818DMGI-37
MULTIPLE BANK READ-WRITE TIMING (BL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
RBD
DESL
DESL
WRA LAL RDA LAL
WRA LAL RDA
LAL
LA
WRA LAL RDA LAL
Command
I
= 1 cycle
I
= 3 cycles
I
= 1 cycle
I
= 3 cycles
I = 1 cycle
WRD
WRD
RWD
WRD
RWD
Address
UA
LA
UA
LA
UA
LA
UA
UA
LA
UA
LA
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
Bank Add.
I
(Bank"a")
RC
I
(Bank"b")
RC
Unidirectional DS/QS mode
CL = 4
DS
(input)
QS
(output)
Low
CL = 4
WL = 3
WL = 4
WL = 5
Hi-Z
DQ
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
Qd0 Qd1 Qd2 Qd3
CL = 5
DS
(input)
QS
(output)
Low
Hi-Z
CL = 5
Qd0 Qd1 Qd2Qd3
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
DQ
CL = 6
DS
(input)
QS
(output)
Low
Hi-Z
CL = 6
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
Qd0 Qd1
DQ
Unidirectional DS/Free Running QS mode
CL = 4
DS
(input)
QS
(output)
CL = 4
WL = 3
Hi-Z
DQ
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
Qd0 Qd1 Qd2 Qd3
CL = 5
DS
(input)
QS
(output)
CL = 5
WL = 4
Hi-Z
DQ
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
Qd0 Qd1 Qd2Qd3
CL = 6
DS
(input)
QS
(output)
CL = 6
WL = 5
Hi-Z
DQ
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
Qd0Qd1
Note: l
to the same bank must be satisfied.
RC
Rev 1.2
2005-11-08 38/55
TC59LM818DMGI-37
WRITE with VARIABLE WRITE LENGTH (VW) CONTROL (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
BL = 2, SEQUENTIAL MODE
Command
WRA LAL
DESL
WRA LAL
DESL
LA=#3
VW=All
LA=#1
VW=1
Address
UA
UA
VW0 = Low
VW1 = don't care
VW0 = High
VW1 = don't care
Bank
"a"
Bank
"a"
Bank Add.
DS
(input)
DQ
D0 D1
D0
(input)
Lower Address #3 #2
#1 (#0)
Last one data is masked.
BL = 4, SEQUENTIAL MODE
Command
Address
WRA LAL
DESL
WRA LAL
DESL
WRA LAL
DESL
LA=#3
LA=#1
LA=#2
UA
UA
UA
VW=All
VW=1
VW=2
VW0 = High
VW1 = Low
VW0 = High
VW1 = High
VW0 = Low
VW1 = High
Bank
"a"
Bank
"a"
Bank
"a"
Bank Add.
DS
(input)
DQ
D0 D1 D2 D3
D0
D0 D1
(input)
Lower Address #3 #0 #1 #2
#1(#2)(#3)(#0)
Last three data are masked.
Note: DS input must be continued till end of burst count even if some of laster data is masked.
#2 #3 (#0)(#1)
Last two data are masked.
Rev 1.2
2005-11-08 39/55
TC59LM818DMGI-37
POWER DOWN TIMING (CL = 4, BL = 4)
Read cycle to Power Down Mode
0
1
2
3
4
5
6
7
8
9
10
n-2
n-1
n
n+1
n+2
CLK
CLK
I
PDA
RDA
or
Command
Address
RDA LAL
DESL
DESL
WRA
UA
LA
UA
t
I
= 2 cycle
PD
IS
t
IH
PD
t
t
PDEX
QPDH
l
, t
RC(min) REFI(max)
Unidirectional DS/QS mode
DS
(input)
QS
Low
(output)
CL = 4
DQ
Hi-Z
Hi-Z
Q0 Q1 Q2 Q3
(output)
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(output)
CL = 4
DQ
(output)
Hi-Z
Hi-Z
Q0 Q1 Q2 Q3
Power Down Entry
Power Down Exit
Note: PD must be kept "High" level until end of Burst data output.
PD should be brought to "High" within t (max.) to maintain the data written into cell.
REFI
In Power Down Mode, PD "Low" and a stable clock signal must be maintained.
When PD is brought to "High", a valid executable command may be applied l
cycles later.
PDA
Rev 1.2
2005-11-08 40/55
TC59LM818DMGI-37
POWER DOWN TIMING (CL = 4, BL = 4)
Write cycle to Power Down Mode
0
1
2
3
4
5
6
7
8
9
10
n-2
n-1
n
n+1
n+2
CLK
CLK
I
PDA
RDA
or
Command
Address
RDA LAL
DESL
DESL
WRA
UA
LA
UA
t
I
= 2 cycle
PD
IS
t
IH
PD
t
t
QPDH
PDEX
l
, t
RC(min) REFI(max)
Unidirectional DS/QS mode
DS
(input)
QS
Low
(output)
WL = 3
DQ
D0 D1 D2 D3
(input)
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(output)
WL = 3
DQ
(input)
D0 D1 D2 D3
Note: PD must be kept "High" level until WL+2 clock cycles from LAL command.
PD should be brought to "High" within t (max.) to maintain the data written into cell.
REFI
In Power Down Mode, PD "Low" and a stable clock signal must be maintained.
When PD is brought to "High", a valid executable command may be applied l
cycles later.
PDA
Rev 1.2
2005-11-08 41/55
TC59LM818DMGI-37
MODE REGISTER SET TIMING (CL = 4, BL = 2)
From Read operation to Mode Register Set operation.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 7 cycles
RSC
RDA
or
Command
A14~A0
RDA LAL
DESL
RDA MRS
DESL
LAL
LA
WRA
Valid
(opcode)
UA
BA
LA
UA
BA
BA0="0"
BA1="0"
BA0, BA1
CL + BL/2
Unidirectional DS/QS mode
DS
(input)
QS
(output)
Low
DQ
Q0 Q1
(output)
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(output)
DQ
Q0 Q1
(output)
Note: Minimum delay from LAL following RDA to RDA of MRS operation is CL+BL/2.
Rev 1.2
2005-11-08 42/55
TC59LM818DMGI-37
MODE REGISTER SET TIMING (CL = 4, BL = 4)
From Write operation to Mode Register Set operation.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 7 cycles
RSC
RDA
or
Command
A14~A0
WRA LAL
DESL
RDA MRS
DESL
LAL
LA
WRA
Valid
(opcode)
UA
BA
LA
UA
BA
BA0="0"
BA1="0"
BA0, BA1
WL+BL/2
Unidirectional DS/QS mode
DS
(input)
QS
Low
(output)
DQ
D0 D1 D2 D3
(input)
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(output)
DQ
D0 D1 D2 D3
(input)
Note: Minimum delay from LAL following WRA to RDA of MRS operation is WL+BL/2.
Rev 1.2
2005-11-08 43/55
TC59LM818DMGI-37
EXTENDED MODE REGISTER SET TIMING (CL = 4, BL = 2)
From Read operation to Extended Mode Register Set operation.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 7 cycles
RSC
RDA
or
Command
A14~A0
RDA LAL
DESL
RDA MRS
DESL
LAL
LA
WRA
Valid
(opcode)
UA
BA
LA
UA
BA
BA0="1"
BA1="0"
BA0, BA1
CL + BL/2
Unidirectional DS/QS mode
DS
(input)
QS
(output)
Low
DQ
Q0 Q1
(output)
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(output)
DQ
Q0 Q1
(output)
Note: Minimum delay from LAL following RDA to RDA of EMRS operation is CL+BL/2.
When DQ strobe mode is changed by EMRS, QS output is invalid for l period.
RSC
DLL switch in Extended Mode Register must be set to enable mode for normal operation.
DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence.
Rev 1.2
2005-11-08 44/55
TC59LM818DMGI-37
EXTENDED MODE REGISTER SET TIMING (CL = 4, BL = 4)
From Write operation to Extended Mode Register Set operation.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 7 cycles
RSC
RDA
or
Command
A14~A0
WRA LAL
DESL
RDA MRS
DESL
LAL
LA
WRA
Valid
(opcode)
UA
BA
LA
UA
BA
BA0="1"
BA1="0"
BA0, BA1
WL+BL/2
Unidirectional DS/QS mode
DS
(input)
QS
Low
(output)
DQ
D0 D1 D2 D3
(input)
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(output)
DQ
(input)
D0 D1 D2 D3
Note: When DQ strobe mode is changed by EMRS, QS output is invalid for l
period.
RSC
DLL switch in Extended Mode Register must be set to enable mode for normal operation.
DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence.
Minimum delay from LAL following WRA to RDA of EMRS operation is WL+BL/2.
Rev 1.2
2005-11-08 45/55
TC59LM818DMGI-37
AUTO-REFRESH TIMING (CL = 4, BL = 4)
Unidirectional DS/QS mode
0
1
2
3
4
5
6
7
n − 1
n
n + 1
n + 2
CLK
CLK
I
= 5 cycles
I
= 19 cycles
RC
REFC
RDA LAL or
WRA
Command
RDA
LAL
DESL
WRA
REF
DESL
or
MRS or
REF
Bank,
UA
Bank, Address
LA
I
= 1 cycle
I
= 4 cycles
I = 1 cycle
RCD
RCD
RAS
QS
Low
Hi-Z
Low
Hi-Z
(output)
CL = 4
DQ
(output)
Q0 Q1 Q2 Q3
Unidirectional DS/Free Running QS mode
CLK
CLK
I
= 5 cycles
I
= 19 cycles
REFC
RC
RDA LAL or
WRA
Command
RDA
LAL
DESL
WRA
REF
DESL
or
MRS or
REF
Bank,
UA
Bank, Address
LA
I
= 1 cycle
I
= 4 cycles
I = 1 cycle
RCD
RCD
RAS
QS
(output)
CL = 4
DQ
(output)
Hi-Z
Note: In case of CL = 4, I
Hi-Z
Q0 Q1 Q2 Q3
must be meet 19 clock cycles.
REFC
When the Auto-Refresh operation is performed, the synthetic average interval of Auto-Refresh command
specified by t
REFI
must be satisfied.
REFI
t
is average interval time in 8 Refresh cycles that is sampled randomly.
t
t
t
t
t
8
1
2
3
7
CLK
WRA REF
WRA REF
WRA REF
WRA REF
WRA REF
8 Refresh cycle
Total time of 8 Refresh cycle
8
t + t + t + t + t + t + t + t
1 2 3 4 5 6 7 8
t
=
=
REFI
8
t
is specified to avoid partly concentrated current of Refresh operation that is activated larger area
REFI
than Read / Write operation.
Rev 1.2
2005-11-08 46/55
TC59LM818DMGI-37
FUNCTIONAL DESCRIPTION
TM
Network FCRAM
The FCRAMTM is an acronym of Fast Cycle Random Access Memory.
The Network FCRAMTM is competent to perform fast random core access, low latency and high-speed data
transfer.
PIN FUNCTIONS
CLOCK INPUTS: CLK &
The CLK and CLK inputs are used as the reference for synchronous operation. CLK is master clock input. The
CS , FN and all address input signals are sampled on the crossing of the positive edge of CLK and the negative
edge of CLK . The QS and DQ output data are aligned to the crossing point of CLK and CLK . The timing
reference point for the differential clock is when the CLK and CLK signals cross during a transition.
POWER DOWN: PD
The PD input controls the entry to the Power Down modes. The PD input does not have a Clock Suspend
function like a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into low state if any Read
or Write operation is being performed.
CS
CHIP SELECT & FUNCTION CONTROL:
& FN
The CS and FN inputs are a control signal for forming the operation commands on FCRAMTM. Each operation
mode is decided by the combination of the two consecutive operation commands using the CS and FN inputs.
BANK ADDRESSES: BA0 & BA1
The BA0 and BA1 inputs are latched at the time of assertion of the RDA or WRA command and are selected the
bank to be used for the operation. BA0 and BA1 also define which mode register is loaded during the Mode Register
Set command (MRS or EMRS).
BA0
BA1
Bank #0
Bank #1
Bank #2
Bank #3
0
1
0
1
0
0
1
1
ADDRESS INPUTS: A0~A14
Address inputs are used to access the arbitrary address of the memory cell array within each bank. The Upper
Addresses with Bank addresses are latched at the RDA or WRA command and the Lower Addresses are latched at
the LAL command. The A0 to A14 inputs are also used for setting the data in the Regular or Extended Mode
Register set cycle.
I/O Organization
18 bits
UPPER ADDRESS
A0~A14
LOWER ADDRESS
A0~A6
Rev 1.2
2005-11-08 47/55
TC59LM818DMGI-37
DATA INPUT/OUTPUT: DQ0~DQ17
The input data of DQ0 to DQ17 are taken in synchronizing with the both edges of DS input signal. The output
data of DQ0 to DQ17 are outputted synchronizing with the both edges of QS output signal.
DATA STROBE: DS, QS
Method of data strobe is chosen by Extended mode register.
(1) Unidirectional DS / QS mode
DS is input signal and QS is output signal. Both edges of DS are used to sample all DQs at Write operation.
Both edges of QS are used for trigger signal of all DQs at Read operation. During Write, Auto-Refresh and
NOP cycle, QS assert always “Low” level.
(2) Unidirectional DS / Free running QS mode
DS is input signal and QS is output signal. Both edge of DS are used to sample all DQs at Write operation.
Both edges of QS are used for trigger signal of all DQs at Read operation. QS assert always toggle signal.
This strobe type is easy to use for pin to pin connect application.
POWER SUPPLY: V , V
, V , V
SS SSQ
DD DDQ
V
and V are power supply pins for memory core and peripheral circuits.
DD
SS
and V
V
DDQ
are power supply pins for the output buffer.
SSQ
REFERENCE VOLTAGE: V
REF
V
REF
is reference voltage for all input signals.
Rev 1.2
2005-11-08 48/55
TC59LM818DMGI-37
COMMAND FUNCTIONS and OPERATIONS
TC59LM818DMBI are introduced the two consecutive command input method. Therefore, except for Power Down
mode, each operation mode decided by the combination of the first command and the second command from
stand-by states of the bank to be accessed.
Read Operation (1st command + 2nd command = RDA + LAL)
Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated
by Bank Address in a read mode. When the LAL command with Lower Addresses is issued at the next clock of the
RDA command, the data is read out sequentially synchronizing with the both edges of QS output signal (Burst
Read Operation). The initial valid read data appears after CAS latency from the issuing of the LAL command.
The valid data is outputted for a burst length. The CAS latency, the burst length of read data and the burst type
must be set in the Mode Register beforehand. The read operated bank goes back automatically to the idle state
after l
.
RC
Write Operation (1st command + 2nd command = WRA + LAL)
Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated
by Bank Address in a write mode. When the LAL command with Lower Addresses is issued at the next clock of the
WRA command, the input data is latched sequentially synchronizing with the both edges of DS input signal (Burst
Write Operation). The data and DS inputs have to be asserted in keeping with clock input after CAS latency-1
from the issuing of the LAL command. The DS has to be provided for a burst length. The CAS latency and the
burst type must be set in the Mode Register beforehand. The write operated bank goes back automatically to the
idle state after l . Write Burst Length is controlled by VW0 and VW1 inputs with LAL command. See VW truth
RC
table.
Auto-Refresh Operation (1st command + 2nd command = WRA + REF)
TC59LM818DMBI are required to refresh like a standard SDRAM. The Auto-Refresh operation is begun with the
REF command following to the WRA command. In a point to notice, the write mode started with the WRA
command is canceled by the REF command having gone into the next clock of the WRA command instead of the
LAL command. The minimum period between the Auto-Refresh command and the next command is specified by
l
. However, about a synthetic average interval of Auto-Refresh command, it must be careful. In case of equally
REFC
distributed refresh, Auto-Refresh command has to be issued within once for every 1.95 µs by the maximum. In case
of burst refresh or random distributed refresh, the average interval of eight consecutive Auto-Refresh commands
has to be more than 400 ns always. In other words, the number of Auto-Refresh cycles that can be performed within
3.2 µs (8 × 400 ns) is to 8 times in the maximum.
Power Down Mode ( PD = “L”)
When all banks are in the idle state and DQ outputs are in Hi-Z states, the TC59LM818DMBI become Power
Down Mode by asserting PD is “Low”. When the device enters the Power Down Mode, all input and output buffers
are disabled after specified time except for PD , CLK, CLK and QS. Therefore, the power dissipation lowers. To
exit the Power Down Mode, PD has to be brought to “High” and the DESL command has to be issued for lPDA
cycle after PD goes high. The Power Down exit function is asynchronous operation.
Rev 1.2
2005-11-08 49/55
TC59LM818DMGI-37
Mode Register Set (1st command + 2nd command = RDA + MRS)
When all banks are in the idle state, issuing the MRS command following to the RDA command can program the
Mode Register. In a point to notice, the read mode started with the RDA command is canceled by the MRS
command having gone into the next clock of the RDA command instead of the LAL command. The data to be set in
the Mode Register is transferred using A0 to A14, BA0 and BA1 address inputs. The TC59LM818DMBI have two
mode registers. These are Regular and Extended Mode Register. The Regular or Extended Mode Register is chosen
by BA0 and BA1 in the MRS command. The Regular Mode Register designates the operation mode for a read or
write cycle. The Regular Mode Register has four function fields.
The four fields are as follows:
(R-1) Burst Length field to set the length of burst data
(R-2) Burst Type field to designate the lower address access sequence in a burst cycle
(R-3) CAS Latency field to set the access time in clock cycle
(R-4) Test Mode field to use for supplier only.
The Extended Mode Register has three function fields.
The three fields are as follows:
(E-1) DLL Switch field to choose either DLL enable or DLL disable
(E-2) Output Driver Impedance Control field.
(E-3) Data Strobe Select
Once those fields in the Mode Register are set up, the register contents are maintained until the Mode Register is
set up again by another MRS command or power supply is lost. The initial value of the Regular or Extended Mode
Register after power-up is undefined, therefore the Mode Register Set command must be issued before proper
operation.
•
Regular Mode Register/Extended Mode Register change bits (BA0, BA1)
These bits are used to choose either Regular MRS or Extended MRS
BA1
BA0
Mode Register Set
0
0
1
0
1
×
Regular MRS
Extended MRS
Reserved
Regular Mode Register Fields
(R-1) Burst Length field (A2 to A0)
This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length
to be 2 or 4 words.
A2
A1
A0
BURST LENGTH
0
0
0
0
1
0
0
1
1
×
0
1
0
1
×
Reserved
2 words
4 words
Reserved
Reserved
(R-2) Burst Type field (A3)
The Burst Type can be chosen Interleave mode or Sequential mode. When the A3 bit is “0”, Sequential
mode is selected. When the A3 bit is “1”, Interleave mode is selected. Both burst types support burst
length of 2 and 4 words.
A3
BURST TYPE
0
1
Sequential
Interleave
Rev 1.2
2005-11-08 50/55
TC59LM818DMGI-37
•
Addressing sequence of Sequential mode (A3)
A column access is started from the inputted lower address and is performed by incrementing the lower
address input to the device.
CAS Latency = 4 (Free Running QS mode)
CLK
CLK
Command
RDA
LAL
QS
Data Data Data Data
DQ
0
1
2
3
Addressing sequence for Sequential mode
DATA
ACCESS ADDRESS
BURST LENGTH
Data 0
Data 1
Data 2
Data 3
N
2 words (address bits is LA0)
not carried from LA0~LA1
n + 1
n + 2
n + 3
4 words (address bits is LA1, LA0)
not carried from LA1~LA2
•
Addressing sequence of Interleave mode
A column access is started from the inputted lower address and is performed by interleaving the address bits
in the sequence shown as the following.
Addressing sequence for Interleave mode
DATA
ACCESS ADDRESS
BURST LENGTH
Data 0
Data 1
Data 2
Data 3
ּּּA8 A7 A6 A5 A4 A3 A2 A1 A0
ּּּA8 A7 A6 A5 A4 A3 A2 A1 A0
ּּּA8 A7 A6 A5 A4 A3 A2 A1 A0
ּּּA8 A7 A6 A5 A4 A3 A2 A1 A0
2 words
4 words
(R-3) CAS Latency field (A6 to A4)
This field specifies the number of clock cycles from the assertion of the LAL command following the RDA
command to the first data read. The minimum value of CAS Latency depends on the frequency of CLK.
In a write mode, the place of clock that should input write data is CAS Latency cycles − 1.
A6
A5
A4
CAS LATENCY
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
Reserved
4
5
6
Reserved
(R-4) Test Mode field (A7)
This bit is used to enter Test Mode for supplier only and must be set to “0” for normal operation.
(R-5) Reserved field in the Regular Mode Register
•
Reserved bits (A8 to A14)
These bits are reserved for future operations. They must be set to “0” for normal operation.
Rev 1.2
2005-11-08 51/55
TC59LM818DMGI-37
Extended Mode Register fields
(E-1) DLL Switch field (A0)
This bit is used to enable DLL. When the A0 bit is set “0”, DLL is enabled. This bit must be set to “0” for
normal operation.
(E-2) Output Driver Impedance Control field (A1 to A4)
This field is used to choose Output Driver Strength. Three types of Driver Strength are supported.
QS and DQ Driver Strength can be chosen separately. A2-A1 specified the DQ Driver Strength. A4-A3
specified the QS Driver Strength.
QS
DQ
OUTPUT DRIVER IMPEDANCE CONTROL
A4
A3
A2
A1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
Normal Output Driver
Strong Output Driver
Weak Output Driver
Reserved
(E-3) Strobe Select (A6 / A5)
Two types of data strobe are supported. This field is used to choose the type of data strobe.
Unidirectional DS/QS mode
(1)
(2)
Data strobe is separated DS for write strobe and QS for read strobe.
DS is used to sample write data at write operation. QS is aligned with read data at Read operation.
Unidirectional DS/Free running QS mode
Data strobe is separated DS for write strobe and QS for read strobe.
DS is used to sample write data at write operation. QS is aligned with read data and always
clocking.
A6
A5
STROBE SELECT
0
0
1
1
0
1
0
1
Reserved
Reserved
Unidirectional DS/QS mode
Unidirectional DS/Free running QS mode
(E-4) Reserved field (A7 to A14)
These bits are reserved for future operations and must be set to “0” for normal operation.
Rev 1.2
2005-11-08 52/55
TC59LM818DMGI-37
PACKAGE DIMENSIONS
P-BGA60-0917-1.00AZ
16.5
0
12.518
-0.15
0.2 S
0.05
0.5
0.08 SAB
1.25
A
1.0
Weight: 0.15g (typ.)
Rev 1.2
2005-11-08 53/55
TC59LM818DMGI-37
REVISION HISTORY
− Rev.1.2 ( Nov.8th ’2005 )
• 1st edition released. Difference between lead product( P/N: TC59LM818DMBI37 ) and this lead-free product
is only part number and comment for “lead-free” on page 1.
Rev 1.2
2005-11-08 54/55
TC59LM818DMGI-37
RESTRICTIONS ON PRODUCT USE
030619EBA
• The information contained herein is subject to change without notice.
• The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of
TOSHIBA or others.
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced
and sold, under any law and regulations.
Rev 1.2
2005-11-08 55/55
相关型号：
TC59LM906AMB-45
IC 64M X 8 DDR DRAM, 22 ns, PBGA60, 13 X 17 MM, 1 MM PITCH, PLASTIC, BGA-60, Dynamic RAM
TOSHIBA
TC59LM906AMG-45
IC 64M X 8 DDR DRAM, 0.6 ns, PBGA64, 13 X 17 MM, 1 MM PITCH, PLASTIC, BGA-64, Dynamic RAM
TOSHIBA
©2020 ICPDF网 联系我们和版权申明