TC59LM836DKB-33 [TOSHIBA]
MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 288Mbits Network FCRAM2; MOS数字集成电路硅单片288Mbits网络FCRAM2
| 型号： | TC59LM836DKB-33 |
| 厂家： | 
TOSHIBA |
| 描述： | MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 288Mbits Network FCRAM2 |
| 文件： | 总65页 (文件大小：832K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TC59LM836DKB-30,-33,-40
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
288Mbits Network FCRAM2
− 2,097,152-WORDS × 4 BANKS × 36-BITS
DESCRIPTION
Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM836DKB is Network
FCRAMTM containing 301,989,888 memory cells. TC59LM836DKB is organized as 2,097,152-words × 4 banks × 36
bits. TC59LM836DKB feature a fully synchronous operation referenced to clock edge whereby all operations are
synchronized at a clock input which enables high performance and simple user interface coexistence.
TC59LM836DKB can operate fast core cycle compared with regular DDR SDRAM.
TC59LM836DKB is suitable for Network and other applications where large memory density and low power
consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data transfer
under light loading condition.
FEATURES
TC59LM836DKB
PARAMETER
-30
-33
-40
CL = 4
CL = 5
CL = 6
4.0 ns
3.5 ns
3.0 ns
20.0 ns
20.0 ns
380 mA
100 mA
15 mA
4.5 ns
5.0 ns
4.5 ns
4.0 ns
25 ns
t
Clock Cycle Time (min)
3.75 ns
3.33 ns
22.5 ns
22.5 ns
360 mA
95 mA
15 mA
CK
t
t
I
Random Read/Write Cycle Time (min)
Random Access Time (max)
RC
25 ns
RAC
DD1S
DD2P
DD6
Operating Current (single bank) (max)
Power Down Current (max)
340 mA
90 mA
15 mA
l
l
Self-Refresh Current (max)
•
•
Fully Synchronous Operation
Double Data Rate (DDR)
•
•
Data input/output are synchronized with both edges of DS / QS.
Differential Clock (CLK and CLK ) inputs
CS , FN and all address input signals are sampled on the positive edge of CLK.
Output data (DQs and QS) is aligned to the crossings of CLK and CLK .
Fast clock cycle time of 3.0 ns minimum
Clock: 333 MHz maximum
Data: 666 Mbps/pin maximum
Quad Independent Banks operation
Fast cycle and Short Latency
Selectable Data Strobe
Distributed Auto-Refresh cycle in 3.9 µs
Self-Refresh
Power Down Mode
Variable Write Length Control
Write Latency = CAS Latency-1
Programable CAS Latency and Burst Length
CAS Latency = 4, 5, 6
•
•
•
•
•
•
•
•
•
Burst Length = 2, 4
•
•
Organization: 2,097,152 words × 4 banks × 36 bits
Power Supply Voltage
V
DD
V
:
2.5 V ± 0.125V
: 1.4 V ~ 1.9 V
DDQ
•
•
•
Low voltage CMOS I/O covered with SSTL_18 (Half strength driver) and HSTL.
JTAG boundary scan
Package: 144Ball BGA, 1mm × 0.8mm Ball pitch (P-TFBGA144-1119-0.80BZ)
Notice: FCRAM is trademark of Fujitsu limited, Japan.
Rev 1.3
2005-03-07 1/65
TC59LM836DKB-30,-33,-40
PIN NAMES
PIN
NAME
A0~A13
BA0, BA1
DQ0~DQ35
CS
Address Input
Bank Address
Data Input/Output
Chip Select
FN
Function Control
Power Down Control
Clock Input
PD
CLK, CLK
LDS, UDS
LQS, UQS
Write Data Strobe
Read Data Strobe
Power (+2.5 V)
Ground
V
V
DD
SS
Power (+1.5V / +1.8 V)
(for DQ buffer)
Ground
V
DDQ
V
V
SSQ
REF
(for DQ buffer)
Reference Voltage
Not Connected
NC
TMS, TDI, TCK, TDO Boundary Scan Test Access Ports
Rev 1.3
2005-03-07 2/65
TC59LM836DKB-30,-33,-40
PIN ASSIGNMENT (TOP VIEW)
ball pitch=1.0 x 0.8mm
1
2
3
4
5
6
7
8
9
10
11
12
0.8mm
Index
A
V
V
V
V
V
V
V
V
DD
DD
SS
SS
DD
DD
SS
SS
V
Q
DQ16 DQ17
DQ14 DQ15
DQ12 DQ13
DQ10 DQ11
LDS DQ9
V
Q
V
Q
DQ0 DQ1
DQ2 DQ3
DQ4 DQ5
DQ6 DQ7
DQ8 LQS
V
Q
DD
DD
DD
DD
B
C
D
E
F
V
V
Q
SS
V
V
Q
SS
V
V
Q
SS
V
V
Q
Q
SS
Q
DD
Q
DD
Q
DD
DD
V
Q
V
Q
V
Q
V
Q
SS
SS
SS
SS
DD
V
Q
Q
V
Q
Q
V
Q
Q
V
Q
DD
DD
DD
V
V
CLK
CLK
A11
A8
V
V
FN
NC
V
SS
Q
A13
CS
BA1
A0
SS
REF
SS
SS
G
H
J
V
PD
A12
A9
V
V
V
SS
SS
SS
SS
V
V
V
BA0
A10
V
DD
DD
DD
DD
V
V
V
V
V
V
V
V
SS
SS
SS
SS
K
A2
A7
A5
A6
A4
A1
A3
L
M
N
P
R
T
DD
DD
DD
DD
V
Q
DD
V
Q
DD
V
Q
DD
V
Q
DD
NC
V
V
Q
SS
UDS DQ26
DQ25 DQ24
DQ23 DQ22
DQ21 DQ20
DQ19 DQ18
V
V
Q
SS
V
V
Q
SS
DQ27 UQS
DQ29 DQ28
DQ31 DQ30
DQ33 DQ32
DQ35 DQ34
V
V
Q
Q
SS
Q
DD
Q
DD
Q
DD
DD
V
V
Q
V
V
Q
V
V
Q
V
V
Q
SS
SS
SS
SS
DD
Q
DD
Q
DD
Q
DD
Q
V
Q
SS
V
Q
SS
V
Q
SS
V
SS
Q
U
V
TMS TCK
V
V
V
V
SS
TDO
TDI
SS
DD
DD
: Depopulated ball
Rev 1.3
2005-03-07 3/65
TC59LM836DKB-30,-33,-40
BLOCK DIAGRAM
CLK
CLK
PD
DLL
CLOCK
BUFFER
To each block
CS
FN
CONTROL
SIGNAL
COMMAND
DECODER
BANK #3
BANK #2
GENERATOR
BANK #1
BANK #0
MODE
REGISTER
MEMORY
A0~A13
CELL ARRAY
ADDRESS
BUFFER
UPPER ADDRESS
LATCH
BA0, BA1
LOWER ADDRESS
LATCH
COLUMN DECODER
READ
DATA
WRITE
DATA
WRITE ADDRESS
REFRESH
COUNTER
LATCH/
ADDRESS
BUFFER
BUFFER
COMPARATOR
BURST
COUNTER
LDS
LQS
UDS
UQS
DQ BUFFER
DQ0~DQ17
DQ18~DQ35
Note: The TC59LM836DKB configuration is 4 Bank of 16384 × 128 × 36 of cell array with the DQ pins numbered DQ0~DQ35.
Rev 1.3
2005-03-07 4/65
TC59LM836DKB-30,-33,-40
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
Power Supply Voltage
RATING
UNIT
NOTES
V
V
V
V
V
−0.3~ 3.3
V
V
DD
Power Supply Voltage (for DQ buffer)
Input Voltage
−0.3~V + 0.3
DD
DDQ
IN
−0.3~V + 0.3
V
DD
Output and DQ pin Voltage
Input Reference Voltage
Operating Temperature (case)
Storage Temperature
−0.3~V
+ 0.3
DDQ
V
OUT
REF
opr
−0.3~V + 0.3
V
DD
T
T
T
0~85
−55~150
260
°C
°C
°C
W
mA
stg
Soldering Temperature (10 s)
Power Dissipation
solder
P
2.5
D
I
Short Circuit Output Current
±50
OUT
Caution: Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device.
The device is not meant to be operated under conditions outside the limits described in the operational section of this
specification.
Exposure to “ABSOLUTE MAXIMUM RATINGS” conditions for extended periods may affect device reliability.
RECOMMENDED DC, AC OPERATING CONDITIONS (Notes: 1)(T
= 0~85°C)
CASE
SYMBOL
PARAMETER
Power Supply Voltage
MIN
TYP.
MAX
UNIT
NOTES
V
V
V
V
V
V
2.375
1.4
2.5
2.625
1.9
V
V
DD
Power Supply Voltage (for DQ buffer)
Reference Voltage
DDQ
REF
V
/2 × 95%
+ 0.125
V
/2
DDQ
V
/2 × 105%
DDQ
V
V
V
V
2
5
DDQ
(DC)
Input DC High Voltage
V
V
+ 0.2
DDQ
IH
IL
REF
(DC)
(DC)
Input DC Low Voltage
−0.1
−0.1
V
− 0.125
5
REF
Differential Clock DC Input Voltage
V
V
V
+ 0.1
+ 0.2
10
ICK
DDQ
DDQ
DDQ
Differential Input Voltage.
CLK and CLK inputs (DC)
V
(DC)
0.4
V
7, 10
ID
V
V
(AC)
Input AC High Voltage
Input AC Low Voltage
V
+ 0.2
REF
+ 0.2
− 0.2
V
V
3, 6
4, 6
IH
IL
(AC)
(AC)
(AC)
−0.1
V
REF
Differential Input Voltage.
V
0.55
V
+ 0.2
V
7, 10
ID
X
DDQ
CLK and CLK inputs (AC)
V
V
Differential AC Input Cross Point Voltage
Differential Clock AC Middle Level
V
V
/2 − 0.125
/2 − 0.125
V
V
/2 + 0.125
/2 + 0.125
V
V
8, 10
9, 10
DDQ
DDQ
(AC)
ISO
DDQ
DDQ
Rev 1.3
2005-03-07 5/65
TC59LM836DKB-30,-33,-40
NOTES:
(1)
All voltages referenced to V , V
.
SS SSQ
(2)
V
is expected to track variations in V
DC level of the transmitting device.
REF
Peak to peak AC noise on V
DDQ
may not exceed ±2% V
(DC).
REF
REF
(3)
(4)
Overshoot limit: V
IH (max)
= V
+ 0.7 V with a pulse width ≤ 5 ns.
DDQ
= −0.7 V with a pulse width ≤ 5 ns.
Undershoot limit: V
IL (min)
(5)
V
IH
V
IH
V
ID
(DC) and V (DC) are levels to maintain the current logic state.
IL
(6)
(AC) and V (AC) are levels to change to the new logic state.
IL
(7)
is differential voltage of CLK input level and CLK input level.
(8)
The value of V (AC) is expected to equal V /2 of the transmitting device.
DDQ
X
(9)
V
ISO
means {V
(CLK) + V (CLK )} /2
ICK
ICK
(10)
Refer to the figure below.
CLK
V
V
V
V
V
V
(AC)
ID
x
x
x
x
x
CLK
V
V
V
V
ICK
ICK
ICK
ICK
V
SS
|V (AC)|
ID
0 V Differential
V
ISO
V
V
ISO (max)
ISO (min)
V
SS
(11)
In the case of external termination, VTT (termination voltage) should be gone in the range of V
(DC)
REF
± 0.04 V.
CAPACITANCE (V = 2.5V, V
= 1.8 V, f = 1 MHz, Ta = 25°C)
DD
DDQ
SYMBOL
PARAMETER
MIN
MAX
Delta
UNIT
C
C
C
C
Input pin Capacitance
1.5
1.5
2.5
3.0
3.0
3.5
1.5
0.25
0.25
0.5
pF
pF
pF
pF
IN
Clock pin (CLK, CLK ) Capacitance
DQ, LDS, UDS, LQS, UQS Capacitance
NC pin Capacitance
INC
I/O
NC
Note: These parameters are periodically sampled and not 100% tested.
Rev 1.3
2005-03-07 6/65
TC59LM836DKB-30,-33,-40
RECOMMENDED DC OPERATING CONDITIONS
(V = 2.5 V ± 0.125 V, V
= 1.4 V ~ 1.9 V, T
= 0 ~ 85°C)
DD
DDQ
CASE
MAX
-33
SYMBOL
PARAMETER
UNIT
NOTES
-30
-40
Operating Current
One bank read or write operation ;
= min; I = min, I = 0mA ;
t
CK
RC
OUT
I
I
I
Burst Length = 4, CAS Latency = 6, Free running QS mode ;
0 V ≤ V ≤ V (AC) (max), V (AC) (min) ≤ V ≤ V
380
360
110
95
340
1, 2
DD1S
DD2N
DD2P
,
DDQ
IN
IL
IH
IN
Address inputs change up to 2 times during minimum I
Read data change twice per clock cycle
,
RC
Standby Current
All banks: inactive state ;
t
= min, CS = V , PD = V
;
IH
CK
IH
120
100
100
1, 2
0 V ≤ V ≤ V (AC) (max), V (AC) (min) ≤ V ≤ V ;
DDQ
IN
IL
IH
IN
Other input signals change one time during 4 × t
,
CK
DQ and DS inputs change twice per clock cycle
Standby (power down) Current
All banks: inactive state ;
t
= min, PD = V (power down) ;
IL
CK
CAS Latency = 6, Free running QS mode ;
0 V ≤ V ≤ V (AC) (max), V (AC) (min) ≤ V ≤ V ;
DDQ
90
1, 2
IN
IL
IH
IN
Other input signals change one time during 4 × t
,
CK
DQ and DS inputs are floating (V
/2)
DDQ
Write Operating Current (4Banks)
4 Bank interleaved continuous burst write operation ;
= min, I = min ;
mA
t
CK
RC
I
I
Burst Length = 4, CAS Latency = 6, Free running QS mode ;
0 V ≤ V ≤ V (AC) (max), V (AC) (min) ≤ V ≤ V
Address inputs change once per clock cycle,
850
850
800
800
750
750
1, 2
DD4W
;
DDQ
IN
IL
IH
IN
DQ and DS inputs change twice per clock cycle
Read Operating Current (4Banks)
4 Bank interleaved continuous burst read operation ;
t
= min, I
= min, I
= 0mA ;
OUT
CK
RC
Burst Length = 4, CAS Latency = 6, Free running QS mode ;
0 V ≤ V ≤ V (AC) (max), V (AC) (min) ≤ V ≤ V
1, 2
DD4R
;
DDQ
IN
IL
IH
IN
Address inputs change once per clock cycle,
Read data change twice per clock cycle
Burst Auto Refresh Current
Refresh command at every I
interval ;
REFC
t
= min; I
= min ;
REFC
CK
I
I
CAS Latency = 6, Free running QS mode ;
0 V ≤ V ≤ V (AC) (max), V (AC) (min) ≤ V ≤ V ,
DDQ
380
15
360
15
340
15
1, 2, 3
DD5B
IN
IL
IH
IN
Address inputs change up to 2 times during minimum I
DQ and DS inputs change twice per clock cycle
,
REFC
Self-Refresh Current
PD = 0.2 V ;
2
DD6
Other input signals are floating (V
/2),
DDQ
DQ and DS inputs are floating (V
/2)
DDQ
Notes: 1. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of
, t and I
t
.
RC
CK RC
2. These parameters define the current between V
and V
.
SS
DD
3.
I
is specified under burst refresh condition. Actual system should use distributed refresh that meet to t
DD5B REFI
specification.
Rev 1.3
2005-03-07 7/65
TC59LM836DKB-30,-33,-40
RECOMMENDED DC OPERATING CONDITIONS (continued)
(V = 2.5 V ± 0.125 V, V
= 1.4 V ~ 1.9 V, T
= 0 ~ 85°C)
DD
DDQ
CASE
SYMBOL
PARAMETER
MIN
MAX
5
UNIT
NOTES
Input Leakage Current
( 0 V ≤ V ≤ V , all other pins not under test = 0 V)
I
I
−5
µA
LI
IN
DDQ
Output Leakage Current
(Output disabled, 0 V ≤ V
−5
5
µA
µA
LO
≤ V
)
OUT
DDQ
I
I
V
Current
REF
−5
5
REF
(DC)
V
V
V
V
V
V
V
V
V
V
= 1.420 V
= 0.280 V
= 1.420 V
= 0.280 V
= 1.420 V
= 0.280 V
−5.6
OH
OL
OH
OL
OH
OL
OH
OL
OH
OL
OH
OL
OH
OL
OH
OL
OH
OL
OH
OL
OH
Normal
Output Driver
I
I
I
I
I
I
I
I
I
I
I
(DC)
(DC)
(DC)
(DC)
(DC)
(DC)
(DC)
(DC)
(DC)
(DC)
(DC)
5.6
−9.8
9.8
−2.8
2.8
−4
Output DC Current
Strong
mA
1
Output Driver
(V
= 1.7V~1.9V)
DDQ
Weak
Output Driver
= V
– 0.4V
DDQ
Normal
Output Driver
= 0.4V
= V
4
– 0.4V
−8
Output DC Current
DDQ
Strong
mA
1
Output Driver
(V
= 1.4V~1.6V)
DDQ
= 0.4V
8
OL
Not defined
Not defined
Weak Output
Driver
Notes: 1. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Register.
Rev 1.3
2005-03-07 8/65
TC59LM836DKB-30,-33,-40
AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2)
(V = 2.5 ± 0.125V, V
= 1.4 ∼ 1.9V, T
= 0 ∼ 85°C)
DD
DDQ
CASE
-30
-33
-40
SYMBOL
PARAMETER
UNIT NOTES
MIN
MAX
MIN
MAX
MIN
MAX
t
t
Random Cycle Time
20.0
4.0
22.5
4.5
25
5.0
4.5
3
3
3
RC
CK
C
L
C
L
C
L
= 4
= 5
= 6
5.0
5.0
7.5
7.5
7.5
7.5
Clock Cycle Time
3.5
3.75
3.0
5.0
20.0
3.33
7.5
22.5
4.0
7.5
25
3
t
t
t
t
t
Random Access Time
Clock High Time
3
RAC
CH
0.45 × t
0.45 × t
0.45 × t
0.45 × t
0.45 × t
0.45 × t
−0.5
3
3
CK
CK
CK
Clock Low Time
CL
CK
CK
CK
QS Access Time from CLK
Data Output Skew from QS
−0.45
0.45
0.2
−0.45
0.45
0.25
0.5
0.3
3, 8,10
CKQS
QSQ
Data Output Skew from QS to
All DQ
t
t
t
0.3
0.5
0.5
0.35
0. 5
0.5
0.4
0.6
0.6
QSQA
AC
Data Access Time from CLK
−0.5
−0.5
−0.5
−0.5
−0.6
−0.6
3, 8,10
3, 8
Data Output Hold Time from
CLK
OH
CLK half period (minimum of
min(t
,
min(t
,
min(t
,
CH
CH
)
CH
)
t
t
t
t
t
3
HP
Actual t , t
)
t
t
t
)
CL
CH CL
CL
CL
t
−
t
−
t
−
HP
HP
HP
QS (read) Pulse Width
4, 8
4, 8
QSP
QSQV
QHS
DQSS
t
t
t
QHS
QHS
QHS
t
−
t
−
t
−
HP
HP
HP
Data Output Valid Time from QS
DQ, QS Hold Skew factor
t
t
t
QHS
QHS
QHS
0.055 ×
+ 0.17
0.055 ×
+ 0.17
0.055 ×
+ 0.17
t
t
t
CK
CK
CK
ns
DS (write) Low to High Setup
Time
0.8×t
1.2×t
0.8×t
1.2×t
0.8×t
1.2×t
CK
3
CK
CK
CK
CK
CK
t
t
t
t
DS (write) Preamble Pulse Width 0.4×t
0.4×t
0
0.4×t
0
4
3
3
4
DSPRE
DSPRES
DSPREH
DSP
CK
CK
CK
DS First Input Setup Time
0
DS First Low Input Hold Time
0.3×t
0.3×t
0.3×t
CK
CK
CK
DS High or Low Input Pulse Width 0.45×t
0.55×t
0.45×t
0.55×t
0.45×t
0.55×t
CK
CK
CK
CK
CK
CK
C
L
C
L
C
L
= 4
= 5
= 6
0.75
0.8
1.0
3, 4
3, 4
3, 4
DS Input Falling
Edge to Clock Setup
Time
t
0.75
0.75
0.8
0.8
1.0
1.0
DSS
t
t
DS (write) Postamble Pulse Width 0.45 × t
0.45 × t
0.8
0.45 × t
1.0
4
DSPST
CK
CK
CK
C
C
C
= 4
= 5
= 6
0.75
0.75
0.75
−0.4 × t
0.3
3, 4
3, 4
3, 4
L
L
L
DS (write) Postamble
Hold Time
0.8
1.0
DSPSTH
0.8
1.0
t
t
t
UDS – LDS Skew
0.4 × t
−0.4 × t
0.35
0.35
0.4 × t
−0.4 × t
0.4
0.4 × t
DSSK
DS
CK
CK
CK
CK
CK
CK
Data Input Setup Time from DS
Data Input Hold Time from DS
4, 11
4, 11
0.3
0.4
DH
Command/Address Input Setup
Time
t
t
0.6
0.6
0.6
0.6
0.7
0.7
3
3
IS
IH
Command/Address Input Hold
Time
Rev 1.3
2005-03-07 9/65
TC59LM836DKB-30,-33,-40
AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2) (continued)
-30
-33
-40
SYMBOL
PARAMETER
UNIT NOTES
MIN
MAX
MIN
MAX
MIN
MAX
Data-out Low Impedance Time from
CLK
t
t
−0.5
−0.5
−0.6
3, 6, 8
3, 7, 8
LZ
Data-out High Impedance Time from
CLK
0.5
0.5
0.6
HZ
t
t
t
Last output to PD High Hold Time
Power Down Exit Time
0
1
0
1
0
1
QPDH
PDEX
T
ns
0.6
0.1
0.6
0.1
0.7
0.1
3
Input Transition Time
PD Low Input Window for
Self-Refresh Entry
t
−0.5 × t
5
−0.5 × t
5
−0.5 × t
CK
5
3
FPDL
CK
CK
t
t
Auto-Refresh Average Interval
Pause Time after Power-up
0.4
200
5
3.9
0.4
200
5
3.9
0.4
200
5
3.9
5
REFI
µs
PAUSE
C
L
C
L
C
L
= 4
= 5
= 6
Random Read/Write
Cycle Time
I
I
I
6
6
6
RC
(applicable to same bank)
7
7
7
RDA/WRA to LAL Command Input
Delay (applicable to same bank)
1
1
1
1
1
1
RCD
RAS
C
L
C
L
C
L
= 4
= 5
= 6
4
5
6
4
5
6
4
5
6
LAL to RDA/WRA
Command Input Delay
(applicable to same bank)
Random Bank Access Delay
(applicable to other bank)
I
I
I
2
2
2
RBD
RWD
WRD
LAL following RDA to
WRA Delay
B
B
= 2
= 4
2
3
2
3
2
3
L
L
(applicable to other bank)
LAL following WRA to RDA Delay
(applicable to other bank)
1
1
1
C
L
C
L
C
L
= 4
= 5
= 6
7
7
7
7
7
7
7
7
7
cycle
Mode Register Set Cycle
Time
I
RSC
PD Low to Inactive State of Input
Buffer
I
I
2
2
2
PD
PD High to Active State of Input
Buffer
1
1
1
PDA
C
L
C
L
C
L
C
L
C
L
C
L
= 4
= 5
= 6
= 4
= 5
= 6
19
23
25
19
23
25
19
23
25
19
23
25
19
23
25
19
23
25
Power down mode valid
from REF command
I
I
PDV
Auto-Refresh Cycle Time
REFC
REF Command to Clock Input
Disable at Self-Refresh Entry
I
I
I
I
I
REFC
CKD
REFC
REFC
DLL Lock-on Time
200
200
200
LOCK
(applicable to RDA command)
Rev 1.3
2005-03-07 10/65
TC59LM836DKB-30,-33,-40
AC TEST CONDITIONS
SYMBOL
PARAMETER
Input High Voltage (minimum)
VALUE
UNIT
NOTES
V
V
V
V
V
V
V
+ 0.2
V
V
IH (min)
IL (max)
REF
REF
REF
Input Low Voltage (maximum)
Input Reference Voltage
− 0.2
/2
V
V
DDQ
Termination Voltage
V
V
TT
REF
Input Signal Peak to Peak Swing
Differential Clock Input Reference Level
Input Differential Voltage
0.8
V
SWING
Vr
V
(AC)
V
X
V
(AC)
1.0
V
ID
SLEW
Input Signal Minimum Slew Rate
Output Timing Measurement Reference Voltage
2.5
V/ns
V
V
V
/2
9
OTR
DDQ
V
DDQ
V
V
(AC)
(AC)
IH min
REF
V
TT
25 Ω
V
SWING
Output
V
IL max
Measurement point
V
SS
∆T
∆T
(AC))/∆T
AC Test Load
SLEW = (V
(AC) − V
IL max
IH min
NOTES:
(1) Transition times are measured between V
(DC) and V
IL max
(DC).
IH min
Transition (rise and fall) of input signals have a fixed slope.
(2) If the result of nominal calculation with regard to t
rounded up to the nearest decimal place.
contains more than one decimal place, the result is
CK
(i.e., t
DQSS
= 0.8 × t , t = 3.3 ns, 0.8 × 3.3 ns = 2.64 ns is rounded up to 2.7 ns.)
CK CK
(3) These parameters are measured from the differential clock (CLK and CLK ) AC cross point.
(4) These parameters are measured from signal transition point of DS crossing V level.
REF
(5) The t
The t
applies to equally distributed refresh method.
applies to both burst refresh method and distributed refresh method.
REFI (max)
REFI (min)
In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400 ns
always. In other words, the number of Auto-Refresh cycles which can be performed within 3.2 µs (8 × 400 ns)
is to 8 times in the maximum.
(6) Low Impedance State is specified at V /2 ± 0.1 V from steady state.
DDQ
(7) High Impedance State is specified where output buffer is no longer driven.
(8) These parameters depend on the clock jitter. These parameters are measured at stable clock.
(9) Output timing is measured by using Normal driver strength at V
= 1.7 V ∼ 1.9 V.
DDQ
= 1.4 V~1.6 V.
Output timing is measured by using Strong driver strength at V
DDQ
(10) These parameters are measured at t
CK
= minimum ∼ 6.0ns. When t is longer than 6.0ns, these parameters
CK
are specified as below for all speed version.
(MIN/MAX) = −0.6ns / 0.6ns, t (MIN/MAX) = −0.65ns / 0.65ns
t
CKQS
AC
(11) These parameters are measured at V
specified as below for all speed version.
= 1.7 V∼1.9 V. Both t
DS
and t
DH
at V
= 1.4 V∼1.6 V are
DDQ
DDQ
t
DS
(MIN) = 0.4 ns , t (MIN) = 0.4 ns
DH
Rev 1.3
2005-03-07 11/65
TC59LM836DKB-30,-33,-40
POWER UP SEQUENCE
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
As for PD , being maintained by the low state (≤ 0.2 V) is desirable before a power-supply injection.
Apply V
Apply V
before or at the same time as V
.
DD
DDQ
before or at the same time as V
.
DDQ
REF
Start clock (CLK, CLK ) and maintain stable condition for 200 µs (min).
After stable power and clock, apply DESL and take PD =H.
Issue EMRS to enable DLL and to define driver strength and data strobe type. (Note: 1)
Issue MRS for set CAS latency (CL), Burst Type (BT), and Burst Length (BL). (Note: 1)
Issue two or more Auto-Refresh commands (Note: 1).
Ready for normal operation after 200 clocks from Extended Mode Register programming.
NOTES:
(1)
Sequence 6, 7 and 8 can be issued in random order.
L = Logic Low, H = Logic High
(2)
(3)
DQ output is Hi-Z state during power upsequence.
2.5V(TYP)
V
DD
1.5V or 1.8V(TYP)
V
DDQ
1/2 V
(TYP)
DDQ
V
REF
CLK
CLK
t
PDEX
l
l
l
l
REFC
RSC
RSC
REFC
200us(min)
PD
l
= 200clock cycle(min)
LOCK
l
PDA
Command
DESLRDA MRS DESL RDA MRS
DESL WRA REF DESL
WRA REF DESL
op-code
EMRS
op-code
Address
MRS
DQ
(Input)
DS
L/UQS
(Uni-QS mode)
Low
L/UQS
(Free Running mode)
EMRS
MRS
Auto Refresh cycle
Normal Operation
Rev 1.3
2005-03-07 12/65
TC59LM836DKB-30,-33,-40
TIMING DIAGRAMS
Input Timing
Command and Address
t
CK
t
t
t
CL
CK
CH
CLK
CLK
t
t
t
t
t
t
t
t
t
t
t
t
IS
IS
IS
IH
IH
IH
IS
IS
IS
IH
IH
IH
CS
FN
1st
1st
2nd
2nd
LA
A0~A13
UA, BA
BA0, BA1
Data
L/UDS
t
t
t
t
DH
DH
DS
DH
DS
DQn (input)
DQm (input)
t
t
t
DH
t
DS
DS
Refer to the Command Truth Table.
Timing of the CLK,
CLK
t
t
CL
CH
V
V
IH
IH
CLK
(AC)
(AC)
V
V
IL
IL
CLK
t
t
T
T
t
CK
CLK
CLK
V
V
IH
IL
V
(AC)
ID
V
V
V
X
X
X
Rev 1.3
2005-03-07 13/65
TC59LM836DKB-30,-33,-40
Read Timing (Burst Length = 4)
Unidirectional DS/QS mode
t
t
t
CK
CH
CL
CLK
CLK
t
t
IS IH
LAL (after RDA)
Input
(control &
addresses)
DESL
DS
(Input)
t
t
CKQS
CKQS
t
t
t
QSP
QSP
CAS latency = 4
CKQS
LQS
Low
Low
(output)
t
t
QSQA
QSQA
t
t
t
QSQ
LZ
QSQV
t
t
t
t
HZ
QSQ
QSQ
QSQV
Q2
LDQ
Hi-Z
Q0
Q1
t
Q3
(output)
t
t
AC
AC
AC
t
OH
t
t
QSQA
QSQA
t
CKQS
t
t
t
QSP QSP
CKQS
UQS
(output)
Low
Low
Hi-Z
t
QSQ
t
t
QSQA
Q1
QSQA
t
t
HZ
QSQV
UDQ
Q0
Q2
t
Q3
(output)
t
LZ
t
AC
AC
t
OH
t
t
AC
t
t
CKQS
CKQS
t
t
QSP
QSP
CAS latency = 5
CKQS
LQS
Low
Low
Hi-Z
(output)
t
t
QSQA
QSQA
t
t
t
QSQ
LZ
QSQV
t
t
t
t
HZ
QSQ
QSQ
QSQV
Q2
LDQ
Q0
Q1
t
Q3
(output)
t
t
AC
AC
AC
t
OH
t
t
QSQA
QSQA
t
CKQS
t
t
t
QSP QSP
CKQS
UQS
(output)
Low
Low
Hi-Z
t
QSQ
t
t
QSQA
Q1
QSQA
t
t
HZ
QSQV
UDQ
Q0
Q2
t
Q3
(output)
t
LZ
t
AC
AC
t
OH
t
AC
Rev 1.3
2005-03-07 14/65
TC59LM836DKB-30,-33,-40
Read Timing (Burst Length = 4)
Unidirectional DS/QS mode
t
t
t
CK
CH
CL
CLK
CLK
t
t
IS IH
LAL (after RDA)
Input
(control &
addresses)
DESL
DS
(Input)
t
t
CKQS
CKQS
t
t
t
QSP
QSP
CAS latency = 6
CKQS
LQS
Low
Low
Hi-Z
(output)
t
t
QSQA
QSQA
t
t
t
QSQ
LZ
QSQV
t
t
t
t
HZ
QSQ
QSQ
QSQV
Q2
LDQ
Q0
Q1
t
Q3
(output)
t
t
AC
AC
AC
t
OH
t
t
QSQA
QSQA
t
CKQS
t
t
t
QSP QSP
CKQS
UQS
(output)
Low
Low
Hi-Z
t
QSQ
t
t
QSQA
Q1
QSQA
t
t
HZ
QSQV
UDQ
Q0
Q2
t
Q3
(output)
t
LZ
t
AC
AC
t
OH
t
AC
Note: DQ0 to DQ35 are aligned with QS.
The correspondence of LQS, UQS to DQ.
LQS
UQS
DQ0~DQ17
DQ18~DQ35
Rev 1.3
2005-03-07 15/65
TC59LM836DKB-30,-33,-40
Read Timing (Burst Length = 4)
Unidirectional DS/Free Running QS mode
t
t
t
CK
CH
CL
CLK
CLK
t
t
IS IH
LAL (after RDA)
Input
(control &
DESL
addresses)
DS
(Input)
t
t
CKQS
CKQS
t
t
t
QSP
QSP
CAS latency = 4
CKQS
LQS
(output)
t
t
QSQA
QSQA
t
t
t
QSQ
LZ
QSQV
t
t
t
t
HZ
QSQ
QSQ
QSQV
Q2
LDQ
Hi-Z
Q0
Q1
t
Q3
(output)
t
t
AC
AC
AC
t
OH
t
t
QSQA
QSQA
t
CKQS
t
t
t
QSP QSP
CKQS
UQS
(output)
t
QSQ
t
t
QSQA
Q1
QSQA
t
t
HZ
QSQV
UDQ
Hi-Z
Q0
Q2
t
Q3
(output)
t
LZ
t
AC
AC
t
OH
t
AC
t
t
CKQS
CKQS
t
t
t
QSP
QSP
CAS latency = 5
CKQS
LQS
(output)
t
t
QSQA
QSQA
t
t
t
QSQ
LZ
QSQV
t
t
t
t
HZ
QSQ
QSQ
QSQV
Q2
LDQ
Hi-Z
Q0
Q1
t
Q3
(output)
t
t
AC
AC
AC
t
OH
t
t
QSQA
QSQA
t
CKQS
t
t
t
QSP QSP
CKQS
UQS
(output)
t
QSQ
t
t
QSQA
Q1
QSQA
t
t
HZ
QSQV
UDQ
Hi-Z
Q0
Q2
t
Q3
(output)
t
LZ
t
AC
AC
t
OH
t
AC
Rev 1.3
2005-03-07 16/65
TC59LM836DKB-30,-33,-40
Read Timing (Burst Length = 4)
Unidirectional DS/Free Running QS mode
t
t
t
CK
CH
CL
CLK
CLK
t
t
IS IH
LAL (after RDA)
Input
(control &
DESL
addresses)
DS
(Input)
t
t
CKQS
CKQS
t
t
t
QSP
QSP
CAS latency = 6
CKQS
LQS
(output)
t
t
QSQA
QSQA
t
t
t
QSQ
LZ
QSQV
t
t
t
t
HZ
QSQ
QSQ
QSQV
Q2
LDQ
Hi-Z
Q0
Q1
t
Q3
(output)
t
t
AC
AC
AC
t
OH
t
t
QSQA
QSQA
t
CKQS
t
t
t
QSP QSP
CKQS
UQS
(output)
t
QSQ
t
t
QSQA
Q1
QSQA
t
t
HZ
QSQV
UDQ
Hi-Z
Q0
Q2
t
Q3
(output)
t
LZ
t
AC
AC
t
OH
t
AC
Note: DQ0 to DQ35 are aligned with QS.
The correspondence of LQS, UQS to DQ.
LQS
UQS
DQ0~DQ17
DQ18~DQ35
Rev 1.3
2005-03-07 17/65
TC59LM836DKB-30,-33,-40
Write Timing (Burst Length = 4)
Unidirectional DS/QS mode, Unidirectional DS/Free Running QS mode
t
t
t
CK
CH
CL
CLK
CLK
t
t
IS IH
LAL (after WRA)
Input
(control &
addresses)
DESL
t
t
DSPSTH
DQSS
t
t
DSS
DSPRES
t
t
t
t
t
DSP DSP DSP DSPST
DSPREH
CAS latency = 4
L/UDS
(input)
t
Preamble
Postamble
DSS
t
DSPRE
t
t
t
t
DS
DS
DS
t
t
DH
DH
DH
DQ
D0
D1
D2
D3
(input)
t
DQSS
t
DSS
t
t
DSPSTH
DSS
t
DSPRES
t
t
t t
DSP DSP DSPST
CAS latency = 5
DSP
t
DSPREH
L/UDS
(input)
Preamble
Postamble
t
DSPRE
t
t
DS
t
DS
DS
t
t
t
DH
DH
DH
DQ
D3
D0
D1
D2
(input)
t
t
DQSS
DQSS
t
DSS
t
t
DSPSTH
DSS
t
DSPRES
t
t
t
t
t
DSP DSP DSP DSPST
CAS latency = 6
t
DSPREH
L/UDS
(input)
Preamble
Postamble
t
DSPRE
t
t
DS
DS
DS
t
t
t
DH
DH
DH
DQ
D3
D0
D1
D2
(input)
t
t
DQSS
DQSS
L/UQS
Low
(Uni-QS)
L/UQS
(Free Runninig)
Note: DQ0 to DQ35 are sampled at both edges of DS.
The correspondence of LDS, UDS to DQ.
LDS
UDS
DQ0~DQ17
DQ18~DQ35
Rev 1.3
2005-03-07 18/65
TC59LM836DKB-30,-33,-40
t
, t
, I
Timing
REFI PAUSE XXXX
CLK
CLK
t
, t
, I
REFI PAUSE XXXX
t
t
t
t
IS IH
IS IH
Input
(control &
addresses)
Command
Command
Note: “I
” means “I ”, “I
”, “I
”, etc.
RAS
XXXX
RC
RCD
Rev 1.3
2005-03-07 19/65
TC59LM836DKB-30,-33,-40
FUNCTION TRUTH TABLE (Notes: 1, 2, 3)
Command Truth Table (Notes: 4)
• The First Command
SYMBOL
FUNCTION
Device Deselect
CS
FN
BA1~BA0
A13~A10
A9~A8
A7
A6~A0
DESL
RDA
H
L
L
×
H
L
×
×
×
×
×
Read with Auto-close
Write with Auto-close
BA
BA
UA
UA
UA
UA
UA
UA
UA
UA
WRA
• The Second Command (The next clock of RDA or WRA command)
BA1~
BA0
A13~
A12
A11~
A10
SYMBOL
FUNCTION
CS
FN
A9
A8
A7
A6~A0
LAL
REF
MRS
Lower Address Latch
Auto-Refresh
H
L
L
×
×
×
×
×
V
×
L
×
×
L
×
×
L
×
×
L
×
×
LA
×
Mode Register Set
V
V
V
Notes: 1. L = Logic Low, H = Logic High, × = either L or H, V = Valid (specified value), BA = Bank Address, UA = Upper Address,
LA = Lower Address
2. All commands are assumed to issue at a valid state.
3. All inputs for command (excluding SELFX and PDEX) are latched on the crossing point of differential clock input where
CLK goes to High.
4. Operation mode is decided by the combination of 1st command and 2nd command. Refer to “STATE DIAGRAM” and
the command table below.
Read Command Table
COMMAND (SYMBOL)
CS
FN
BA1~BA0
A13~A10
A9~A8
A7
A6~A0
NOTES
RDA (1st)
LAL (2nd)
L
H
BA
UA
UA
UA
UA
LA
H
×
×
×
×
×
Write Command Table
COMMAND(SYMBOL)
CS
FN
BA1~BA0
A13
A12
A11
A10
A9~A8
A7
A6~A0
WRA (1st)
LAL (2nd)
L
L
BA
UA
UA
UA
UA
UA
UA
UA
LA
H
×
×
VW0
VW1
×
×
×
×
Notes: 5. A13~ A12 are used for Variable Write Length (VW) control at Write Operation.
VW Truth Table
Burst Length
Function
Write All Words
VW0
VW1
L
H
L
×
×
BL=2
Write First One Word
Reserved
L
Write All Words
H
L
L
BL=4
Write First Two Words
Write First One Word
H
H
H
Rev 1.3
2005-03-07 20/65
TC59LM836DKB-30,-33,-40
FUNCTION TRUTH TABLE (continued)
Mode Register Set Command Table
COMMAND (SYMBOL)
CS
FN
BA1~BA0
A13~A9
A8
A7
A6~A0
NOTES
6
RDA (1st)
L
L
H
×
×
×
×
×
MRS (2nd)
×
V
V
V
V
V
Notes: 6. Refer to “MODE REGISTER TABLE”.
Auto-Refresh Command Table
PD
COMMAND CURRENT
FUNCTION
CS
FN BA1~BA0 A13~A9 A8
A7 A6~A0 NOTES
(SYMBOL)
STATE
n − 1
H
n
H
H
Active
WRA (1st)
REF (2nd)
Standby
Active
L
L
L
×
×
×
×
×
×
×
×
×
×
Auto-Refresh
H
×
Self-Refresh Command Table
PD
COMMAND CURRENT
FUNCTION
CS
FN BA1~BA0 A13~A9 A8
A7 A6~A0 NOTES
(SYMBOL)
STATE
n − 1
H
n
H
L
Active
WRA (1st)
REF (2nd)
Standby
Active
L
L
L
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Self-Refresh Entry
Self-Refresh Continue
Self-Refresh Exit
H
7, 8
9
Self-Refresh
Self-Refresh
L
L
×
SELFX
L
H
H
Power Down Table
PD
COMMAND CURRENT
FUNCTION
CS
FN BA1~BA0 A13~A9 A8
A7 A6~A0 NOTES
(SYMBOL)
STATE
n − 1
n
L
Power Down Entry
Power Down Continue
Power Down Exit
PDEN
Standby
H
L
L
H
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
8
9
Power Down
Power Down
L
PDEX
H
H
Notes:
7. PD has to be brought to Low within t
from REF command.
FPDL
8. PD should be brought to Low after DQ’s state turned high impedance.
9. When PD is brought to High from Low, this function is executed asynchronously.
Rev 1.3
2005-03-07 21/65
TC59LM836DKB-30,-33,-40
FUNCTION TRUTH TABLE (continued)
PD
CURRENT STATE
CS FN
ADDRESS COMMAND
ACTION
NOTES
n − 1
n
H
H
H
H
H
L
H
H
H
L
H
L
×
H
L
×
×
×
×
×
×
×
×
×
×
×
×
×
×
H
L
×
×
×
×
DESL
RDA
WRA
PDEN
NOP
BA, UA
Row activate for Read
Row activate for Write
Power Down Entry
Illegal
L
BA, UA
Idle
H
L
×
10
L
×
×
×
×
Refer to Power Down State
Begin Read
H
H
H
H
L
H
H
L
H
L
LA
LAL
Op-code
MRS/EMRS Access to Mode Register
PDEN Illegal
MRS/EMRS Illegal
Row Active for Read
Row Active for Write
H
L
×
L
×
×
×
×
Invalid
H
H
H
H
L
H
H
L
H
L
LA
LAL
Begin Write
Auto-Refresh
Illegal
×
REF
PDEN
H
L
×
L
×
REF (self) Self-Refresh Entry
×
×
×
DESL
RDA
WRA
PDEN
Invalid
H
H
H
H
H
L
H
H
H
L
H
L
×
Continue Burst Read to End
BA, UA
Illegal
Illegal
Illegal
Illegal
Invalid
11
11
L
BA, UA
Read
H
L
×
×
×
L
×
×
Data Write&Continue Burst Write to
End
H
H
H
×
×
DESL
H
H
H
H
L
H
H
L
L
L
H
L
×
H
L
L
H
L
×
H
L
L
H
L
×
×
×
H
L
×
×
×
×
H
L
×
×
×
×
H
L
×
×
×
×
×
BA, UA
RDA
WRA
PDEN
Illegal
Illegal
Illegal
Illegal
Invalid
11
11
BA, UA
Write
×
L
×
×
×
H
H
H
H
H
L
H
H
H
L
×
DESL
RDA
WRA
PDEN
NOP → Idle after I
Illegal
REFC
BA, UA
BA, UA
Illegal
Auto-Refreshing
×
Self-Refresh Entry
Illegal
12
L
×
×
×
Refer to Self-Refreshing State
H
H
H
H
H
L
H
H
H
L
×
DESL
RDA
WRA
PDEN
NOP → Idle after I
Illegal
RSC
BA, UA
BA, UA
Illegal
Mode Register
Accessing
×
×
×
×
×
Illegal
L
Illegal
×
Invalid
H
L
×
Invalid
L
Maintain Power Down Mode
Power Down
Exit Power Down Mode → Idle after
L
H
H
×
×
PDEX
t
PDEX
L
H
L
L
L
H
×
L
×
×
×
×
×
×
×
×
×
×
×
Illegal
Invalid
L
×
Maintain Self-Refresh
Exit Self-Refresh → Idle after I
Illegal
Self-Refreshing
H
H
H
L
SELFX
REFC
Notes: 10. Illegal if any bank is not idle.
11. Illegal to bank in specified states; Function may be legal in the bank inidicated by Bank Address (BA).
12. Illegal if t is not satisfied.
FPDL
Rev 1.3
2005-03-07 22/65
TC59LM836DKB-30,-33,-40
MODE REGISTER TABLE
Regular Mode Register (Notes: 1)
*1
*1
*3
ADDRESS
Register
BA1
BA0
A13~A8
0
A7
A6~A4
CL
A3
BT
A2~A0
BL
0
0
TE
A7
TEST MODE (TE)
A3
BURST TYPE (BT)
0
1
Regular (default)
Test Mode Entry
0
1
Sequential
Interleave
A6
A5
A4
CAS LATENCY (CL)
A2
A1
A0
BURST LENGTH (BL)
*2
*2
0
0
0
1
1
1
1
0
1
1
0
0
1
1
×
0
1
0
1
0
1
Reserved
0
0
0
0
1
0
0
1
1
×
0
1
0
1
×
Reserved
*2
Reserved
2
4
*2
Reserved
4
5
6
*2
Reserved
*2
Reserved
Extended Mode Register (Notes: 4)
*4
*4
*5
ADDRESS
Register
BA1
BA0
A13~A7
0
A6~A5
SS
A4~A3
A2~A1
A0
0
1
DIC (QS)
DIC (DQ)
DS
QS
DQ
OUTPUT DRIVE IMPEDANCE CONTROL
(DIC)
A6 A5
STROBE SELECT
A4 A3 A2 A1
*2
0
0
1
1
0
1
0
1
Reserved
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
Normal Output Driver
Strong Output Driver
Weak Output Driver
Reserved
*2
Reserved
Unidirectional DS/QS
Unidirectional DS/Free Running QS
A0
DLL SWITCH (DS)
0
1
DLL Enable
DLL Disable
Notes: 1. Regular Mode Register is chosen using the combination of BA0 = 0 and BA1 = 0.
2. “Reserved” places in Regular Mode Register should not be set.
3. A7 in Regular Mode Register must be set to “0” (low state).
Because Test Mode is specific mode for supplier.
4. Extended Mode Register is chosen using the combination of BA0 = 1 and BA1 = 0.
5. A0 in Extended Mode Register must be set to "0" to enable DLL for normal operation.
Rev 1.3
2005-03-07 23/65
TC59LM836DKB-30,-33,-40
STATE DIAGRAM
SELF-
REFRESH
POWER
DOWN
SELFX
PDEX
( PD = H)
( PD = H)
PD = L
PDEN
( PD = L)
STANDBY
(IDLE)
PD = H
AUTO-
MODE
REFRESH
REGISTER
WRA
RDA
REF
MRS
ACTIVE
(RESTORE)
ACTIVE
LAL
LAL
WRITE
(BUFFER)
READ
Command input
Automatic return
The second command at Active state
must be issued 1 clock after RDA or
WRA command input.
Rev 1.3
2005-03-07 24/65
TC59LM836DKB-30,-33,-40
TIMING DIAGRAMS
SINGLE BANK READ TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 5 cycles
I
= 5 cycles
I = 5 cycles
RC
RC
RC
Command
RDA LAL
=1 cycle
DESL
RDA LAL
DESL
= 4 cycles
RDA LAL
DESL
RDA
I
I
= 4 cycles
I
=1 cycle
I
I
=1 cycle
I
= 4 cycles
RAS
RCD
RAS
RCD
UA
RAS
RCD
UA
Address
UA
#0
LA
LA
LA
UA
#0
Bank Add.
#0
#0
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
Low
(output)
CL = 4
CL = 4
CL = 4
DQ
(output)
Hi-Z
Q0 Q1
Q0 Q1
Q0
BL = 4
DS
(input)
QS
(output)
Low
Hi-Z
CL = 4
CL = 4
CL = 4
DQ
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Q0
(output)
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
CL = 4
CL = 4
CL = 4
DQ
Hi-Z
Q0 Q1
Q0 Q1
Q0
(output)
BL = 4
DS
(input)
QS
(output)
CL = 4
CL = 4
CL = 4
DQ
Hi-Z
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Q0
(output)
Rev 1.3
2005-03-07 25/65
TC59LM836DKB-30,-33,-40
SINGLE BANK READ TIMING (CL = 5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 6 cycles
I
= 6 cycles
RC
RC
Command
RDA LAL
DESL
= 5 cycles
RDA LAL
DESL
RDA LAL
DESL
I
=1 cycle
I
I
=1 cycle
I
= 5 cycles
I
=1 cycle
RCD
RAS
RCD
UA
RAS
RCD
Address
UA
LA
LA
UA
LA
Bank Add.
#0
#0
#0
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
CL = 5
CL = 5
DQ
Hi-Z
Q0 Q1
Q0 Q1
(output)
BL = 4
DS
(input)
QS
Low
Hi-Z
(output)
CL = 5
CL = 5
DQ
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
(output)
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
CL = 5
CL = 5
DQ
(output)
Hi-Z
Q0 Q1
Q0 Q1
BL = 4
DS
(input)
QS
(output)
CL = 5
CL = 5
DQ
(output)
Hi-Z
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Rev 1.3
2005-03-07 26/65
TC59LM836DKB-30,-33,-40
SINGLE BANK READ TIMING (CL = 6)
0
1
2
3
4
5
6
7
8
9
10
I
11
12
13
14
15
CLK
CLK
= 7 cycles
I
= 7 cycles
RC
RC
Command
RDA LAL
=1 cycle
DESL
RDA LAL
DESL
RDA LAL
I
I
= 6 cycles
I
=1 cycle
I
= 6 cycles
I
=1 cycle
RCD
RAS
RCD
UA
RAS
RCD
UA
Address
UA
#0
LA
LA
LA
Bank Add.
#0
#0
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
CL = 6
CL = 6
DQ
Hi-Z
Q0 Q1
Q0 Q1
(output)
BL = 4
DS
(input)
QS
Low
Hi-Z
(output)
CL = 6
CL = 6
DQ
Q0 Q1 Q2 Q3
Q0 Q1 Q2
(output)
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
CL = 6
CL = 6
DQ
(output)
Hi-Z
Q0 Q1
Q0 Q1
BL = 4
DS
(input)
QS
(output)
CL = 6
CL = 6
DQ
(output)
Hi-Z
Q0 Q1 Q2 Q3
Q0 Q1 Q2
Rev 1.3
2005-03-07 27/65
TC59LM836DKB-30,-33,-40
SINGLE BANK WRITE TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 5 cycles
I
= 5 cycles
I = 5 cycles
RC
RC
RC
Command
WRA LAL
DESL
WRA LAL
DESL
WRA LAL
DESL
WRA
I
=1 cycle
I
= 4 cycles
I
=1 cycle
I
= 4 cycles
I
=1 cycle
I
= 4 cycles
RAS
RCD
RAS
RCD
RAS
RCD
Address
UA
LA
UA
#0
LA
UA
#0
LA
UA
#0
Bank Add.
#0
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
WL = 3
WL = 3
WL = 3
DQ
(input)
D0 D1
D0 D1
D0 D1
BL = 4
DS
(input)
QS
Low
(output)
WL = 3
WL = 3
WL = 3
DQ
D0 D1 D2 D3
D0 D1 D2 D3
D0 D1 D2 D3
(input)
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
WL = 3
WL = 3
WL = 3
DQ
D0 D1
D0 D1
D0 D1
(input)
BL = 4
DS
(input)
QS
(output)
WL = 3
WL = 3
WL = 3
DQ
D0 D1 D2 D3
D0 D1 D2 D3
D0 D1 D2 D3
(input)
Rev 1.3
2005-03-07 28/65
TC59LM836DKB-30,-33,-40
SINGLE BANK WRITE TIMING (CL = 5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 6 cycles
I
= 6 cycles
RC
RC
Command
WRA LAL
=1 cycle
DESL
WRA LAL
DESL
WRA LAL
DESL
I
I
= 5 cycles
I
=1 cycle
I
= 5 cycles
I
=1 cycle
RCD
RAS
RCD
UA
RAS
RCD
UA
Address
UA
#0
LA
LA
LA
Bank Add.
#0
#0
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
WL = 4
WL = 4
DQ
D0 D1
D0 D1
(input)
BL = 4
DS
(input)
QS
Low
(output)
WL = 4
WL = 4
DQ
(input)
D0 D1 D2 D3
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
WL = 4
WL = 4
DQ
D0 D1
D0 D1
(input)
BL = 4
DS
(input)
QS
(output)
WL = 4
WL = 4
DQ
D0 D1 D2 D3
D0 D1 D2 D3
(input)
Rev 1.3
2005-03-07 29/65
TC59LM836DKB-30,-33,-40
SINGLE BANK WRITE TIMING (CL = 6)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 7 cycles
I
= 7 cycles
RC
RC
Command
WRA LAL
DESL
WRA LAL
DESL
WRA LAL
I
=1 cycle
I
= 6 cycles
I
=1 cycle
I
= 6 cycles
I
=1 cycle
RCD
RAS
RCD
RAS
RCD
Address
UA
LA
UA
LA
UA
LA
Bank Add.
#0
#0
#0
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
WL = 5
WL = 5
DQ
(input)
D0 D1
D0 D1
BL = 4
DS
(input)
QS
Low
(output)
WL = 5
WL = 5
DQ
D0 D1 D2 D3
D0 D1 D2 D3
(input)
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
WL = 5
WL = 5
DQ
D0 D1
D0 D1
(input)
BL = 4
DS
(input)
QS
(output)
WL = 5
WL = 5
DQ
D0 D1 D2 D3
D0 D1 D2 D3
(input)
Rev 1.3
2005-03-07 30/65
TC59LM836DKB-30,-33,-40
SINGLE BANK READ-WRITE TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 5 cycles
I
= 5 cycles
RC
I
= 5 cycles
RC
RC
Command
Address
RDA LAL
DESL
WRA LAL
DESL
RDA LAL
DESL
WRA
UA
UA
#0
LA
UA
#0
LA
UA
#0
LA
Bank Add.
#0
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
CL = 4
WL = 3
CL = 4
Hi-Z
DQ
Q0 Q1
D0 D1
Q0
BL = 4
DS
(input)
QS
Low
(output)
CL = 4
WL = 3
CL = 4
Hi-Z
DQ
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Q0
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
CL = 4
WL = 3
CL = 4
Hi-Z
DQ
Q0 Q1
D0 D1
Q0
BL = 4
DS
(input)
QS
(output)
CL = 4
WL = 3
CL = 4
Hi-Z
DQ
Q0 Q1 Q2 Q3
Read data
D0 D1 D2 D3
Write data
Q0
Rev 1.3
2005-03-07 31/65
TC59LM836DKB-30,-33,-40
SINGLE BANK READ-WRITE TIMING (CL = 5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 6 cycles
I
= 6 cycles
RC
RC
Command
Address
RDA LAL
DESL
WRA LAL
DESL
RDA LAL
DESL
UA
#0
LA
UA
#0
LA
UA
#0
LA
Bank Add.
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
CL = 5
WL = 4
Hi-Z
DQ
Q0 Q1
D0 D1
BL = 4
DS
(input)
QS
Low
(output)
WL = 4
CL = 5
Hi-Z
DQ
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
CL = 5
WL = 4
Hi-Z
DQ
Q0 Q1
D0 D1
BL = 4
DS
(input)
QS
(output)
WL = 4
CL = 5
Hi-Z
DQ
Q0 Q1 Q2 Q3
Read data
D0 D1 D2 D3
Write data
Rev 1.3
2005-03-07 32/65
TC59LM836DKB-30,-33,-40
SINGLE BANK READ-WRITE TIMING (CL = 6)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 7 cycles
I
= 7 cycles
RC
RC
Command
Address
RDA LAL
DESL
WRA LAL
DESL
RDA LAL
UA
#0
LA
UA
#0
LA
UA
#0
LA
Bank Add.
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
CL = 6
WL = 5
Hi-Z
DQ
Q0 Q1
D0 D1
BL = 4
DS
(input)
QS
Low
(output)
WL = 5
CL = 6
Hi-Z
DQ
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
CL = 6
WL = 5
Hi-Z
DQ
Q0 Q1
D0 D1
BL = 4
DS
(input)
QS
(output)
WL = 5
CL = 6
DQ
(output)
Hi-Z
Q0 Q1 Q2 Q3
Read data
D0 D1 D2 D3
Write data
Rev 1.3
2005-03-07 33/65
TC59LM836DKB-30,-33,-40
MULTIPLE BANK READ TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
I
= 2 cycles I
= 2 cyclesI
= 2 cycles I
= 2 cycles
RBD
RBD
RBD
RBD
RBD
Command
Address
RDA LAL RDA LAL DESL RDA LAL RDA LAL RDA LAL RDA LAL RDA LAL RDA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank Add.
I
(Bank"a") = 5 cycles
RC
I
(Bank"b") = 5 cycles
RC
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
Low
(output)
CL = 4
CL = 4
DQ
(output)
Hi-Z
Qa0Qa1
Qb0Qb1
Qa0Qa1
Qb0Qb1
Qc0Qc1
BL = 4
DS
(input)
QS
(output)
Low
Hi-Z
CL = 4
CL = 4
DQ
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3Qc0Qc1Qc2
(output)
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
CL = 4
CL = 4
Hi-Z
DQ
Qa0Qa1
Qb0Qb1
Qa0Qa1
Qb0Qb1
Qc0Qc1
(output)
BL = 4
DS
(input)
QS
(output)
CL = 4
CL = 4
DQ
Hi-Z
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3Qc0Qc1Qc2
(output)
Note: l
to the same bank must be satisfied.
RC
Rev 1.3
2005-03-07 34/65
TC59LM836DKB-30,-33,-40
MULTIPLE BANK READ TIMING (CL = 5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
I
= 2 cycles I
= 2 cycles I
= 2 cycles I
= 2 cycles
RBD
RBD
RBD
RBD
RBD
LAL
LA
Command
Address
RDA LAL RDA LAL
DESL
RDA LAL RDA LAL RDA LAL RDA LAL RDA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank Add.
I
(Bank"a") = 6 cycles
RC
I
(Bank"b") = 6 cycles
RC
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
Low
(output)
CL = 5
CL = 5
DQ
Hi-Z
Qa0Qa1
Qb0Qb1
Qa0Qa1
Qb0Qb1
(output)
BL = 4
DS
(input)
QS
Low
Hi-Z
(output)
CL = 5
CL = 5
DQ
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
Qa0Qa1Qa2Qa3Qb0Qb1Qb2
(output)
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
CL = 5
CL = 5
DQ
Hi-Z
Qa0Qa1
Qb0Qb1
Qa0Qa1
Qb0Qb1
(output)
BL = 4
DS
(input)
QS
(output)
CL = 5
CL = 5
DQ
Hi-Z
Note: l
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
Qa0Qa1Qa2Qa3Qb0Qb1Qb2
(output)
to the same bank must be satisfied.
RC
Rev 1.3
2005-03-07 35/65
TC59LM836DKB-30,-33,-40
MULTIPLE BANK READ TIMING (CL = 6)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
I
= 2 cycles I
= 2 cycles I
= 2 cycles I
= 2 cycles
RBD
RBD
RBD
RBD
RBD
Command
Address
RDA LAL RDA LAL
DESL
RDA LAL RDA LAL RDA LAL RDA LAL RDA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank Add.
I
(Bank"a") = 7 cycles
RC
I
(Bank"b") = 7 cycles
RC
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
Low
(output)
CL = 6
CL = 6
DQ
Hi-Z
Qa0Qa1
Qb0Qb1
Qa0Qa1
(output)
BL = 4
DS
(input)
QS
(output)
Low
Hi-Z
CL = 6
CL = 6
DQ
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
Qa0Qa1Qa2
(output)
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
CL = 6
CL = 6
DQ
Hi-Z
Qa0Qa1
Qb0Qb1
Qa0Qa1
(output)
BL = 4
DS
(input)
QS
(output)
CL = 6
CL = 6
DQ
(output)
Hi-Z
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
Qa0Qa1Qa2
Note: l to the same bank must be satisfied.
RC
Rev 1.3
2005-03-07 36/65
TC59LM836DKB-30,-33,-40
MULTIPLE BANK WRITE TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
I
= 2 cycles I
= 2 cycles I
= 2 cycles I
= 2 cycles
RBD
RBD
RBD
RBD
RBD
Command
Address
WRA LAL WRA LAL DESL WRA LAL WRA LAL WRA LAL WRA LAL WRA LAL WRA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
Bank Add.
I
(Bank"a") = 5 cycles
RC
I
(Bank"b") = 5 cycles
RC
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
Low
(output)
WL = 3
WL = 3
DQ
Da0Da1
Db0Db1
Da0Da1
Db0Db1
Dc0Dc1
Dd0Dd1
(input)
BL = 4
DS
(input)
QS
Low
(output)
WL = 3
WL = 3
DQ
Da0Da1Da2Da3Db0Db1Db2Db3
Da0Da1Da2Da3Db0Db1Db2Db3Dc0Dc1Dc2Dc3Dd0Dd1
(input)
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
WL = 3
WL = 3
DQ
Da0Da1
Db0Db1
Da0Da1
Db0Db1
Dc0Dc1
Dd0Dd1
(input)
BL = 4
DS
(input)
QS
(output)
WL = 3
WL = 3
DQ
Da0Da1Da2Da3Db0Db1Db2Db3
Da0Da1Da2Da3Db0Db1Db2Db3Dc0Dc1Dc2Dc3Dd0Dd1
(input)
Note: l
to the same bank must be satisfied.
RC
Rev 1.3
2005-03-07 37/65
TC59LM836DKB-30,-33,-40
MULTIPLE BANK WRITE TIMING (CL = 5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
I
= 2 cycles I
= 2 cycles I
= 2 cycles I
= 2 cycles
RBD
RBD
RBD
RBD
RBD
Command
Address
WRA LAL WRA LAL
DESL
WRA LAL WRA LAL WRA LAL WRA LAL WRA LAL
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank Add.
I
(Bank"a") = 6 cycles
RC
I
(Bank"b") = 6 cycles
RC
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
Low
(output)
WL = 4
WL = 4
DQ
Da0Da1
Db0Db1
Da0Da1
Db0Db1
Dc0Dc1
(input)
BL = 4
DS
(input)
QS
Low
(output)
WL = 4
WL = 4
DQ
(input)
Da0Da1Da2Da3Db0Db1Db2Db3
Da0Da1Da2Da3Db0Db1Db2Db3Dc0Dc1
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
WL = 4
WL = 4
DQ
Da0Da1
Db0Db1
Da0Da1
Db0Db1
Dc0Dc1
(input)
BL = 4
DS
(input)
QS
(output)
WL = 4
WL = 4
DQ
(input)
Da0Da1Da2Da3Db0Db1Db2Db3
Da0Da1Da2Da3Db0Db1Db2Db3Dc0Dc1
Note: l
to the same bank must be satisfied.
RC
Rev 1.3
2005-03-07 38/65
TC59LM836DKB-30,-33,-40
MULTIPLE BANK WRITE TIMING (CL = 6)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
I
= 2 cycles I
= 2 cycles I
= 2 cycles I
= 2 cycles
RBD
RBD
RBD
RBD
RBD
Command
Address
WRA LAL WRA LAL
WRA LAL WRA LAL WRA LAL WRA LAL WRA
DESL
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank Add.
I
(Bank"a") = 7 cycles
RC
I
(Bank"b") = 7 cycles
RC
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
Low
(output)
WL = 5
WL = 5
DQ
Da0Da1
Db0Db1
Da0Da1
Db0Db1
(input)
BL = 4
DS
(input)
QS
Low
(output)
WL = 5
WL = 5
DQ
(input)
Da0Da1Da2Da3Db0Db1Db2Db3
Da0Da1Da2Da3Db0Db1
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
WL = 5
WL = 5
DQ
Da0Da1
Db0Db1
Da0Da1
Db0Db1
(input)
BL = 4
DS
(input)
QS
(output)
WL = 5
WL = 5
DQ
(input)
Da0Da1Da2Da3Db0Db1Db2Db3
Da0Da1Da2Da3Db0Db1
Note: l
to the same bank must be satisfied.
RC
Rev 1.3
2005-03-07 39/65
TC59LM836DKB-30,-33,-40
MULTIPLE BANK READ-WRITE TIMING (BL = 2)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
RBD
WRA LAL RDA LAL DESL WRA LAL RDA LAL DESL WRA LAL RDA LAL DESL WRA
Command
I
= 1 cycle
I
= 2 cycles
I
= 1 cycle
I
= 2 cycles
RWD
WRD
RWD
WRD
Address
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
Bank
"c"
Bank Add.
I
(Bank"a")
RC
I
(Bank"b")
RC
Unidirectional DS/QS mode
CL = 4
DS
(input)
QS
(output)
Low
Hi-Z
CL = 4
WL = 3
WL = 4
WL = 5
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
Da0 Da1
DQ
CL = 5
DS
(input)
QS
(output)
Low
Hi-Z
CL = 5
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
Da0 Da1
DQ
CL = 6
DS
(input)
QS
(output)
Low
Hi-Z
CL = 6
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
DQ
Unidirectional DS/Free Running QS mode
CL = 4
DS
(input)
QS
(output)
CL = 4
WL = 3
Hi-Z
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
Da0 Da1
Da0 Da1
DQ
CL = 5
DS
(input)
QS
(output)
CL = 5
WL = 4
Hi-Z
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
Da0 Da1
DQ
CL = 6
DS
(input)
QS
(output)
CL = 6
WL = 5
Hi-Z
to the same bank must be satisfied.
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
DQ
Note: l
RC
Rev 1.3
2005-03-07 40/65
TC59LM836DKB-30,-33,-40
MULTIPLE BANK READ-WRITE TIMING (BL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
RBD
DESL
= 3 cycles
DESL
= 3 cycles
Command
WRA LAL RDA LAL
WRA LAL RDA LAL
WRA LAL RDA LAL
I
= 1 cycle
I
I
= 1 cycle
I
I
= 1 cycle
WRD
RWD
WRD
RWD
WRD
Address
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
Bank Add.
I
(Bank"a")
RC
I
(Bank"b")
RC
Unidirectional DS/QS mode
CL = 4
DS
(input)
QS
(output)
Low
Hi-Z
CL = 4
WL = 3
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
Qd0 Qd1 Qd2 Qd3
DQ
CL = 5
DS
(input)
QS
(output)
Low
Hi-Z
CL = 5
WL = 4
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
Qd0 Qd1 Qd2 Qd3
DQ
CL = 6
DS
(input)
QS
(output)
Low
Hi-Z
CL = 6
WL = 5
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
Qd0 Qd1
DQ
Unidirectional DS/Free Running QS mode
CL = 4
DS
(input)
QS
(output)
CL = 4
WL = 3
Hi-Z
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
Qd0 Qd1 Qd2 Qd3
DQ
CL = 5
DS
(input)
QS
(output)
CL = 5
WL = 4
Hi-Z
DQ
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
Qd0 Qd1 Qd2 Qd3
CL = 6
DS
(input)
QS
(output)
CL = 6
WL = 5
Hi-Z
to the same bank must be satisfied.
DQ
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
Qd0 Qd1
Note: l
RC
Rev 1.3
2005-03-07 41/65
TC59LM836DKB-30,-33,-40
WRITE with VARIABLE WRITE LENGTH (VW) CONTROL (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
BL = 2, SEQUENTIAL MODE
Command
WRA LAL
DESL
WRA LAL
DESL
LA=#3
VW=All
LA=#1
VW=1
Address
UA
UA
VW0 = Low
VW1 = don't care
VW0 = High
VW1 = don't care
Bank
"a"
Bank
"a"
Bank Add.
DS
(input)
DQ
D0 D1
D0
(input)
Lower Address #3 #2
#1 (#0)
Last one data is masked.
BL = 4, SEQUENTIAL MODE
Command
Address
WRA LAL
DESL
WRA LAL
DESL
WRA LAL
DESL
LA=#3
LA=#1
LA=#2
UA
UA
UA
VW=All
VW=1
VW=2
VW0 = High
VW1 = Low
VW0 = High
VW1 = High
VW0 = Low
VW1 = High
Bank
"a"
Bank
"a"
Bank
"a"
Bank Add.
DS
(input)
DQ
D0 D1 D2 D3
D0
D0 D1
(input)
Lower Address #3 #0 #1 #2
#1(#2)(#3)(#0)
Last three data are masked.
#2 #3 (#0)(#1)
Last two data are masked.
Note: DS input must be continued till end of burst count even if some of laster data is masked.
Rev 1.3
2005-03-07 42/65
TC59LM836DKB-30,-33,-40
POWER DOWN TIMING (CL = 4, BL = 4)
Read cycle to Power Down Mode
0
1
2
3
4
5
6
7
8
9
10
n-2
n-1
n
n+1
n+2
CLK
CLK
I
PDA
RDA
or
Command
Address
RDA LAL
DESL
DESL
WRA
UA
LA
UA
t
I
= 2 cycle
PD
IS
t
IH
PD
t
t
PDEX
QPDH
l
, t
RC(min) REFI(max)
Unidirectional DS/QS mode
DS
(input)
QS
Low
(output)
CL = 4
DQ
Hi-Z
Hi-Z
Q0 Q1 Q2 Q3
(output)
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(output)
CL = 4
DQ
(output)
Hi-Z
Hi-Z
Q0 Q1 Q2 Q3
Power Down Entry
Note: PD must be kept "High" level until end of Burst data output.
Power Down Exit
cycles later.
PD should be brought to "High" within t
(max.) to maintain the data written into cell.
REFI
In Power Down Mode, PD "Low" and a stable clock signal must be maintained.
When PD is brought to "High", a valid executable command may be applied l
PDA
Rev 1.3
2005-03-07 43/65
TC59LM836DKB-30,-33,-40
POWER DOWN TIMING (CL = 4, BL = 4)
Write cycle to Power Down Mode
0
1
2
3
4
5
6
7
8
9
10
n-2
n-1
n
n+1
n+2
CLK
CLK
I
PDA
RDA
or
Command
Address
WRA LAL
DESL
DESL
WRA
UA
LA
UA
t
I
= 2 cycle
PD
IS
t
IH
PD
WL = 3
2 clock cycles
t
PDEX
l
, t
RC(min) REFI(max)
Unidirectional DS/QS mode
DS
(input)
QS
Low
(output)
WL = 3
DQ
D0 D1 D2 D3
(input)
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(output)
WL = 3
DQ
(input)
D0 D1 D2 D3
Note: PD must be kept "High" level until WL+2 clock cycles from LAL command.
PD should be brought to "High" within t (max.) to maintain the data written into cell.
REFI
In Power Down Mode, PD "Low" and a stable clock signal must be maintained.
When PD is brought to "High", a valid executable command may be applied l
cycles later.
PDA
Rev 1.3
2005-03-07 44/65
TC59LM836DKB-30,-33,-40
MODE REGISTER SET TIMING (CL = 4, BL = 2)
From Read operation to Mode Register Set operation.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 7 cycles
RSC
RDA
or
Command
Address
RDA LAL
DESL
RDA MRS
DESL
LAL
LA
WRA
Valid
(opcode)
UA
BA
LA
UA
BA
BA0="0"
BA1="0"
Bank Add.
CL + BL/2
Unidirectional DS/QS mode
DS
(input)
QS
(output)
Low
DQ
Q0 Q1
(output)
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(output)
DQ
Q0 Q1
(output)
Note: Minimum delay from LAL following RDA to RDA of MRS operation is CL+BL/2 clock cycles.
Rev 1.3
2005-03-07 45/65
TC59LM836DKB-30,-33,-40
MODE REGISTER SET TIMING (CL = 4, BL = 4)
From Write operation to Mode Register Set operation.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 7 cycles
RSC
RDA
or
Command
Address
WRA LAL
DESL
RDA MRS
DESL
LAL
LA
WRA
Valid
(opcode)
UA
BA
LA
UA
BA
BA0="0"
BA1="0"
Bank Add.
WL+BL/2
Unidirectional DS/QS mode
DS
(input)
QS
Low
(output)
DQ
D0 D1 D2 D3
(input)
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(output)
DQ
D0 D1 D2 D3
(input)
Note: Minimum delay from LAL following WRA to RDA of MRS operation is WL+BL/2 clock cycles.
Rev 1.3
2005-03-07 46/65
TC59LM836DKB-30,-33,-40
EXTENDED MODE REGISTER SET TIMING (CL = 4, BL = 2)
From Read operation to Extended Mode Register Set operation.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 7 cycles
RSC
RDA
or
Command
Address
RDA LAL
DESL
RDA MRS
DESL
LAL
LA
WRA
Valid
(opcode)
UA
BA
LA
UA
BA
BA0="1"
BA1="0"
Bank Add.
CL + BL/2
Unidirectional DS/QS mode
DS
(input)
QS
Low
(output)
DQ
(output)
Q0 Q1
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(output)
DQ
Q0 Q1
(output)
Note: Minimum delay from LAL following RDA to RDA of EMRS operation is CL+BL/2 clock cycles.
When DQ strobe mode is changed by EMRS, QS output is invalid for l period.
RSC
DLL switch in Extended Mode Register must be set to enable mode for normal operation.
DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence.
Rev 1.3
2005-03-07 47/65
TC59LM836DKB-30,-33,-40
EXTENDED MODE REGISTER SET TIMING (CL = 4, BL = 4)
From Write operation to Extended Mode Register Set operation.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 7 cycles
RSC
RDA
or
Command
Address
WRA LAL
DESL
RDA MRS
DESL
LAL
LA
WRA
Valid
(opcode)
UA
BA
LA
UA
BA
BA0="1"
BA1="0"
Bank Add.
WL+BL/2
Unidirectional DS/QS mode
DS
(input)
QS
Low
(output)
DQ
D0 D1 D2 D3
(input)
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(output)
DQ
D0 D1 D2 D3
(input)
Note: When DQ strobe mode is changed by EMRS, QS output is invalid for l
period.
RSC
DLL switch in Extended Mode Register must be set to enable mode for normal operation.
DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence.
Minimum delay from LAL following WRA to RDA of EMRS operation is WL+BL/2 clock cycles.
Rev 1.3
2005-03-07 48/65
TC59LM836DKB-30,-33,-40
AUTO-REFRESH TIMING (CL = 4, BL = 4)
Unidirectional DS/QS mode
0
1
2
3
4
5
6
7
n − 1
n
n + 1
n + 2
CLK
CLK
I
= 5 cycles
I
= 19 cycles
REFC
RC
RDA LAL or
or MRS or
WRA REF
Command
RDA
LAL
DESL
WRA
REF
DESL
Bank,
UA
Bank,Address
LA
I
= 1 cycle
I
= 4 cycles
I = 1 cycle
RCD
RCD
RAS
QS
(output)
Low
Hi-Z
Low
Hi-Z
CL = 4
DQ
Q0 Q1 Q2 Q3
(output)
Unidirectional DS/Free Running QS mode
CLK
CLK
I
= 5 cycles
I
= 19 cycles
REFC
RC
RDA LAL or
or MRS or
WRA REF
Command
RDA
LAL
LA
DESL
WRA
REF
DESL
Bank,
UA
Bank,Address
I
= 1 cycle
I
= 4 cycles
I = 1 cycle
RCD
RCD
RAS
QS
(output)
CL = 4
DQ
(output)
Hi-Z
Hi-Z
Q0 Q1 Q2 Q3
Note: In case of CL = 4, I
must be meet 19 clock cycles.
REFC
When the Auto-Refresh operation is performed, the synthetic average interval of Auto-Refresh
command specified by t must be satisfied.
REFI
t
is average interval time in 8 Refresh cycles that is sampled randomly.
REFI
t
t
t
t
t
8
1
2
3
7
CLK
WRA REF
WRA REF
WRA REF
WRA REF
WRA REF
8 Refresh cycle
Total time of 8 Refresh cycle
8
t + t + t + t + t + t + t + t
1 2 3 4 5 6 7 8
t
=
=
REFI
8
t
is specified to avoid partly concentrated current of Refresh operation that is activated larger area
REFI
than Read / Write operation.
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TC59LM836DKB-30,-33,-40
SELF-REFRESH ENTRY TIMING
Unidirectional DS/QS mode
0
1
2
3
4
5
m − 1
m
m + 1
CLK
CLK
I
= 1 cycle
I
REFC
RCD
Command
PD
WRA
REF
DESL
t
t
FPDL (min) FPDL (max)
Auto Refresh
Self Refresh Entry
*2
I
PDV
t
QPDH
I
CKD
QS
Hi-Z
(output)
Low
DQ
Hi-Z
Qx
Notes: 1.
(output)
is don’t care.
2. PD must be brought to "Low" within the timing between t
(min) and t (max) to Self
FPDL FPDL
Refresh mode. When PD is brought to "Low" after l
, TC59LM836DKB perform Auto Refresh
PDV
and enter Power down mode. In case of PD fall between t
(max) and l
FPDL
, TC59LM836DKB
PDV
will either entry Self-Refresh mode or Power down mode after Auto-Refresh operation.
3. It is desirable that clock input is continued at least l
brought to “Low” for Self-Refresh Entry.
from REF command even though PD is
CKD
4. In case of Self-Refresh entry after Write Operation, the delay time from the LAL command
following WRA to the REF command is Write latency (WL)+2 clock cycles minimum.
SELF-REFRESH EXIT TIMING
Unidirectional DS/QS mode
0
1
2
m − 1
m
m + 1 m + 2
n − 1
n
n + 1
p − 1
p
CLK
CLK
*2
*5
Command (1st)
Command (2nd)
I
I
*5
*6
REFC
REFC
*3
*4
*4
*6
Command
PD
DESL
WRA
REF
DESL
RDA
LAL
I
= 1 cycle
I
= 1 cycle
RCD
RCD
t
PDEX
I
LOCK
QS
Hi-Z
Hi-Z
Low
(output)
DQ
(output)
Self-Refresh Exit
Notes: 1. is don’t care.
2. Clock should be stable prior to PD = “High” if clock input is suspended in Self-Refresh mode.
3. DESL command must be asserted during I after PD is brought to “High”.
REFC
4. It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any
other operation.
5. Any command (except Read command) can be issued after I
.
REFC
6. Read command (RDA + LAL) can be issued after I
.
LOCK
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TC59LM836DKB-30,-33,-40
SELF-REFRESH ENTRY TIMING
Unidirectional DS/Free Running QS mode
0
1
2
3
4
5
m − 1
m
m + 1
CLK
CLK
I
= 1 cycle
I
REFC
RCD
Command
PD
WRA
REF
DESL
t
t
FPDL (min) FPDL (max)
Auto Refresh
Self Refresh Entry
*2
I
PDV
t
QPDH
I
CKD
QS
Hi-Z
Hi-Z
(output)
DQ
(output)
Qx
Notes: 1.
is don’t care.
2. PD must be brought to "Low" within the timing between t
(min) and t (max) to Self
FPDL FPDL
Refresh mode. When PD is brought to "Low" after l
, TC59LM836DKB perform Auto Refresh
PDV
and enter Power down mode. In case of PD fall between t
(max) and l
FPDL
, TC59LM836DKB
PDV
will either entry Self-Refresh mode or Power down mode after Auto-Refresh operation.
3. It is desirable that clock input is continued at least l
brought to “Low” for Self-Refresh Entry.
from REF command even though PD is
CKD
SELF-REFRESH EXIT TIMING
Unidirectional DS/Free Running QS mode
0
1
2
m − 1
m
m + 1 m + 2
n − 1
n
n + 1
p − 1
p
CLK
CLK
*2
*5
Command (1st)
Command (2nd)
I
I
REFC
*5
*6
REFC
*3
*4
*4
*6
Command
PD
DESL
WRA
REF
DESL
RDA
LAL
I
= 1 cycle
I
= 1 cycle
RCD
RCD
t
PDEX
I
LOCK
QS
(output)
DQ
Hi-Z
(output)
Self-Refresh Exit
Notes: 1. is don’t care.
2. Clock should be stable prior to PD = “High” if clock input is suspended in Self-Refresh mode.
3. DESL command must be asserted during I after PD is brought to “High”.
REFC
4. It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any
other operation.
5. Any command (except Read command) can be issued after I
.
REFC
6. Read command (RDA + LAL) can be issued after I
.
LOCK
7. QS output is invalid until DLL lock from Self-Refresh exit.
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TC59LM836DKB-30,-33,-40
FUNCTIONAL DESCRIPTION
TM
Network FCRAM
The FCRAMTM is an acronym of Fast Cycle Random Access Memory.
The Network FCRAMTM is competent to perform fast random core access, low latency and high-speed data
transfer.
PIN FUNCTIONS
CLOCK INPUTS: CLK & CLK
The CLK and CLK inputs are used as the reference for synchronous operation. CLK is master clock input.
The CS , FN and all address input signals are sampled on the crossing of the positive edge of CLK and the
negative edge of CLK . The QS and DQ output data are aligned to the crossing point of CLK and CLK . The
timing reference point for the differential clock is when the CLK and CLK signals cross during a transition.
POWER DOWN: PD
The PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a
Clock Suspend function like a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into
low state if any Read or Write operation is being performed.
CS
CHIP SELECT & FUNCTION CONTROL:
& FN
The CS and FN inputs are a control signal for forming the operation commands on FCRAMTM. Each
operation mode is decided by the combination of the two consecutive operation commands using the CS and
FN inputs.
BANK ADDRESSES: BA0 & BA1
The BA0 and BA1 inputs are latched at the time of assertion of the RDA or WRA command and are selected
the bank to be used for the operation. BA0 and BA1 also define which mode register is loaded during the Mode
Register Set command (MRS or EMRS).
BA0
BA1
Bank #0
Bank #1
Bank #2
Bank #3
0
1
0
1
0
0
1
1
ADDRESS INPUTS: A0~A13
Address inputs are used to access the arbitrary address of the memory cell array within each bank. The
Upper Addresses with Bank addresses are latched at the RDA or WRA command and the Lower Addresses are
latched at the LAL command. The A0 to A13 inputs are also used for setting the data in the Regular or
Extended Mode Register set cycle.
I/O Organization
36 bits
UPPER ADDRESS
A0~A13
LOWER ADDRESS
A0~A6
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TC59LM836DKB-30,-33,-40
DATA INPUT/OUTPUT: DQ0~DQ35
The input data of DQ0 to DQ35 are taken in synchronizing with the both edges of DS input signal. The output
data of DQ0 to DQ35 are outputted synchronizing with the both edges of QS output signal.
DATA STROBE: LDS, UDS, LQS, UQS
Method of data strobe is chosen by Extended mode register. LDS and LQS are for DQ0 to DQ17. UDS and
UQS are for DQ18 to DQ35.
(1) Unidirectional DS / QS mode
DS is input signal and QS is output signal. Both edges of DS are used to sample all DQs at Write
operation. Both edges of QS are used for trigger signal of all DQs at Read operation. During Write,
Auto-Refresh and NOP cycle, QS assert always “Low” level. QS is Hi-Z in Self-Refresh mode.
(2) Unidirectional DS / Free running QS mode
DS is input signal and QS is output signal. Both edge of DS are used to sample all DQs at Write operation.
Both edges of QS are used for trigger signal of all DQs at Read operation. QS assert always toggle signal
except Self-Refresh mode. This strobe type is easy to use for pin to pin connect application.
POWER SUPPLY: V , V
, V , V
SS SSQ
DD DDQ
V
and V are power supply pins for memory core and peripheral circuits.
DD
SS
and V
V
DDQ
are power supply pins for the output buffer.
SSQ
REFERENCE VOLTAGE: V
REF
V
REF
is reference voltage for all input signals.
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TC59LM836DKB-30,-33,-40
COMMAND FUNCTIONS and OPERATIONS
TC59LM836DKB are introduced the two consecutive command input method. Therefore, except for Power Down
mode, each operation mode decided by the combination of the first command and the second command from
stand-by states of the bank to be accessed.
Read Operation (1st command + 2nd command = RDA + LAL)
Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank
designated by Bank Address in a read mode. When the LAL command with Lower Addresses is issued at the
next clock of the RDA command, the data is read out sequentially synchronizing with the both edges of QS
output signal (Burst Read Operation). The initial valid read data appears after CAS latency from the issuing
of the LAL command. The valid data is outputted for a burst length. The CAS latency, the burst length of read
data and the burst type must be set in the Mode Register beforehand. The read operated bank goes back
automatically to the idle state after l
.
RC
Write Operation (1st command + 2nd command = WRA + LAL)
Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank
designated by Bank Address in a write mode. When the LAL command with Lower Addresses is issued at the
next clock of the WRA command, the input data is latched sequentially synchronizing with the both edges of DS
input signal (Burst Write Operation). The data and DS inputs have to be asserted in keeping with clock input
after CAS latency-1 from the issuing of the LAL command. The DS has to be provided for a burst length. The
CAS latency and the burst type must be set in the Mode Register beforehand. The write operated bank goes
back automatically to the idle state after l . Write Burst Length is controlled by VW0 and VW1 inputs with
RC
LAL command. See VW truth table.
Auto-Refresh Operation (1st command + 2nd command = WRA + REF)
TC59LM836DKB are required to refresh like a standard SDRAM. The Auto-Refresh operation is begun with
the REF command following to the WRA command. The Auto-Refresh mode can be effective only when all banks
are in the idle state. In a point to notice, the write mode started with the WRA command is canceled by the REF
command having gone into the next clock of the WRA command instead of the LAL command. The minimum
period between the Auto-Refresh command and the next command is specified by l . However, about a
REFC
synthetic average interval of Auto-Refresh command, it must be careful. In case of equally distributed refresh,
Auto-Refresh command has to be issued within once for every 3.9 µs by the maximum. In case of burst refresh
or random distributed refresh, the average interval of eight consecutive Auto-Refresh commands has to be more
than 400 ns always. In other words, the number of Auto-Refresh cycles that can be performed within 3.2 µs (8 ×
400 ns) is to 8 times in the maximum.
Self-Refresh Operation (1st command + 2nd command = WRA + REF with
In case of Self-Refresh operation, refresh operation can be performed automatically by using an internal timer.
= “L”)
PD
When all banks are in the idle state and all outputs are in Hi-Z states, the TC59LM836DKB become
Self-Refresh mode by issuing the Self-Refresh command. PD has to be brought to “Low” within t
FPDL
from the
REF command following to the WRA command for a Self-Refresh mode entry. In order to satisfy the refresh
period, the Self-Refresh entry command should be asserted within 3.9 µs after the latest Auto-Refresh command.
Once the device enters Self-Refresh mode, the DESL command must be continued for l
it is desirable that clock input is kept in l
CKD
period. In addition,
REFC
period. The device is in Self-Refresh mode as long as PD held
“Low”. During Self-Refresh mode, all input and output buffers are disabled except for PD , therefore the power
dissipation lowers. Regarding a Self-Refresh mode exit, PD has to be changed over from “Low” to “High” along
with the DESL command, and the DESL command has to be continuously issued in the number of clocks
specified by l
. The Self-Refresh exit function is asynchronous operation. It is required that one
REFC
Auto-Refresh command is issued to avoid the violation of the refresh period just after l
exit.
from Self-Refresh
REFC
Power Down Mode (
= “L”)
PD
When all banks are in the idle state and DQ outputs are in Hi-Z states, the TC59LM836DKB become Power
Down Mode by asserting PD is “Low”. When the device enters the Power Down Mode, all input and output
buffers are disabled after specified time except for PD , CLK, CLK and QS. Therefore, the power dissipation
lowers. To exit the Power Down Mode, PD has to be brought to “High” and the DESL command has to be
issued for lPDA cycle after PD goes high. The Power Down exit function is asynchronous operation.
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TC59LM836DKB-30,-33,-40
Mode Register Set (1st command + 2nd command = RDA + MRS)
When all banks are in the idle state, issuing the MRS command following to the RDA command can program
the Mode Register. In a point to notice, the read mode started with the RDA command is canceled by the MRS
command having gone into the next clock of the RDA command instead of the LAL command. The data to be set
in the Mode Register is transferred using A0 to A13, BA0 and BA1 address inputs. The TC59LM836DKB have
two mode registers. These are Regular and Extended Mode Register. The Regular or Extended Mode Register is
chosen by BA0 and BA1 in the MRS command. The Regular Mode Register designates the operation mode for a
read or write cycle. The Regular Mode Register has four function fields.
The four fields are as follows:
(R-1) Burst Length field to set the length of burst data
(R-2) Burst Type field to designate the lower address access sequence in a burst cycle
(R-3)CAS Latency field to set the access time in clock cycle
(R-4) Test Mode field to use for supplier only.
The Extended Mode Register has three function fields.
The three fields are as follows:
(E-1) DLL Switch field to choose either DLL enable or DLL disable
(E-2) Output Driver Impedance Control field.
(E-3) Data Strobe Select
Once those fields in the Mode Register are set up, the register contents are maintained until the Mode
Register is set up again by another MRS command or power supply is lost. The initial value of the Regular or
Extended Mode Register after power-up is undefined, therefore the Mode Register Set command must be issued
before proper operation.
•
Regular Mode Register/Extended Mode Register change bits (BA0, BA1)
These bits are used to choose either Regular MRS or Extended MRS
BA1
BA0
Mode Register Set
0
0
1
0
1
×
Regular MRS
Extended MRS
Reserved
Regular Mode Register Fields
(R-1) Burst Length field (A2 to A0)
This field specifies the data length for column access using the A2 to A0 pins and sets the Burst
Length to be 2 or 4 words.
A2
A1
A0
BURST LENGTH
0
0
0
0
1
0
0
1
1
×
0
1
0
1
×
Reserved
2 words
4 words
Reserved
Reserved
(R-2) Burst Type field (A3)
The Burst Type can be chosen Interleave mode or Sequential mode. When the A3 bit is “0”,
Sequential mode is selected. When the A3 bit is “1”, Interleave mode is selected. Both burst types
support burst length of 2 and 4 words.
A3
BURST TYPE
0
1
Sequential
Interleave
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TC59LM836DKB-30,-33,-40
• Addressing sequence of Sequential mode (A3)
A column access is started from the inputted lower address and is performed by incrementing the lower
address input to the device
CAS Latency = 4 (Free Running QS mode)
CLK
CLK
Command
RDA
LAL
QS
Data Data Data Data
DQ
0
1
2
3
Addressing sequence for Sequential mode
DATA
ACCESS ADDRESS
BURST LENGTH
Data 0
Data 1
Data 2
Data 3
n
2 words (address bits is LA0)
not carried from LA0~LA1
n + 1
n + 2
n + 3
4 words (address bits is LA1, LA0)
not carried from LA1~LA2
• Addressing sequence of Interleave mode
A column access is started from the inputted lower address and is performed by interleaving the address
bits in the sequence shown as the following.
Addressing sequence for Interleave mode
DATA
ACCESS ADDRESS
BURST LENGTH
Data 0
Data 1
Data 2
Data 3
ּּּA8 A7 A6 A5 A4 A3 A2 A1 A0
ּּּA8 A7 A6 A5 A4 A3 A2 A1 A0
ּּּA8 A7 A6 A5 A4 A3 A2 A1 A0
ּּּA8 A7 A6 A5 A4 A3 A2 A1 A0
2 words
4 words
(R-3) CAS Latency field (A6 to A4)
This field specifies the number of clock cycles from the assertion of the LAL command following the
RDA command to the first data read. The minimum value of CAS Latency depends on the frequency
of CLK. In a write mode, the place of clock that should input write data is CAS Latency cycles − 1.
A6
A5
A4
CAS LATENCY
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
Reserved
4
5
6
Reserved
(R-4) Test Mode field (A7)
This bit is used to enter Test Mode for supplier only and must be set to “0” for normal operation.
(R-5) Reserved field in the Regular Mode Register
• Reserved bits (A8 to A13)
These bits are reserved for future operations. They must be set to “0” for normal operation.
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TC59LM836DKB-30,-33,-40
Extended Mode Register fields
(E-1) DLL Switch field (A0)
This bit is used to enable DLL. When the A0 bit is set “0”, DLL is enabled. This bit must be set to “0”
for normal operation.
(E-2) Output Driver Impedance Control field (A1 to A4)
This field is used to choose Output Driver Strength. Three types of Driver Strength are supported.
QS and DQ Driver Strength can be chosen separately. A2-A1 specified the DQ Driver Strength. A4-A3
specified the QS Driver Strength.
QS
DQ
OUTPUT DRIVER IMPEDANCE CONTROL
A4
A3
A2
A1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
Normal Output Driver
Strong Output Driver
Weak Output Driver
Reserved
(E-3) Strobe Select (A6 / A5)
Two types of data strobe are supported. This field is used to choose the type of data strobe.
(1) Unidirectional DS/QS mode
Data strobe is separated DS for write strobe and QS for read strobe.
DS is used to sample write data at write operation. QS is aligned with read data at Read
operation.
(2) Unidirectional DS/Free running QS mode
Data strobe is separated DS for write strobe and QS for read strobe.
DS is used to sample write data at write operation. QS is aligned with read data and always
clocking.
A6
A5
STROBE SELECT
0
0
1
1
0
1
0
1
Reserved
Reserved
Unidirectional DS/QS mode
Unidirectional DS/Free running QS mode
(E-4) Reserved field (A7 to A13)
These bits are reserved for future operations and must be set to “0” for normal operation.
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TC59LM836DKB-30,-33,-40
BOUNDARY SCAN TEST ACCESS PORT OPERATIONS
The TC59LM836DKB has a serial boundary scan test access port (TAP) which is compatible with IEEE Standard
1149.1 – 1990, but which does not implement all the functions required for 1149.1 – 1990. TCK must be tied to VSS
or VDD to disable the TAP when TAP operation is not required.
Test Access Port Signals
SYMBOL
DESCRIPTION
All Test Access Port inputs are sampled on the rising edge of TCK. To disable
TCK
Test Clock Input
the TAP, TCK must be tied to V or V
.
SS
DD
The signal presented at TMS is sampled on the rising edge of TCK. This input
is internally pulled up so as to recognize a floating input as a logical High
(Test-Logic-Reset).
TMS
Test Mode Select Input
Values presented at TDI are clocked into the selected register on the rising
edge of TCK. This input is internally pulled up. This enables detection of when
the TDI input to the board is open-circuit.
TDI
Test Data Input
TDO is the serial output for test instructions and data from the test logic. This
output is controlled by the falling edge of TCK.
TDO
Test Data Output
Test Access Port Registers
REGISTER
SYMBOL
IR [ 2 : 0 ]
LENGTH (bits)
3
DESCRIPTION
The Instruction register controls five states (EXTEST,
Sample-Z, Sample, Bypass, ID code).
Instruction Register
Test Data Register
The register includes information on revision number,
organization and TOSHIBA ID number.
ID Register
IDR [ 31 : 0 ]
BR
32
1
Bypass Register
The register connects TDI and TDO.
The Boundary Scan register is comprised of boundary scan
cells at each input and I/O pin. The BSCs are serially
connected between TDI and TDO.
Boundary Scan Register
BSR [ 62 : 0 ]
63
TAP Controller Instruction Set
IR2
IR1
IR0
INSTRUCTION
DESCRIPTION
Moves the Preloaded data on to the output pins. Samples the inputs
connected to the BSCs.
0
0
0
EXTEST
0
0
0
0
1
1
1
0
1
ID CODE
SAMPLE – Z
RESERVED
Access ID code.
Tristates the RAM outputs and samples the inputs connected to the BSCs.
This instruction is reserved for future use.
Samples the inputs connected to the BSCs. Load the sampled data at I/Os
to the parallel output of the BSCs. Does not affect RAM operation.
1
0
0
SAMPLE
1
1
1
0
1
1
1
0
1
RESERVED
RESERVED
BYPASS
This instruction is reserved for future use.
This instruction is reserved for future use.
Bypasses TDI and TDO using the Bypass register.
Note: The first bit to be scanned into TDI is taken to be the least significant bit (IR0).
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TC59LM836DKB-30,-33,-40
ID Register
BIT # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
0
8
1
7
0
6
0
5
1
4
1
3
0
2
0
1
0
0
1
Value
0
0
0
1
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
Fi
xe
d
Content
Memory Type
TOSHIBA ID number
Boundary Scan Order
BIT
BALL LAYOUT BALL NAME
BIT
BALL LAYOUT BALL NAME
0
U10
U11
T10
T11
R10
R11
P10
P11
N10
N11
M3
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
UQS
A4
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
B10
B3
B2
C3
C2
D3
DQ0
DQ17
DQ16
DQ15
DQ14
DQ13
1
2
3
4
5
6
7
D2
E3
E2
F3
F2
G3
H3
H2
J2
DQ12
DQ11
DQ10
DQ9
LDS
/CLK
CLK
/PD
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
M11
L10
L11
K10
K11
J10
J11
A3
A2
A1
A0
A10
A12
BA1
BA0
A13
J3
A11
K2
K3
L2
A9
G10
G11
H10
F11
F10
E11
E10
D11
D10
C11
C10
B11
A8
FN
A7
/CS
L3
A6
LQS
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
M2
N2
N3
P2
P3
R2
A5
UDS
DQ26
DQ25
DQ24
DQ23
R3
T2
T3
U2
U3
DQ22
DQ21
DQ20
DQ19
DQ18
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TC59LM836DKB-30,-33,-40
TAP CONTROLLER STATE DIAGRAM
TMS = 1
TMS = 0
Test – Logic - Reset
TMS = 0
TMS = 1
TMS = 1
TMS = 1
Run – Test / Idle
Select – DR - Scan
TMS = 0
Select – IR - Scan
TMS = 0
TMS = 1
Capture - DR
TMS = 0
Capture - IR
TMS = 1
TMS = 0
TMS = 0
TMS = 1
TMS = 0
TMS = 1
Shift - DR
TMS = 1
Shift - IR
TMS = 1
Exit1 - IR
TMS = 0
Pause - IR
TMS = 1
Exit1 - DR
TMS = 0
TMS = 0
Pause - DR
TMS = 1
TMS = 0
TMS = 0
Exit2 - DR
TMS = 1
Exit2 - IR
TMS = 0
TMS = 1
Update - IR
Update - DR
TMS = 0
TMS = 1
TMS = 1
TMS = 0
Notes:
1. To enter the Test-Logic-Reset state in order to initialize the device, keep TMS High for at least five rising edges of the TCK.
2. The TDO output buffer is active only during shift operations (the Shift-DR and Shift-IR states) and is inactive (High-Z) during
other states.
Rev 1.3
2005-03-07 60/65
TC59LM836DKB-30,-33,-40
TAP DC OPERATING CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITION
MIN
TYP
MAX
10
UNIT
Output Leakage Current
(TDO pin)
Output Deselected
I
I
−10
µA
LO
V
=0 to V
DD
OUT
V
= 1.7V to V
−20
10
10
µA
µA
IN
DD
Input Leakage Current
(TCK, TMS, TDI pins)
I
V
= 0 to 0.7V
−100
IN
Input High Voltage
V
V
V
+0.4
V +0.2
DD
V
V
IH
IL
REF
(TCK, TMS, TDI pins)
Input Low Voltage
−0.1
V
−0.4
REF
(TCK, TMS, TDI pins)
V
V
Output High Voltage (TDO pin)
Output Low Voltage (TDO pin)
I
= −2 mA
1.5
V
DD
V
V
OH
OL
OH
I
= 2 mA
0.45
OL
AC CHARACTERISTICS ( V
= 2.5V ± 0.125V, V
= 1.4V ~ 1.9V, T = 0 ~ 85°C )
CASE
DD
DDQ
TC59LM836DKB
SYMBOL
PARAMETER
UNIT
MIN
50
20
20
10
10
10
10
10
10
0
MAX
20
5
t
t
t
t
t
t
t
t
t
t
t
t
t
TCK Cycle Time
THTH
TCK High Pulse Width
THTL
TLTH
MVTH
THMX
CS
TCK Low Pulse Width
TMS Setup Time to TCK
TMS Hold Time to TCK
Capture Setup time to TCK
Capture Hold time to TCK
TDI Setup Time to TCK
ns
CH
DVTH
THDX
TLQV
TLQX
TLQLZ
TLQHZ
TDI Hold Time to TCK
Output Valid Time from TCK Low
Output Hold Time from TCK Low
Output Low-Z Time from TCK Low
Output High-Z Time from TCK Low
5
Rev 1.3
2005-03-07 61/65
TC59LM836DKB-30,-33,-40
TAP AC TEST CONDITIONS
CONDITION
PARAMETER
Input Pulse Level
Z = 50 Ω
TDO
1.8V / 0.0V
2ns
R = 50 Ω
L
Input Pulse Rise and Fall Time
Input Timing Measurement Reference Level
Output Timing Measurement Reference Level
V = 0.9V
L
0.9V
Output Load
0.9V
TAP TIMING DIAGRAMS
t
t
t
TLTH
THTH
THTL
TCK
t
t
t
MVTH THMX
TMS
TDI
t
DVTH THDX
t
t
CS CH
Capture
Data
t
TLQV
t
t
t
TLQHZ
TLQLZ
TLQX
TDO
Rev 1.3
2005-03-07 62/65
TC59LM836DKB-30,-33,-40
PACKAGE DIMENSIONS
P-TFBGA144-1119-0.80BZ
18.5
0.2 S
0.05
0.5
0.08 SAB
0.75
A
0.5
1.0
Weight: 0.30g (typ.)
Rev 1.3
2005-03-07 63/65
TC59LM836DKB-30,-33,-40
REVISION HISTORY
− Rev.1.0 (Feb. 26 ’2004)
− Rev.1.1 (May. 25 ‘2004)
• I
spec changed from 10mA to 15mA (page 1, 7)
DD6
• V
in AC Test conditions changed from 0.7 V to 0.8 V (page 11)
SWING
• Corrected typo (page 54)
− Rev.1.2 (Aug. 27 ‘2004)
• Some notes in the page 8 moved to page 7 (page 7, 8).
• Note 2 changed as below (page 7).
Before: These parameters depend on the output loading. The specified values are obtained with the
output open
After: These parameters define the current between V
and V .
SS
DD
• Corrected TYPO (page 9, 14~18, 61, 62).
• t
CK,MAX
for “-30” changed from 7.5 ns to 5.0 ns (page 9)
• Package drawing minor change (page 63).
• Package weight (0.30g) added (page 63)
− Rev.1.3 (Mar.7 ‘2005)
• Corrected figure of lPDA based AC timing spec table (page 12, 43, 44, 50, 51).
Rev 1.3
2005-03-07 64/65
TC59LM836DKB-30,-33,-40
RESTRICTIONS ON PRODUCT USE
030619EBA
• The information contained herein is subject to change without notice.
• The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of
TOSHIBA or others.
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced
and sold, under any law and regulations.
Rev 1.3
2005-03-07 65/65
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