TC59LM906AMB-45 [TOSHIBA]
IC 64M X 8 DDR DRAM, 22 ns, PBGA60, 13 X 17 MM, 1 MM PITCH, PLASTIC, BGA-60, Dynamic RAM;
| 型号： | TC59LM906AMB-45 |
| 厂家： | 
TOSHIBA |
| 描述： | IC 64M X 8 DDR DRAM, 22 ns, PBGA60, 13 X 17 MM, 1 MM PITCH, PLASTIC, BGA-60, Dynamic RAM 时钟 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总57页 (文件大小：710K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TC59LM914/06AMB-37,-45,-50
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TM
4,194,304-WORDS × 8 BANKS × 16-BITS Network FCRAM
8,388,608-WORDS × 8 BANKS × 8-BITS Network FCRAM
TM
DESCRIPTION
Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM914/06AMB is Network
FCRAMTM containing 536,870,912 memory cells. TC59LM914AMB is organized as 4,194,304-words × 8 banks × 16
bits, TC59LM906AMB is organized as 8,388,608-words × 8 banks × 8 bits. TC59LM914/06AMB feature a fully
synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence. TC59LM914/06AMB can operate fast core cycle
compared with regular DDR SDRAM.
TC59LM914/06AMB is suitable for Network, Server and other applications where large memory density and low
power consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data
transfer under light loading condition.
FEATURES
TC59LM914/06
PARAMETER
-37
-45
5.5 ns
5.0 ns
4.5 ns
25 ns
22.0 ns
TBD
-50
6.0 ns
5.5 ns
5.0 ns
27.5 ns
24.0 ns
TBD
CL = 3
CL = 4
CL = 5
5.5 ns
4.5 ns
3.75 ns
22.5 ns
22.0 ns
TBD
t
Clock Cycle Time (min)
CK
t
t
I
l
l
Random Read/Write Cycle Time (min)
Random Access Time (max)
Operating Current (single bank) (max)
Power Down Current (max)
RC
RAC
DD1S
DD2P
DD6
TBD
TBD
TBD
Self-Refresh Current (max)
TBD
TBD
TBD
•
•
Fully Synchronous Operation
Double Data Rate (DDR)
•
•
Data input/output are synchronized with both edges of DQS.
Differential Clock (CLK and CLK ) inputs
CS , FN and all address input signals are sampled on the positive edge of CLK.
Output data (DQs and DQS) is aligned to the crossings of CLK and CLK .
Fast clock cycle time of 3.75 ns minimum
Clock: 266 MHz maximum
Data: 533 Mbps/pin maximum
Fast cycle and Short Latency
Differential Data Strobe DQS : TC59LM906AMB
Distributed Auto-Refresh cycle in 3.9 µs
Self-Refresh
Power Down Mode
Variable Write Length Control
Write Latency = CAS Latency-1
Programable CAS Latency and Burst Length
CAS Latency = 3, 4, 5
•
•
•
•
•
•
•
•
Burst Length = 2, 4
•
•
Organization: TC59LM914AMB : 4,194,304 words × 8 banks × 16 bits
TC59LM906AMB : 8,388,608 words × 8 banks × 8 bits
Power Supply Voltage
V
DD
V
:
2.5 V ± 0.15V
: 1.4 V ~ 1.9 V
DDQ
•
•
Low voltage CMOS I/O covered with SSTL-18 (Half strength driver) and HSTL.
Package: 60Ball BGA, 1mm × 1mm Ball pitch
Notice : FCRAM is trademark of Fujitsu Limited, Japan.
2003-08-04 1/57
TC59LM914/06AMB-37,-45,-50
TC59LM906AMB
PIN NAMES
PIN ASSIGNMENT (TOP VIEW)
ball pitch=1.0 x 1.0mm
PIN
NAME
Address Input
x8
A0~A13
BA0~BA2
DQ0~DQ7
CS
1
2
3
4
5
6
Bank Address
Index
Data Input/Output
Chip Select
A
B
V
DQ7
DQ0
V
DD
FN
Function Control
Power Down Control
Clock Input
NC
DQ6
NC
V
Q
V
Q
DD
NC
DQ1
NC
PD
CLK, CLK
DQS / DQS
V
Q
V
Q
C
D
DD
Write/Read Data Strobe
Power (+2.5 V)
Ground
DQ5
DQ2
V
V
DD
SS
NC
V
Q
V
Q
DD
NC
E
F
Power (+1.5V / +1.8 V)
(for I/O buffer)
V
DDQ
DQ4
NC
V
Q
Q
V
Q
DQ3
NC
DD
Ground
(for I/O buffer)
V
V
SSQ
REF
V
V
Q
G
H
J
DD
Reference Voltage
Not Connected
NC
DQS
NC
DQS
NC
VREF
CLK
A12
A11
A8
V
V
DD
BA2
A13
NC
CLK
PD
A9
FN
K
L
CS
BA1
A0
BA0
A10
A1
M
N
A7
A5
A6
A2
A3
P
R
V
A4
V
DD
2003-08-04 2/57
TC59LM914/06AMB-37,-45,-50
TC59LM914AMB
PIN NAMES
PIN ASSIGNMENT (TOP VIEW)
ball pitch=1.0 x 1.0mm
PIN
NAME
Address Input
X16
A0~A13
BA0~BA2
DQ0~DQ15
CS
1
2
3
4
5
6
Bank Address
Index
Data Input/Output
Chip Select
A
B
V
DQ15
DQ0
V
DD
FN
Function Control
Power Down Control
Clock Input
DQ14
DQ13
V
V
Q
Q
V
Q
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
NC
DD
PD
CLK, CLK
UDQS / LDQS
V
Q
C
D
DD
Write/Read Data Strobe
Power (+2.5 V)
Ground
DQ12 DQ11
DQ4
V
DD
SS
V
DQ10
DQ9
DQ8
NC
V
V
Q
Q
V
Q
E
F
DD
Power (+1.5V / +1.8 V)
(for I/O buffer)
V
DDQ
V
Q
DD
Ground
(for I/O buffer)
V
V
SSQ
V
Q
V
Q
G
H
J
DD
Reference Voltage
Not Connected
REF
UDQS
LDQS
NC
VREF
CLK
A12
A11
A8
V
V
DD
BA2
A13
NC
CLK
PD
A9
FN
K
L
CS
BA1
A0
BA0
A10
A1
M
N
A7
A5
A6
A2
A3
P
R
V
A4
V
DD
2003-08-04 3/57
TC59LM914/06AMB-37,-45,-50
BLOCK DIAGRAM
CLK
CLK
PD
DLL
CLOCK
BUFFER
To each block
BANK #7
BANK #6
BANK #5
BANK #4
BANK #3
BANK #2
BANK #1
CS
FN
CONTROL
SIGNAL
GENERATOR
COMMAND
DECODER
BANK #0
MODE
REGISTER
MEMORY
CELL ARRAY
A0~A13
ADDRESS
BUFFER
UPPER ADDRESS
LATCH
BA0~BA2
LOWER ADDRESS
LATCH
COLUMN DECODER
READ
DATA
BUFFER
WRITE
DATA
BUFFER
WRITE ADDRESS
REFRESH
COUNTER
LATCH/
ADDRESS
COMPARATOR
BURST
COUNTER
DQS
DQS
DQ BUFFER
DQ0~DQn
Note: The TC59LM906AMB configuration is 8 Bank of 16384 × 512 × 8 of cell array with the DQ pins numbered DQ0~DQ7.
The TC59LM914AMB configuration is 8 Bank of 16384 × 256 × 16 of cell array with the DQ pins numbered DQ0~DQ15.
TC59LM906AMB has DQS pin for Differential Data Strobe.
TC59LM914AMB has UDQS and LDQS.
2003-08-04 4/57
TC59LM914/06AMB-37,-45,-50
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
Power Supply Voltage
RATING
UNIT
NOTES
V
V
V
V
V
−0.3~ 3.3
V
V
DD
Power Supply Voltage (for I/O buffer)
Input Voltage
−0.3~V + 0.3
DD
DDQ
IN
−0.3~V + 0.3
DD
V
Output and I/O pin Voltage
Input Reference Voltage
Operating Temperature (Ambient)
Storage Temperature
−0.3~V
DDQ
+ 0.3
V
OUT
REF
opr
−0.3~V + 0.3
V
DD
T
T
T
0~70
−55~150
260
°C
°C
°C
W
mA
stg
Soldering Temperature (10 s)
Power Dissipation
solder
P
D
2
I
Short Circuit Output Current
±50
OUT
Caution: Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device.
The device is not meant to be operated under conditions outside the limits described in the operational section of this
specification.
Exposure to “ABSOLUTE MAXIMUM RATINGS” conditions for extended periods may affect device reliability.
RECOMMENDED DC, AC OPERATING CONDITIONS (Notes: 1) (T
= 0~85°C)
CASE
SYMBOL
PARAMETER
Power Supply Voltage
MIN
TYP.
MAX
UNIT
NOTES
V
V
V
V
V
V
2.375
1.4
2.5
2.625
1.9
V
V
DD
Power Supply Voltage (for I/O buffer)
Input Reference Voltage
DDQ
REF
V
/2 × 95%
+ 0.125
V
/2
V
/2 × 105%
V
V
V
V
2
5
DDQ
DDQ
DDQ
(DC)
Input DC High Voltage
V
V
+ 0.2
IH
IL
REF
DDQ
(DC)
(DC)
Input DC Low Voltage
−0.1
−0.1
V
− 0.125
5
REF
Differential Clock DC Input Voltage
V
V
V
+ 0.1
+ 0.2
10
ICK
DDQ
DDQ
DDQ
Input Differential Voltage.
CLK and CLK inputs (DC)
V
(DC)
0.4
V
7, 10
ID
V
V
(AC)
Input AC High Voltage
Input AC Low Voltage
V
+ 0.2
+ 0.2
− 0.2
V
V
3, 6
4, 6
IH
REF
(AC)
(AC)
(AC)
−0.1
V
REF
IL
Input Differential Voltage.
CLK and CLK inputs (AC)
V
0.55
V
+ 0.2
V
7, 10
ID
X
DDQ
V
V
Differential AC Input Cross Point Voltage
Differential Clock AC Middle Level
V
V
/2 − 0.125
/2 − 0.125
V
V
/2 + 0.125
/2 + 0.125
V
V
8, 10
9, 10
DDQ
DDQ
(AC)
ISO
DDQ
DDQ
2003-08-04 5/57
TC59LM914/06AMB-37,-45,-50
Note:
(1) All voltages referenced to V , V
.
SS SSQ
(2) V
is expected to track variations in V
DC level of the transmitting device.
REF
DDQ
Peak to peak AC noise on V
may not exceed ±2% V
(DC).
REF
REF
(3) Overshoot limit: V
= V
+ 0.7 V with a pulse width ≤ 5 ns.
IH (max)
DDQ
(4) Undershoot limit: V
= −0.7 V with a pulse width ≤ 5 ns.
IL (min)
(5) V (DC) and V (DC) are levels to maintain the current logic state.
IH
IL
(6) V (AC) and V (AC) are levels to change to the new logic state.
IH
IL
(7) V is magnitude of the difference between CLK input level and CLK input level.
ID
(8) The value of V (AC) is expected to equal V
/2 of the transmitting device.
DDQ
X
(9) V
means {V
(CLK) + V
(CLK )} /2
ISO
ICK
ICK
(10) Refer to the figure below.
CLK
V
x
V
x
V
x
V
x
V
x
V (AC)
ID
CLK
V
ICK
V
ICK
V
ICK
V
ICK
V
SS
|V (AC)|
ID
0 V Differential
V
ISO
V
V
ISO (max)
ISO (min)
V
SS
(11) In the case of external termination, VTT (termination voltage) should be gone in the range of V
0.04 V.
(DC) ±
REF
CAPACITANCE (V = 2.5V, V
= 1.8 V, f = 1 MHz, Ta = 25°C)
DD
DDQ
SYMBOL
PARAMETER
MIN
MAX
Delta
UNIT
C
C
C
C
Input pin Capacitance
1.5
1.5
2.5
2.5
2.5
4
0.25
0.25
0.5
pF
pF
pF
pF
IN
Clock pin (CLK, CLK ) Capacitance
DQ, DQS, UDQS, LDQS, DQS Capacitance
NC pin Capacitance
INC
I/O
NC
4
Note: These parameters are periodically sampled and not 100% tested.
2003-08-04 6/57
TC59LM914/06AMB-37,-45,-50
RECOMMENDED DC OPERATING CONDITIONS
(V =2.5V ± 0.125V, V
=1.8V ± 0.1V, T
= 0~85°C)
DD
DDQ
CASE
MAX
-45
SYMBOL
PARAMETER
UNIT
NOTES
1, 2
-37
-50
Operating Current
= min; I = min,
t
CK
RC
Read/Write command cycling,
0 V ≤ V ≤ V (AC) (max), V (AC) (min) ≤ V ≤ V
I
TBD
TBD
TBD
DD1S
,
,
IN IL IH IN
DDQ
1 bank operation, Burst length = 4,
Address change up to 2 times during minimum I
Standby Current
.
RC
t
= min, CS = V , PD = V ,
IH IH
CK
I
I
0 V ≤ V ≤ V (AC) (max), V (AC) (min) ≤ V ≤ V
TBD
TBD
TBD
TBD
TBD
TBD
1
1
1
DD2N
IN IL IH IN
DDQ
All banks: inactive state,
Other input signals are changed one time during 4 × t
.
CK
mA
Standby (power down) Current
t
= min, CS = V , PD = V (power down),
CK
IH
IL
DD2P
0 V ≤ V ≤ V
,
IN
DDQ
All banks: inactive state
Auto-Refresh Current
t
= min; I
= min, t
= min,
CK
REFC REFI
I
I
Auto-Refresh command cycling,
TBD
TBD
TBD
TBD
TBD
TBD
DD5
0 V ≤ V ≤ V (AC) (max), V (AC) (min) ≤ V ≤ V
DDQ
,
IN
IL
IH
IN
Address change up to 2 times during minimum I
.
REFC
Self-Refresh Current
Self-Refresh mode
DD6
PD = 0.2 V, 0 V ≤ V ≤ V
IN
DDQ
SYMBOL
LI
PARAMETER
MIN
MAX
5
UNIT
NOTES
Input Leakage Current
I
I
−5
µA
( 0 V ≤ V ≤ V
, all other pins not under test = 0 V)
IN
DDQ
Output Leakage Current
−5
−5
5
5
µA
µA
LO
(Output disabled, 0 V ≤ V
≤ V
)
DDQ
OUT
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
V
REF
Current
REF
(DC)
(DC)
(DC)
(DC)
(DC)
(DC)
(DC)
(DC)
(DC)
(DC)
(DC)
(DC)
(DC)
(DC)
(DC)
(DC)
V
V
V
V
V
V
V
V
V
V
V
V
= 1.420 V
= 0.280 V
= 1.420 V
= 0.280 V
= 1.420 V
= 0.280 V
= 1.420 V
= 0.280 V
−5.6
5.6
−9.8
9.8
−2.8
2.8
−13.4
13.4
−4
3
3
3
3
3
3
3
3
3
3
3
3
OH
OL
OH
OL
OH
OL
OH
OL
OH
OL
OH
OL
OH
OL
OH
OL
OH
OL
OH
OL
OH
OL
OH
OL
OH
OL
OH
Normal Output Driver
Strong Output Driver
Weak Output Driver
Output DC Current
(V = 1.7V~1.9V)
mA
DDQ
Full Strength Output Driver
Normal Output Driver
Strong Output Driver
Weak Output Driver
= V
DDQ
– 0.4V
= 0.4V
4
= V
– 0.4V
−8
DDQ
= 0.4V
8
OL
Output DC Current
(V = 1.4V~1.6V)
mA
DDQ
Not defined
Not defined
V
V
= V
DDQ
– 0.4V
−10
10
3
3
OH
Full Strength Output Driver
= 0.4V
OL
Notes: 1. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of
, t and I
t
.
RC
CK RC
2. These parameters depend on the output loading. The specified values are obtained with the output open.
3. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Register.
4. In case of Full Strength Output Driver, OCD calibration (Off chip Driver impedance adjustment) can be used. The
specification of Full Strength Output Driver defines the default value after power-up.
2003-08-04 7/57
TC59LM914/06AMB-37,-45,-50
AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2)
(V =2.5V±0.125V, V
=1.8V±0.1V, T
=0~85°C)
CASE
DD
DDQ
-37
-45
-50
SYMBOL
PARAMETER
UNIT NOTES
MIN
MAX
MIN
25
MAX
MIN
27.5
6.0
MAX
t
t
Random Cycle Time
22.5
5.5
3
3
RC
C
L
C
L
C
L
= 3
= 4
= 5
8.5
5.5
8.5
8.5
Clock Cycle Time
4.5
8.5
5.0
8.5
5.5
8.5
3
CK
3.75
8.5
4.5
8.5
22.0
5.0
8.5
24
3
3
t
t
t
t
t
t
t
Random Access Time
Clock High Time
22.0
RAC
0.45 × t
0.45 × t
0.45 × t
0.45 × t
−0.5
0.45 × t
0.45 × t
−0.6
3
CH
CK
CK
CK
Clock Low Time
3
CL
CK
CK
CK
DQS Access Time from CLK
Data Output Skew from DQS
Data Access Time from CLK
Data Output Hold Time from CLK
−0.45
0.45
0.25
0.5
0.5
0.5
0.3
0.6
0.6
0.6
0.35
0.65
0.65
3, 8
4
CKQS
QSQ
AC
−0.5
−0.5
−0.6
−0.65
−0.65
3, 8
3, 8
−0.6
OH
DQS (read) Preamble Pulse
Width
t
0.9 × t
CK
1.1 × t
0.9 × t
1.1 × t
0.9 × t
CK
1.1 × t
CK
3, 8
QSPRE
CK
CK
CK
CLK half period (minimum of
min(t
,
min(t
,
min(t
,
CH
CH
CH
t
t
t
3
HP
Actual t
,
t )
CL
t
)
t
)
t
)
CH
CL
CL
CL
DQS (read) Pulse Width
t
t
−t
t
t
−t
t
t
−t
4, 8
4, 8
QSP
QSQV
HP QHS
HP QHS
HP QHS
Data Output Valid Time from
DQS
−t
−t
−t
HP QHS
HP QHS
HP QHS
0.055 ×
+0.17
0.055 ×
+0.17
0.055 ×
t +0.17
CK
t
t
t
DQ Hold Skew factor
QHS
t
t
CK
CK
DQS (write) Low to High Setup
Time
0.75 × t
CK
1.25 × t
0.75 × t
CK
1.25 × t
0.75 × t
CK
1.25 × t
3
DQSS
DSPRE
CK
CK
CK
DQS (write) Preamble Pulse
Width
0.25 ×
0.25 ×
0.25 ×
ns
4
t
t
t
CK
CK
CK
t
t
DQS First Input Setup Time
0
0
0
3
3
DSPRES
DQS First Low Input Hold Time
0.25 × t
0.35 × t
0.25 × t
0.35 × t
0.25 × t
0.35 × t
DSPREH
CK
CK
CK
DQS High or Low Input Pulse
Width
t
0.65 × t
0.65 × t
0.65 × t
4
DSP
CK
CK
CK
CK
CK
CK
C
L
C
L
C
L
= 3
= 4
= 5
0.75
0.75
0.75
0.9
0.9
0.9
1.0
1.0
1.0
3, 4
3, 4
3, 4
DQS Input Falling
Edge to Clock Setup
Time
t
DSS
DQS Input Falling Edge Hold Time
from CLK
t
t
0.55
0.65
0.75
3, 4
4
DSH
DQS (write) Postamble Pulse
Width
0.4 × t
0.4 × t
0.4 × t
DSPST
CK
CK
CK
C
L
C
L
C
L
= 3
= 4
= 5
0.75
0.75
0.75
0.9
0.9
0.9
1.0
1.0
1.0
3, 4
3, 4
3, 4
DQS (write)
t
DSPSTH
Postamble Hold Time
t
t
t
UDQS – LDQS Skew (×16)
−0.5× t
CK
0.5× t
−0.5× t
0.4
0.5× t
−0.5× t
CK
0.5× t
DSSK
CK
CK
CK
CK
Data Input Setup Time from DQS
Data Input Hold Time from DQS
0.35
0.35
0.45
0.45
4
4
DS
0.4
DH
Command/Address Input Setup
Time
t
0.5
0.5
0.6
0.6
0.7
0.7
3
3
IS
IH
Command/Address Input Hold
Time
t
2003-08-04 8/57
TC59LM914/06AMB-37,-45,-50
AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2) (continued)
-37
-45
-50
SYMBOL
PARAMETER
UNIT NOTES
MAX
MIN
MAX
MIN
MIN
MAX
Data-out Low Impedance Time
from CLK
t
t
t
t
t
−0.5
−0.6
−0.65
3,6,8
3,7,8
3,6,8
3,7,8
LZ
Data-out High Impedance Time
from CLK
−0.5
−0.5
0
0.5
−0.6
−0.6
0
0.6
−0.65
−0.65
0
0.65
HZ
DQS-out Low Impedance Time
from CLK
QSLZ
QSHZ
QPDH
DQS-out High Impedance Time
from CLK
0.5
0.6
0.65
Last output to PD High Hold
Time
ns
t
t
Power Down Exit Time
Input Transition Time
0.6
0.1
0.7
0.1
0.8
0.1
3
PDEX
1
1
1
T
PD Low Input Window for
Self-Refresh Entry
t
−0.5 × t
5
−0.5 × t
5
−0.5 × t
CK
5
3
FPDL
CK
CK
t
t
Auto-Refresh Average Interval
Pause Time after Power-up
0.4
200
5
3.9
0.4
200
5
3.9
0.4
200
5
3.9
5
REFI
µs
PAUSE
C
L
C
L
C
L
= 3
= 4
= 5
Random Read/Write
Cycle Time
I
5
5
5
RC
(applicable to same
bank)
6
6
6
RDA/WRA to LAL Command Input
Delay
I
I
1
1
1
1
1
1
RCD
RAS
(applicable to same bank)
C
L
C
L
C
L
= 3
= 4
= 5
4
4
5
4
4
5
4
4
5
LAL to RDA/WRA
Command Input Delay
(applicable to same
bank)
Random Bank Access Delay
(applicable to other bank)
I
I
I
2
2
2
RBD
RWD
WRD
LAL following RDA to
B
= 2
= 4
2
3
2
3
2
3
L
L
WRA Delay
(applicable to other
bank)
B
LAL following WRA to RDA Delay
(applicable to other bank)
1
1
1
C
L
C
L
C
L
= 3
= 4
= 5
5
5
6
5
5
6
5
5
6
cycle
Mode Register Set
Cycle Time
I
RSC
PD Low to Inactive State of Input
Buffer
I
I
1
1
1
1
1
1
PD
PD High to Active State of Input
Buffer
PDA
C
L
C
L
C
L
C
L
C
L
C
L
= 3
= 4
= 5
= 3
= 4
= 5
15
18
22
15
18
22
15
18
22
15
18
22
15
18
22
15
18
22
Power down mode valid
from REF command
I
PDV
Auto-Refresh Cycle
Time
I
REFC
REF Command to Clock Input
Disable at Self-Refresh Entry
I
I
I
I
I
CKD
REFC
REFC
REFC
DLL Lock-on Time (applicable to
RDA command)
200
200
200
LOCK
2003-08-04 9/57
TC59LM914/06AMB-37,-45,-50
AC TEST CONDITIONS
SYMBOL
PARAMETER
Input High Voltage (minimum)
VALUE
UNIT
NOTES
V
V
V
V
V
V
V
+ 0.2
V
V
IH (min)
IL (max)
REF
REF
REF
Input Low Voltage (maximum)
Input Reference Voltage
− 0.2
/2
V
V
DDQ
Termination Voltage
V
V
TT
REF
0.7
(AC)
Input Signal Peak to Peak Swing
Differential Clock Input Reference Level
Input Differential Voltage
V
SWING
Vr
V
X
V
V
ID
(AC)
1.0
2.5
V
SLEW
Input Signal Minimum Slew Rate
Output Timing Measurement Reference Voltage
V/ns
V
V
OTR
V
/2
9
DDQ
V
TT
V
DDQ
50 Ω
V
V
(AC)
(AC)
IH min
Z = 50 Ω
25 Ω
V
SWING
REF
Output
V
IL max
Z = 50 Ω
50 Ω
V
SS
V
TT
∆T
∆T
(AC))/∆T
AC Test Load
SLEW = (V
(AC) − V
IL max
IH min
Note:
(1)
Transition times are measured between V
(DC) and V
(DC).
IH min
IL max
Transition (rise and fall) of input signals have a fixed slope.
(2)
If the result of nominal calculation with regard to t contains more than one decimal place, the result is
CK
rounded up to the nearest decimal place.
(i.e., t
= 0.75 × t , t
= 5 ns, 0.75 × 5 ns = 3.75 ns is rounded up to 3.8 ns.)
DQSS
CK CK
(3)
(4)
There parameters are measured from the differential clock (CLK and CLK ) AC cross point.
These parameters are measured from signal transition point of DQS crossing V level.
REF
In case of DQS enable mode, these parameters are measured from the crossing point of DQS and DQS .
(5)
The t
The t
applies to equally distributed refresh method.
applies to both burst refresh method and distributed refresh method.
REFI (max)
REFI (min)
In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400 ns
always. In other words, the number of Auto-Refresh cycles which can be performed within 3.2 µs (8 × 400 ns)
is to 8 times in the maximum.
(6)
(7)
(8)
(9)
Low Impedance State is specified at V
/2 ± 0.2 V from steady state.
DDQ
High Impedance State is specified where output buffer is no longer driven.
These parameters depend on the clock jitter. These parameters are measured at stable clock.
Output timing is measured by using Normal driver strength.
2003-08-04 10/57
TC59LM914/06AMB-37,-45,-50
POWER UP SEQUENCE
(1)
(2)
(3)
(4)
(5)
(6)
As for PD , being maintained by the low state (≤ 0.2 V) is desirable before a power-supply injection.
Apply V
Apply V
before or at the same time as V
.
DD
DDQ
before or at the same time as V
.
DDQ
REF
Start clock (CLK, CLK ) and maintain stable condition for 200 µs (min).
After stable power and clock, apply DESL and take PD =H.
Issue EMRS to enable DLL and to define driver strength with OCD calibration mode exit command
(A7∼A9=0). (Note: 1, 2)
(7)
(8)
Issue MRS for set CAS latency (CL), Burst Type (BT), and Burst Length (BL). (Note: 1)
Issue two or more Auto-Refresh commands (Note: 1).
(9)
Ready for normal operation after 200 clocks from Extended Mode Register programming.
If OCD calibration (Off Chip Driver impedance adjustment) is used, execute OCD calibration sequence.
(10)
Notes:
(1)
Sequence 6, 7 and 8 can be issued in random order.
Set DQS mode for TC59LM906AMB.
L = Logic Low, H = Logic High
(2)
(3)
2.5V(TYP)
1.8V(TYP)
V
DD
V
DDQ
0.9V(TYP)
V
REF
CLK
CLK
t
PDEX
l
l
l
l
l
REFC
200us(min)
PDA
RSC
RSC
REFC
PD
Command
Address
DQ
200clock cycle(min)
DESL RDA MRS DESL RDA MRS
DESL WRA REF DESL
WRA REF DESL
op-code
EMRS
op-code
MRS
Hi-Z
Hi-Z
DQS
DQS
Normal Operation
EMRS
MRS
Auto Refresh cycle
2003-08-04 11/57
TC59LM914/06AMB-37,-45,-50
TIMING DIAGRAMS
Input Timing
Command and Address
t
t
t
CL
CK
CH
t
CK
CLK
CLK
t
t
t
t
t
t
t
t
IS
IH
IS
IH
CS
FN
1st
1st
2nd
IS
IH
IS
IH
2nd
LA
t
IS
t
IH
t
IS
t
IH
A0~A13
BA0~BA2
UA, BA
Data
• TC59LM906AMB DQS enable mode
DQS
DQS
t
t
t
t
DS DH
DS DH
DQ (input)
Data
• TC59LM906AMB DQS disable mode
• TC59LM914AMB
DQS
t
t
t
t
DS DH
DS DH
DQ (input)
Refer to the Command Truth Table.
Timing of the CLK, CLK
t
t
CL
CH
V
V
IH
IH
CLK
CLK
(AC)
(AC)
V
IL
IL
V
t
T
t
T
t
CK
CLK
CLK
V
V
IH
V
ID
(AC)
IL
V
X
V
X
V
X
2003-08-04 12/57
TC59LM914/06AMB-37,-45,-50
Read Timing (Burst Length = 4)
t
t
t
CK
CH
CL
CLK
CLK
t
t
IS IH
LAL (after RDA)
Input
(control &
DESL
addresses)
t
t
t
CKQS
CKQS
t
QSLZ
t
t
t
QSHZ
CKQS
QSP QSP
CAS latency = 3
t
QSPRE
DQS/ DQS
(output)
Hi-Z
Preamble
Postamble
t
t
LZ
t
QSQV
QSQ
t
t
t
t
HZ
QSQ
QSQ
QSQV
DQ
(output)
Hi-Z
Q0
Q1
Q2
Q3
t
t
t
AC
AC
AC
t
OH
t
CKQS
t
CKQS
t
QSLZ
t
CKQS
t
CAS latency = 4
t
t
QSHZ
QSP QSP
t
QSPRE
DQS/ DQS
(output)
Hi-Z
Hi-Z
Preamble
Postamble
t
t
t
QSQ
LZ
QSQV
t
t
t
t
HZ
QSQ
QSQ
QSQV
DQ
(output)
Q0
Q1
Q2
Q3
t
t
t
AC
AC
AC
t
OH
t
CKQS
t
CKQS
t
QSLZ
t
CKQS
t
t
t
t
CAS latency = 5
QSP QSP
QSHZ
t
QSPRE
DQS/ DQS
(output)
Hi-Z
Hi-Z
Preamble
Postamble
t
LZ
t
t
QSQV
QSQ
t
t
t
QSQ
QS
QSQV
HZ
DQ
(output)
Q0
Q1
Q2
Q3
t
t
t
AC
AC
AC
t
OH
Note: TC59LM914AMB doesn’t have DQS .
The correspondence of LDQS, UDQS to DQ. (TC59LM914AMB)
LDQS
UDQS
DQ0∼DQ7
DQ8∼DQ15
The condition of DQS is changed from Hi-Z to “Low” at Premble and the condition of DQS is changed from
“Low” to Hi-Z at Postamble.
DQS is Hi-Z in DQS disable mode.
DQS mode is chosen by EMRS. (TC59LM906AMB)
When DQS is enable, the condtion of DQS is changed from Hi-Z to “High” at Premble and the condition
of DQS is changed from “High” to Hi-Z at Postamble.
2003-08-04 13/57
TC59LM914/06AMB-37,-45,-50
Write Timing (Burst Length = 4)
t
t
t
CK
CH
CL
CLK
CLK
t
t
IS IH
LAL (after WRA)
Input
(control &
DESL
addresses)
t
DSPSTH
t
DQSS
t
DSS
t
DSPRES
t
t
t
t
DSP DSP DSP DSPST
t
DSPREH
CAS latency = 3
DQS/ DQS
(input)
t
DSS
Preamble
Postamble
t
DSPRE
t
t
DS
t
DS
DS
t
t
DH
t
DH
DH
DQ
(input)
D0
D1
D2
D3
t
DQSS
t
t
DSS
t
DSPRES
t
DSPSTH
DSS
t
t
t t t
DSP DSP DSPST
DSPREH
CAS latency = 4
DSP
DQS/ DQS
(input)
Preamble
DSPRE
Postamble
t
t
t
DS
t
DS
DS
t
t
t
DH
DH
DH
DQ
(input)
D3
D0
D1
D2
t
t
DQSS
DQSS
t
DSS
t
DSPRES
t
DSS
t
DSPSTH
t
t
t
t
t
DSPREH
DSP DSP DSP DSPST
CAS latency = 5
DQS/ DQS
(input)
Preamble
Postamble
t
DSPRE
t
t
DS
t
DS
DS
t
t
t
DH
DH
DH
DQ
(input)
D3
D0
D1
D2
t
t
DQSS
DQSS
Note: TC59LM914AMB doesn’t have DQS .
The correspondence of LDQS, UDQS to DQ. (TC59LM914AMB)
LDQS
UDQS
DQ0∼DQ7
DQ8∼DQ15
DQS is ignored in DQS disable mode.
DQS mode is chosen by EMRS. (TC59LM906AMB)
2003-08-04 14/57
TC59LM914/06AMB-37,-45,-50
t
, t
, Ixxxx Timing
REFI PAUSE
CLK
CLK
t
, t
, I
REFI PAUSE XXXX
t
t
t
t
IS IH
IS IH
Input
(control &
addresses)
Command
Command
Note: “I
XXXX
” means “I ”, “I
”, “I
”, etc.
RAS
RC RCD
2003-08-04 15/57
TC59LM914/06AMB-37,-45,-50
Write Timing (x16 device) (Burst Length =4)
CLK
CLK
Input
WRA
LAL
(control &
(DESL)
addresses)
t
t
t
t
DSSK DSSK DSSK DSSK
CAS latency = 3
LDQS
Preamble
t
Postamble
t
DS
t
t
t
DS
DS
DS
t
t
DH
t
DH
DH
DH
DQ0~DQ7
UDQS
D0
D1
D2
D3
Preamble
Postamble
DH
t
t
t
DS
t
DS
DS
DS
t
t
t
t
DH
DH
DH
D0
D1
D3
DQ8~DQ15
t
t
t
t
DSSK DSSK DSSK DSSK
CAS latency = 4
LDQS
Preamble
t
Postamble
t
t
t
DS
t
DS
DS
DS
t
t
t
DH
DH
DH
DH
DQ0~DQ7
UDQS
D0
D1
D2
D3
Preamble
t
Postamble
t
t
t
t
DS
DS
DS
DS
t
t
DH
t
DH
DH
DH
D0
D1
D2
D3
DQ8~DQ15
t
t
t
t
DSSK DSSK DSSK DSSK
CAS latency = 5
LDQS
Preamble
t
Postamble
t
t
t
t
DS
DS
DS
DS
t
t
t
DH
DH
DH
DH
DQ0~DQ7
UDQS
D0
D1
D2
D3
Preamble
t
Postamble
t
t
t
t
DS
DS
DS
DS
t
DH
t
t
DH
DH
DH
D0
D1
D2
D3
DQ8~DQ15
2003-08-04 16/57
TC59LM914/06AMB-37,-45,-50
FUNCTION TRUTH TABLE (Notes: 1, 2, 3)
Command Truth Table (Notes: 4)
• The First Command
SYMBOL
FUNCTION
Device Deselect
CS
FN
BA2~BA0
A13~A9
A8
A7
A6~A0
DESL
RDA
H
L
L
×
H
L
×
×
×
×
×
Read with Auto-close
Write with Auto-close
BA
BA
UA
UA
UA
UA
UA
UA
UA
UA
WRA
• The Second Command (The next clock of RDA or WRA command)
BA1~
BA0
A12~ A10~A
SYMBOL
FUNCTION
CS
FN
BA2
A13
A8
A7
A6~A0
A11
9
LAL
LAL
Lower Address Latch (x16)
Lower Address Latch (x8)
Auto-Refresh
H
H
L
×
×
×
×
×
×
×
V
×
×
×
L
V
V
×
V
×
×
L
×
×
×
L
×
LA
×
LA
LA
×
LA
LA
×
REF
MRS
Mode Register Set
L
L
L
V
V
Notes: 1. L = Logic Low, H = Logic High, × = either L or H, V = Valid (specified value), BA = Bank Address, UA = Upper Address,
LA = Lower Address
2. All commands are assumed to issue at a valid state.
3. All inputs for command (excluding SELFX and PDEX) are latched on the crossing point of differential clock input where
CLK goes to High.
4. Operation mode is decided by the combination of 1st command and 2nd command. Refer to “STATE DIAGRAM” and
the command table below.
Read Command Table
COMMAND (SYMBOL)
CS
FN
BA2~BA0
A13~A9
A8
A7
A6~A0
NOTES
5
RDA (1st)
LAL (2nd)
L
H
BA
UA
UA
LA
UA
LA
UA
LA
H
×
×
×
Note 5 : For x16 device, A8 is “X” (either L or H).
Write Command Table
• TC59LM914AMB
BA1~
A10~
A9
COMMAND (SYMBOL)
CS
FN
BA2
BA
A13
UA
A12
UA
A11
UA
A8
A7
A6~A0
BA0
WRA (1st)
LAL (2nd)
L
L
BA
UA
UA
UA
LA
UA
LA
H
×
×
LVW0 LVW1 UVW0 UVW1
×
×
• TC59LM906AMB
BA1~
BA0
A10~
A9
COMMAND (SYMBOL)
CS
FN
BA2
A13
A12
A11
A8
A7
A6~A0
WRA (1st)
LAL (2nd)
L
L
BA
BA
UA
UA
UA
UA
UA
LA
UA
LA
UA
LA
H
×
×
VW0
VW1
×
×
×
Notes: 6. BA2 and A13~A11 are used for Variable Write Length (VW) control at Write Operation.
2003-08-04 17/57
TC59LM914/06AMB-37,-45,-50
FUNCTION TRUTH TABLE (continued)
VW Truth Table
Burst Length
Function
Write All Words
VW0
VW1
L
H
L
×
×
BL=2
Write First One Word
Reserved
L
Write All Words
H
L
L
BL=4
Write First Two Words
Write First One Word
H
H
H
Note 7 : For x16 device, LVW0 and LVW1 control DQ0~DQ7.
UVW0 and UVW1 control DQ8~DQ15.
Mode Register Set Command Table
COMMAND (SYMBOL)
CS
FN
BA2~BA0
A13~A9
A8
A7
A6~A0
NOTES
8
RDA (1st)
L
L
H
×
×
×
×
×
MRS (2nd)
×
V
V
V
V
V
Notes: 8. Refer to “MODE REGISTER TABLE”.
Auto-Refresh Command Table
PD
COMMAND CURRENT
FUNCTION
CS
FN BA2~BA0 A13~A9 A8
A7 A6~A0 NOTES
(SYMBOL)
STATE
n − 1
H
n
H
H
Active
WRA (1st)
REF (2nd)
Standby
Active
L
L
L
×
×
×
×
×
×
×
×
×
×
Auto-Refresh
H
×
Self-Refresh Command Table
PD
COMMAND CURRENT
FUNCTION
CS
FN BA2~BA0 A13~A9 A8
A7 A6~A0 NOTES
(SYMBOL)
STATE
n − 1
H
n
H
L
Active
WRA (1st)
REF (2nd)
Standby
Active
L
L
L
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Self-Refresh Entry
Self-Refresh Continue
Self-Refresh Exit
H
9, 10
11
Self-Refresh
Self-Refresh
L
L
×
SELFX
L
H
H
Power Down Table
PD
COMMAND CURRENT
FUNCTION
CS
FN BA2~BA0 A13~A9 A8
A7 A6~A0 NOTES
(SYMBOL)
STATE
n − 1
n
L
Power Down Entry
Power Down Continue
Power Down Exit
PDEN
Standby
H
L
L
H
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
10
11
Power Down
Power Down
L
PDEX
H
H
Notes: 9. PD has to be brought to Low within t
from REF command.
FPDL
10. PD should be brought to Low after DQ’s state turned high impedance.
11. When PD is brought to High from Low, this function is executed asynchronously.
2003-08-04 18/57
TC59LM914/06AMB-37,-45,-50
FUNCTION TRUTH TABLE (continued)
PD
CURRENT STATE
CS
FN
ADDRESS COMMAND
ACTION
NOTES
12
n − 1
H
H
H
H
H
L
n
H
H
H
L
H
L
L
H
L
×
H
L
×
×
×
×
×
×
×
×
×
×
×
×
×
×
H
L
×
×
×
×
DESL
RDA
WRA
PDEN
NOP
BA, UA
BA, UA
Row activate for Read
Row activate for Write
Power Down Entry
Illegal
Idle
×
L
×
×
×
×
Refer to Power Down State
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
L
H
H
L
L
×
H
L
H
L
LA
LAL
Begin Read
Op-code
MRS/EMRS Access to Mode Register
PDEN Illegal
MRS/EMRS Illegal
Row Active for Read
Row Active for Write
×
×
×
×
Invalid
H
H
L
L
×
H
L
H
L
×
LA
LAL
Begin Write
Auto-Refresh
Illegal
×
REF
PDEN
×
×
REF (self) Self-Refresh Entry
×
DESL
RDA
WRA
PDEN
Invalid
H
H
H
L
L
×
H
L
L
H
L
×
Continue Burst Read to End
BA, UA
BA, UA
Illegal
Illegal
Illegal
Illegal
Invalid
13
13
Read
×
×
×
×
Data Write & Continue Burst Write to
H
H
H
×
×
DESL
End
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
L
L
×
L
L
H
L
×
H
L
×
×
×
×
H
L
×
×
×
×
H
L
×
×
×
×
×
BA, UA
BA, UA
RDA
WRA
PDEN
Illegal
Illegal
Illegal
Illegal
Invalid
NOP → Idle after I
Illegal
Illegal
Self-Refresh Entry
Illegal
Refer to Self-Refreshing State
NOP → Idle after I
Illegal
Illegal
13
13
Write
×
×
×
H
H
H
L
L
×
H
L
L
H
L
×
×
DESL
RDA
WRA
PDEN
REFC
BA, UA
BA, UA
Auto-Refreshing
×
14
×
×
H
H
H
L
L
×
H
L
L
H
L
×
×
DESL
RDA
WRA
PDEN
RSC
BA, UA
BA, UA
Mode Register
Accessing
×
×
×
×
×
Illegal
Illegal
Invalid
Invalid
H
L
×
×
L
×
Maintain Power Down Mode
Power Down
Exit Power Down Mode → Idle after
L
H
H
×
×
PDEX
t
PDEX
L
H
L
L
L
H
×
L
×
×
×
×
×
×
×
×
×
×
×
Illegal
Invalid
L
H
H
×
Maintain Self-Refresh
Exit Self-Refresh → Idle after I
Illegal
Self-Refreshing
H
L
SELFX
REFC
Notes: 12. Illegal if any bank is not idle.
13. Illegal to bank in specified states; Function may be legal in the bank inidicated by Bank Address (BA).
14. Illegal if t is not satisfied.
FPDL
2003-08-04 19/57
TC59LM914/06AMB-37,-45,-50
MODE REGISTER TABLE
Regular Mode Register (Notes: 1)
*1
*1
*3
A7
ADDRESS
Register
BA1
0
BA0
0
BA2, A13~A8
0
A6~A4
CL
A3
BT
A2~A0
BL
TE
A7
TEST MODE (TE)
A3
BURST TYPE (BT)
0
1
Regular (default)
Test Mode Entry
0
1
Sequential
Interleave
A6
A5
A4
CAS LATENCY (CL)
A2
A1
A0
BURST LENGTH (BL)
*2
*2
*2
0
0
0
1
1
1
1
0
1
1
0
0
1
1
×
0
1
0
1
0
1
Reserved
0
0
0
0
1
0
0
1
1
×
0
1
0
1
×
Reserved
Reserved
2
4
3
4
5
*2
Reserved
*2
*2
Reserved
Reserved
Extended Mode Register (Notes: 4)
*4
*4
*6
*7
A10
*5
ADDRESS
Register
BA1
0
BA0
1
BA2, A13~A12 A11
A9~A7
OCD
A6
A5~A2
A1
DIC
A0
DS
0
0
DQS
DIC
0
OUTPUT DRIVE IMPEDANCE
CONTROL (DIC)
A9 A8 A7 Driver Impedance Adjustment
A6
A1
0
0
0
0
OCD
exit
Calibration
mode
0
Normal Output Driver
0
0
1
Drive (1)
Drive (0)
0
1
1
1
0
1
Strong Output Driver
Weak Output Driver
0
1
1
1
0
1
0
0
1
Adjust mode
Full Strength Output Driver
OCD Calibration default
A10
DQS Enable
A0
DLL SWITCH (DS)
0
1
Disable
Enable
0
1
DLL Enable
DLL Disable
Notes: 1. Regular Mode Register is chosen using the combination of BA0 = 0 and BA1 = 0.
2. “Reserved” places in Regular Mode Register should not be set.
3. A7 in Regular Mode Register must be set to “0” (low state).
Because Test Mode is specific mode for supplier.
4. Extended Mode Register is chosen using the combination of BA0 = 1 and BA1 = 0.
5. A0 in Extended Mode Register must be set to "0" to enable DLL for normal operation.
6. A11 in Extended Mode Register must be set to “0”.
7. TC59LM914AMB, A10 in Extended Mode Register is ignored. DQS is available only TC59LM906AMB.
2003-08-04 20/57
TC59LM914/06AMB-37,-45,-50
STATE DIAGRAM
SELF-
REFRESH
POWER
DOWN
SELFX
( PD = H)
PDEX
( PD = H)
PD = L
PDEN
( PD = L)
STANDBY
(IDLE)
PD = H
AUTO-
REFRESH
MODE
REGISTER
WRA
RDA
REF
MRS
ACTIVE
(RESTORE)
ACTIVE
LAL
LAL
WRITE
(BUFFER)
READ
Command input
Automatic return
The second command at Active state
must be issued 1 clock after RDA or
WRA command input.
2003-08-04 21/57
TC59LM914/06AMB-37,-45,-50
TIMING DIAGRAMS
SINGLE BANK READ TIMING (CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 5 cycles
I
= 5 cycles
I
= 5 cycles
RC
RC
RC
Command
RDA LAL
DESL
RDA LAL
DESL
RDA LAL
DESL
RDA
I =1 cycle
RCD
I
= 4 cycles
I =1 cycle
RCD
I
= 4 cycles
I =1 cycle
RCD
I
= 4 cycles
RAS
Address
UA
#0
UA
LA
UA
#0
LA
UA
#0
LA
Bank Add.
#0
BL = 2
Hi-Z
DQS/ DQS
(output)
CL = 3
CL = 3
CL = 3
DQ
Hi-Z
Hi-Z
Q0 Q1
Q0 Q1
Q0 Q1
(output)
BL = 4
DQS/ DQS
(output)
CL = 3
CL = 3
CL = 3
DQ
(output)
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Note : TC59LM914AMB doesn’t have DQS .
2003-08-04 22/57
TC59LM914/06AMB-37,-45,-50
SINGLE BANK READ TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 5 cycles
I
= 5 cycles
I
= 5 cycles
RC
RC
RC
Command
RDA LAL
DESL
RDA LAL
DESL
RDA LAL
DESL
RDA
I =1 cycle
RCD
I
= 4 cycles
I =1 cycle
RCD
I
= 4 cycles
I =1 cycle
RCD
I
= 4 cycles
RAS
RAS
RAS
Address
UA
LA
UA
#0
LA
UA
LA
UA
#0
Bank Add.
#0
#0
BL = 2
Hi-Z
DQS/ DQS
(output)
CL = 4
CL = 4
CL = 4
DQ
Hi-Z
Hi-Z
Q0 Q1
Q0 Q1
Q0
(output)
BL = 4
DQS/ DQS
(output)
CL = 4
CL = 4
CL = 4
DQ
(output)
Hi-Z
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Q0
Note : TC59LM914AMB doesn’t have DQS .
2003-08-04 23/57
TC59LM914/06AMB-37,-45,-50
SINGLE BANK READ TIMING (CL = 5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 6 cycles
I
= 6 cycles
RC
RC
Command
RDA LAL
DESL
RDA LAL
DESL
RDA LAL
DESL
I =1 cycle
RCD
I
= 5 cycles
I =1 cycle
RCD
I
= 5 cycles
I =1 cycle
RCD
RAS
RAS
Address
UA
#0
LA
UA
LA
UA
LA
Bank Add.
#0
#0
BL = 2
Hi-Z
DQS/ DQS
(output)
CL = 5
CL = 5
DQ
Hi-Z
Hi-Z
Q0 Q1
Q0 Q1
(output)
BL = 4
DQS/ DQS
(output)
CL = 5
CL = 5
DQ
(output)
Hi-Z
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Note : TC59LM914AMB doesn’t have DQS .
2003-08-04 24/57
TC59LM914/06AMB-37,-45,-50
SINGLE BANK WRITE TIMING (CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 5 cycles
I
= 5 cycles
I
= 5 cycles
RC
RC
RC
Command
WRA LAL
DESL
WRA LAL
DESL
WRA LAL
DESL
WRA
I =1 cycle
RCD
I
= 4 cycles
I =1 cycle
RCD
I
= 4 cycles
I =1 cycle
RCD
I
= 4 cycles
RAS
RAS
RAS
Address
UA
LA
UA
#0
LA
UA
#0
LA
UA
#0
Bank Add.
#0
BL = 2
DQS/ DQS
(input)
WL = 2
WL = 2
WL = 2
DQ
(input)
D0 D1
D0 D1
D0 D1
BL = 4
DQS/ DQS
(input)
WL = 2
WL = 2
WL = 2
DQ
(input)
D0 D1 D2 D3
Note : TC59LM914AMB doesn’t have DQS .
D0 D1 D2 D3
D0 D1 D2 D3
2003-08-04 25/57
TC59LM914/06AMB-37,-45,-50
SINGLE BANK WRITE TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 5 cycles
I
= 5 cycles
I
= 5
RC
RC
RC
Command
WRA LAL
DESL
= 4 cycles
WRA LAL
DESL
WRA LAL
DESL
WRA
I =1 cycle
RCD
I
I =1 cycle
RCD
I
= 4 cycles
I =1 cycle
RCD
I
= 4 cycles
RAS
RAS
RAS
Address
UA
LA
UA
#0
LA
UA
#0
LA
UA
#0
Bank Add.
#0
BL = 2
DQS/ DQS
(input)
WL = 3
WL = 3
WL = 3
DQ
(input)
D0 D1
D0 D1
D0 D1
BL = 4
DQS/ DQS
(input)
WL = 3
WL = 3
WL = 3
DQ
(input)
D0 D1 D2 D3
D0 D1 D2 D3
D0 D1 D2 D3
Note : TC59LM914AMB doesn’t have DQS .
2003-08-04 26/57
TC59LM914/06AMB-37,-45,-50
SINGLE BANK WRITE TIMING (CL = 5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 6 cycles
I
= 6 cycles
RC
RC
Command
WRA LAL
DESL
WRA LAL
DESL
WRA LAL
DESL
I =1 cycle
RCD
I
= 5 cycles
I =1 cycle
RCD
I
= 5 cycles
I =1 cycle
RCD
RAS
RAS
Address
UA
LA
UA
#0
LA
UA
LA
Bank Add.
#0
#0
BL = 2
DQS/ DQS
(input)
WL = 4
WL = 4
DQ
(input)
D0 D1
D0 D1
BL = 4
DQS/ DQS
(input)
WL = 4
WL = 4
DQ
(input)
D0 D1 D2 D3
D0 D1 D2 D3
Note : TC59LM914AMB doesn’t have DQS .
2003-08-04 27/57
TC59LM914/06AMB-37,-45,-50
SINGLE BANK READ-WRITE TIMING (CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 5 cycles
I
= 5 cycles
I
= 5 cycles
RC
RC
RC
Command
Address
RDA LAL
DESL
WRA LAL
DESL
RDA LAL
DESL
WRA
UA
UA
#0
LA
UA
#0
LA
UA
#0
LA
Bank Add.
#0
BL = 2
Hi-Z
DQS
Hi-Z
Hi-Z
DQS
DQ
CL = 3
CL = 3
WL = 2
Q0 Q1
D0 D1
Q0 Q1
BL = 4
Hi-Z
Hi-Z
DQS
DQS
DQ
CL = 3
CL = 3
WL = 2
Hi-Z
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Q0 Q1 Q2 Q3
Note : TC59LM914AMB doesn’t have DQS .
2003-08-04 28/57
TC59LM914/06AMB-37,-45,-50
SINGLE BANK READ-WRITE TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 5 cycles
I
= 5 cycles
I
= 5 cycles
RC
RC
RC
Command
Address
RDA LAL
DESL
WRA LAL
DESL
RDA LAL
DESL
WRA
UA
UA
#0
LA
UA
#0
LA
UA
#0
LA
Bank Add.
#0
BL = 2
Hi-Z
DQS
Hi-Z
Hi-Z
DQS
CL = 4
WL = 3
CL = 4
DQ
Q0 Q1
D0 D1
Q0
BL = 4
Hi-Z
Hi-Z
DQS
DQS
DQ
CL = 4
WL = 3
CL = 4
Hi-Z
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Q0
Note : TC59LM914AMB doesn’t have DQS .
2003-08-04 29/57
TC59LM914/06AMB-37,-45,-50
SINGLE BANK READ-WRITE TIMING (CL = 5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 6 cycles
I
= 6 cycles
RC
RC
Command
Address
RDA LAL
DESL
WRA LAL
DESL
RDA LAL
DESL
UA
#0
LA
UA
#0
LA
UA
#0
LA
Bank Add.
BL = 2
Hi-Z
DQS
Hi-Z
Hi-Z
DQS
CL = 5
WL = 4
Q0 Q1
D0 D1
DQ
BL = 4
Hi-Z
Hi-Z
DQS
DQS
DQ
WL = 4
CL = 5
Hi-Z
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Note : TC59LM914AMB doesn’t have DQS .
2003-08-04 30/57
TC59LM914/06AMB-37,-45,-50
MULTIPLE BANK READ TIMING (CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
I
= 2 cycles I
RBD
= 2 cyclesI
RBD
= 2 cycles I = 2 cycles
RBD
RBD
RBD
Command
Address
RDA LAL RDA LAL DESL RDA LAL RDA LAL RDA LAL RDA LAL RDA LAL RDA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank Add.
I
(Bank"a") = 5 cycles
RC
I
(Bank"b") = 5 cycles
RC
BL = 2
Hi-Z
DQS/ DQS
(output)
CL = 3
CL = 3
DQ
Hi-Z
Hi-Z
Qa0Qa1
Qb0Qb1
Qa0Qa1
Qb0Qb1
Qc0Qc1
Qd0Qd1
(output)
BL = 4
DQS/ DQS
(output)
CL = 3
CL = 3
DQ
(output)
Hi-Z
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3Qc0Qc1Qc2Qc3Qd0Qd1
Note: l
to the same bank must be satisfied.
RC
TC59LM914AMB doesn’t have DQS .
2003-08-04 31/57
TC59LM914/06AMB-37,-45,-50
MULTIPLE BANK READ TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
I
= 2 cycles I
RBD
= 2 cyclesI
RBD
= 2 cycles I = 2 cycles
RBD
RBD
RBD
Command
Address
RDA LAL RDA LAL DESL RDA LAL RDA LAL RDA LAL RDA LAL RDA LAL
RDA
UA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank Add.
I
(Bank"a") = 5 cycles
RC
I
(Bank"b") = 5 cycles
RC
BL = 2
Hi-Z
DQS/ DQS
(output)
CL = 4
CL = 4
Hi-Z
Hi-Z
DQ
Qa0Qa1
Qb0Qb1
Qa0Qa1
Qb0Qb1
Qc0Qc1
(output)
BL = 4
DQS/ DQS
(output)
CL = 4
CL = 4
DQ
(output)
Hi-Z
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3Qc0Qc1Qc2
Note: l
to the same bank must be satisfied.
RC
TC59LM914AMB doesn’t have DQS .
2003-08-04 32/57
TC59LM914/06AMB-37,-45,-50
MULTIPLE BANK READ TIMING (CL = 5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
I
= 2 cycles
I
= 2 cycles I
RBD
= 2 cycles
I
= 2 cycles
RBD
RBD
RBD
RBD
Command
Address
RDA LAL RDA LAL
DESL
RDA LAL RDA LAL RDA LAL RDA LAL RDA LAL
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank Add.
I
(Bank"a") = 6 cycles
RC
I
(Bank"b") = 6 cycles
RC
BL = 2
Hi-Z
DQS/ DQS
(output)
CL = 5
CL = 5
DQ
Hi-Z
Hi-Z
Qa0Qa1
Qb0Qb1
Qa0Qa1
Qb0Qb1
(output)
BL = 4
DQS/ DQS
(output)
CL = 5
CL = 5
DQ
(output)
Hi-Z
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
Qa0Qa1Qa2Qa3Qb0Qb1Qb2
Note: l
to the same bank must be satisfied.
RC
TC59LM914AMB doesn’t have DQS .
2003-08-04 33/57
TC59LM914/06AMB-37,-45,-50
MULTIPLE BANK WRITE TIMING (CL = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
I
= 2 cycles I
= 2 cycles I
RBD
= 2 cycles I = 2 cycles
RBD
RBD
RBD
RBD
Command
Address
WRA LAL WRA LAL DESL WRA LAL WRA LAL WRA LAL WRA LAL WRA LAL WRA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
Bank Add.
I
(Bank"a") = 5 cycles
RC
I
(Bank"b") = 5 cycles
RC
BL = 2
DQS/ DQS
(input)
WL = 2
WL = 2
DQ
(input)
Da0Da1
Db0Db1
Da0Da1
Db0Db1
Dc0Dc1
Dd0Dd1
BL = 4
DQS/ DQS
(input)
WL = 2
WL = 2
DQ
(input)
Da0Da1Da2Da3Db0Db1Db2Db3
Da0Da1Da2Da3Db0Db1Db2Db3Dc0Dc1Dc2Dc3Dd0Dd1Dd2Dd3
Note: l
to the same bank must be satisfied.
RC
TC59LM914AMB doesn’t have DQS .
2003-08-04 34/57
TC59LM914/06AMB-37,-45,-50
MULTIPLE BANK WRITE TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
I
= 2 cycles I
= 2 cycles I
RBD
= 2 cycles I = 2 cycles
RBD
RBD
RBD
RBD
Command
Address
WRA LAL WRA LAL DESL WRA LAL WRA LAL WRA LAL WRA LAL WRA LAL WRA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
Bank Add.
I
(Bank"a") = 5 cycles
RC
I
(Bank"b") = 5 cycles
RC
BL = 2
DQS/ DQS
(input)
WL = 3
WL = 3
DQ
(input)
Da0Da1
Db0Db1
Da0Da1
Db0Db1
Dc0Dc1
Dd0Dd1
BL = 4
DQS/ DQS
(input)
WL = 3
WL = 3
DQ
(input)
Da0Da1Da2Da3Db0Db1Db2Db3
Da0Da1Da2Da3Db0Db1Db2Db3Dc0Dc1Dc2Dc3Dd0Dd1
Note: l
to the same bank must be satisfied.
RC
TC59LM914AMB doesn’t have DQS .
2003-08-04 35/57
TC59LM914/06AMB-37,-45,-50
MULTIPLE BANK WRITE TIMING (CL = 5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
I
= 2 cycles I
RBD
= 2 cycles I
RBD
= 2 cycles I = 2 cycles
RBD
RBD
RBD
Command
Address
WRA LAL WRA LAL
DESL
WRA LAL WRA LAL WRA LAL WRA LAL WRA LAL
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
Bank
"a"
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank Add.
I
(Bank"a") = 6 cycles
RC
I
(Bank"b") = 6 cycles
RC
BL = 2
DQS/ DQS
(input)
WL = 4
WL = 4
DQ
(input)
Da0Da1
Db0Db1
Da0Da1
Db0Db1
Dc0Dc1
BL = 4
DQS DQS
(input)
WL = 4
WL = 4
DQ
(input)
Da0Da1Da2Da3Db0Db1Db2Db3
Da0Da1Da2Da3Db0Db1Db2Db3Dc0Dc1
Note: l
to the same bank must be satisfied.
RC
TC59LM914AMB doesn’t have DQS .
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TC59LM914/06AMB-37,-45,-50
MULTIPLE BANK READ-WRITE TIMING (BL = 2)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
RBD
Command
WRA LAL RDA LAL DESL WRA LAL RDA LAL DESL WRA LAL RDA LAL DESL WRA
I
= 1 cycle
I
= 2 cycles
I
= 1 cycle
I
= 2 cycles
WRD
RWD
WRD
RWD
Address
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
Bank
"c"
Bank Add.
I
(Bank"a")
RC
I
(Bank"b")
RC
CL = 3
DQS
DQS
CL = 3
WL = 2
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
Da0 Da1
DQ
CL = 4
DQS
DQS
DQ
CL = 4
WL = 3
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
Da0 Da1
CL = 5
DQS
DQS
CL = 5
WL = 4
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
Da0 Da1
DQ
Note: l
to the same bank must be satisfied.
RC
TC59LM914AMB doesn’t have DQS .
2003-08-04 37/57
TC59LM914/06AMB-37,-45,-50
MULTIPLE BANK READ-WRITE TIMING (BL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
= 2 cycles
RBD
Command
DESL
= 3 cycles
DESL
WRA LAL RDA LAL
WRA LAL RDA
LAL
LA
WRA LAL RDA LAL
I
= 1 cycle
I
I
= 1 cycle
I
= 3 cycles
I
= 1 cycle
WRD
RWD
WRD
RWD
WRD
Address
UA
LA
UA
LA
UA
LA
UA
UA
LA
UA
LA
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
Bank Add.
I
(Bank"a")
RC
I
(Bank"b")
RC
CL = 3
DQS
DQS
CL = 3
WL = 2
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
Qd0 Qd1 Qd2 Qd3
DQ
CL = 4
DQS
DQS
CL = 4
WL = 3
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
Qd0 Qd1 Qd2 Qd3
DQ
CL = 5
DQS
DQS
DQ
CL = 5
WL = 4
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
Qd0 Qd1 Qd2 Qd3
Note: l
to the same bank must be satisfied.
RC
TC59LM914AMB doesn’t have DQS .
2003-08-04 38/57
TC59LM914/06AMB-37,-45,-50
WRITE with VARIAVLE WRITE LENGTH (VW) CONTROL (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
BL = 2, SEQUENTIAL MODE
Command
WRA LAL
DESL
WRA LAL
DESL
LA=#3
VW=All
LA=#1
VW=1
Address
UA
UA
Bank
"a"
Bank
VW=1
"a"
Bank Add.
VW=A11
VW0 = Low
VW1 = don't care
VW0 = High
VW1 = don't care
DQS/ DQS
(input)
DQ
(input)
D0 D1
D0
Lower Address #3 #2
#1 (#0)
Last one data is masked.
BL = 4, SEQUENTIAL MODE
Command
Address
WRA LAL
DESL
WRA LAL
DESL
WRA LAL
DESL
LA=#3
LA=#1
LA=#2
UA
UA
UA
VW=All
VW=1
VW=2
Bank
"a"
Bank
VW=1
"a"
Bank
VW=2
"a"
Bank Add.
VW=A11
VW0 = High
VW1 = Low
VW0 = High
VW1 = High
VW0 = Low
VW1 = High
DQS/ DQS
(input)
DQ
(input)
D0 D1 D2 D3
D0
D0 D1
Lower Address #3 #0 #1 #2
#1(#2)(#3)(#0)
Last three data are masked.
Note: DQS ( DQS ) input must be continued till end of burst count even if some of laster data is masked.
#2 #3 (#0)(#1)
Last two data are masked.
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TC59LM914/06AMB-37,-45,-50
POWER DOWN TIMING (CL = 4, BL = 4)
Read cycle to Power Down Mode
0
1
2
3
4
5
6
7
8
9
10
n-1
n
n+1
n+2
n+3
CLK
CLK
I
PDA
RDA
or
Command
Address
RDA LAL
DESL
DESL
WRA
UA
LA
UA
t
IS
I
= 1 cycle
PD
t
IH
PD
t
t
QPDH
PDEX
l
, t
RC(min) REFI(max)
Hi-Z
DQS
(output)
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQS
(output)
CL = 4
DQ
(output)
Q0 Q1 Q2 Q3
Power Down Entry
Note: PD must be kept "High" level until end of Burst data output.
Power Down Exit
cycles later.
PD should be brought to "High" within t
(max.) to maintain the data written into cell.
REFI
In Power Down Mode, PD "Low" must be maintained.
When PD is brought to "High", a valid executable command may be applied l
TC59LM914AMB doesn’t have DQS .
PDA
2003-08-04 40/57
TC59LM914/06AMB-37,-45,-50
POWER DOWN TIMING (CL = 4, BL = 4)
Write cycle to Power Down Mode
0
1
2
3
4
5
6
7
8
9
10
n-1
n
n+1
n+2
n+3
CLK
CLK
I
PDA
RDA
or
Command
Address
WRA LAL
DESL
DESL
WRA
UA
LA
UA
t
IS
I
= 1 cycle
PD
t
IH
PD
WL = 3
2 clock cycles
t
PDEX
l
, t
RC(min) REFI(max)
DQS
(input)
DQS
(input)
WL = 3
DQ
(input)
D0 D1 D2 D3
Note: PD must be kept "High" level until WL+2 clock cycles from LAL command.
PD should be brought to "High" within t (max.) to maintain the data written into cell.
REFI
In Power Down Mode, PD "Low" must be maintained.
When PD is brought to "High", a valid executable command may be applied l
TC59LM914AMB doesn’t have DQS .
cycles later.
PDA
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TC59LM914/06AMB-37,-45,-50
MODE REGISTER SET TIMING (CL = 4, BL = 2)
From Read operation to Mode Register Set operation.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
RSC
RDA
or
Command
A13~A0
RDA LAL
DESL
RDA MRS
DESL
LAL
LA
WRA
Valid
(opcode)
UA
BA
LA
UA
BA
BA0="0"
BA1="0"
BA2="0"
BA0~BA2
CL + BL/2
Hi-Z
DQS
(output)
Hi-Z
DQS
DQ
(output)
Q0 Q1
Note: Minimum delay from LAL following RDA to RDA of MRS operation is CL+BL/2.
TC59LM914AMB doesn’t have DQS .
2003-08-04 42/57
TC59LM914/06AMB-37,-45,-50
MODE REGISTER SET TIMING (CL = 4, BL = 4)
From Write operation to Mode Register Set operation.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
RSC
RDA
or
Command
A13~A0
WRA LAL
DESL
RDA MRS
DESL
LAL
LA
WRA
Valid
(opcode)
UA
BA
LA
UA
BA
BA0="0"
BA1="0"
BA2="0"
BA0~BA2
WL+BL/2
DQS
(input)
DQS
(input)
DQ
(input)
D0 D1 D2 D3
Note: Minimum delay from LAL following WRA to RDA of MRS operation is WL+BL/2.
TC59LM914AMB doesn’t have DQS .
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TC59LM914/06AMB-37,-45,-50
EXTENDED MODE REGISTER SET TIMING (CL = 4, BL = 2)
From Read operation to Extended Mode Register Set operation.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
RSC
RDA
or
Command
A13~A0
RDA LAL
DESL
RDA MRS
DESL
LAL
LA
WRA
Valid
(opcode)
UA
BA
LA
UA
BA
BA0="1"
BA1="0"
BA2="0"
BA0~BA2
CL + BL/2
Hi-Z
DQS
(output)
Hi-Z
DQS
(output)
DQ
(output)
Q0 Q1
Note: Minimum delay from LAL following RDA to RDA of EMRS operation is CL+BL/2.
DLL switch in Extended Mode Register must be set to enable mode for normal operation.
DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence.
TC59LM914AMB doesn’t have DQS .
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TC59LM914/06AMB-37,-45,-50
EXTENDED MODE REGISTER SET TIMING (CL = 4, BL = 4)
From Write operation to Extended Mode Register Set operation.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
I
RSC
RDA
or
Command
A13~A0
WRA LAL
DESL
RDA MRS
DESL
LAL
LA
WRA
Valid
(opcode)
UA
BA
LA
UA
BA
BA0="1"
BA1="0"
BA2="0"
BA0~BA2
WL+BL/2
DQS
(input)
DQS
(input)
DQ
(input)
D0 D1 D2 D3
Note: DLL switch in Extended Mode Register must be set to enable mode for normal operation.
DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence.
Minimum delay from LAL following WRA to RDA of EMRS operation is WL+BL/2.
TC59LM914AMB doesn’t have DQS .
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TC59LM914/06AMB-37,-45,-50
AUTO-REFRESH TIMING (CL = 4, BL = 4)
0
1
2
3
4
5
6
7
n − 1
n
n + 1
n + 2
CLK
CLK
I
= 5 cycles
I
= 18 cycles
RC
REFC
RDA LAL or
Command
RDA
LAL
LA
DESL
WRA
REF
DESL
or
MRS or
REF
Bank,
UA
Bank, Address
I
= 1 cycle
I
= 4 cycles
I = 1 cycle
RCD
RCD
RAS
DQS/ DQS
(output)
Hi-Z
Hi-Z
Hi-Z
CL = 4
DQ
(output)
Hi-Z
Q0 Q1 Q2 Q3
Note: In case of CL = 4, I
must be meet 18 clock cycles.
REFC
When the Auto-Refresh operation is performed, the synthetic average interval of Auto-Refresh command
specified by t
REFI
TC59LM914AMB doesn’t have DQS .
must be satisfied.
REFI
is average interval time in 8 Refresh cycles that is sampled randomly.
t
t
1
t
2
t
3
t
7
t
8
CLK
WRA REF
WRA REF
WRA REF
WRA REF
WRA REF
8 Refresh cycle
Total time of 8 Refresh cycle
8
t + t + t + t + t + t + t + t
1 2 3 4 5 6 7 8
t
=
=
REFI
8
t
is specified to avoid partly concentrated current of Refresh operation that is activated larger area
REFI
than Read / Write operation.
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TC59LM914/06AMB-37,-45,-50
SELF-REFRESH ENTRY TIMING
0
1
2
3
4
5
m − 1
m
m + 1
CLK
CLK
I
= 1 cycle
I
REFC
RCD
Command
WRA
REF
DESL
t
t
FPDL (min) FPDL (max)
Auto Refresh
PD
Self Refresh Entry
*2
I
PDV
I
t
QPDH
CKD
Hi-Z
Hi-Z
DQS/ DQS
(output)
DQ
(output)
Qx
Notes: 1.
is don’t care.
2. PD must be brought to "Low" within the timing between t
(min) and t
(max) to Self Refresh
FPDL
FPDL
mode. When PD is brought to "Low" after l
, TC59LM914/06AMB perform Auto Refresh and
PDV
enter Power down mode. In case of PD fall between t
(max) and l
, TC59LM914/06AMB will
FPDL
PDV
either entry Self-Refresh mode or Power down mode after Auto-Refresh operation. It can’t be
specified which mode TC59LM914/06AMB operates.
3. It is desirable that clock input is continued at least l
brought to “Low” for Self-Refresh Entry.
4. TC59LM914AMB doesn’t have DQS .
from REF command even though PD is
CKD
5. In case of Self-Refresh entry after Write Operation, the delay time from the LAL command following
WRA to the REF command is Write latency (WL)+3 clock cycles minimum.
SELF-REFRESH EXIT TIMING
0
1
2
m − 1
m
m + 1
m + 2
n − 1
n
n + 1
p − 1
p
CLK
CLK
*2
*6
Command (1st)
I
I
*6
REFC
REFC
Command (2nd)
*3
*5
*5
*7
*7
Command
PD
DESL
WRA
REF
DESL
RDA
LAL
*4
I
= 1 cycles
I
= 1 cycle
I
= 1 cycle
PDA
RCD
RCD
t
PDEX
I
LOCK
DQS/ DQS
(output)
Hi-Z
DQ
(output)
Hi-Z
Self-Refresh Exit
Notes: 1. is don’t care.
2. Clock should be stable prior to PD = “High” if clock input is suspended in Self-Refresh mode.
3. DESL command must be asserted during I after PD is brought to “High”.
REFC
is defined from the first clock rising edge after PD is brought to “High”.
4.
I
PDA
5. It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any
other operation.
6. Any command (except Read command) can be issued after I
.
REFC
7. Read command (RDA + LAL) can be issued after I
.
LOCK
8. TC59LM914AMB doesn’t have DQS .
2003-08-04 47/57
TC59LM914/06AMB-37,-45,-50
FUNCTIONAL DESCRIPTION
TM
Network FCRAM
FCRAMTM is an acronym of Fast Cycle Random Access Memory. The Network FCRAMTM is competent to
perform fast random core access, low latency and high-speed data transfer.
PIN FUNCTIONS
CLOCK INPUTS: CLK & CLK
The CLK and CLK inputs are used as the reference for synchronous operation. CLK is master clock input.
The CS , FN and all address input signals are sampled on the crossing of the positive edge of CLK and the
negative edge of CLK . The DQS and DQ output are aligned to the crossing point of CLK and CLK . The
timing reference point for the differential clock is when the CLK and CLK signals cross during a transition.
POWER DOWN: PD
The PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a
Clock Suspend function like a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into
low state if any Read or Write operation is being performed.
CS
CHIP SELECT & FUNCTION CONTROL:
& FN
The CS and FN inputs are a control signal for forming the operation commands on FCRAMTM. Each
operation mode is decided by the combination of the two consecutive operation commands using the CS and
FN inputs.
BANK ADDRESSES: BA0~BA2
The BA0 to BA2 inputs are latched at the time of assertion of the RDA or WRA command and are selected the
bank to be used for the operation. BA0 and BA1 also define which mode register is loaded during the Mode
Register Set command (MRS or EMRS).
BA0
BA1
BA2
Bank #0
Bank #1
Bank #2
Bank #3
Bank #4
Bank #5
Bank #6
Bank #7
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
ADDRESS INPUTS: A0~A13
Address inputs are used to access the arbitrary address of the memory cell array within each bank. The
Upper Addresses with Bank addresses are latched at the RDA or WRA command and the Lower Addresses are
latched at the LAL command. The A0 to A13 inputs are also used for setting the data in the Regular or
Extended Mode Register set cycle.
UPPER ADDRESS
LOWER ADDRESS
TC59LM906AMB
TC59LM914AMB
A0~A13
A0~A13
A0~A8
A0~A7
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TC59LM914/06AMB-37,-45,-50
DATA INPUT/OUTPUT: DQ0~DQ7 or DQ15
The input data of DQ0 to DQ15 are taken in synchronizing with the both edges of DQS input signal. The
output data of DQ0 to DQ15 are outputted synchronizing with the both edges of DQS output signal.
DATA STROBE: DQS, DQS
The DQS is bi-directional signal. Both edge of DQS are used as the reference of data input or output. In write
operation, the DQS used as an input signal is utilized for a latch of write data. In read operation, the DQS is an
output signal provides the read data strobe.
TC59LM906AMB has differential data strobe pin ( DQS ). When DQS is enable mode, DQS is differential
output signal for DQS in read operation, data input are latched at the crossing point of DQS and DQS in Write
operation. When DQS is disable mode, DQS is always Hi-Z, and data input are latched at the crossing point
of DQS and VREF level. DQS mode is set at Extended Mode Register Set Cycle.
TC59LM914AMB doesn’t have DQS pin. Data input are latched at the crossing point of L/UDQS and VREF
level in Write operation. LDQS is strobe signal for DQ0-DQ7. UDQS is strobe signal for DQ8-DQ15.
POWER SUPPLY: V , V
, V , V
DD DDQ SS SSQ
V
DD
and V are power supply pins for memory core and peripheral circuits.
SS
V
DDQ
and V
are power supply pins for the output buffer.
SSQ
REFERENCE VOLTAGE: V
REF
V
REF
is reference voltage for all input signals.
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TC59LM914/06AMB-37,-45,-50
COMMAND FUNCTIONS and OPERATIONS
TC59LM914/06AMB are introduced the two consecutive command input method. Therefore, except for Power
Down mode, each operation mode decided by the combination of the first command and the second command from
stand-by states of the bank to be accessed.
Read Operation (1st command + 2nd command = RDA + LAL)
Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank
designated by Bank Address in a read mode. When the LAL command with Lower Addresses is issued at the next
clock of the RDA command, the data is read out sequentially synchronizing with the both edges of DQS/ DQS
output signal (Burst Read Operation). The initial valid read data appears after CAS latency from the issuing of
the LAL command. The valid data is outputted for a burst length. The CAS latency, the burst length of read
data and the burst type must be set in the Mode Register beforehand. The read operated bank goes back
automatically to the idle state after l . DQS is differential data strobe signal supported TC59LM906AMB.
RC
Write Operation (1st command + 2nd command = WRA + LAL)
Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank
designated by Bank Address in a write mode. When the LAL command with Lower Addresses is issued at the
next clock of the WRA command, the input data is latched sequentially synchronizing with the both edges of
DQS/ DQS input signal (Burst Write Operation). The data and DQS/ DQS inputs have to be asserted in keeping
with clock input after CAS latency-1 from the issuing of the LAL command. The DQS/ DQS has to be provided
for a burst length. The CAS latency and the burst type must be set in the Mode Register beforehand. The write
operated bank goes back automatically to the idle state after l . Write Burst Length is controlled by VW0 and
RC
VW1 inputs with LAL command. See VW truth table. DQS is differential data strobe signal supported
TC59LM906AMB.
Auto-Refresh Operation (1st command + 2nd command = WRA + REF)
TC59LM914/06AMB are required to refresh like a standard SDRAM. The Auto-Refresh operation is begun with
the REF command following to the WRA command. The Auto-Refresh mode can be effective only when all banks
are in the idle state and all outputs are in Hi-Z states. In a point to notice, the write mode started with the WRA
command is canceled by the REF command having gone into the next clock of the WRA command instead of the
LAL command. The minimum period between the Auto-Refresh command and the next command is specified by
l . However, about a synthetic average interval of Auto-Refresh command, it must be careful. In case of
REFC
equally distributed refresh, Auto-Refresh command has to be issued within once for every 3.9 µs by the maximum.
In case of burst refresh or random distributed refresh, the average interval of eight consecutive Auto-Refresh
command has to be more than 400 ns always. In other words, the number of Auto-Refresh cycles that be
performed within 3.2 µs (8 × 400 ns) is to 8 times in the maximum.
PD
= “L”)
Self-Refresh Operation (1st command + 2nd command = WRA + REF with
In case of Self-Refresh operation, refresh operation can be performed automatically by using an internal timer.
When all banks are in the idle state and all outputs are in Hi-Z states, the TC59LM914/06AMB become
Self-Refresh mode by issuing the Self-Refresh command. PD has to be brought to “Low” within t
from the
FPDL
REF command following to the WRA command for a Self-Refresh mode entry. In order to satisfy the refresh
period, the Self-Refresh entry command should be asserted within 3.9 µs after the latest Auto-Refresh command.
Once the device enters Self-Refresh mode, the DESL command must be continued for l
period. In addition, it
REFC
is desirable that clock input is kept in l
period. The device is in Self-Refresh mode as long as PD held “Low”.
CKD
During Self-Refresh mode, all input and output buffers are disabled except for PD , therefore the power
dissipation lowers. Regarding a Self-Refresh mode exit, PD has to be changed over from “Low” to “High” along
with the DESL command, and the DESL command has to be continuously issued in the number of clocks specified
by l . The Self-Refresh exit function is asynchronous operation. It is required that one Auto-Refresh
REFC
command is issued to avoid the violation of the refresh period just after l
from Self-Refresh exit.
REFC
PD
= “L”)
Power Down Mode (
When all banks are in the idle state and DQ outputs are in Hi-Z states, the TC59LM914/06AMB become Power
Down Mode by asserting PD is “Low”. When the device enters the Power Down Mode, all input and output
buffers are disabled after specified time except for PD . Therefore, the power dissipation lowers. To exit the
Power Down Mode, PD has to be brought to “High” and the DESL command has to be issued for two clock cycle
after PD goes high. The Power Down exit function is asynchronous operation.
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TC59LM914/06AMB-37,-45,-50
Mode Register Set (MRS) and Extended Mode Register Set (EMRS)
(1st command + 2nd command = RDA + MRS)
When all banks are in the idle state, issuing the MRS command following to the RDA command can program
the Mode Register. In a point to notice, the read mode started with the RDA command is canceled by the MRS
command having gone into the next clock of the RDA command instead of the LAL command. The data to be set
in the Mode Register is transferred using A0 to A13, BA0 to BA2 address inputs. The TC59LM914/06AMB have
two mode registers. These are Regular and Extended Mode Register. The Regular or Extended Mode Register is
chosen by BA0 and BA1 in the MRS command. The Regular Mode Register designates the operation mode for a
read or write cycle. The Regular Mode Register has four function fields.
The four fields are as follows:
(R-1) Burst Length field to set the length of burst data
(R-2) Burst Type field to designate the lower address access sequence in a burst cycle
(R-3) CAS Latency field to set the access time in clock cycle
(R-4) Test Mode field to use for supplier only.
The Extended Mode Register has five function fields.
The five fields are as follows:
(E-1) DLL Switch field to choose either DLL enable or DLL disable
(E-2) Output Driver Impedance Control field.
(E-3) Off-Chip Driver (OCD) Impedance Adjustment for Full Strength Output Driver
(E-4) DQS enable field
(E-5) Interface mode select
Once those fields in the Mode Register are set up, the register contents are maintained until the Mode Register
is set up again by another MRS command or power supply is lost. The initial value of the Regular or Extended
Mode Register after power-up is undefined, therefore the Mode Register Set command must be issued before
proper operation.
•
Regular Mode Register/Extended Mode Register change bits (BA0, BA1)
These bits are used to choose either Regular MRS or Extended MRS
BA1
BA0
BA2, A13~A0
0
0
1
0
1
×
Regular MRS Cycle
Extended MRS Cycle
Reserved
Regular Mode Register Fields
(R-1) Burst Length field (A2 to A0), (BL)
This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length
to be 2 or 4 words.
A2
A1
A0
BURST LENGTH
0
0
0
0
1
0
0
1
1
×
0
1
0
1
×
Reserved
2 words
4 words
Reserved
Reserved
(R-2) Burst Type field (A3), (BT)
The Burst Type can be chosen Interleave mode or Sequential mode. When the A3 bit is “0”, Sequential
mode is selected. When the A3 bit is “1”, Interleave mode is selected. Both burst types support burst
length of 2 and 4 words.
A3
BURST TYPE
0
1
Sequential
Interleave
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TC59LM914/06AMB-37,-45,-50
•
Addressing sequence of Sequential mode
A column access is started from the inputted lower address and is performed by incrementing the lower
address input to the device.
CAS Latency = 4
CLK
CLK
Command
RDA
LAL
DQS/
DQS
DQ
Data Data Data Data
0
1
2
3
Addressing sequence for Sequential mode
DATA
ACCESS ADDRESS
BURST LENGTH
Data 0
Data 1
Data 2
Data 3
n
2 words (address bits is LA0)
not carried from LA0~LA1
n + 1
n + 2
n + 3
4 words (address bits is LA1, LA0)
not carried from LA1~LA2
•
Addressing sequence of Interleave mode
A column access is started from the inputted lower address and is performed by interleaving the address bits
in the sequence shown as the following.
Addressing sequence for Interleave mode
DATA
ACCESS ADDRESS
BURST LENGTH
Data 0
Data 1
Data 2
Data 3
ּּּA8 A7 A6 A5 A4 A3 A2 A1 A0
ּּּA8 A7 A6 A5 A4 A3 A2 A1 A0
ּּּA8 A7 A6 A5 A4 A3 A2 A1 A0
ּּּA8 A7 A6 A5 A4 A3 A2 A1 A0
2 words
4 words
(R-3) CAS Latency field (A6 to A4), (CL)
This field specifies the number of clock cycles from the assertion of the LAL command following the
RDA command to the first data read. The minimum values of CAS Latency depends on the frequency
of CLK. In a write mode, the place of clock that should input write data is CAS Latency cycles − 1.
A6
A5
A4
CAS LATENCY
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
3
4
5
Reserved
Reserved
(R-4) Test Mode field (A7), (TE)
This bit is used to enter Test Mode for supplier only and must be set to “0” for normal operation.
(R-5) Reserved field in the Regular Mode Register
•
Reserved bits (A8 to A13, BA2)
These bits are reserved for future operations. They must be set to “0” for normal operation.
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TC59LM914/06AMB-37,-45,-50
Extended Mode Register fields
(E-1) DLL Switch field (A0), (DS)
This bit is used to enable DLL. When the A0 bit is set “0”, DLL is enabled. This bit must set to “0” for
normal operation.
(E-2) Output Driver Impedance Control field (A1, A6) (DIC)
This field is used to choose Output Driver Strength. Four types of Driver Strength are supported.
Output Driver Strength can be set by field in EMRS with OCD calibration default (A7~A9 = 1 at EMRS)
or OCD calibration mode exit (A7~A9 = 0 at EMRS).
A6
A1
OUTPUT DRIVER IMPEDANCE CONTROL
0
0
1
1
0
1
0
1
Normal Output Driver
Strong Output Driver
Weak Output Driver
Full Strength Output Driver
(E-3) Off-Chip Driver (OCD) Impedance Adjustment (A7 to A9) (OCD)
OCD calibration (Off Chip Driver impedance adjustment) is available only for Full Strength Output
Driver. When OCD calibration is performed, A1 and A6 inputs at EMRS must be “1” for Full Strength
Output Driver.
Output Driver Strength can be set by DIC field (E-2). This Driver strength is the initial driver level at
OCD Impedance Adjustment.
The Network FCRAMTM supports driver calibration feature and the flow chart below is an example of
sequence. Every calibration mode command should be followed by “OCD calibration mode exit” before
any other command being issued. MRS should be set before entering OCD impedance adjustment.
MRS should be set before entering OCD impedance adjustment.
Start
EMRS: OCD calibration mode exit
EMRS: Drive(1)
DQ &DQS High; DQS Low
EMRS: Drive(0)
DQ &DQS Low; DQS High
ALL OK
Need Calibration
ALL OK
Test
Test
Need Calibration
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
EMRS:
Enter Adjust Mode
EMRS:
Enter Adjust Mode
BL=4 code Input to all DQs
Inc, Dec, or NOP
BL=4 code Input to all DQs
Inc, Dec, or NOP
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
End
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Extended Mode Register Set for OCD Impedance adjustment
OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs are
driven out by Network FCRAM. In drive (1) mode, all DQ, DQS signals are driven high and DQS signals are
driven low. In drive (0) mode, all DQ, DQS signals are driven low and DQS signals are driven high. In adjust
mode, BL=4 of operation code data must be used
A9
A8
A7
Operation
0
0
0
1
1
0
0
1
0
1
0
1
0
0
1
OCD calibration mode exit
Drive (1) DQ, DQS high and DQS low
Drive (0) DQ, DQS low and DQS high
Adjust mode
OCD calibration default
OCD impedance adjust
To adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a 4bit
burst code to Network FCRAM. For this operation, Burst Length has to be set to BL=4 via MRS command
before activating OCD and controllers must drive this burst code to all DQs at the same time. DT0 means all
DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all DQs
simultaneously and after OCD calibration, all DQs of a given Network FCRAM will be adjusted to the same
driver strength setting. The maximum step count for adjustment is 16 and when the limit is reached, further
increment or decrement code has no effect.
Off-Chip Driver Program
4bit burst code inputs to all DQs
Operation
D
T0
D
T1
D
T2
D
T3
Pull-up driver strength
Pull-down driver strength
0
0
0
0
1
0
0
1
1
0
0
0
1
0
1
1
0
0
0
0
1
0
0
0
1
0
1
0
1
0
0
0
1
0
1
0
NOP (No operation)
Increase by 1 step
Decrease by 1 step
NOP
NOP (No operation)
NOP
NOP
Increase by 1 step
Decrease by 1 step
Increase by 1 step
Increase by 1 step
Decrease by 1 step
Decrease by 1 step
NOP
Increase by 1 step
Decrease by 1 step
Increase by 1 step
Decrease by 1 step
Other Combinations
Reserved
For proper operation of adjust mode, WL=CL-1 clocks and tDS / tDH should be met as the following timing
diagram. For input data pattern for adjustment, DT0~DT3 is a fixed order and “not affected by MRS
addressing mode (i.e. Sequential or interleave).
Driver strength is controlled within the following range by OCD impedance adjustment.
SYMBOL
PARAMETER
Output Source DC Current for V Q = 1.7V~1.9V
MIN
MAX
UNIT NOTES
mA
DD
I
(DC)
(DC)
−14.0
−18.7
OH
V Q = 1.7V
DD
V
OH
= 1.420V
Full Strength
Output Driver
Output Sink DC Current for V Q = 1.7V~1.9V
DD
I
14.0
18.7
OL
V Q = 1.7V
DD
V
OL
= 0.280V
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TC59LM914/06AMB-37,-45,-50
OCD adjust mode
EMRS
OCD calibration mode exit
Command
RDA
NOP
NOP
NOP
NOP
RDA
EMRS
NOP
CLK
CLK
WL
1clock
DQS
DQS_in
DQ_in
t
t
DS DH
D
D
T1
D
T2
D
T3
T0
Drive mode
Drive mode, both Drive (1) and Drive (0), is used for controllers to measure Network FCRAM Driver
impedance. In this mode, all outputs are driven out tOIT after “enter drive mode” command and all output
drivers are turned-off tOIT after “OCD calibration mode exit” command as the following timing diagram.
OCD calibration mode exit
EMRS NOP
Enter Drive mode
EMRS
Command
RDA
NOP
NOP
RDA
CLK
CLK
DQS,
DQS
DQS high & DQS low for Drive (1), DQS low & DQS high for Drive (0)
DQs high for Drive (1), DQs low for Drive (0)
DQ
t
t
OIT
OIT
(E-4) DQS enable field (A10), ( DQS )
This bit is used to enable Differential Data strobe.
DQS is available on TC59LM906AMB. This field of TC59LM914AMB is ignored.
A10
DQS Enable
0
1
Disable
Enable
(E-5) Interface mode select (A11)
This bit must be always set “0”.
(E-6) Reserved field (A2 to A5, A12, A13, BA2)
These bits are reserved for future operations and must be set to “0” for normal operation.
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TC59LM914/06AMB-37,-45,-50
PACKAGE DIMENSIONS
P-BGA64-1317-1.00AZ
16.5
0
13.086-0.15
0.2 S
0.5 0.05
1.25
0.08
S
AB
B
1.0
2.0
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TC59LM914/06AMB-37,-45,-50
RESTRICTIONS ON PRODUCT USE
030619EBA
• The information contained herein is subject to change without notice.
• The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of
TOSHIBA or others.
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
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• TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced
and sold, under any law and regulations.
2003-08-04 57/57
相关型号：
TC59LM906AMG-45
IC 64M X 8 DDR DRAM, 0.6 ns, PBGA64, 13 X 17 MM, 1 MM PITCH, PLASTIC, BGA-64, Dynamic RAM
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