TC59WM815BFT-75_技术文档

TC59WM815/07/03BFT-70,-75,-80

TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC

4,194,304-WORDS × 4 BANKS × 16-BITS SYNCHRONOUS DYNAMIC RAM

8,388,608-WORDS × 4 BANKS × 8-BITS SYNCHRONOUS DYNAMIC RAM

16,777,216-WORDS × 4 BANKS × 4-BITS SYNCHRONOUS DYNAMIC RAM

DESCRIPTION

TC59WM815BFT is a CMOS Double Data Rate synchronous dynamic random access memory organized as

4,194,304 words × 4 banks × 16 bits and TC59WM807BFT is organized as 8,388,608 words × 4 banks × 8 bits and

the TC59WM803BFT is organized as 16,777,216 words × 4 banks × 4 bits. All inputs reference to the positive edge

of CLK (except for DQ, DM, and CKE). The timing reference point for the differential clock is when the CLK and

CLK signals cross during a transition. And Write and Read data are synchronized with both edges of DQS (Data

Strobe). These devices are ideal for main memory applications such as work-stations.

FEATURES

TC59WM815/07/03

PARAMETER

-70

7.5 ns

7 ns

-75

-80

10 ns

8 ns

CL = 2

8 ns

t

Clock Cycle Time (min)

CK

CL = 2.5

7.5 ns

45 ns

65 ns

110 mA

155 mA

3 mA

t

I

Active to Precharge Command Period (min)

Active to Ref/Active Command Period (min)

Operation Current (max) (Single bank)

Burst Operation Current (max)

45 ns

65 ns

110 mA

165 mA

3 mA

50 ns

70 ns

100 mA

150 mA

3 mA

RAS

RC

DD1

DD4

DD6

l

Self-Refresh Current (max)

•

Fully Synchronous Operation

•

Double Data Rate (DDR)

Data Input/Output and DM are synchronized with both edges of DQS (Write/Read Data Strobe).

Differential Clock inputs

•

All input signals reference to the positive edge of CLK (except for DQ, DM and CKE).

The timing reference point for the differential clock is when the CLK and CLK signals cross during a

transition.

Fast cycle time of 7 ns minimum

Clock: 143 MHz maximum

Data: 286 Mbps/pin maximum

Auto Refresh and Self Refresh

Precharged Power Down and Active Power Down

Write Data Mask

•

Write Latency = 1

Organization: x4

x8

8K row × 2K col. × 4 banks × 4 bits

8K row × 1K col. × 4 banks × 8 bits

8K row × 512 col. × 4 banks × 16 bits

x16

•

Output Strobe Signal: Bidirectional

Programmable CAS Latency and Burst Length: CAS Latency = 2, 2.5

Burst Length = 2, 4, 8

•

Interface:

Package:

SSTL-2

400 × 875 mil, 66 pin TSOP II, 0.65 mm Pin pitch (TSOPII66-P-400-0.65)

000707EBA2

• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general

can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the

buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and

to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or

damage to property.

In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the

most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling

Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..

• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal

equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are

neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or

failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy

control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control

instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document

shall be made at the customer’s own risk.

2001-03-19 1/44

TC59WM815/07/03BFT-70,-75,-80

PIN NAMES

PIN ASSIGNMENT (TOP VIEW)

A0~A12

Address

TC59WM803BFT

TC59WM807BFT

TC59WM815BFT

BS0, BS1

Bank Address

DQ0~DQ3

(x4)

1

66 V^SS

V^SS

V^SSQ

V^SS

V^SSQ

V^DD

NC²

V^DDQ

NC²

DQ0

V^SSQ

NC²

V^DDQ

NC²

DQ1

V^SSQ

NC²

NC¹

V^SSQ

NC²

NC¹

V^DD

DQ0

V^DDQ

NC²

DQ1

V^SSQ

NC²

DQ2

V^DDQ

NC²

DQ3

V^SSQ

NC²

NC¹

V^DDQ

NC²

NC¹

V^DD

DQ0

V^DDQ

DQ1

DQ2

V^SSQ

DQ3

DQ4

V^DDQ

DQ5

DQ6

V^SSQ

DQ7

NC¹

2

65 DQ15 DQ7 NC²

DQ0~DQ7

(x8)

3

64 V^SSQ

Data Input/Output

4

63 DQ14 NC²NC²

62 DQ13 DQ6 DQ3

5

6

61 V^DDQ

V^DDQ

DQ0~DQ15

(x16)

7

60 DQ12 NC²NC²

8

59 DQ11 DQ5 NC²

9

58 V^SSQ

V^SSQ

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

57 DQ10 NC²NC²

56 DQ9 DQ4 DQ2

CS

Chip Select

RAS

CAS

WE

Row Address Strobe

Column Address Strobe

Write Enable

55 V^DDQ

V^DDQ

54 DQ8 NC²NC²

53 NC¹NC¹NC¹

52 V^SSQ

V^SSQ

V^DDQ

LDQS

NC¹

51 UDQS DQS DQS

50 NC¹NC¹NC¹

49 V^REF

48 V^SS

V^REF

V^SS

V^REF

V^SS

DM

V^DD

NC¹

NC²

NC¹

NC²

NC¹

DM

(x4/x8)

47 UDM DM

LDM

46

Write Mask

CLK

CLK CLK

WE

CAS

RAS

CS

WE

CAS

RAS

CS

WE

CAS

RAS

CS

45 CLK CLK CLK

44 CKE CKE CKE

43 NC¹NC¹NC¹

42 A12 A12 A12

UDM/LDM

(x16)

NC¹

BS0

BS1

NC¹

BS0

BS1

NC¹

BS0

BS1

CLK, (/CLK)

Clock input

41 A11

40 A9

39 A8

38 A7

37 A6

36 A5

35 A4

34 V^SS

A11

A9

A8

A7

A6

A5

A4

V^SS

A11

A9

A8

A7

A6

A5

A4

V^SS

DQS

(x4/x8)

A10/AP A10/AP A10/AP

A0

A1

A0

A1

A0

A1

Write/Read Data Strobe

A2

U/LDQS

(x16)

A3

V^DD

CKE

Clock Enable

Power (+2.5 V)

Ground

V

DD

SS

Power (+2.5 V)

(for I/O buffer)

V

DDQ

SSQ

Ground

(for I/O buffer)

V

Reference Voltage

Not Connected

REF

1

2

NC , NC

000707EBA2

• The products described in this document are subject to the foreign exchange and foreign trade laws.

• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by

TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its

use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or

others.

• The information contained herein is subject to change without notice.

2001-03-19 2/44

TC59WM815/07/03BFT-70,-75,-80

BLOCK DIAGRAM

CLK

DLL CLOCK

CLK

BUFFER

CKE

CONTROL

SIGNAL

GENERATOR

CS

COMMAND

DECODER

RAS

CAS

WE

COLUMN DECODER

CELL ARRAY

BANK #0

CELL ARRAY

BANK #1

A10

MODE

SENSE AMPLIFIER

REGISTER

ADDRESS

BUFFER

A0~A9

A11

A12

Prefetch Register

DATA CONTROL

CIRCUIT

BS0

BS1

DQ0~DQn

DQ BUFFER

REFRESH

COUNTER

COLUMN

COUNTER

DQS

DM

COLUMN DECODER

CELL ARRAY

BANK #2

CELL ARRAY

BANK #3

SENSE AMPLIFIER

Note: The TC59WM803BFT configuration is 8192 × 2048 × 4 of cell array with the DQ pins numbered DQ~DQ3.

The TC59WM807BFT configuration is 8192 × 1024 × 8 of cell array with the DQ pins numbered DQ0~DQ7.

The TC59WM815BFT configuration is 8192 × 512 × 16 of cell array with the DQ pins numbered DQ0~DQ15.

2001-03-19 3/44

TC59WM815/07/03BFT-70,-75,-80

ABSOLUTE MAXIMUM RATINGS

SYMBOL

, V

PARAMETER

Input, Output Voltage

RATING

UNITS

NOTES

V

−0.3~V

+ 0.3

V

1

IN OUT

DDQ

, V

DD DDQ

Power Supply Voltage

Operating Temperature

Storage Temperature

−0.3~3.6

T

0~70

−55~150

260

°C

W

opr

stg

Soldering Temperature (10 s)

Power Dissipation

solder

P

1

D

I

Short Circuit Output Current

50

mA

OUT

RECOMMENDED DC OPERATING CONDITIONS (Ta = 0°~70°C)

SYMBOL

PARAMETER

Power Supply Voltage

MIN

TYP.

MAX

2.7

UNITS

NOTES

V

2.3

2.5

V

2

DD

Power Supply Voltage (for I/O buffer)

Input Reference Voltage

V

DD

DDQ

0.49 × V

0.50 × V

0.51 × V

DDQ

2, 3

2, 8

2

REF

DDQ

REF

Termination Voltage (system)

Input High Voltage (DC)

V

− 0.04

+ 0.15

V

+ 0.04

+ 0.3

TT

REF



V

IH (DC)

IL (DC)

ICK (DC)

DDQ

REF

Input Low Voltage (DC)

−0.3

V

− 0.15

+ 0.3

2

Differential Clock DC Input Voltage

−0.3

V

15

DDQ

Input Differential Voltage. CLK and

CLK inputs (DC)

V

0.36



V

+ 0.6

V

13, 15

ID (DC)

V

Input High Voltage (AC)

Input Low Voltage (AC)

V

+ 0.31

REF



V

2

IH (AC)

IL (AC)



V

− 0.31

+ 0.6

REF

Input Differential Voltage. CLK and

CLK inputs (AC)

V

0.7



V

13, 15

ID (AC)

DDQ

V

Differential AC Input Cross Point Voltage

Differential Clock AC Middle Point

V

/2 − 0.2



V

/2 + 0.2

V

12, 15

14, 15

X (AC)

DDQ

V

ISO (AC)

DDQ

Note: Undershoot limit: V (min) = −0.9 V with a pulsewidth ≤ 5 ns

IL

Overshoot limit:

V

(max) = V

+ 0.9 V with a pulsewidth ≤ 5 ns

IH

DDQ

V

and V

are levels to maintain the current logic state.

are levels to change to the new logic state.

IH (DC)

IH (AC)

IL (DC)

IL (AC)

2001-03-19 4/44

TC59WM815/07/03BFT-70,-75,-80

CAPACITANCE

(V = V

= 2.5 V 0.2 V, f = 1 MHz, Ta = 25°C, V

= V /2,

DDQ

DD

DDQ

OUT (DC)

V

= 0.2 V)

OUT (Peak to Peak)

SYMBOL

PARAMETER

MIN

MAX

DELTA (MAX)

UNIT

Input Capacitance (except for CLK pin)

Input Capacitance (CLK pin)

2.0

4.0



3.0

5.0

1.5

5.0

0.5

0.25

0.5



pF

C

IN1

C

DQ, DQS, DM Capacitance

I/O

1

NC pin Capacitance

NC

2

NC pin Capacitance

4.0



Note: These parameters are periodically sampled and not 100% tested.

2

The NC pins have additional capacitance for adjustment of the adjacent pin capacitance.

2

The NC pins have Power or Ground clamp.

2001-03-19 5/44

TC59WM815/07/03BFT-70,-75,-80

RECOMMENDED DC OPERATING CONDITIONS

MAX

SYMBOL

PARAMETER

UNITS

NOTES

-70

-75

-80

OPERATING CURRENT: One Bank

Active-Precharge; t

= t min; t = t min;

RC CK CK

RC

I

DQ, DM and DQS inputs changing twice per clock

cycle; Address and control inputs changing once

per clock cycle

110

100

7

DD0

OPERATING CURRENT: One Bank

Active-Read-Precharge; Burst = 2; t

= t min;

RC

I

110

2

110

2

100

2

7, 9

DD1

CL = 2.5; t = t min; I = 0 mA; Address

CK

OUT

and control inputs changing once per clock cycle

Precharge Power-Down Standby Current: All

Banks Idle; Power down mode; CKE ≤ V max;

DD2P

DD2F

IL

t

= t min; V = V

for DQ, DQS and DM

REF

CK

IN

Idle Floating Standby Current: CS ≥ V min; All

IH

Banks Idle; CKE ≥ V min; Address and other

IH

45

40

35

7

control inputs changing once per clock cycle; V

IN

= V

for DQ, DQS and DM

REF

Idle Standby Current: CS ≥ V min; All Banks

IH

Idle; CKE ≥ V min; t = t min; Address and

IH

CK

I

other control inputs changing once per clock

45

40

35

DD2N

cycle; V ≥ V min or V ≤ V max for DQ,

IN

IH

IN

IL

DQS and DM

Idle Quiet Standby Current: CS ≥ V min; All

IH

Banks Idle; CKE ≥ V min; t = t min;

IH

CK

I

40

20

35

20

30

20

DD2Q

DD3P

Address and other control inputs stable; V

≥

IN

V

for DQ, DQS and DM

REF

mA

Active Power-Down Standby Current: One Bank

Active; Power down mode; CKE ≤ V max; t

=

IL

CK

t

min

CK

Active Standby Current: CS ≥ V min; CKE ≥

IH

V

min; One Bank Active-Precharge; t

= t

IH

RC RAS

I

max; t = t min; DQ, DM and DQS inputs

changing twice per clock cycle; Address and other

control inputs changing once per clock cycle

70

65

60

7

DD3N

DD4R

DD4W

CK

Operating Current: Burst = 2; Reads; Continuous

burst; One Bank Active; Address and control

inputs changing once per clock cycle; CL = 2.5;

165

155

150

7, 9

t

= t min; I

CK

= 0 mA

CK

OUT

Operating Current: Burst = 2; Write; Continuous

burst; One Bank Active; Address and control

inputs changing once per clock cycle; CL = 2.5;

7

t

= t min; DQ, DM and DQS inputs changing

CK

twice per clock cycle

I

Auto Refresh Current: t

= t min

RFC

190

3

190

3

170

3

DD5

DD6

RC

Self Refresh Current: CKE ≤ 0.2 V

Random Read Current: 4 banks active read with

activate every 20 ns, Auto-Precharge read every

I

20 ns; Burst = 4; t

= 3 t ; I = 0 mA; DQ,

270

DD7

RCD

CK OUT

DM and DQS inputs changing twice per clock

cycle; Address changing once per clock cycle

2001-03-19 6/44

TC59WM815/07/03BFT-70,-75,-80

RANDOM READ CURRENT TIMING (I 7)

DD

t

= 10 ns

CK

t

RC

CK

t

RCD

READ

AP

READ

AP

READ

AP

Command ACT

ACT

AP

Bank0

Address

Bank3

Col c

Bank1

Row e

Bank0

Col d

Bank2

Row f

Bank1

Col e

Bank3

Row g

Bank2

Col f

Bank0

Row h

Row d

DQS

DQ

Qa

Qb

Qc

Qd

Qe

PARAMETER

SYMBOL

MIN

MAX

2

UNITS

NOTES

INPUT LEAKAGE CURRENT

(0 V ≤ V ≤ V All other pins not under test = 0 V)

I (L)

I

−2

µA

IN

DDQ

OUTPUT LEAKAGE CURRENT

(Output disabled, 0 V ≤ V ≤ V

I (L)

−5

5

µA

V

O

)

DDQ

OUT

OUTPUT HIGH VOLTAGE

(Under AC test load condition)

V

+ 0.76

TT



OH

OUTPUT LOW VOLTAGE

(Under AC test load condition)

V



V

− 0.76

TT

V

OL

Full Strength

Half Strength

OUTPUT MINIMUM SOURCE DC CURRENT

OUTPUT MINIMUM SINK DC CURRENT

OUTPUT MINIMUM SOURCE DC CURRENT

OUTPUT MINIMUM SINK DC CURRENT

I

−15.2

15.2



mA

4, 6

5

OH (DC)

I

OL (DC)

OH (DC)

I

−10.4

10.4

I

5

OL (DC)

2001-03-19 7/44

TC59WM815/07/03BFT-70,-75,-80

AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 10, 12)

-70

-75

-80

SYMBOL

PARAMETER

UNITS NOTES

MIN

MAX

MIN

MAX

MIN

MAX

t

Active to Ref/Active Command Period

Ref to Ref/Active Command Period

Active to Precharge Command Period

65

75

45

65

75

45

70

80

50

RC

t

RFC

RAS

100000

ns

Active to Read/Write Command Delay

Time

t

15

20

RCD

Active to Read with Auto Precharge

enable

t

RAP

CCD

Read/Write (a) to Read/Write (b)

Command Period

t

1

t

CK

t

Precharge to Active Command Period

20

15

30

20

15

30

20

15

35

RP

Active (a) to Active (b) Command

Period

RRD

WR

DAL

Write Recovery Time

Auto Precharge Write Recovery +

Precharge time

ns

CL = 2

CLK Cycle Time

CL = 2.5

7.5

7

15

8

15

10

8

15

t

CK

7.5

t

Data Access time from CLK, CLK

−0.75

0.75

−0.75

0.75

−0.8

0.8

AC

16

11

DQS output access time from CLK,

CLK

−0.75

0.75

0.5

−0.75

0.75

0.5

−0.8

0.8

0.6

DQSCK

DQSQ

Data Strobe Edge to Output Data

Edge Skew

t

CLK High level width

0.45

min

0.55

0.45

min

0.55

0.45

min

0.55

CH

CL

t

CK

CLK Low level width

CLK half period (minimum of actual

t

HP

QH

t

, t

CH CL

)

(t , t

CL CH

)

(t , t

CL CH

)

(t , t

CL CH

)

ns

t

HP

− 0.75

HP

DQ output data hold time from DQS

t

− 1.0

HP

− 0.75

t

DQS Read Preamble Time

DQS Read Postamble Time

DQ and DM Setup Time

DQ and DM Hold Time

0.9

1.1

0.6

0.9

1.1

0.6

0.9

1.1

0.6

RPRE

RPST

DS

t

11

CK

0.4

0.6

0.5

DH

ns

DQ and DM input pulse width (for

each input)

t

1.75

2

DIPW

t

DQS input high pulse width

0.35

0.2

0.35

0.2

0.35

0.2

DQSH

DQSL

DSS

DQS input low pulse width

t

11

CK

DQS falling edge to CLK setup time

DQS falling edge hold time from CLK

0.2

DSH

Clock to DQS Write Preamble Set-Up

Time

t

0

ns

WPRES

2001-03-19 8/44

TC59WM815/07/03BFT-70,-75,-80

-70

-75

-80

SYMBOL

PARAMETER

UNITS NOTES

MIN

MAX

MIN

MAX

MIN

MAX

t

DQS Write Preamble Time

DQS Write Postamble Time

0.25

0.4

0.25

0.4

0.25

0.4

WPRE

WPST

11

t

CK

Write command to first DQS latching

transition

t

0.75

1.25

0.25

0.75

1.25

0.25

0.75

1.25

0.25

DQSS

t

UDQS-LDQS Skew (x16)

Input Setup Time

−0.25

0.9

−0.25

0.9

−0.25

1.2

DSSK

IS

Input Hold Time

0.9

1.2

IH

Control & Address input pulse width

(for each input)

t

2.2

2.5

IPW

HZ

ns

Data-out High-impedance Time from

CLK, CLK

−0.75

0.75

−0.75

0.75

−0.8

0.8

Data-out Low-impedance Time from

CLK, CLK

t

−0.75

0.5

1

0.75

1.5

−0.75

0.5

1

0.75

1.5

−0.8

0.5

1

0.8

1.5

LZ

SSTL Input Transition

T (SS)

WTR

Internal Write to Read command

delay

t

CK

Exit Self Refresh to non-Read

comand

t

75

10

75

10

80

10

ns

XSNR

t

Exit Self Refresh to Read command

Refresh Time (8K)

t

CK

XSRD

REF

64

ms

Mode Register Set cycle time

15

16

ns

MRD

2001-03-19 9/44

TC59WM815/07/03BFT-70,-75,-80

AC TEST CONDITIONS

SYMBOL

PARAMETER

Input High voltage (AC)

VALUE

UNITS

NOTES

V

+ 0.31

V

IH

REF

Input Low voltage (AC)

− 0.31

IL

Input reference voltage

0.5 × V

1.0

V

REF

TT

DDQ

Termination voltage

V

Input signal peak to peak swing

Differential Clock Input Reference Voltage

Input Differential Voltage. CLK and CLK inputs (AC)

Input signal minimum slew rate

Output timing measurement reference voltage

V

SWING

Vr

V

X (AC)

V

1.5

1.0

V

ID (AC)

SLEW

V/ns

V

0.5 × V

DDQ

OTR

V

DDQ

V

IH min (AC)

REF

V

SWING (max)

V

R

TT

measurement point

Z = 50 Ω

V

IL max (AC)

= 50 Ω

T

Output

V

SS

30 pF

Output

∆T

SLEW = (V

∆T

− V

)/∆T

IL max (AC)

AC test load

IH min (AC)

2001-03-19 10/44

TC59WM815/07/03BFT-70,-75,-80

Note:

(1)

Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent

damage to the device.

(2)

(3)

(4)

(5)

(6)

All voltages are referenced to V , V

.

SS SSQ

Peak to peak AC noise on V

REF

may not exceed 2% V

.

REF (DC)

V

OH

V

OH

= 1.95 V, V

= 0.35 V

= 0.4 V

OL

= 1.9 V, V

OL

The values of I

is based on V

= 2.3 V and V = 1.19 V.

TT

OH (DC)

OL (DC)

DDQ

is based on V

= 2.3 V and V = 1.11 V.

TT

(7)

(8)

These parameters depend on the cycle rate and these values are measured at a cycle rate with the

minimum values of t and t

.

CK RC

V

TT

is not applied directly to the device. V

is a system supply for signal termination resistors, is

TT

expected to be set equal to V

and must track variations in the DC level of V

.

REF

(9)

These parameters depend on the output loading. Specified values are obtained with the output open.

(10)

Transition times are measured between V

signals have a fixed slope.

and V . Transition (rise and fall) of input

IL max (AC)

IH min (AC)

(11)

If the result of nominal calculation with regard to t

rounded up to the nearest decimal place.

contains more than one decimal place, the result is

CK

(i.e., t

DQSS

= 0.75 × t , t = 7.5 ns, 0.75 × 7.5 ns = 5.625 ns is rounded up to 5.6 ns.)

CK CK

(12)

(13)

(14)

(15)

V

is the differential clock cross point voltage where input timing measurement is referenced.

X

is magnitude of the difference between CLK input level and CLK input level.

ID

ISO

means {V

(CLK) + V

ICK

(CLK )}/2.

ICK

Refer to the figure below.

CLK

V

X

V

ID (AC)

ICK

V

X

CLK

V

ICK

V

SS

V

ID (AC)

0 V Differential

V

ISO

V

(min)

V

(max)

ISO

V

SS

(16)

t

AC

and t

depend on the clock jitter. These timing are measured at stable clock.

DQSCK

2001-03-19 11/44

TC59WM815/07/03BFT-70,-75,-80

POWER UP SEQUENCE

(1)

Apply power and attempt to CKE at a low state (≤ 0.2 V).

(all other inputs may be undefined)

1)

2)

Apply V

before or at the same time as V

.

DD

DDQ

before or at the same time as V and V .

REF

DDQ

TT

(2)

(3)

(4)

(5)

Start Clock and maintain stable condition for 200 µs (min).

After stable power and clock, apply NOP and take CKE high.

Issue EMRS-enable DLL and establish Output Driver Type.

Issue MRS-reset DLL and set device to idle with bit A8.

(an additional 200 cycles (min) of clock are required for DLL Lock)

Issue precharge command for all banks of the device.

Issue two or more Auto Refresh commands.

(6)

(7)

(8)

Issue MRS-Initialize device operation.

(If device operation mode is set at sequence 5, sequence 8 can be skipped.)

EMRS: Extended Mode Register Set

MRS: Mode Register Set

2001-03-19 12/44

TC59WM815/07/03BFT-70,-75,-80

TIMING DIAGRAMS

Command Input Timing

t

CK

t

CL

CK

CH

CLK

t

IS

IH

CS

RAS

CAS

WE

A0~A12

BS0, 1

Refer to the Command Truth Table.

Timing of the CLK, /CLK

t

CL

CH

/CLK

CLK

V

IH

V

IH (AC)

IL (AC)

IL

t

T

t

CK

/CLK

CLK

V

IH

IL

V

X

2001-03-19 13/44

TC59WM815/07/03BFT-70,-75,-80

Read Timing (Burst Length = 4)

t

CK

CH

CL

CLK

t

IH

IS

CMD

READ

t

IS

IH

ADD

Col

t

DQSCK

t

RPST

DQSCK

t

RPRE

CAS latency = 2

Hi-Z

DQS

Preamble

t

Postamble

QH

t

DQSQ

QH

DQSQ

Output

(Data)

QA0

QA1

QA2

QA3

t

AC

t

HZ

DQSCK

t

DQSCK

LZ

t

DQSCK

CAS latency = 2.5

t

RPST

RPRE

DQS

Preamble

t

Postamble

t

DQSQ

QH

t

QH

DQSQ

QA1

DQSQ

Output

(Data)

QA0

QA2

QA3

t

AC

t

HZ

LZ

Note: The correspondence of LDQS, UDQS to DQ. (TC59WM815BFT)

LDQS

UDQS

DQ0~7

DQ8~15

2001-03-19 14/44

TC59WM815/07/03BFT-70,-75,-80

Write Timing (Burst Length = 4)

t

CK

CH

CL

CLK

t

IH

IS

CMD

WRIT

t

DSS

IS

IH

DSH

DSS

DSH

ADD

Col

t

WPST

WPRES

DQSH

DQSL

DQSH

x4, x8 device

DQS

t

WPRE

Preamble

Postamble

t

DS

t

DH

t

DH

Input

(Data)

DA0

DA1

DA2

DA3

t

DSS

DSH

DSS

DSH

t

DQSS

t

WPST

WPRES

DQSH

DQSL

DQSH

x16 device

LDQS

t

WPRE

Preamble

Postamble

t

DS

t

DH

t

DH

DQ0~7

DA0

DA1

DA2

DA3

t

DQSS

t

DSSK

t

DSSK

t

DSH

DQSH

DSS

DSH

DSS

t

WPST

t

WPRE

t

WPRES

DQSL

DQSH

UDQS

Preamble

DA0

t

DS

Postamble

t

DS

t

DH

DQ8~15

DA1

DA2

DA3

t

DQSS

Note: x16 has 2DQS’s (UDQS for uper byte and LDQS for lower byte). Even if one of the

2 bytes is not used, both UDQS and LDQS must be toggled.

2001-03-19 15/44

TC59WM815/07/03BFT-70,-75,-80

DM, DATA MASK (TC59WM807/M803BFT)

CLK

/CLK

CMD

WRIT

DQS

DM

t

DH

DS

DS DH

t

DIPW

D3

DQ

D0

D1

t

Masked

DIPW

DM, DATA MASK (TC59WM815BFT)

CLK

/CLK

CMD

WRIT

LDQS

LDM

t

DS

DS DH

DH

t

DIPW

DQ0~

DQ7

D0

D1

D3

t

Masked

DIPW

UDQS

UDM

t

DH

DS

DS DH

t

DIPW

DQ8~

DQ15

D0

D2

D3

Masked

t

DIPW

2001-03-19 16/44

TC59WM815/07/03BFT-70,-75,-80

Mode Register Set (MRS) Timing

CLK

/CLK

t

MRD

CMD

ADD

MRS

NEXT CMD

Register Set data

Burst Length

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A2

0

A1

0

A0

0

Sequential

Interleaved

Burst Length

Addressing Mode

CAS Latency

Reserved

0

1

2

4

8

2

4

8

0

1

0

1

0

1

0

1

Reserved

1

0

1

A3

Addressing Mode

0

1

Sequential

Interleaved

“0”

Reserved

DLL Reset

A6

A5

A4

CAS Latency

Reserved

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

“0”

A10 “0”

A11 “0”

A12 “0”

BS0 “0”

BS1 “0”

Reserved

2.5

Reserved

Mode Register Set

or Extended Mode

Register Set

A8

DLL Reset

0

1

No

Yes

※ “Reserved” should stay “0” during

MRS cycle.

BS1

BS0

MRS or EMRS

0

1

0

1

0

1

Regular MRS cycle

Extended MRS cycle

Reserved

2001-03-19 17/44

TC59WM815/07/03BFT-70,-75,-80

Extended Mode Register Set (EMRS) Timing

CLK

/CLK

t

MRD

CMD

ADD

EMRS

NEXT CMD

Register Set data

A0

DLL Switch

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

DLL Switch

0

1

Enable

Disable

Output Driver

“0”

A1

Output Driver Size

0

1

Full Strength

Half Strength

BS1

BS0

MRS or EMRS

Reserved

0

1

0

1

0

1

Regular MRS cycle

Extended MRS cycle

Reserved

A10 “0”

A11 “0”

A12 “0”

BS0 “1”

BS1 “0”

Mode Register

Set or Extended

Mode Register

Set

※ “Reserved” should stay “0” during EMRS cycle.

2001-03-19 18/44

TC59WM815/07/03BFT-70,-75,-80

Auto Precharge Timing (Read cycle, CL = 2)

1).

t

(READA) ≥ t (min) − (BL/2) × t

RAS CK

RCD

t

RP

RAS

CLK

/CLK

BL = 2

CMD

ACT

READA

AP

ACT

DQS

DQ

Q0 Q1

BL = 4

CMD

DQS

DQ

ACT

READA

AP

ACT

Q0 Q1 Q2 Q3

BL = 8

CMD

DQS

DQ

ACT

READA

AP

ACT

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

Note: CL2 shown; same command operation timing with CL = 2.5

In this case, the internal precharge operation begin after BL/2 cycle from READA command.

represents the start of internal precharging.

AP

The Read with Auto precharge command cannot be interrupted by any other command.

2001-03-19 19/44

TC59WM815/07/03BFT-70,-75,-80

2).

t

(min) ≤ t

RCD

(READA) < t (min) − (BL/2) × t

RAS CK

RCD/RAP

t

RP

RAS

CLK

/CLK

BL = 2

CMD

ACT

READA

AP

ACT

t

RAP

t

RCD

DQS

DQ

Q0 Q1

BL = 4

CMD

ACT

READA

AP

t

RAP

t

RCD

DQS

DQ

Q0 Q1 Q2 Q3

BL = 8

CMD

ACT

READA

AP

t

RAP

t

RCD

DQS

DQ

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

Note: CL2 shown; same command operation timing with CL = 2.5

In this case, the internal precharge operation does not begin until after t

(min) has command.

RAS

represents the start of internal precharging.

AP

The Read with Auto Precharge command cannot be interrupted by any other command.

2001-03-19 20/44

TC59WM815/07/03BFT-70,-75,-80

Auto Precharge Timing (Write cycle)

CLK

/CLK

t

DAL

BL = 2

WRITA

AP

ACT

CMD

DQS

DQ

D0 D1

t

DAL

BL = 4

CMD

DQS

DQ

AP

ACT

D0 D1 D2 D3

t

DAL

BL = 8

CMD

DQS

DQ

AP

ACT

D0 D1 D2 D3 D4 D5 D6 D7

The Write with Auto Precharge command cannot be interrupted by any other command.

AP represents the start of internal precharg.

2001-03-19 21/44

TC59WM815/07/03BFT-70,-75,-80

Read Interrupted by Read (CL = 2, BL = 2, 4, 8)

CLK

/CLK

CMD

ADD

DQS

DQ

ACT

READ A

READ B

READ C

READ D

READ E

t

CCD

RCD

CCD

Row Address

Col. Add. A

Col. Add. B

Col. Add. C

Col. Add. D

Col. Add. E

QA0

QA1

QB0

QB1

QC0

Burst Read Stop (BL = 8)

CLK

/CLK

CMD

READ

BST

CAS Latency = 2

DQS

CAS Latency

Q0 Q1 Q2 Q3 Q4 Q5

DQ

CAS Latency = 2.5

DQS

CAS Latency

Q0 Q1 Q2 Q3 Q4 Q5

DQ

2001-03-19 22/44

TC59WM815/07/03BFT-70,-75,-80

Read Interrupted by Write & BST (BL = 8)

CLK

/CLK

CAS Latency = 2

CMD

DQS

DQ

READ

BST

WRIT

Q0 Q1 Q2 Q3 Q4 Q5

D0 D1 D2 D3 D4 D5 D6 D7

CAS Latency = 2.5

CMD

DQS

DQ

READ

BST

WRIT

Q0 Q1 Q2 Q3 Q4 Q5

D0 D1 D2 D3 D4 D5 D6 D7

Burst Read cycle must be terminated by BST Command to avoid I/O conflict.

Read Interrupted by Precharge (BL = 8)

CLK

/CLK

CMD

READ

PRE

CAS Latency = 2

DQS

CAS Latency

DQ

Q0 Q1 Q2 Q3 Q4 Q5

CAS Latency = 2.5

DQS

CAS Latency

DQ

Q0 Q1 Q2 Q3 Q4 Q5

2001-03-19 23/44

TC59WM815/07/03BFT-70,-75,-80

Write Interrupted by Write (BL = 2, 4, 8)

CLK

/CLK

CMD

ADD

DQS

DQ

ACT

WRIT A

WRIT B

WRIT C

WRIT D

WRIT E

t

CCD

RCD

CCD

Row Address

Col. Add. A Col. Add. B Col. Add. C Col. Add. D Col. Add. E

DA0 DA1 DB0 DB1 DC0 DC1 DD0 DD1

Write Interrupted by Read (CL = 2, BL = 8)

CLK

/CLK

CMD

DQS

DM

WRIT

READ

t

WTR

DQ

D0 D1 D2 D3 D4 D5 D6 D7

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

Data must be

masked by DM.

Data Masked by READ Command,

DQS input ignored.

2001-03-19 24/44

TC59WM815/07/03BFT-70,-75,-80

Write Interrupted by Read (CL = 2.5, BL = 4)

CLK

/CLK

CMD

DQS

DM

WRIT

READ

t

WTR

DQ

D0 D1 D2 D3

Q0 Q1 Q2 Q3

Data must be masked by DM.

Write Interrupted by Precharge (BL = 8)

CLK

/CLK

CMD

DQS

DM

WRIT

PRE

ACT

t

PR

WR

DQ

D0 D1 D2 D3 D4 D5 D6 D7

Data must be

masked by DM.

Data masked by PRE command,

DQS input ignored.

2001-03-19 25/44

TC59WM815/07/03BFT-70,-75,-80

2 Bank Interleave Read Operation (CL = 2, BL = 2) ※ t = 100 MHz

CK

CLK

/CLK

t

RC (b)

t

RC (a)

t

RRD

CMD

DQS

DQ

ACTa

ACTb

READAa

READAb

ACTa

ACTb

t

RCD (a)

t

RP (a)

RAS (a)

t

RCD (b)

t

RP (b)

RAS (b)

Preamble Postamble Preamble

Postamble

CL (a)

CL (b)

Q0a Q1a

Q0b Q1b

ACTa/b : Bank Act. CMD of bank a/b

READAa/b: Read with Auto Pre. CMD of bank a/b

APa/b : Auto Pre. of bank a/b

APa

APb

2 Bank Interleave Read Operation (CL = 2, BL = 4)

CLK

/CLK

t

RC (b)

t

RC (a)

t

RRD

CMD

DQS

DQ

ACTa

ACTb

READAa

READAb

ACTa

ACTb

t

RCD (a)

t

RP (a)

RAS (a)

t

RCD (b)

t

RP (b)

RAS (b)

Preamble

Postamble

CL (a)

CL (b)

Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b

ACTa/b

: Bank Act. CMD of bank a/b

READAa/b: Read with Auto Pre. CMD of bank a/b

APa/b : Auto Pre. of bank a/b

APa

APb

2001-03-19 26/44

TC59WM815/07/03BFT-70,-75,-80

4 Bank Interleave Read Operation (CL = 2, BL = 2)

CLK

/CLK

t

RC (a)

t

RRD

CMD

ACTa

ACTb

ACTc

READAa

ACTd

READAb

ACTa

READAc

t

RCD (a)

t

RP

RAS (a)

t

RCD (b)

t

RAS (b)

t

RCD (c)

t

RAS (c)

t

RCD (d)

t

RAS (d)

DQS

DQ

Preamble Postamble Preamble

CL (a) CL (b)

Q0a Q1a

Q0b Q1b

ACTa/b/c/d : Bank Act. CMD of bank a/b/c/d

READAa/b/c/d: Read with Auto Pre. CMD of bank a/b/c/d

APa/b/c/d : Auto Pre. of bank a/b/c/d

APa

APb

4 Bank Interleave Read Operation (CL = 2, BL = 4)

CLK

/CLK

t

RC (a)

t

RRD

CMD

ACTa

ACTb

READAa

ACTc

READAb

ACTd

READAc

ACTa

READAd

t

RCD (a)

t

RP (a)

RAS (a)

t

RCD (b)

t

RAS (b)

t

RCD (c)

t

RAS (c)

t

RCD (d)

t

RAS (d)

DQS

DQ

Preamble

CL (a)

CL (b)

CL (c)

Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b Q0c Q1c

ACTa/b/c/d : Bank Act. CMD of bank a/b/c/d

READAa/b/c/d: Read with Auto Pre. CMD of bank a/b/c/d

APa/b/c/d : Auto Pre. of bank a/b/c/d

APa

APb

APc

2001-03-19 27/44

TC59WM815/07/03BFT-70,-75,-80

Auto Refresh cycle

CLK

/CLK

CKE

CMD

PREA

NOP

AREF

NOP

AREF

NOP

CMD

t

RFC

RP

RFC

CKE has to be kept “High” level for Auto-Refresh cycle.

Active Power Down Mode Entry and Exit Timing

CLK

/CLK

t

IS

IH

IS

CK

IH

CKE

CMD

Entry

NOP

Exit

NOP

CMD

NOP

Precharged Power Down Mode Entry and Exit Timing

CLK

/CLK

t

IS

IH

IS

CK

IH

CKE

CMD

Entry

NOP

Exit

NOP

CMD

NOP

2001-03-19 28/44

TC59WM815/07/03BFT-70,-75,-80

Self Refresh Entry and Exit Timing

/CLK

CLK

t

CK

t

IS

IH

IS

IH

CKE

CMD

PREA

NOP

SELF

SELEX

NOP

CMD

t

RP

Entry

Exit

CLK

/CLK

t

XSNR

t

XSRD

CKE

CMD

SELF

Entry

SELEX

NOP

ACT

NOP

REANDOP NOP

Exit

2001-03-19 29/44

TC59WM815/07/03BFT-70,-75,-80

PIN FUNCTIONS

CLOCK INPUTS: CLK &

CLK

The CLK & CLK inputs are used as the reference for SDRAM operation. All inputs reference to the positive

edges of CLK (except for DQ, DM, and CKE).

The timing reference point for the differential clock is when the CLK and CLK signals cross during a

transition.

CLOCK ENABLE: CKE

The CKE input controls the entry to the Power Down or Self Refresh modes.

BANK SELECTS: BS0, BS1

The BS0, BS1 inputs are latched at the time of assertion of the operation commands and selects the bank to

be used for the operation.

BS0

BS1

0

1

0

1

0

1

Bank#0

Bank#1

Bank#2

Bank#3

ADDRESS INPUTS: A0~A12

The A0~A12 inputs are address to access the memory cell array. The row address bits are latched at the Bank

Active command and column address bits are latched on the Read or Write command. Also, the A0~A12 inputs

are used to set the data in the Mode register in a Mode Register Set Cycle.

Row Address

Column Address

TC59WM803BFT

TC59WM807BFT

TC59WM815BFT

A0~A12

A0~A9, A11 (A10 is used for auto precharge) (A12: Don’t care)

A0~A9 (A10 is used for auto precharge) (A11~A12: Don’t care)

A0~A8 (A10 is used for auto precharge) (A9, A11~A12: Don’t care)

CS

CHIP SELECT:

When CS is asserted “low”, it controls the latching of commands. No commands are latched as long as CS

in held “high”.

RAS

ROW ADDRESS STROBE:

The RAS input defines the operation commands in conjunction with the CAS and WE inputs, and is

latched at the cross points of CLK rising edge and CLK falling edge.

CAS

COLUMN ADDRESS STROBE:

The CAS input defines the operation commands in conjunction with the RAS and WE inputs, and is

latched at the cross points of CLK rising edge and CLK falling edge.

WRITE ENABLE:

WE

The WE input defines the operation commands in conjunction with the RAS and CAS inputs, and is

latched at the cross points of CLK rising edge and CLK falling edge.

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TC59WM815/07/03BFT-70,-75,-80

WRITE MASK: DM or LDM, UDM

When DM is asserted “high” in burst write, the input data is masked. DM is synchronized with both edges of

DQS. The LDM input can mask DQ0~DQ7 in a Write cycle and the UDM can mask DQ8~DQ15 in a Write cycle.

DATA INPUT/OUTPUT: DQ0~DQ15

The DQ0~DQ15 input and output data are synchronized with both edges of DQS or UDQS, LDQS.

REFERENCE VOLTAGE: V

REF

V

REF

is Reference voltage for inputs.

DATA STROBE: DQS or UDQS, LDQS

Both edges of DQS are used as the reference of data input/output.

DQS is Bi-directional signal. DQS is input signal in write operation and output signal in read operation.

POWER SUPPLY: V , V

DD DDQ

V

DD

are power supply and V are DQ power supply.

DDQ

GROUND: V , V

SS

SSQ

V

SS

are ground and V

are DQ ground.

SSQ

2001-03-19 31/44

TC59WM815/07/03BFT-70,-75,-80

Operation Mode

The following table shows the operation commands.

Simplified Truth Table (Note (1) and (2))

A12,

A10 A11,

A9~A0

BS0,

BS1

(4)

Symbol

Command

Device State CKE

(3)

CKE DM

CS

RAS

CAS

WE

n-1

n

ACT

Bank Active

Idle

H

X

V

X

V

L

V

X

V

L

H

L

H

L

(3)

PRE

Bank Precharge

Precharge All

Write

Any

X

PREA

WRIT

Any

H

L

(3)

Active

Idle

H

Write with Auto

Precharge

WRITA

READ

READA

MRS

H

X

V

H

L

V

L

H

L

H

L

Read

Read with Auto

Precharge

V

H

V

Mode Register Set

L, L

H, L

Extended Mode

Register Set

EMRS

Idle

L

NOP

BST

No Operation

Any

H

X

H

L

X

L

H

X

L

H

X

L

H

L

Burst Read Stop

Device Deselect

Auto Refresh

Active

Any

DSL

H

L

X

H

X

AREF

SELF

Idle

Self Refresh Entry

Idle

L

Idle

(Self

Refresh)

H

X

SELEX

PD

Self Refresh Exit

L

H

L

H

L

X

L

H

L

H

X

H

X

H

X

H

X

(5)

Power down mode entry Idle/Active

Any

(Power

Down)

H

PDEX

Power down mode exit

H

L

X

H

X

H

X

WDE

WDD

Data write enable

Data write disable

Active

H

X

L

X

H

Note: 1. V = Valid X = Don’t Care L = Low level H = High level

2. CKE signal is input level when commands are issued.

n

CKE signal is input level one clock cycle before the commands are issued.

n-1

3. These are state designated by the BS0, BS1 signals.

4. LDM, UDM (TC59WM815BFT)

5. Power Down Mode can not entry in the burst cycle.

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TC59WM815/07/03BFT-70,-75,-80

Function Truth Table (Note 1)

Current State CS RAS

CAS WE

Address

Command

DSL

NOP/BST

Action

Notes

Idle

H

L

H

L

H

L

H

L

X

H

L

X

H

L

X

H

L

X

Nop

BS, CA, A10 READ/READA

BS, CA, A10 WRIT/WRITA

ILLEGAL

Row activating

Nop

3

L

H

L

H

L

BS, RA

ACT

L

BS, A10

PRE/PREA

AREF/SELF

MRS/EMRS

DSL

L

H

L

X

Refresh or Self refresh

Mode register accessing

Nop

2

L

Op-Code

Row active

X

H

L

X

H

L

X

H

L

X

NOP/BST

Nop

BS, CA, A10 READ/READA

BS, CA, A10 WRIT/WRITA

Begin read: Determine AP

Begin write: Determine AP

ILLEGAL

4

3

5

L

H

L

H

L

BS, RA

ACT

L

BS, A10

PRE/PREA

AREF/SELF

MRS/EMRS

DSL

Precharge

L

H

L

X

ILLEGAL

L

Op-Code

ILLEGAL

Read

X

H

L

X

H

L

X

H

L

X

Continue burst to end

Burst stop

NOP

BST

H

L

BS, CA, A10 READ/READA

BS, CA, A10 WRIT/WRITA

Term burst, new read: Determine AP

ILLEGAL

6

3

L

H

L

H

L

BS, RA

ACT

ILLEGAL

L

BS, A10

PRE/PREA

AREF/SELF

MRS/EMRS

DSL

Term burst, precharging

ILLEGAL

L

H

L

X

L

Op-Code

ILLEGAL

Write

X

H

L

X

H

L

X

H

L

X

Continue burst to end

ILLEGAL

NOP

BST

H

L

BS, CA, A10 READ/READA

BS, CA, A10 WRIT/WRITA

Term burst, start read: Determine AP

Term burst, new write: Determine AP

ILLEGAL

6, 7

6

L

H

L

H

L

BS, RA

BS, A10

X

ACT

3

L

PRE/PREA

AREF/SELF

MRS/EMRS

Term burst. precharging

ILLEGAL

8

L

H

L

Op-Code

ILLEGAL

2001-03-19 33/44

TC59WM815/07/03BFT-70,-75,-80

Current State CS RAS

CAS WE

Address

Command

DSL

Action

Notes

Read with auto

precharge

H

L

H

L

H

L

H

L

X

H

L

X

H

L

X

H

L

X

Continue burst to end

ILLEGAL

NOP

BST

H

L

BS, CA, A10 READ/READA

BS, CA, A10 WRIT/WRITA

ILLEGAL

L

ILLEGAL

H

L

H

L

BS, RA

ACT

ILLEGAL

3

L

BS, A10

PRE/PREA

AREF/SELF

MRS/EMRS

DSL

ILLEGAL

L

H

L

X

ILLEGAL

L

Op-Code

ILLEGAL

Write with auto

precharge

X

H

L

X

H

L

X

H

L

X

Continue burst to end

ILLEGAL

NOP

BST

H

L

BS, CA, A10 READ/READA

BS, CA, A10 WRIT/WRITA

ILLEGAL

L

ILLEGAL

H

L

H

L

BS, RA

ACT

ILLEGAL

3

L

BS, A10

PRE/PREA

AREF/SELF

MRS/EMRS

DSL

ILLEGAL

L

H

L

X

ILLEGAL

L

Op-Code

ILLEGAL

Precharging

X

H

L

X

H

L

X

H

L

X

Nop → Idle after t

ILLEGAL

RP

NOP

BST

H

L

BS, CA, A10 READ/READA

BS, CA, A10 WRIT/WRITA

ILLEGAL

3

L

ILLEGAL

H

L

H

L

BS, RA

ACT

ILLEGAL

L

BS, A10

PRE/PREA

AREF/SELF

MRS/EMRS

DSL

Nop → Idle after t

ILLEGAL

RP

L

H

L

X

L

Op-Code

ILLEGAL

Row activating

X

H

L

X

H

L

X

H

L

X

Nop → Row active after t

ILLEGAL

RCD

NOP

RCD

BST

H

L

BS, CA, A10 READ/READA

BS, CA, A10 WRIT/WRITA

ILLEGAL

3

L

ILLEGAL

H

L

H

L

BS, RA

BS, A10

X

ACT

ILLEGAL

L

PRE/PREA

AREF/SELF

MRS/EMRS

ILLEGAL

L

H

L

ILLEGAL

L

Op-Code

ILLEGAL

2001-03-19 34/44

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Current State CS RAS

CAS WE

Address

Command

DSL

Action

Notes

Write

H

L

H

L

H

L

X

H

L

X

H

L

X

H

L

X

Nop → Row active after t

ILLEGAL

WR

recovering

NOP

BST

WR

H

L

BS, CA, A10 READ/READA

BS, CA, A10 WRIT/WRITA

ILLEGAL

3

L

ILLEGAL

H

L

H

L

BS, RA

ACT

ILLEGAL

L

BS, A10

PRE/PREA

AREF/SELF

MRS/EMRS

DSL

ILLEGAL

L

H

L

X

ILLEGAL

L

Op-Code

ILLEGAL

Write

recovering with

auto precharge

X

H

L

X

H

L

X

H

L

X

Nop → Enter precharge after t

ILLEGAL

WR

NOP

WR

BST

H

L

BS, CA, A10 READ/READA

BS, CA, A10 WRIT/WRITA

ILLEGAL

3

L

ILLEGAL

H

L

H

L

BS, RA

ACT

ILLEGAL

L

BS, A10

PRE/PREA

AREF/SELF

MRS/EMRS

DSL

ILLEGAL

L

H

L

X

ILLEGAL

L

Op-Code

ILLEGAL

Refreshing

X

H

L

X

H

L

X

H

L

X

Nop → Idle after t

ILLEGAL

RFC

NOP

BST

X

READ/WRIT

ACT/PRE/PREA

ILLEGAL

H

ILLEGAL

AREF/SELF/MRS/

EMRS

L

X

ILLEGAL

Mode register

accessing

H

L

X

H

X

H

L

X

H

L

X

DSL

Nop → Idle after t

ILLEGAL

MRD

NOP

BST

X

READ/WRIT

ACT/PRE/PREA/

ILLEGAL

L

X

AREF/SELF/MRS/ ILLEGAL

EMRS

Note: 1. All entries assume that CKE was active (High level) during the preceding clock cycle and the current clock cycle.

2. Illegal if any bank is not idle.

3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BS), depending on the

state of that bank.

4. Illegal if t

5. Illegal if t

is not satisfied.

RCD

RAS

6. Must satisfy burst interrupt condition.

7. Must avoid bus contention, bus turn around, and/or satisfy write recovery requirements.

8. Must mask preceding data which don’t satisfy t

.

WR

Remark: H = High level, L = Low level, X = High or Low level (Don’t care), V = Valid data

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TC59WM815/07/03BFT-70,-75,-80

Function Truth Table for CKE

CKE

Current State

CS

RAS

CAS

WE

Address

Action

Notes

n-1

H

L

n

X

Self refresh

X

H

L

X

H

L

X

H

L

X

H

X

H

X

INVALID

H

L

Exit Self Refresh → Idle after t

ILLEGAL

XSNR

L

X

H

X

H

L

ILLEGAL

L

X

H

L

X

H

X

H

L

Maintain Self Refresh

INVALID

Power Down

All banks idle

H

×

L

H

Exit Power Down → Idle after 1 clock cycle

L

H

L

X

H

L

X

H

L

Maintain power down mode

Refer to Function Truth Table

Enter Power down

Self Refresh

H

L

2

1

L

H

L

ILLEGAL

L

X

H

L

ILLEGAL

X

H

L

X

H

L

Power down

2

Row Active

H

L

Refer to Function Truth Table

Enter Power down

ILLEGAL

2

L

H

L

ILLEGAL

L

X

ILLEGAL

X

Power down

Any state other

than listed

above

H

X

Refer to Function Truth Table

Note: 1. Self refresh can enter only from the all banks idle state.

2. Power down can enter only from bank idle or row active state.

Remark: H = High level, L = Low level, X = High or Low level (Don’t care), V = Valid data

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TC59WM815/07/03BFT-70,-75,-80

SIMPLIFIED STATE DIAGRAM

SELF

REFRESH

SELF

SELEX

AREF

MRS/EMR

MODE

REGISTER

SET

AUTO

REFRESH

IDLE

ACT

PD

PDEX

POWER

DOWN

POWER

DOWN

PD

PDEX

WRIT

ROW

ACTIVE

BST

READ

WRITE

READ

WRITA

READA

WRITA

READA

PRE

WRITEA

READA

PRE

POWER

APPLIED

POWER

ON

PRE

CHARGE

PRE

Automatic Sequence

Command Sequence

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TC59WM815/07/03BFT-70,-75,-80

1. Command Function

1-1

Bank Activate command

( RAS = L, CAS = H, WE = H, BS0, BS1 = Bank, A0~A12 = Row Address)

The Bank Activate command activates the bank designated by the BS (Bank Address) signal.

Row addresses are latched on A0~A12 when this command is issued and the cell data is read out of the

sense amplifiers. The maximum time that each bank can be held in the active state is specified as t

(max). After this command is issued, Read or Write operation can be executed.

RAS

1-2

1-3

1-4

Bank Precharge command

( RAS = L, CAS = H, WE = L, BS0, BS1 = Bank, A10 = L, A0~A9, A11, A12 = Don’t care)

The Bank Precharge command precharges the bank designated by BS. The precharged bank is

switched from the active state to the idle state.

Precharge All command

( RAS = L, CAS = H, WE = L, BS0, BS1 = Don’t care, A10 = H, A0~A9, A11, A12 = Don’t care)

The Precharge All command precharges all banks simultaneously. Then all banks are switched to the

idle state.

Write command

( RAS = H, CAS = L, WE = L, BS0, BS1 = Bank, A10 = L, A0~A9, A11 = Column Address)

The Write command performs a Write operation to the bank designated by BS. The write data are

latched at both edges of DQS. The length of the write data (Burst Length) and column access sequence

(Addressing Mode) must be in the Mode Register at power-up prior to the Write operation.

1-5

1-6

Write with Auto Precharge command

( RAS = H, CAS = L, WE = L, BS0, BS1 = Bank, A10 = H, A0~A9, A11 = Column Address)

The Write with Auto Precharge command performs the Precharge operation automatically after the

Write operation. This command must not be interrupted by any other commands.

Read command

( RAS = H, CAS = L, WE = H, BS0, BS1 = Bank, A10 = L, A0~A9, A11 = Column Address)

The Read command performs a Read operation to the bank designated by BS. The read data are

synchronized with both edges of DQS. The length of read data (Burst Length), Addressing Mode and

CAS Latency (access time from CAS command in a clock cycle) must be programmed in the Mode

Register at power-up prior to the Read operation.

1-7

Read with Auto Precharge command

( RAS = H, CAS = L, WE = H, BS0, BS1 = Bank, A10 = H, A0~A9, A11 = Column Address)

The Read with Auto Precharge command automatically performs the Precharge operation after the

Read operation.

1) READA ≥ t

RAS

(min) − (BL/2) × t

CK

Internal precharge operation begin after BL/2 cycle from Read with Auto Precharge command.

2) t (min) ≤ READA < t (min) − (BL/2) × t

RCD RAS CK

Data can be read with shortest latency, but the internal precharge operation does not begin until

after t

RAS

(min) has completed.

This command muest not be interrupted by any other command.

1-8

Mode Register Set command

( RAS = L, CAS = L, WE = L, BS0 = L, BS1 = L, A0~A12 = Register Data)

The Mode Register Set command programs the values of CAS latency, Addressing Mode, Burst

Length and DLL reset in the Mode Register. The default values in the Mode Register after power-up are

undefined, therefore this command must be issued during the power-up sequence. Also, this command

can be issued while all banks are in the idle state. Refer to the table for specific codes.

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TC59WM815/07/03BFT-70,-75,-80

1-9

Extended Mode Register Set command

( RAS = L, CAS = L, WE = L, BS0 = H, BS1 = L, A0~A12 = Register Data)

The Extended Mode Register Set command can be implemented as needed for function extensions to

the standard (SDR-SDRAM). Currently the available mode in EMRS are DLL enable/disable and Output

Driver Size Control. The default value of the extended mode register is not defined, therefore this

command must be issued during the power-up sequence. Refer to the table for specific codes.

1-10 No-Operation command

( RAS = H, CAS = H, WE = H)

The No-Operation command simply performs no operation (same command as Device Deselect).

1-11 Burst Read stop command

( RAS = H, CAS = H, WE = L)

The Burst stop command is used to stop the burst operation. This command is only valid during a

Burst Read operation.

1-12 Device Deselect command

(CS = H)

The Device Deselect command disables the command decoder so that the RAS , CAS , WE and

Address inputs are ignored. This command is similar to the No-Operation command.

1-13 Auto Refresh command

( RAS = L, CAS = L, WE = H, CKE = H, BS0, BS1, A0~A12 = Don’t care)

The Auto Refresh command is used to refresh the row address provided by the internal refresh counter.

The Refresh operation must be performed 8192 times within 64 ms. The next command can be issued

after t

from the end of the Auto Refresh command. When the Auto Refresh command is issued, all

RFC

banks must be in the idle state.

1-14 Self Refresh Entry command

( RAS = L, CAS = L, WE = H, CKE = L, BS0, BS1, A0~A12 = Don’t care)

The Self Refresh Entry command is used to enter Self Refresh mode. While the device is in Self Refresh

mode, all input and output buffers (except the CKE buffer) are disabled and the Refresh operation is

automatically performed. Self Refresh mode is exited by taking CKE “high” (the Self Refresh Exit

command). During Self Refresh, DLL is disabled.

1-15 Self Refresh Exit command

(CKE = H, CS = H or CKE = H, RAS = H, CAS = H)

This command is used to exit from Self Refresh mode. Any subsequent commands can be issued after

t

(t for Read Command) from the end of this command.

XSNR XSRD

1-16 Data Write Enable/Disable command

(DM = L/H or LDM, UDM = L/H)

During a Write cycle, the DM or LDM, UDM signal functions as Data Mask and can control every word

of the input data. The LDM signal controls DQ0~DQ7 and UDM signal controls DQ8~DQ15.

2. Read Operation

Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read command is

issued after t

RCD

from the Bank Activate command, the data is read out sequentially, synchronized with both

edges of DQS (Burst Read operation). The initial read data becomes available after CAS latency from the

issuing of the Read command. The CAS latency must be set in the Mode Register at power-up. In addition, the

burst length of read data and Addressing Mode must be set in the Mode Register at power-up.

When the Precharge Operation is performed on a bank during a Burst read operation, the Burst operation is

terminated.

When the Read with Auto Precharge command is issued, the Prechage operation is performed automatically

after the Read cycle, then the bank is switched to the idle state. This command cannot be interrupted by any

other commands. Refer to the diagrams for Read operation.

2001-03-19 39/44

TC59WM815/07/03BFT-70,-75,-80

3. Write Operation

Issuing the Write command after t

from the Bank Activate command, the input data is latched

RCD

sequentially, synchronizing with both edges (rising & falling) of DQS after the Write command (Burst Write

operation). The burst length of the Write data (Burst Length) and Addressing Mode must be set in the Mode

Register at power-up.

When the Precharge operation is performed in a bank during a Burst Write operation, the Burst operation is

terminated.

When the Write with Auto Precharge command is issued, the Precharge operation is performed automatically

after the Write cycle, then the bank is switched to the idle state. The Write with Auto Precharge command

cannot be interrupted by any other command for the entire burst data duration. Refer to the diagrams for Write

operation.

4. Precharge

There are two commands which perform the Precharge operation (Bank Precharge and Precharge All). When

the Bank Precharge command is issued to the active bank, the bank is precharged and then switched to the idle

state. The Bank Precharge command can precharge one bank independently of the other bank and hold the

unprecharged bank in the active state. The maximum time each bank can be held in the active state is specifed

as t

RAS

(max). Therefore, each bank must be precharged within t (max) from the Bank Activate command.

RAS

The Precharge All command can be used to precharge all banks simultaneously. Even if banks are not in the

active state, the Precharge All command can still be issued. In this case, the Precharge operation is performed

only for the active bank and the precharged bank is then switched to the idle state.

5. Burst Termination

When the Precharge command is issued for a bank in a Burst cycle, the Burst operation is terminated. When

the Burst Read cycle is interrupted by the Precharge command, read operation is disabled after clock cycle of

(CAS latency) from the Precharge command. When the Burst Write cycle is interrupted by the Precharge

command, the input circuit is reset at the same clock cycle at which the Precharge command is issued. In this

case, the DM signal must be asserted “High” during t

WR

to prevent writing the invalid data to the cell array.

When the Burst Read Stop command is issued for the bank in a Burst Read cycle, the Burst Read operation is

terminated. The Burst Read Stop command is not supported during a write burst operation. Refer to the

diagrams for Burst termination.

6. Refresh Operation

Two types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh. By repeating

the Auto Refresh cycle, each bank in turn refreshed automatically. The Refresh operation must be performed

8192 times (rows) within 64 ms. The period between the Auto Refresh command and the next command is

specified by t

.

RFC

Self Refresh mode enter issuing the Self Refresh command (CKE asserted “low”) while all banks are in the

idle state. The device is in Self Refresh mode for as long as CKE held “low”. In the case of 8192 burst Auto

Refresh commands, 8192 burst Auto Refresh commands must be performed within 7.8 µs before entering and

after exiting the Self Refresh mode. In the case of distributed Auto Refresh commands, distributed Auto Refresh

commands must be issued every 7.8 µs and the last distributed Auto Refresh command must be performed

within 7.8 µs before entering the Self Refresh mode. After exiting from the Self Refresh mode, the refresh

operation must be performed within 7.8 µs. In Self Refresh mode, all input/output buffers are disabled, resulting

in lower power dissipation (except CKE buffer). Refer to the diagrams for Refresh operation.

7. Power Down Mode

Two types of Power Down Mode can be performed on the device: Active Standby Power Down Mode and

Precharge Standby Power Down Mode.

When the device enters the Power Down Mode, all input/output buffers and DLL are disabled resulting in

lower power dissipation (except CKE buffer).

Power Down Mode enter asserting CKE “low” while the device is not running a Burst cycle. Taking CKE

“high” can exit this mode. When CKE goes high, a No-operation command must be input at next CLK rising

edge. Refer to the diagrams for Power down mode.

2001-03-19 40/44

TC59WM815/07/03BFT-70,-75,-80

8. Mode Register Operation

The Mode Register is programmed by the Mode Register Set Command (MRS/EMRS) when all banks are in

the idle state. The data to be set in the Mode Register is transferred using the A0~A12 and BS0, BS1 address

inputs.

The Mode register designates the operation mode for the Read or Write cycle. This register is divided into five

fields; (1) Burst Length field to set the length of burst data (2) Addressing Mode selected bit to designate the

column access sequence in a Burst cycle (3) CAS Latency field to set the access time in clock cycle (4) DLL

Reset field to reset the DLL (5) Regular/Extended Mode Register field to select a type of MRS

(Regular/Extended MRS). EMRS cycles can be implemented the extended function (DLL Enable/Disable mode).

The initial value of the Mode Register (including EMRS) after power-up is undefined, therefore the Mode

Register Set command must be issued before proper operation.

(1) Burst Length field (A2~A0)

This field specifies the data length for column access using the A2~A0 pins and sets the Burst Length to

be 2, 4 and 8 words.

A2

A1

A0

Burst Length

0

1

0

1

X

0

1

0

1

X

Reserved

2 words

4 words

8 words

Reserved

(2) Addressing Mode Select (A3)

The Addressing Mode can be one of two modes; Interleave mode or Sequential Mode. When the A3 bit is

“0”, Sequential mode is selected. When the A3 bit is “1”, Interleave mode is selected. Both Addressing Mode

support burst length 2, 4 and 8 words.

A3

Addressing Mode

0

1

Sequential

Interleave

2001-03-19 41/44

TC59WM815/07/03BFT-70,-75,-80

•

Addressing sequence of Sequential mode

A column access is performed by incrementing the column address input to the device. The address is

varied by the Burst Length as the following.

CAS Latency = 2

CLK, /CLK

Command

DQS

Read

DQS

Data0 Data1 Data2 Data3 Data4 Data5 Data6 Data7

Addressing sequence for Sequential mode

DATA

Access Address

Burst Length

Data0

Data1

Data2

Data3

Data4

Data5

Data6

Data7

n

2 words (Address bits is A0)

not carried from A0~A1

n + 1

n + 2

n + 3

n + 4

n + 5

n + 6

n + 7

4 words (Address bits is A1, A0)

not carried from A1~A2

8 words (Address bits is A2, A1, A0)

not carried from A2~A3

•

Addressing sequence of Interleave mode

A column access is started from the inputed column address and is performed by interleaving the address

bits in the sequence shown as the following.

Addressing sequence for Interleave mode

DATA

Access Address

Burst Length

Data0

Data1

Data2

Data3

Data4

Data5

Data6

Data7

…A8 A7 A6 A5 A4 A3 A2 A1 A0

2 words

4 words

8 words

2001-03-19 42/44

TC59WM815/07/03BFT-70,-75,-80

(3) CAS Latency field (A6~A4)

This field specifies the number of clock cycles from the assertion of the Read command to the first data

read. The minimum values of CAS Latency depends on the frequency of CLK.

A6

A5

A4

CAS Latency

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reserved

2

Reserved

2.5

Reserved

(4) DLL Reset bit (A8)

This bit is used to reset DLL. When the A8 bit is “1”, DLL is reset.

(5) Mode Register/Extended Mode Register change bits (BS0, BS1)

These bits are used to select MRS/EMRS.

BS1

BS0

A12~A0

0

1

0

1

X

Regular MRS Cycle

Extended MRS Cycle

Reserved

(6) Extended Mode Resister field

1) DLL Switch field (A0)

This bit is used to select DLL enable or disable.

A0

DLL

0

1

Enable

Disable

2) Output Driver Size Control field (A1)

This bit is used to select Output Driver Size.

Both Full strength and Half strength are based on JEDEC Standard.

A1

Output Driver

0

1

Full strength

Half strength

(7) Reserved field

•

Test mode entry bit (A7)

This bit is used to enter Test mode and must be set to “0” for normal operation.

Reserved bits (A9, A10, A11, A12)

•

These bits are reserved for future operations. They must be set to “0” for normal operation.

2001-03-19 43/44

TC59WM815/07/03BFT-70,-75,-80

PACKAGE DIMENSIONS

Unit: mm

2001-03-19 44/44


型号：	TC59WM815BFT-75
厂家：	TOSHIBA
描述：	IC 16M X 16 DDR DRAM, 0.75 ns, PDSO66, 0.400 X 0.875 INCH, 0.65 MM PITCH, PLASTIC, TSOP2-66, Dynamic RAM 动态存储器双倍数据速率光电二极管内存集成电路
文件：	总44页 (文件大小：1742K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TC59WM815BFT-75 [TOSHIBA]

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