TC9446FG [TOSHIBA]

Audio Digital Processor for Decode of Dolby Digital (AC-3), MPEG2 Audio; 音频数字处理器的杜比数字（ AC- 3 ）， MPEG2音频解码的


型号：	TC9446FG
厂家：	TOSHIBA
描述：	Audio Digital Processor for Decode of Dolby Digital (AC-3), MPEG2 Audio 音频数字处理器的杜比数字（ AC- 3 ）， MPEG2音频解码的消费电路商用集成电路
文件：	总41页 (文件大小：563K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TC9446FG

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

TC9446FG

Audio Digital Processor for Decode of Dolby Digital (AC-3), MPEG2 Audio

TC9446FG is the various digital signal processor for decoding.

It contains the decode processing program which embraced

encoding signals, such as Dolby Digital (AC-3)/Pro Logic (Note 1),

MPEG2 audio and DTS (Note 2).

Decoding of Dolby Digital or MPEG2 audio is made with a

single chip. Moreover, an external memory can be connected to

the TC9446FG to decode DTS.

P-QFP100-1420-0.65Q

Weight: 1.57 g (typ.)

Features

•

Dolby digital (AC-3) or MPEG2 audio decode

Acceptable bit rate upto 640 kbps

•

Audio interface

4 output port, 2 input port (2 port of LRCK and BCK)

DIR (digital audio interface receiver) built-in

DIT (digital audio interface transmitter) built-in

DIR and DIT are available upto 96 kHz sampling of 2 channel

Operating clock: DLL oscillator upto 6th times for DSP clock

Instruction cycle: 20 ns/1 instruction at 50 MIPS operation

DSP

•

Processor: 24 bit × 24 bit + 51 bit multiplier and adder, 51 bit ALU

Data bus: 24 bit × 3

Data RAM: 12 k word

Coefficient ROM: 4 k word

Program ROM: 12 k word

Program RAM: 128 word

•

MCU interface: Serial interface or I²C bus interface

Others

It is possible to connect external RAM, 256 k or 1 M SRAM

External interruption input terminal

Flag input terminal: 4 inputs

General-purpose output port: 8 outputs (The ports can be used as interrupt outputs to MCU and logic control

outputs.)

incorrect operation detect

•

Operating Voltage: 3.0 ± 0.3 V

In CMOS structure and high-speed processing

100 pin flat package design

Note 1: “Dolby”, “Pro Logic”, and the double-D symbol are trademarks of Dolby Laboratories.

Note 2: “DTS” and “DTS Digital Surround” are registered trademarks of Digital Theater Systems, Inc.

Note 3: Since this product has a weak terminal in serge voltage, please advise handling it enough.

2005-09-28

TC9446FG

Pin Connection

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

100

PO0

PO1

PO2

PO3

PO4

PO5

PO6

PO7

LOCK

CKO

SSA

CKI

AMPO

AMPI

PLON

DDA

DDDL

LPFO

DLON

TC9446FG

PDO

TSTSUB2

TSTSUB1

FCONT

TSTSUB0

DLCKS

SCKO

SSDL

SCKI

SSX

TEST3

TEST2

TXO

DDX

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

2005-09-28

TC9446FG

Block Diagram

Program

Timing

DLL

SCKO

SCKI

ROM

4 k word × 3

Address operator

×2

DLON

LPFO

XRAM

YRAM

CROM

ERAM

X pointer

Y pointer

C pointer

RAM

128 word

4 k word

40 bit

Program

Instruction

control

X bus

Y bus

Instruction

Decoder

Bus switch

IRQ

X0, X1, X2

Y0, Y2, Y3

I bus

CE , OE , WR

Interrupt

External SRAM

interface

ADn

IOn

SDIn

Audio

Interface

SDOn

General output

port

LRCK/BCK

POn

FIn

MAC

ALU

DIR

Flag

DIT

LOCK

TXO

RST

MIMD

MICS

MILP

Timer

Round/Limiter

MIDIO

MICK

MCU interface

MIACK

2005-09-28

TC9446FG

Pin Functions

Symbol

No.

I/O

Description of Pin Functions

Remarks

Pull-up resistor,

Schmitt input

RST

Reset signal input terminal (L: reset, H: normal operation)

Pull-down resistor,

Schmitt input

MIMD

Mode select input for MCU interface (L: serial, H: I C bus)

MICS

MILP

Chip select input for MCU interface

Latch pulse input for MCU interface

Schmitt input

Schmitt input/

Open-drain output

MIDIO

I/O Data input and output for MCU interface

MICK

Clock input for MCU interface

Schmitt input

MIACK

Acknowledge output for MCU interface

Pull-up resistor,

Schmitt input

FI0

FI1

FI2

FI3

IRQ

Flag input 0

Flag input 1

Flag input 2

Flag input 3

Interruption input

Pull-up resistor,

Schmitt input

Pull-up resistor,

Schmitt input

Pull-up resistor,

Schmitt input

Pull-down resistor,

Schmitt input

⎯

Digital ground

LRCKA

BCKA

SDO0

SDO1

SDO2

SDO3

LRCKB

BCKB

SDI0

LR clock input-A for audio interface

Bit clock input-A for audio interface

Data output-0 for audio interface

Data output-1 for audio interface

Data output-2 for audio interface

Data output-3 for audio interface

LR clock input-B for audio interface

Bit clock input-B for audio interface

Data input-0 for audio interface

Data input-1 for audio interface

Digital power supply

Schmitt input

SDI1

⎯

LRCKOA

BCKOA

LR clock output-A for audio interface

Bit clock output-A for audio interface

Pull-up resistor,

Schmitt input

TEST0

TEST1

Test input-0 (L: test, H: normal operation)

Test input-1 (L: test, H: normal operation)

Pull-up resistor,

Schmitt input

LRCKOB

BCKOB

TXO

LR clock output-B for audio interface

Bit clock output-B for audio interface

SPDIF output

Pull-up resistor,

Schmitt input

TEST2

Test input-2 (L: test, H: normal operation)

Test input-3 (L: test, H: normal operation)

Pull-up resistor,

Schmitt input

TEST3

SPDIF input

Schmitt input

⎯

Digital ground

2005-09-28

TC9446FG

No.

Symbol

I/O

Description of Pin Functions

Remarks

Pull-up resistor,

Schmitt input

TSTSUB0

FCONT

Test sub input-0 (L: test, H: normal operation)

Frequency control output for VCO circuit

Test sub input-1 (L: test, H: normal operation)

Tri-state output

Pull-up resistor,

Schmitt input

TSTSUB1

Pull-up resistor,

Schmitt input

TSTSUB2

PDO

Test sub input-2 (L: test, H: normal operation)

Phase detect signal output

Analog power supply

Tri-state output

⎯

DDA

Pull-up resistor,

Schmitt input

PLON

Clock selection input (L: external clock, H: VCO clock)

AMPI

AMPO

CKI

Amplifier input for Low pass filter

Amplifier output for Low pass filter

External clock input

⎯

Analog ground

SSA

CKO

DIR clock output

LOCK

VCO lock output

Digital ground

Write signal output for external SRAM

Enable signal output for external SRAM

Chip enable signal output for external SRAM

Digital power supply

IO7

IO6

IO5

IO4

IO3

IO2

IO1

IO0

I/O Data I/O-7 for external SRAM

I/O Data I/O-6 for external SRAM

I/O Data I/O-5 for external SRAM

I/O Data I/O-4 for external SRAM

I/O Data I/O-3 for external SRAM

I/O Data I/O-2 for external SRAM

I/O Data I/O-1 for external SRAM

I/O Data I/O-0 for external SRAM

Pull-up resistor

⎯

Digital ground

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

Address output-0 for external SRAM

Address output-1 for external SRAM

Address output-2 for external SRAM

Address output-3 for external SRAM

Address output-4 for external SRAM

Address output-5 for external SRAM

Address output-6 for external SRAM

Address output-7 for external SRAM

Digital power supply

Pull-up resistor

AD8

AD9

Address output-8 for external SRAM

Address output-9 for external SRAM

Address output-10 for external SRAM

Address output-11 for external SRAM

Address output-12 for external SRAM

Address output-13 for external SRAM

Pull-up resistor

AD10

AD11

AD12

AD13

2005-09-28

TC9446FG

No.

Symbol

I/O

Description of Pin Functions

Address output-14 for external SRAM

Remarks

AD14

AD15

AD16

⎯

Pull-up resistor

Address output-15 for external SRAM

Address output-16 for external SRAM

Digital ground

Pull-up resistor

PO0

PO1

PO2

PO3

PO4

PO5

PO6

PO7

General output port-0

Pull-up resistor

General output port-1

General output port-2

General output port-3

General output port-4

General output port-5

General output port-6

General output port-7

Power supply for DLL circuit

Low pass filter output for DLL circuit

DDDL

LPFO

DLON

DLCKS

SCKO

DLCKS pin

DLON pin

“L”

DLL clock setting

Pull-up resistor

“L”

SCKI input (DLL = off)

“L”

“H”

^thtimes of XI clock

^rdtimes of XI clock

^thtimes of XI clock

“H”

“L”

“H”

⎯

ASP clock output

Ground for DLL circuit

External system clock input

Ground for crystal oscillator

Crystal oscillator output

Crystal oscillator input

Digital power supply

SSDL

SCKI

⎯

SSX

100

⎯

DDX

2005-09-28

TC9446FG

Description of Operation

1. Micro Controller Interface

The TC9446FG can perform transmission and reception of serial data with a micro controller in the

serial mode or the I C mode.

MIMD terminal performs a change in the serial mode and the I C mode, and input and output of data

are performed at MSB first.

The use terminal and the function in the serial mode and the I C mode are shown in Table 1.

The bit composition of a 24 bit command is shown in Table 2.

Note 4: This data sheet shows the general control method, refer to the program explanation data of an

attached sheet for a detailed command list, the control method, etc.

Table 1 Use Terminal and Function in the Serial Mode and the I C Mode

Transmission Mode

Input/Output

Serial Mode (MIMD = L)

Functions

I C Mode (MIMD = H)

Terminal

MICS

Functions

Input (3-5 V)

Chip selection signal input

Latch pulse signal input

Data input/output

Not used (fixed “L”)

MILP

MIDIO

MICK

Input (3-5 V)

Not used (fixed “L”)

Data input/output (SDA)

Clock input (SCL)

Input (3-5 V)/Output (3 V)

Input (3-5 V)

Clock input

Acknowledge signal output and out of

control detection output

MIACK

Output (3 V)

Out of control detection output

Note 5: MIDIO terminal needs pull-up resistance for the terminal exterior because of an open-drain output.

When using it by I C bus, pull-up resistance is required also for MICK terminal.

Note 6: The addresses of an I C bus are write-in address 3Ah and read-out address 3Bh.

Table 2 Bit Composition of 24 Bit Command

Bit Assign

23-8

Functions

Remarks

Refer to the command list of the program explanation

data sheet

16 bit address

Starting the incorrect operation detection output

Starting the program RAM boot

Setting the soft reset

Starting the incorrect operation detection output by “1”

Starting the program RAM boot by “1”

Setting the soft reset ON by “1”

Setting the read by “1”

“0h”; a word

Setting the Read/Write (R/W)

3-0

Setting the number of words for transmission

↓

“Fh”; 16 words

2005-09-28

TC9446FG

2. Data Transmission Format

2-1. Serial Mode Setting

2-1-1. Data Transmission Format in the Serial Mode

A data transmission format in the serial mode is shown in Figure 1.

After the data transmission at the time of the serial mode sets MICS signal to “L”, fundamentally, it checks that MIACK signal is “L” and transmits a 24 bit

command at MSB first.

However, it cannot transmit at the time of MIACK signal = “H”.

Then, the word set up by the 24 bit command which the Read or Write (R/W) of 24 bit data of a number (1-16 word) is performed, and, finally, MICS signal is

set to “H”.

However, since there is a term when MIACK signal after transmission is set to “H” in a 24 bit command, at the time of Read, command transmission back also

needs to check that MIACK signal is set to “L”.

Transmission data (1 to 16 words)

MICS

MIACK

MILP

MICK

MIDIO

COMMAND (24 bit)

DATA-1 (24 bit)

DATA-16 (24 bit)

Figure 1 Serial Mode Data Transmission Format

2-1-2. Data Transmission Method in the Serial Transmission Mode

1) Program boot and a program start

As for TC9446FG, RAM is assigned 128 words of program address 0000h-007Fh, and the interruption vector address is become 0000h-0009h.

Therefore, in order to operate TC9446FG, it needs to interrupt and a program needs to be booted to a vector address. In addition, a program load needs to be

continuously performed to an interruption vector address to store a program in 000Ah-007Fh.

In order to perform program boot, the program RAM boot start bit and the soft reset bit in the 24 bit command transmitted after reset need to be set to “H”.

(command = 000060h) And, after command transmission, program data (40 bit) is divided into 20 bit of a higher rank/low rank, and it transmits by the low-rank

stuffing of 24 bit data in the order of a higher rank (20 bit) and a low rank (20 bit).

Since a write-in address is made automatic (+1) from 0000h, if it transmits the required number of words and MICS is set to “H”, program boot will complete

it.

In addition, the write-in address of program boot always starts from 0000h.

A start of a program carries out and transmits the soft reset bit in a 24 bit command to “L”, and is performed by setting MICS to “H”, without performing

data transmission.

The procedure of program boot and a program start is shown in Figure 2.

2005-09-28

TC9446FG

Reset of Hardware

(or reset of software by command)

MICS = “L”

Checking of MIACK = “L”

(waiting for becoming to MIACK = “L” at the MIACK = “H”)

Setting “H” for bit of program boot

and soft reset bit.

Write of the 24 bit command

(program boot = 000060h)

Write of program data

(higher rank 20 bit at address 0000h)

Program data is 20 bit lower assign.

It is possible to do the program boot for address

of 007Fh maximum.

Write of program data

(low rank 20 bit at address 0000h)

Write of program data

(higher rank 20 bit at address 0007h)

Write of program data

(low rank 20 bit at address 0007h)

MICS = “H”

MICS = “L”

It finished the program boot.

Checking of MIACK = “L”

(waiting for becoming to MIACK = “L” at the MIACK = “H”)

Write of the 24 bit command

(soft reset off = 000000h)

MICS = “H”

Program starting

Figure 2 Procedure of Program Boot and Program Start

2005-09-28

TC9446FG

Write of 24 bit data

The number of words of data written in while data required for the 16 bit address in a 24 bit

command is set up and R/W bit is set to “L”, when writing in data from a MCU to TC9446FG during

program operation is set up.

And, 24 bit data of the number required after transmitting a 24 bit command of words is written in.

The procedure of the write of 24 bit data is shown in Figure 3.

MICS = “L”

Checking of MIACK = “L”

(at the MIACK = “L”, waiting for becoming to MIACK = “L”)

Setting of 16 bit address and umber of the

transmission word.

Write of 24 bit command

(write of data = xxxx0xh)

Write of 24 bit data (1)

Write of 24 bit data (2)

Write of 24 bit data (n)

It is possible to write the 24 bit data until

16 word maximum.

MICS = “H”

It finished to write the data

Figure 3 Procedure of Write of 24 Bit Data

2005-09-28

TC9446FG

Read-out of 24 bit data

The number of words of data read while data required for the 16 bit address in a 24 bit command is

set up and R/W bit is set to “H”, when reading data of TC9446FG from a MCU during program

operation is set up.

And, after transmitting a 24 bit command, MIACK = “L” is checked and 24 bit data of the required

number of words is read.

MIACK = “L” is checked after command transmission for waiting to set data which should be read

to data buffer. The procedure of read-out of 24 bit data is shown in Figure 4.

MICS = “L”

Checking of MIACK = “L”

(waiting for becoming to MIACK = “L” at the MIACK = “H”)

A 16 bit address and a transmission word

number are set up.

Write of 24 bit command

(read of data = xxxx1xh)

Checking of MIACK = “L”

(waiting for becoming to MIACK = “L” at the MIACK = “H”)

Read of 24 bit data (1)

Read of 24 bit data (2)

Read of 24 bit data (n)

It is possible to read out the 24 bit data

until 16 word maximum.

MICS = “H”

It finished to read of the data

Figure 4 Procedure of Read-Out of 24 Bit Data

2005-09-28

TC9446FG

ON/OFF of soft reset

The case where a program is started after program boot, and in restarting a program, it performs

ON/OFF of soft reset.

ON/OFF of soft reset are performed by carrying out and transmitting the bit of the soft reset in a 24

bit command to “H” (ON) and “L” (OFF).

Since data with which ON/OFF of soft reset follow a command is not required, it is made into

MICS = “H” after 24 bit command transmission.

In addition, in order to return from a incorrect operation state, when turning ON soft reset, a 24 bit

command can be transmitted irrespective of the state of MIACK signal.

The procedure of ON/OFF of soft reset is shown in Figure 5.

MICS = “L”

It is possible to transmit the command

Checking of MIACK = “L”

(waiting for becoming to MIACK = “L” at the MIACK = “H”)

data of soft reset ON at MIACK = “H”.

Soft reset ON: Bit = “1”.

Soft reset OFF: Bit = “0”.

Transmission of 24 bit command

(soft reset ON/OFF = 0000x0h)

MICS = “H”

Soft reset ON/OFF

Figure 5 Procedure of ON/OFF of Soft Reset

2005-09-28

TC9446FG

Incorrect operation detection

Incorrect operation detection of the internal program of TC9446FG can be made to perform by

setting the incorrect operation detection start bit in a 24 bit command to “H”. As for this incorrect

operation detection start bit, the reversal output only of the case of MICS terminal = “H” is carried

out from MIACK terminal.

And, since this incorrect operation detection start bit is periodically cleared by “L” when an internal

program is operating normally, MIACK terminal at the time of MICS terminal = “H” is set to “H”

from “L”.

However, since it will stop being cleared if an internal program becomes a incorrect operation state,

as for MIACK terminal at the time of MICS terminal = “H”, the state of “L” will continue.

Thus incorrect operation detection of a program is attained by supervising MIACK terminal at the

time of MICS terminal = “H”. Moreover, although it checks that MIACK terminal is “L” after setting

MICS terminal to “L” in case a MCU starts access to TC9446FG, MCU can judge that an internal

program is a incorrect operation state, when the state of MIACK = “H” continues.

In addition, when a incorrect operation state is detected, it can return from a incorrect operation

state by initializing by transmitting the soft reset command which the reset terminal was set to “L” or

was mentioned above.

The procedure of incorrect operation detection is shown in Figure 6.

MICS = “L”

When not set to “L” with “H”, it is the state

of incorrect operation.

Checking of MIACK = “L”

(waiting for becoming to MIACK = “L” at the MIACK = “H”)

It starts the incorrect operation detection

by “1”.

Transmission of 24 bit command

(starting the incorrect operation detection = 000080h)

MICS = “H”

MIACK = “L”

MIACK = “L” is continue at incorrect

operation, as detection bit isn’t cleared.

Program makes to clear the incorrect operation

detection bit

MIACK = “H”

Figure 6 Procedure of Incorrect Operation Detection

2005-09-28

TC9446FG

2-2. I C Mode Setting

2-2-1. Data Transmission Format in I C Mode

The foundations of a data transmission format in the I C mode are shown in Figure 7.

Fundamentally, the data transmission at the time of the I C mode checks that ACK bit is set to “L”, after making I C Address (write = 3Ah) to transmission.

However, at the time of “H”, ACK bit performs Start Condition again, without performing STOP Condition, and transmits I C Address (3Ah). I C Transmit 24

bit command after Address transmission.

And, at the time of data Write of TC9446FG, Write of 24 bit data of the number (1-16 word) of words set up by 24 bit command is performed from a MCU, and,

finally, END Condition is transmitted.

Moreover, it checks that transmit I C Address (read = 3Bh) from TC9446FG at the time of Read to a MCU, without performing END Condition after 24 bit

command transmission, and ACK bit is set to “L”.

However, at the time of “H”, ACK bit performs Start Condition again, without performing STOP Condition, and transmits I C Address (3Bh).

The word set up by 24 bit command after checking that ACK bit is “L”. Although Read of 24 bit data of a number (1-16 word) is performed, as for the inside of

Read, a MCU needs to set ACK bit to “L” for every 8-bit Read data.

And, only ACK bit added to the last 8 bits is set to “H”, and STOP Condition is transmitted.

Moreover, at the time of transmission of only a 24 bit command which does not perform R/W of data, END Condition is transmitted after 24 bit command

transmission.

In addition, in TC9446FG, polling of the access demand from a MCU is carried out every about 6 ms at the time of decode processing. Therefore, R/W of data

from a MCU need to be performed at the interval of 6 ms or more.

At the time of Write-in, Read-out and a command only shows the transmission format to Figure 7 to Figure 10.

SDA

SCL

I²C Address (3Ah)

I²C Address

R/W ACK

DATA Hi (8 bit)

ACK

DATA Mid (8 bit)

ACK

DATA Lo (8 bit)

ACK

24 bit DATA (1 word to 16 word)

START Condition

STOP Condition

Figure 7 Data Transmission Format in the I C Mode

2005-09-28

TC9446FG

(3Ah)

24 bit COMMAND

COMMAND (M)

24 bit Write DATA (1 word to 16 word)

DATA (M)

START

I²C Address W A COMMAND (H)

COMMAND (L)

DATA (H)

DATA (L)

STOP

All of ACK are returned to MCU from TC9446FG

The interval of 6 ms or more is

required until next START.

Figure 8 Format at Time of Write

(3Ah)

24 bit COMMAND

COMMAND (M)

These of ACK are returned to MCU from TC9446FG

(3Bh)

I²C Add.

24 bit Read DATA (1 word to 16 word)

RD (H) RD (M) RD(L)

START

I²C Add.

W A COMMAND (H)

COMMAND (L)

START

STOP

These of ACK are retarned to TC9446FG from MCU

The interval of 6 ms or

more is required

This ACK is MCU

set up at “H”.

Figure 9 Format at Time of Read

(3Ah)

I²C Address W A COMMAND (H)

All of ACK are returned to MCU from TC9446FG.

24 bit COMMAND

START

COMMAND (M)

COMMAND (L)

STOP

Figure 10 Format Only a Command at the Time of Transmission.

2005-09-28

TC9446FG

2-2-2. The Data Transmission Method in I C Mode

1) Program boot and a program start

As for TC9446FG, RAM is assigned 128 words of program address 0000h-007Fh, and the

interruption vector address is become 0000h-0009h.

Therefore, in order to operate TC9446FG, it needs to interrupt at least and a program needs to be

booted to a vector address.

In addition, a program load needs to be continuously performed to an interruption vector address to

store a program in 000Ah-007Fh.

In order to perform program boot, the program RAM boot start bit and the soft reset bit in the 24

bit command transmitted after reset need to be set to “H”. (command = 000060h)

And after command transmission, program data (40 bits) is divided into 20 bits of a higher rank/low

rank, and it transmits by the low-rank stuffing of 24 bit data in the order of a higher rank (20 bits)

and a low rank (20 bits).

Since a write-in address is made automatic (+1) from 0000h, if it transmits the required number of

words and END Condition is transmitted, program boot will complete it.

In addition, the write-in address of program boot always starts from 0000h.

A start of a program is performed by carrying out and transmitting the soft reset bit in a 24 bit

command to “L”, and transmitting END Condition, without performing data transmission.

The procedure of program boot and a program start is shown in Figure 11.

2005-09-28

TC9446FG

Reset of hardware

(or reset of software by command)

START Condition

At the time of ACK = “H”, it resumes from

START Condition.

Transmission of I C Address (3Ah)

Checking of ACK bit = “L”

The bit of program boot and soft reset is

set to “H”.

Write of 24 bit command

(program boot = 000060h)

Write of program data

(higher rank 20 bit at address 0000h)

Program data is 20 bits of low-rank

stuffing.

Boot is possible to the address of a

maximum of 007Fh.

Write of program data

(low rank 20 bit at address 0000h)

Write of program data

(higher rank 20 bit at address 0007h)

Write of program data

(low rank 20 bit at address 0007h)

START Condition

STOP Condition

The completion of program boot.

At the time of ACK = “H”, it resumes from

START Condition.

Transmission of I C Address (3Ah)

Checking of ACK bit = “L”

Write of 24 bit command

(soft reset OFF = 000000h)

STOP Condition

Program starting

Figure 11 Procedure of Program Boot and Program Start

2005-09-28

TC9446FG

Write of 24 bit data

The number of words of data written in while data required for the 16 bit address in a 24 bit

command is set up and R/W bit is set to “L”, when writing in data from a MCU to TC9446FG during

program operation is set up.

And, 24 bit data of the number required after transmitting a 24 bit command of words is written in.

In addition, completion of internal taking in of write-in data requires the time of about 6 ms of the

maximum from END Condition.

Therefore, access of a next MCU needs to keep the term for about 6 ms after END Condition

transmission.

The procedure of the write of 24 bit data is shown in Figure 12.

START Condition

At the time of ACK = “H”, it resumes from

START Condition.

Transmission of I C Address (3Ah)

Checking of ACK bit = “L”

A 16 bit address and a transmission word

number are set up.

Write of 24 bit command

(write of data = xxxx0xh)

Write of 24 bit data (1)

Write of 24 bit data (2)

Write of 24 bit data (n)

STOP Condition

It is possible to Write in the 24 bit data

until 16 word maximum.

It is data write-in completion after STOP Condition

transmission and within about 6 ms term.

Figure 12 Procedure of Write of 24 Bit Data

2005-09-28

TC9446FG

Read of 24 bit data

The number of words of data read while data required for the 16 bit address in a 24 bit command is

set up and R/W bit is set to “L”, when reading data of TC9446FG from a MCU during program

operation is set up.

And, after transmitting a 24 bit command, I C Address is set to 3Bh after the term progress for

about 6 ms, and it transmits with START Condition. Then, 24 bit data of the required number of

words is read.

Although ACK bit of a data Read term needs to give “L” from a MCU, it needs to set only ACK bit

added to last 8 bit data to “H”.

This is because the Basra in of SDA where TC9446FG are the master is opened wide and a MCU

can transmit STOP Condition.

In addition, the term progress for about 6 ms after command transmission is for waiting to set data

which should be read to data buffer of TC9446FG.

The procedure of read-out of 24 bit data is shown in Figure 13.

START Condition

At the time of ACK = “H”, it resumes from

START Condition.

Transmission of I C Address (3Ah)

Checking of ACK bit = “L”

A 16 bit address and a transmission word

number are set up.

Transmission of 24 bit command

(read of data = xxxx1xh)

A term is stood by for about 6 ms.

START Condition

At the time of ACK = “H”, it resumes from

START Condition.

Transmission of I C Address (3Bh)

Checking of ACK bit = “L”

Read of 24 bit data (1)

Read of 24 bit data (2)

Read of 24 bit data (n)

It is possible to Write in the 24 bit data

until 16 word maximum.

The last ACK bit is set to “H”.

STOP Condition

It finished to read of the data

Figure 13 Procedure of Read-Out of 24 Bit Data

2005-09-28

TC9446FG

ON/OFF of soft reset

The case where a program is started after program boot, and in restarting a program, it performs

ON/OFF of soft reset. ON/OFF of soft reset are performed by carrying out and transmitting the bit of

the soft reset in a 24 bit command to “H” (ON) and “L” (OFF).

Since data with which ON/OFF of soft reset follows a command is not required, STOP Condition is

transmitted after 24 bit command transmission.

In addition, in order to return from a incorrect operation state, when turning ON soft reset, it is

also possible to transmit a 24 bit command irrespective of the state of ACK bit.

The procedure of ON/OFF of soft reset is shown in Figure 14.

START Condition

At the time of ACK = “H”, it resumes from

START Condition. However, it is possible

to disregard and carry out command

transmission of the ACK bit at the time of

a reckless run.

Transmission of I C Address (3Ah)

Checking of ACK bit = “L”

Soft reset ON: Bit = “1”.

Soft reset OFF: Bit = “0”.

Transmission of 24 bit command

(soft reset ON/OFF = 0000x0h)

STOP Condition

Soft reset ON/OFF

Figure 14 Procedure of ON/OFF of Soft Reset

Incorrect operation detection

Incorrect operation detection of the internal program of TC9446FG is judged by the existence of the

reaction to the access demand from a MCU. Therefore, R/W of data need to be performed from a MCU

to TC9446FG at the interval of about 6 ms or more.

ACK bit is set to “L”, when the following access demand opens the interval of about 6 ms or more

and is performed, since R/W of data were performed between about 6 ms back to the access demand

from a MCU when TC9446FG were operating normally.

However, if TC9446FG become a incorrect operation state, even if it is going to stop receiving the

access demand from a MCU, it is going to open the interval of about 6 ms or more and MCU is going

to make it access again, it will become a state ACK bit is “H” continued.

A MCU can perform incorrect operation detection by seeing this ACK bit.

That is, since TC9446FG are in a incorrect operation state when it is “H” fixation, even if ACK bit

passes about 6 ms or more, ACK bit is disregarded, soft reset is turned ON, and each setup of

TC9446FG is performed again.

2005-09-28

TC9446FG

3. Setting Procedure Until it Starts Decode Program Operation

Setting procedure until it starts operation of the decode program built in TC9446FG is shown below.

First, 10 words program data is transmitted in the program boot mode after release of the power-on reset

at the time of a power-supply injection.

However, when there is a program required for others, program data of a maximum of 128 words can be

transmitted.

And, if the command of soft reset-off is transmitted, a program will begin to operate and decode will be

started by transmitting addresses of the write-in command shown in an attached sheet (the program

explanation data) after that 9 words of 0000h-0008h.

Procedure until it starts operation of a decode program to Figure 15 is shown.

Power ON reset

Program boot

Soft reset OFF

Write-in command transmission.

(9 word of 0000h to 0008h)

(9 word of continuing from 0000h are transmitted.)

Starting of decode

Figure 15 Procedure to Decode Program Operation Start

Note 7: Internal RAM is cleared, in order to muting for output, after transmitting a setup of command 0003h “decode

off” in the case of AC-3 decoder program. Please transmit following data after checking that ACK is set to

“L” from “H”, since such a case has the time for about 23 ms (maximum) in this processing. If processing of

the internal RAM clearance by the “decode off” command is completed, it will return at the waiting time for 1

or less ms.

In addition, according to the kind of decode program, please transmit following data after checking that ACK

is set to “L” from “H”, since the waiting time which the data transmission at the time of decode on/off takes

differs.

2005-09-28

TC9446FG

4. Read/Write of Command

Write and a read of command change with decode programs built in.

For details, please refer to program explanation data.

5. Digital Audio Interface (DIR/DIT)

A setup of DIR/DIT

The digital reception recovery (DIR) for the audio interfaces and the abnormal-conditions

transmission (DIT) based on CEI “IEC958 standard” and the JEITA “CP-1201 standard” are built in.

DIR corresponds to the input of 96 kHz sampling (2 channels). Please refer to program explanation

data about the various contents of a setting of DIR/DIT.

VCO oscillation and PLL

Since VCO oscillation circuit is built in, PLL circuit can consist of connecting an external low path

filter simply. VCO oscillation circuit and the example of composition of PLL are shown in Figure 16.

(A) Crystal/XI clock

Setting of command register

LOCK

CKO

Clock output

Timing

generator

DDA

SSA

Selector

External clock input

(when CKI does not use, it

SSA

CKI

connect to V line.)

VCO circuit

AMPO

AMPI

L: CKI/XI clock

H: VCO clock

PLON

DDA

Phase detector

PDO

FCONT

Frequency

detector

Demodulation

circuit

SSA

DIR input

Modulation circuit

DIT output

TXO

Figure 16 VCO Oscillation Circuit and Example of Composition of PLL

2005-09-28

TC9446FG

DIR input part

When you input a signal into DIR, please be sure to input, as shown in Figure 17 through a signal

amplification circuit, a 5 V-3 V conversion circuit, etc.

3 V

DIR

COAXIAL

(3 V input)

5 V-3 V level shifter

5 V

OPTICAL

Figure 17 DIR Input Part

Lock detection

When VCO circuit locks LOCK terminal and it is operating, “H” level is outputted and “L” level is

outputted at the time of the Ann lock. At the time of the Ann lock, latch operation of reception

recovery data and channel status is stopped, and it holds last value. If the state of a no error

continues the time of the following table, LOCK terminal will be set to “H” level and a reception

recovery will be started.

Period of error

LOCK Terminal

Data of Receiving

Demodulation

Channel Status

Figure 18 Internal Operation Timing at Time of Error

Table 3 Release Time After the Lock Detection Operation

Sampling Frequency (kHz)

Data of Receiving Demodulation t (ms)

Channel Status t (ms)

44.1

384.0

278.6

256.0

128.0

288.0

209.0

192.0

96.0

2005-09-28

TC9446FG

Non-inputted detection

When existence of the edge of the input signal from RX terminal is detected and there is no fixed

time edge, VCO oscillation operates by free run. Since VCO oscillation frequency and CKO terminal

output are set to about 80 MHz, please change it to an external clock automatically by the internal

program at the time of less inputting, or choose XI input by setup of command register.

Table 4 Non-Inputted Judgment Time of Input Signal

Sampling Frequency (kHz)

Time of Last Edge (ms)

44.1

approx. 1000

approx. 750

approx. 700

approx. 350

Miss lock detection

By comparing the input signal and the oscillation frequency from RX terminal, a Miss lock is

detected and the signal for escaping from a miss lock is outputted from FCONT terminal.

Higher than objective frequency

Objective frequency

Lower than objective frequency

FCONT Output

Hiz

Figure 19 Miss Lock Detection Operation Timing

6. DSP Part Clock Generating Circuit

It is the circuit which generates a clock required in order to operate a decode program. DLL circuit can

generate the DLL clock of a crystal oscillation clock.

DLL circuit and a crystal oscillation circuit block are shown in Figure 20.

(A) CKI/XI selector

DLL oscillator

(*3, *4, *6)

SSX

External clock input

(when the SCKI does not use,

SCKI

it connect to V line.)

Selector

Clock output

SCKO

DLCKS

DLON

LPFO

Internal DSP clock

Figure 20 Crystal Oscillation Circuit and DLL Circuit Block

2005-09-28

TC9446FG

DLL oscillation clock can be chosen with DLCKS terminal and DLON terminal, as shown in Table 5.

Table 5 Setup of DLL Circuit

DLCKS Terminal (93 pin)

DLON Terminal (92 pin)

DLL Oscillation Clock

“L”

“H”

“L”

“H”

“L”

“H”

SCKI input (DLL = off)

XI input * 4^thtimes

XI input * 3^rdtimes

XI input * 6^thtimes

When DLCKS terminal and DLON terminal are “L”, the external clock input from SCKI terminal is

chosen.

An internal clock of operation is a half divided clock of the DLL clock, and processing speed can

correspond a maximum of 75 MIPS. The clock outputted from DLL circuit should choose a crystal

oscillation clock to be set to less than 150 MHz. The example of DLL clock by the crystal oscillation clock is

shown in Table 6.

Table 6 Crystal Oscillation Clock and DLL Clock

Crystal Oscillation Clock

6^thTimes Clock

4^thTimes Clock

3^rdTimes Clock

12.288 MHz

(48 kHz*256)

18.432 MHz

(48 kHz*384)

24.576 MHz

(48 kHz*512)

25.00 MHz

73.728 MHz

(36 MIPS operation)

110.592 MHz

49.152 MHz

(24 MIPS operation)

73.728 MHz

38.864 MHz

(18 MIPS operation)

55.296 MHz

(55 MIPS operation)

147.456 MHz

(36 MIPS operation)

98.304 MHz

(27 MIPS operation)

73.728 MHz

(73 MIPS operation)

to 150 MHz

(49 MIPS operation)

100.00 MHz

(36 MIPS operation)

75.00 MHz

(asynchronous)

27.00 MHz

(75 MIPS operation)

(50 MIPS operation)

108.00 MHz

(37 MIPS operation)

81.00 MHz

Not available

(asynchronous)

30.0 MHz

(54 MIPS operation)

to 120 MHz

(40 MIPS operation)

90.00 MHz

(asynchronous)

36.864 MHz

(48 kHz*768)

(60 MIPS operation)

(45 MIPS operation)

110.592 MHz

Not available

(55 MIPS operation)

Note 8: Crystal oscillation clock is as asynchronous as the system clocks (AD converter, DA converter, etc.) of

external LSI. A case needs to input the clock oscillated externally into CKI terminal, and needs to

synchronize with them.

7. Flag Input (FI0-FI3 terminal)

It is used when inputting a flag from a MCU. However, a function changes with built-in programs. FI0 to

FI3 terminal should fix each terminal to “H”, or since pull-up resistance is built in, when not being

specified by the program, please it be open and be used for it.

8. Interruption Input (IRQ terminal)

It is used when interrupting and inputting from a MCU. However, operation changes with built-in

programs. IRQ terminal should fix a terminal to “L”, or since pull down resistance is built in, when not

being specified by the program, please it be open and be used for it.

9. General-Purpose Output Terminal (PO0-PO7 terminal)

It can be used when carrying out logic control of the case where it is used as an interruption output to the

flag and the MCU for detection of internal operation, or the external LSI. However, the function and

operation of a terminal change with built-in programs. Since PO0-PO7 terminal contains pull-up resistance,

when not being specified by the program, please carry out and use each output terminal for opening.

At the time of a power-supply injection, the output of a general-purpose output terminal becomes unfixed.

“L” level will be outputted if it initializes with a reset terminal.

2005-09-28

TC9446FG

10. External SRAM Connection

It can be used by the ability of able to connect external SRAM to processing of data tables, such as

coefficient data, or data delay.

The function of the terminal for external SRAM control is shown in Table 7. Moreover, the example of

connection of external SRAM is shown in Figure 21.

Table 7 Function of Terminal for External SRAM Control

Terminal Name

Functions

WR terminal

OE terminal

CE terminal

Write signal output terminal for external SRAM

Output enable signal output terminal for external SRAM

Chip enable signal output terminal for external SRAM

Data input/output terminal for external SRAM (8 bit I/O)

It is 3^rdtimes accessing at 24 bit I/O.

IO0 to IO7 terminal

Address output terminal for external SRAM

AD0 to AD16 terminal

It can access to address 00000h to 20000h.

Example of High-speed 1 M SRAM connection

Example of High-speed 256 k SRAM connection

TC9446FG (3.3

1 M HS SRAM (3.3 V)

256 k HS SRAM (3.3 V)

AD15, 16

N.C

AD0¯AD16

IO0¯IO7

AD0¯AD16

IO0¯IO7

AD0¯AD14

IO0¯IO7

Figure 21 Example of Connection of External SRAM

2005-09-28

TC9446FG

11. Serial Data Input-and-Output Terminal

Since two terminals (SDI0 and SDI1 terminal) are prepared for an audio serial data input and four

terminals (SDO0-SDO3 terminal) are prepared for an output, the connection with external AD/DA

converter LSI is easy.

Although an input terminal (SDI0, SDI1, LRCKA, BCKA, LRCKB, and BCKB terminal) can be inputted

by 3-5 V, an output terminal (SDO0-3, LRCKOA, BCKOA, LRCKOB, and BCKOB terminal) is outputted by

3 V. Therefore, when the input terminal of external LSI does not correspond to TTL level input, please

carry out level conversion using a level shifter circuit etc.

Figure 22 the example of connection of AD/DA converter is shown. However, when an input-and-output

signal has the same sampling frequency, it is restricted. Since a sampling frequency differs when the signal

of 2 fs is inputted and it outputs a signal by 1 fs, the connection method needs to be changed.

AD/DA converter

DATA OUT

TC9446FG

SDI0 (fs)

RX (2 fs/fs)

DIR input

Analog input

SDO0 (not used)

SDO1

TXO (2 fs/fs) DIT

DIT output

DATA IN0

DATA IN1

DATA IN2

SDO2

Analog output

SDO3

LRCKI

BCKI

LRCKOA (2 fs/fs)

BCKOA

LRCKA

SCKI

BCKA

LRCKOB (not used)

BCKOB (not used)

LRCKB

BCKB

SDI1 (not used)

CKO

Figure 22 Example of AD/DA Converter Connection

2005-09-28

TC9446FG

12. Example of Processing of Dolby Digital (AC-3) (Note 9) Decoder

Dolby Digital

Configuration

IEC958

SFC

(AC-3) 5.1 ch

decode

C/Sch delay

Dolby Digital

(AC-3) 5.1 ch

decode

2 ch Down Mix

Dolby Digital

(AC-3) 5.1 ch

decode

3D sound

Dolby Digital

(AC-3) 2 ch

decode

Dolby

SFC

Pro Logic

Dolby Digital

(AC-3) 2 ch

decode

Dolby

3D sound

Pro Logic

Dolby Digital

(AC-3) 2 ch

decode

3D sound

Note 9: “Dolby”,”Pro Logic”, and the double-D symbol are trademarks of Dolby Laboratories.

2005-09-28

TC9446FG

13. Example of System Application

MCU

TC9446FG

MCU Interface

CKO

384 fs

DIR

L OUT

RX (IEC958)

LRCKOA

BCKOA

(VCO)

TIMING

64 fs

DAC

R OUT

CKI

384 fs

LRCKA

BCKA

SL OUT

SR OUT

DLL (×6)

18.432 MHz

110.592 MHz

SDO0¯3

C OUT

SDI0

L IN

R IN

LRCK

BCK

DAC

ADC

DECODE (55 MIPS)

LFE OUT

384 fs

DIT

TXO (IEC958)

2005-09-28

TC9446FG

14. Example of Application Circuit

SRAM I/F (3.3 V)

AUDIO SCK

MCU I/F

PO0

PO1

PO2

PO3

PO4

PO5

PO6

PO7

LOCK

CKO

SSA

CKI

0.01 µF

AMPO

AMPI

0.47 µF 100 Ω

PLON

DDA

DDDL

0.033 µF to 0.1 µF

TC9446FG

(top view)

10 kΩ

LPFO

PDO

TSTSUB2

TSTSUB1

FCONT

DLON

DLCKS

SCKO

TSTSUB0

SSDL

SCKI

DIR IN

0.1 µF

TEST3

TEST2

TXO

SSX

18.432 MHz

2.2 M

DIT OUT

DDX

100

MCU I/F (3.3 V)

AUDIO I/F (3.3 V)

DDX

and V

line which the *-mark attached should dissociate and connect with other V

SSX DD

and V line.

Note 10: According to the diving noise of outside which receives a power supply line and GND line, etc., or jitters of the input signal, and other operating conditions (power-supply voltage, temperature conditions, etc.), the lock of PLL may separate from this product

and it may become unstable.

Please determine constant value according to the characteristic of a circuit in the case of use of this product. In addition, the constant value in the example of an application circuit is for explaining operation of this product, and application, and does not offer a

guarantee of operation.

2005-09-28

TC9446FG

Maximum Ratings (Ta = 25°C)

Characteristics

Power supply voltage

Input voltage-1

Symbol

Rating

Unit

−0.3 to +4.0

−0.3 to

IN1

+ 0.3

−0.3 to

+ 3.0

(Note 11)

1500

Input voltage-2

IN2

Power dissipation

°C

Operating temperature

Storage temperature

opr

−40 to +85

stg

−55 to +150

°C

Note 11: MICS , MILP , MIDIO, MICK , LRCKA, BCKA, LRCKB, BCKB, SDI0, SDI1, RX (schmitt input terminals)

Electrical Characteristics

(unless otherwise specified, Ta = 25°C, V = V

= V

= V = 3.3 V)

DDDL

DDX

DDA

DC Characteristics

Test

Circuit

Characteristics

Symbol

Test Condition

Ta = −40 to +85°C,

Min

3.0

3.1

⎯

Typ.

3.3

⎯

Max

3.6

Unit

Operating power supply voltage-1

Operating power supply voltage-2

Operating frequency range-1

⎯

DD1

DD2

opr1

140 MHz

opr

Ta = −40 to +85°C,

⎯

3.6

> 140 MHz

opr

DLL oscillation frequency (4^th

times)

120

MHz

DLL oscillation frequency (6^th

Operating frequency range-2

Power supply current

⎯

150

160

MHz

times), At f_opr> 140 MHz,

opr2

= 3.1 to 3.6 V.

f_opr= 150 MHz 75 MIPS

110

operating

Clock Terminals

“H” level

⎯

2.5

⎯

0.8

−8

⎯

IH1

Input voltage

XI pin, (Note 14)

“L” level

IL1

“H” level

Output current

= 2.8 V

= 0.5 V

⎯

OH1

XO pin

“L” level

OL1

Note 14: CKI, SCKI (CMOS input terminals)

2005-09-28

TC9446FG

Test

Circuit

Characteristics

Symbol

Test Condition

Min

Typ.

Max

Unit

Input Terminals

“H” level

⎯

2.8

⎯

IH2

(Note 11), (Note 12), (Note 13),

(Note 15)

Input voltage

“L” level

⎯

0.5

IL2

(Note 11),

(Note 12),

(Note 15),

“H” level

⎯

= V

⎯

±10

Input leakage

current

AMPI pin

µA

(Note 11),

(Note 13)

“L” level

= 0 V

AMPI pin

Output Terminals

= 2.8 V

(Note 15),

(Note 16),

(Note 17)

“H” level

⎯

−8

⎯

−1

⎯

OH2

Output current

= 0.5 V

= 2.8 V

= 0.5 V

“L” level

“H” level

“L” level

OL2

OH3

AMPO pin

OL3

3-State Output Terminals

“H” level

⎯

= 2.8 V

= 0.5 V

⎯

−8

OH4

Output current

FCONT,

pins

“L” level

⎯

OL4

= V

= 0 V

Output off leakage current

⎯

±10

µA

OZ4

Open-Drain Output Terminals

Output current

“L” level

⎯

= 0.5 V

⎯

OL6

MIDIO pin

= V ,

= 0 V

Output off leakage current

⎯

±10

µA

Pull-Up Resistor and Pull-Down Resistor Built-In Terminals

(Note 12),

Pull-up resistor

Rup

⎯

= 0 V

(Note 15),

(Note 16)

⎯

kΩ

Pull-down resistor

Rdwn

= 3.3 V

(Note 13)

Note 11: MICS , MILP , MIDIO, MICK , LRCKA, BCKA, LRCKB, BCKB, SDI0, SDI1, RX (schmitt input terminals)

Note 12: RST , TSTSUB0 to 2, TEST0 to 3, PLON, DLON, DLCKS, FI0 to 3 (schmitt input terminals with pull-up

resistor)

Note 13: MIMD, IRQ (schmitt input terminals with pull-down resistor)

Note 15: IO0 to 7 (input/output terminals with pull-up resistor)

Note 16: PO0 to 7, AD0 to 16, WE , OE , CE (output terminals with pull-up resistor)

Note 17: MIACK, SDO0 to 3, LRCKOA, BCKOA, LRCKOB, BCKOB, TXO, CKO, SCKO, LOCK (output terminals)

2005-09-28

TC9446FG

Test

Circuit

Characteristics

Symbol

Test Condition

Min

Typ.

Max

Unit

AC Characteristics (1) Timing

Clock Input Terminals

(XI)

DLL oscillation circuit (4^th

times)

Clock frequency

Clock duty

⎯

MHz

⎯

DTY

Clock Input Terminals (CKI)

Clock frequency

Clock “H” duration

Clock “L” duration

⎯

384 fs, fs = 96 kHz

⎯

MHz

⎯

CIH

CIL

Clock Input Terminals (SCKI)

Clock frequency

Clock “H” duration

Clock “L” duration

⎯

75 MIPS operating

⎯

150

⎯

MHz

⎯

3.3

SIH

⎯

SIL

Reset Terminal

(

)

RST

Stand-by time

Reset pulse width

⎯

RRS

µs

WRS

Audio Serial Interface

(LRCKA to B, BCKA to B, LRCKOA to B, BCKOA to B, SDI0 to 1, SDO0 to 3)

LRCK setup time

⎯

= 30 pF, fs = 96 kHz

−60

160

⎯

LBS

LBH

LRCK hold time

SDI setup time

SDI

HDI

SDI hold time

BCK clock cycle

BCK

BCH

BCK clock “H” duration

BCK clock “L” duration

SDO output delay time-1

SDO output delay time-2

LRCK output delay time

BCL

DO1

DO2

⎯

DCLR

2005-09-28

TC9446FG

Test

Circuit

Characteristics

Symbol

Test Condition

Min

Typ.

Max

Unit

Micro Controller Interface

Serial Transmission Mode

(

, MIDIO,

, MIACK)

MILP

MICS MICK

Stand-by time

⎯

0.5

1.0

0.5

⎯

0.5

⎯

0.1

⎯

µs

STB

MICS fall-MICK rise setup time

MIACK fall-MICK rise setup time

MICK clock cycle

MICK “L” duration

MICK “H” duration

MICK rise-MILP fall setup time

MILP “duration

MIDIO input data setup time

MIDIO input data hold time

MIDIO output data delay time

MICS “H” duration

0.5

⎯

MIACK output delay time

MILP rise-MICS rise setup time

0.5

Note 18: “H” duration of MIACK signal depends on firmware of TC9446FG.

I C Mode (

, MIDIO)

MICK

MICK clock frequency

MICK “H” duration

MICK “L” duration

Data setup time

⎯

= 400 pF

⎯

400

⎯

kHz

µs

IFCK

0.6

1.3

0.1

⎯

µs

⎯

µs

Data hold time

⎯

µs

Transmission start condition hold time

0.6

⎯

µs

SCH

Repeat transmission start condition

setup time

⎯

= 400 pF

0.6

⎯

µs

SCS

ECS

Transmission end condition setup

time

Data transmission interval

I²C rise time

⎯

= 400 pF

1.3

⎯

0.1

⎯

µs

BUF

I²C fall time

0.5

2005-09-28

TC9446FG

Test

Circuit

Characteristics

Symbol

Test Condition

Min

Typ.

Max

Unit

External RAM Memory Interface (WR, OE, CE, IO0 to 7, AD0 to 16)

(1) Memory read input/output

Address setup time

Address hole time

Pre-charge time

Read cycle width

⎯

= 30 pF, 75 MIPS operating

⎯

ASR

AHR

PCR

⎯

8 bit, one time access

= 30 pF, 75 MIPS operating

Until read end from chip select

⎯

16 bit, two times access

= 30 pF, 75 MIPS operating

24 bit, three times access

OE access time of external SRAM

CE access time of external SRAM

⎯

= 30 pF, 75 MIPS operating

⎯

Output data hold time of external

SRAM

⎯

= 30 pF, 75 MIPS operating

⎯

Address access time of external

SRAM

⎯

= 30 pF, 75 MIPS operating

⎯

ACC

CE disable time of external SRAM

COD

(2) Memory write output

Address setup time

WR pulse width

Address hold time

Pre-charge time

Write cycle width

⎯

= 30 pF, 75 MIPS operating

⎯

ASW

AHW

PCW

⎯

8 bit, one time access

= 30 pF, 75 MIPS operating

Until write end from chip select

⎯

16 bit, two times access

= 30 pF, 75 MIPS operating

24 bit, three times access

Output data setup time

Output data hold time

OE setup time

⎯

= 30 pF, 75 MIPS operating

⎯

OES

OEH

OE hold time

2005-09-28

TC9446FG

AC Characteristics Measurement Points

(1) Clock terminal (XI, CKI, SCKI)

Clock

50%

t , t

, t

t , t , t

L CIL SIL

CIH SIH

, f , f

XI CI SI

Duty cycle (f

) = t /(t + t ) × 100 (%)

DTY

(2) Reset

100%

90%

RST

WRS

RRS

(3) Audio serial interface (LRCKx, BCKx, SDIx, LRCKOx, BCKOx, SDOx, CKO)

CKO

50%

DCLR

50%

100%

LRCKOx

BCK

BCH

BCL

LRCKx/

LRCKOx

LBH

BCKx/

LBS

BCKOx

SDIx

HDI

SDI

SDOx

DO2

DO1

2005-09-28

TC9446FG

(4) Micro controller interface

(4-1) Serial transmission interface mode ( MICS , MICK , MIDIO, MILP , MIACK )

RST

MICS

STB

MICS

ΜΙΑCΚ

MICK

MILP

MIDIO

DATA IN

DATA OUT

MICS

ΜΙΑCΚ

MICK

MILP

MIDIO

DATA IN

DATA OUT

2005-09-28

TC9446FG

(4-2) I C mode ( MICK , MIDIO)

RST

MIDIO

(SDA)

STB

BUF

MIDIO

(SDA)

MICK

(SCL)

ECS

SCH

SCS

2005-09-28

TC9446FG

(5) External RAM memory interface

(5-1) READ cycle timing

AD0-AD16

ADDRESS

ASR

AHR

PCR

ACC

COD

IO0-IO7

DATA IN

(5-2) WRITE cycle timing

AD0-AD16

ADDRESS

ASW

AHW

PCW

OEH

OES

IO0-IO7

DATA OUT

2005-09-28

TC9446FG

Package Dimensions

P-QFP100-1420-0.65Q

Unit : mm

(Note) Palladium plate

Weight: 1.57 g (typ.)

2005-09-28

TC9446FG

2005-09-28

TC9446FG [TOSHIBA]

相关型号：

TC9447F

TC9452F

TC9455F

TC9455N

TC9456F

TC9457F

TC9459

TC9459F

TC9459N

TC9462F

TC9462F_01

TC9464FN