TC9462F_01 [TOSHIBA]
Digital Servo Single Chip Processor; 数字伺服单芯片处理器
| 型号： | TC9462F_01 |
| 厂家： | 
TOSHIBA |
| 描述： | Digital Servo Single Chip Processor |
| 文件： | 总17页 (文件大小：228K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TC9462F
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC9462F
Digital Servo Single Chip Processor
The TC9462F is a single chip processor which incorporates the
following function: synchronous separation protection and
interpolation, EFM demodulation, Error correction,
microcontroller interface, digital equalizer for use in servo LSI
and servo control circuit.
In addition, the TC9462F incorporates a 1 bit DA converter. In
combination with the head amplifier TA2109F, TA2153FN for
digital servo, the TC9462F allow simplified, adjustment-free
structuring of CD player system.
Features
Weight: 1.6 g (typ.)
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Capable of decode the text data.
Sync pattern detection, sync signal protection and synchronization can be made correctly.
Built in EFM demodulation circuit, subcode demodulation circuit.
Capable of correcting dual C1 correction and quadruple C2 correction using the CIRC correction theoretical
format.
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The TC9462F respond to variable playback system.
Jitter absorbing capacity of ±6 frames.
Built in 16 KB RAM.
Built in digital out circuit.
Built in L/R independent digital attenuator.
Audio output responds to bilingual function.
Reed timing free subcode Q data and capable of synchronous output with audio data.
Built in data slicer and analog PLL (free-adjustment VCO).
Capable of automatic adjustment function of focus servo and tracking servo, for loop gain, offset and balance.
Built in RF gain automatic adjustment circuit.
Built in digital equalizer for phase compensation.
Built in RAM for digital equalizer for coefficient, and capable of variable pickup.
Built in focus, tracking servo control circuit.
Search control corresponds to every mode and can realize high speed and stable search.
Lens-kick are using speed controlled form.
Built in AFC circuit and APC circuit for CLV servo of disc motor.
Built in anti-defect and anti-shock circuit.
Built in 8 times oversampling digital filter and 1 bit DA converter.
Built in analog filter for 1 bit DA converter.
Built in zero data detect output circuit.
The TC9462F capable of 4 times speed operation.
Built in microcontroller interface circuit.
CMOS silicon structure and high speed, low power consumption.
100 pin flat package.
1
2001-11-05
TC9462F
Block Diagram (top view)
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
RFGC
TEBC
FMO
TMAX
TMAXS
PDO
51
52
53
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
FVO 54
DMO
ZDET
HSSW
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P2V
REF
2V
REF
SEL
TESIO0
FLGA
FLGB
FLGC
FLGD
V
DD
MONIT
COFS
SPDA
SPCK
SBSY
SFSY
DATA
V
DD
V
SS
IO0
IO1
IO2
V
SS
IO3
V
DD
DMOUT
CKSE
DACT
TESIN
TESIO1
CLCK
SBOK
IPF
MBOV
DOUT
AOUT
BCK
V
8
SS
PXI
7
PXO
V
6
SS
V
LRCK
EMPH
UHSO
HSO
5
DD
XV
SS
4
XI
3
XO
2
XV
DD
TEST0
1
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
2
2001-11-05
TC9462F
Pin Function
Pin No.
1
Symbol
I/O
I
Functional Description
Remarks
TEST0
HSO
Test mode terminal. Normally, keep at open.
Playback speed mode flag output terminal.
With pull-up resistor.
2
3
O
O
UHSO
HSO
Playback Speed
H
H
L
H
L
Normal
2 times
4 times
¾
¾
H
L
UHSO
L
Subcode Q data emphasis flag output terminal.
Emphasis ON at “H” level and OFF at “L” level.
The output polarity can invert by command.
4
5
EMPH
LRCK
O
O
¾
¾
Channel clock output terminal. (44.1 kHz)
L-ch at “L” level and R-ch at “H” level. The output polarity can
invert by command.
6
7
8
9
V
¾
O
O
O
Digital GND terminal.
¾
¾
¾
¾
SS
BCK
AOUT
DOUT
Bit clock output terminal. (1.4112 MHz)
Audio data output terminal.
Digital data output terminal.
Buffer memory over signal output terminal.
Over at “H” level.
10
11
MBOV
IPF
O
O
¾
¾
Correction flag output terminal.
At “H” level, AOUT output is made to correction impossibility
by C correction processing.
2
Subcode Q data CRCC check adjusting result output
terminal. The adjusting result is OK at “H” level.
12
13
SBOK
CLCK
O
¾
Subcode P~W data readout clock input/output terminal.
This terminal can select by command bit.
I/O
Schmitt input
14
15
16
17
18
19
20
V
¾
¾
O
O
O
O
O
Digital power supply voltage terminal.
Digital GND terminal.
¾
¾
¾
¾
¾
¾
¾
DD
V
SS
DATA
SFSY
SBSY
SPCK
SPDA
Subcode P~W data output terminal.
Play-back frame sync signal output terminal.
Subcode block sync signal output terminal.
Processor status signal readout clock output terminal.
Processor status signal output terminal.
Correction frame clock output terminal.
(7.35 kHz)
21
COFS
O
¾
Internal signal (DSP internal flag and PLL clock) output
terminal. Selected by command.
This terminal output the text data with serial by command.
22
23
24
MONIT
O
¾
I
¾
¾
¾
V
Digital power supply voltage terminal.
DD
Test input/output terminal. Normally, keep at “L” level.
The terminal that inputted the clock for read of text data by
command.
TESIO0
P2V
25
26
27
28
¾
O
O
O
PLL double reference voltage supply terminal.
¾
REF
2-state output.
HSSW
ZDET
PDO
This terminal is used to output PV
or HiZ by command.
REF
(PV
, HiZ)
REF
1 bit DA converter zero detect flag output terminal.
¾
Phase difference signal output terminal of EFM signal and
PLCK signal.
3-state output.
(P2V , PV
, V )
REF SS
REF
3
2001-11-05
TC9462F
Pin No.
29
Symbol
TMAXS
I/O
O
Functional Description
Remarks
TMAX detection result output terminal. Selected by
command bit (TMPS).
3-state output.
(P2V , PV
, V )
REF SS
REF
TMAX detection result output terminal. Selected by
command bit (TMPS).
TMAX Detection
TMAX Output
“P2V
3-state output.
(P2V , HiZ, V
30
TMAX
O
Longer than fixed freq.
Shorter than fixed freq.
Within the fixed freq.
”
REF
)
SS
REF
“V
”
SS
“HiZ”
31
32
33
LPFN
LPFO
I
LPF amplifier inverting input terminal for PLL.
LPF amplifier output terminal for PLL.
PLL reference voltage supply terminal.
Analog input.
O
¾
Analog output.
PV
¾
REF
VCO center frequency reference level terminal.
34
VCOREF
VCOF
I
¾
Normally, keep at “PV
” level.
REF
35
36
37
O
¾
O
VCO filter terminal.
Analog output.
AV
Analog GND terminal.
¾
SS
SLCO
RFI
Data slice level output terminal.
RF signal input terminal.
Analog output.
Analog input.
38
39
40
I
¾
I
(Z : selected by command)
in
AV
Analog power supply voltage terminal.
RFRP signal center level input terminal.
¾
DD
Analog input.
(Z : 50 kW)
in
RFCT
41
42
43
44
45
RFZI
RFRP
FEI
I
I
I
I
I
RFRP zero cross input terminal.
RF ripple signal input terminal.
Analog input.
Analog input.
Analog input.
Analog input.
Analog input.
Focus error signal input terminal.
Sub-beam adder signal input terminal.
Test input terminal. Normally, keep at “V
SBAD
TSIN
” level.
REF
Tracking error signal input terminal.
Take in at tracking servo on.
46
47
TEI
I
I
Analog input.
Analog input.
(Z : 10 kW)
in
TEZI
Tracking error zero cross input terminal.
Focus servo equalizer output terminal.
48
49
50
FOO
TRO
O
O
Analog output.
(2V
~AV
REF
)
SS
Tracking servo equalizer output terminal.
Analog reference voltage supply terminal.
V
¾
¾
REF
RF amplitude adjustment control signal output terminal.
3-state PWM signal output. (PWM carrier = 88.2 kHz)
51
52
53
54
RFGC
TEBC
FMO
FVO
O
O
O
O
Tracking balance control signal output terminal.
3-state PWM signal output. (PWM carrier = 88.2 kHz)
3-state output.
Feed equalizer output terminal.
3-state PWM signal output. (PWM carrier = 88.2 kHz)
(2V
, V
, V
)
REF REF SS
Speed error signal or feed search equalizer output terminal.
3-state PWM signal output. (PWM carrier = 88.2 kHz)
Disc equalizer output terminal.
(PWM carrier = 88.2 kHz for DSP, Synchronize to PXO)
55
56
DMO
O
2V
¾
Analog double reference voltage supply terminal.
¾
¾
REF
APC circuit ON/OFF indication signal output terminal.
At the laser on time, “HiZ” level at UHS = L and “H” level at
UHS = H.
57
SEL
O
4
2001-11-05
TC9462F
Pin No.
58
Symbol
FLGA
I/O
O
Functional Description
Remarks
External flag output terminal for internal signal.
¾
¾
¾
¾
Can select signal from TEZC, FOON , FOK and RFZC by
command.
External flag output terminal for internal signal.
Can select signal from DFCT , FOON , FMON and RFZC
59
60
61
FLGB
FLGC
FLGD
O
O
O
by command.
External flag output terminal for internal signal.
Can select signal from TRON , TRSR , FOK and SRCH
by command.
External flag output terminal for internal signal.
Can select signal from TRON , DMON , HYS and SHC
by command.
62
63
64
65
66
67
V
¾
¾
Digital power supply voltage terminal.
¾
¾
DD
V
Digital GND terminal.
SS
IO0
IO1
IO2
IO3
General I/O terminal be changed over input port or output
port by command. At the input port mode, it can readout a
state of terminal (H/L) by read command. At the output port
mode, it outputs (H/L/HiZ) by command.
I/O
¾
“L” active, when this terminal is set “L”, IO 0/1 and 2/3 output
feed equalizer signal and disc equalizer signal of 2-state
PWM respectively.
68
DMOUT
I
With pull-up resistor.
69
70
71
72
73
CKSE
DACT
I
I
Normally, keep at open.
With pull-up resistor.
DAC test mode terminal. Normally, keep at open.
Test input terminal. Normally, keep at “L” level.
Test input/output terminal. Normally, keep at “L” level.
Digital GND terminal.
With pull-up resistor.
TESIN
TESIO1
I
Analog input.
I
¾
¾
V
¾
SS
Crystal oscillator connecting input terminal for DSP.
Normally, keep at “L” level.
74
PXI
I
¾
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
PXO
O
¾
¾
I
Crystal oscillator connecting output terminal for DSP.
Digital power supply voltage terminal.
V
¾
DD
XV
Oscillator GND terminal for system clock.
¾
SS
XI
XO
Crystal oscillator connecting input terminal for system clock.
Crystal oscillator connecting output terminal for system clock.
Oscillator power supply voltage terminal for system clock.
Analog GND terminal for DA converter. (R-ch)
R channel data forward output terminal.
¾
O
¾
XV
¾
¾
O
¾
DD
SR
DV
¾
RO
¾
DV
¾
¾
O
Analog supply voltage terminal for DA converter.
Reference voltage terminal for DA converter.
L channel data forward output terminal.
¾
DD
DVR
LO
¾
¾
DV
¾
I
Analog GND terminal for DA converter. (L-ch)
Test mode terminal. Normal, keep at open.
Test mode terminal. Normal, keep at open.
Test mode terminal. Normal, keep at open.
¾
SL
TEST1
TEST2
TEST3
BUS0
BUS1
BUS2
BUS3
With pull-up resistor.
With pull-up resistor.
With pull-up resistor.
I
I
I/O
I/O
I/O
I/O
¾
Schmitt input.
Micon interface data input/output terminal.
With pull-up resistor.
V
Digital power supply voltage terminal.
¾
DD
5
2001-11-05
TC9462F
Pin No.
Symbol
I/O
Functional Description
Digital GND terminal.
Remarks
95
96
V
―
¾
SS
BUCK
I
Micon interface clock input terminal.
Schmitt input.
Schmitt input.
Command and data sending/receiving chip enable signal
input terminal.
97
CCE
I
The bus line becomes active at “L” level.
98
99
TEST4
TSMOD
RST
I
I
I
Test mode terminal. Normal, keep at open.
Local test mode selection terminal.
With pull-up resistor.
With pull-up resistor.
With pull-up resistor.
100
Reset signal input terminal. Reset at “L” level.
Maximum Ratings (Ta = 25°C)
Characteristics
Symbol
Rating
Unit
Power supply voltage
Input voltage
V
-0.3~6.0
V
V
DD
V
-0.3~V
+ 0.3
DD
IN
Power dissipation
Operating temperature
Storage temperature
P
1420
mW
°C
°C
D
T
-40~85
opr
T
-55~150
stg
6
2001-11-05
TC9462F
Electrical Characteristics
(unless otherwise specified, V = AV = DV = XV = 5 V, 2V
= P2V
= 4.2 V,
DD
DD
DD
DD
REF
REF
V
REF
= PV
= 2.1 V, Ta = 25°C)
REF
DC Characteristics
Test
Circuit
Characteristics
Symbol
Test Condition
Min
4.5
45
Typ.
5.0
50
Max
Unit
V
Assured supply voltage
V
¾
Ta = -40~85°C
5.5
60
DD
Normal
speed
XI =
16.9344 MHz
Assured supply current
I
¾
mA
DD
4 times
speed
50
55
65
“H” Level
V
¾
¾
¾
3.5
¾
¾
¾
¾
¾
IH
CMOS input terminal
(except analog input)
Input voltage
Input current
V
“L” Level
“H” Level
V
1.5
1.0
IL
I
V
V
= 5 V
= 0 V
CMOS Input
Terminal
(except analog
input)
¾
IH
IH
IL
mA
mA
“L” Level
I
¾
-1.0
¾
¾
IL
“H” Level
“L” Level
“H” Level
“L” Level
“H” Level
“L” Level
“H” Level
“L” Level
“H” Level
“L” Level
I
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
V
V
V
V
V
V
V
V
V
V
= 5 V
= 0 V
¾
-0.1
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
0.1
¾
TLH
IH
Tri-state
leak current
following (1)
I
TLL
IL
I
= 4.6 V following (1)
-1.0
¾
OH (1)
OH
(except TMAXS,
TMAX)
I
= 0.4 V
= 4.6 V
= 0.4 V
= 4.6 V
= 0.4 V
= 3.8 V
= 0.4 V
2.0
¾
OL (1)
OH (2)
OL
I
I
I
-1.0
¾
OH
OH
OH
OL
OH
OL
following (2)
I
2.0
-1.4
0.6
¾
OL (2)
OH (3)
Output current
mA
-0.6
1.4
-1.0
¾
following (3)
following (4)
I
OL (3)
OH (4)
I
2.0
OL (4)
following (4)
(except TMAXS, TMAX)
V
output ON resistor
R
¾
¾
¾
¾
25.0
1.0
¾
50.0
2.0
500
75.0
3.0
W
REF
ON
Pull-up resistor
Osc. Amp. feedback resistor
R
following (5)
kW
MW
UP
between XI-XO and PXI-PXO
terminal
R
N
Terminal Name
HSO , UHSO , EMPH, DOUT, MBOV, IPF, SBOK, CLCK, TESIO1
DATA, SFSY, SBSY, SPCK, MONIT, TESIO0, TMAXS, TMAX, SEL
FLGA, FLGB, FLGC, FLGD, IO0, IO1, IO2, IO3
(1) Terminal
(2) Terminal
(3) Terminal
(4) Terminal
(5) Terminal
LRCK, BCK, AOUT, SPDA, COFS, ZDET
BUS0~3
PDO, TMAXS, TMAX, RFGC, TEBC, FMO, FVO, DMO
DMOUT , CKSE , DACT , TSMOD, RST , TEST0~4
7
2001-11-05
TC9462F
AC Characteristics
1. Microcomputer Interface Timing
Test
Circuit
Characteristics
Symbol
Test Condition
Min
Typ.
Max
Unit
CCE “H” clock pulse width
t
¾
¾
¾
120
0
¾
¾
¾
¾
CC
CCE status data access time
t
CCE falling reference
CS
Status data disable time
t
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
CCE rising reference
CCE falling reference
Write, SRC mode
0
0
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
SZ1
CCE , BUCK delay pulse width
t
CB
t
t
120
240
120
3000
1500
800
60
BLW
BLW
BUCK “L” clock pulse width
QDRC mode
BUCK “H” clock pulse width (1)
BUCK “H” clock pulse width (2)
BUCK “H” clock pulse width (3)
BUCK “H” clock pulse width (4)
Write data set-up time
t
t
t
t
Write, SRC mode
BHW
BHW
BHW
BHW
QDRC mode (´1)
ns
QDRC mode (´2)
QDRC mode (´4)
t
BUCK rising reference
BUCK rising reference
BUCK falling reference
BUCK falling reference
BUCK falling reference
BUCK rising reference
WS
WH
Write data hold time
t
20
PRTY data access time
Data disable time
t
0
BA
t
t
0
SZ2
Read data access time
Data disable time
t
0
RD
0
SZ3
(1) Idle mode
t
CC
CCE
BUCK
BUSi
ST
BUSi
(output)
t
t
SZ1
CS
Idol mode
8
2001-11-05
TC9462F
(2) Write command mode
t
CC
CCE
t
t
BLW BHW
BUCK
t
t
t
CB
WS WH
BUSi
CM
CL
DM
DL
(input)
t
t
t
t
SZ3
CS
SZ2
BA
BUSi
ST
Idol mode
PRTY
(output)
Write mode
(3) BXXXXX, FXXXXX command at
t
CC
CCE
t
t
BLW BHW
BUCK
t
CB
t
t
WS WH
BUSi
(input)
CM
CL
DM
DL
EM
EL
t
t
t
t
SZ3
CS
SZ2
BA
BUSi
ST
PRTY
(output)
(4) Read command mode
t
CC
CCE
t
t
BLW BHW
BUCK
t
t
t
CB
WS WH
BUSi
(input)
CM
t
SZ3
t
t
t
t
t
SZ3
CS
SZ2
RD
BA
BUSi
ST
Idol mode
RD0
RDn
PRTY
(output)
Write mode
9
2001-11-05
TC9462F
2. AOUT Terminal Output Data Timing
Test
Circuit
Characteristics
Symbol
Test Condition
Min
Typ.
Max
Unit
ns
“H” Level
“L” Level
t
t
¾
¾
¾
¾
¾
¾
5
5
pLH
pHL
Transfer time (1)
BCK
BCK ® AOUT
tpHL
tpLH
AOUT
3. SPDA Output Timing
Test
Circuit
Characteristics
Symbol
Test Condition
Min
Typ.
Max
Unit
ns
“H” Level
t
t
¾
¾
¾
¾
3
3
¾
¾
pLH
pHL
Transfer time
SPCK ® SPDA
“L” Level
SPCK
SPDA
tpHL
tpLH
10
2001-11-05
TC9462F
4. DATA, CLCK Input/Output Timing
(1) CLCK input mode
Test
Circuit
Characteristics
Symbol
Test Condition
Min
Typ.
Max
Unit
ns
“H” Level
t
¾
¾
¾
¾
¾
¾
200
200
200
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
5
HW
Clock pulse width
“L” Level
t
LW
Input set-up time
Transfer time (1)
t
Su
CLCK input mode
“L” Level
“H” Level
“L” Level
t
t
t
pHL1
pLH2
pHL2
¾
20
20
Transfer time (2)
¾
t
t
pHL2
pLH2
t
pHL1
SFSY/COFS
CLCK
t
SU
t
t
LW
HW
DATA
SUBP
SUBQ
(2) CLCK output mode (tHW, tLW, tpLH3; 2 times speed = 1/2, 4 times speed = 1/4)
Test
Circuit
Characteristics
Symbol
Test Condition
Min
Typ.
Max
Unit
ns
“H” Level
t
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
1000
1000
5
HW
Clock pulse width
Transfer time (1)
Transfer time (2)
Transfer time (3)
“L” Level
“L” Level
“H” Level
“L” Level
“H” Level
t
¾
LW
t
t
t
t
¾
pHL1
pLH2
pHL2
pLH3
CLCK output mode
¾
20
¾
20
¾
900
t
t
pHL2
pLH2
t
pHL1
SFSY/COFS
CLCK
t
pLH3
t
t
LW
HW
DATA
SUBP
SUBQ
11
2001-11-05
TC9462F
5. SBSY, SBOK Input/Output Control
Test
Circuit
Characteristics
Symbol
Test Condition
Min
Typ.
Max
Unit
ns
“H” Level
t
t
t
t
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
5
5
pLH1
pHL1
pLH2
pHL2
Transfer time (1)
Transfer time (2)
SBSY
SBOK
“L” Level
“H” Level
“L” Level
15
15
SFSY/COFS
SBSY
t
t
pHL1
pLH1
SBOK
t
t
pLH2
pHL2
6. Output Terminal Timing
Test
Circuit
Characteristics
Symbol
Test Condition
Min
Typ.
Max
Unit
Output rising time (1)
Output falling time (1)
Output rising time (2)
Output falling time (2)
Output rising time (3)
Output falling time (3)
t
t
t
t
t
t
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
20
15
20
15
20
15
20
10
15
10
or1
of1
or2
of2
or3
of3
Terminal (1)
Terminal (2)
Terminal (3)
ns
V
V
® 2V
REF
REF
REF
Output falling time (4)
Output rising time (4)
t
¾
¾
or4
of4
® V
SS
REF
Terminal (4)
2V
® V
REF
t
V
® V
SS
REF
Terminal Name
(1) Terminal
(2) Terminal
AOUT, BCK, COFS, LRCK
BUS0, BUS1, BUS2, BUS3, CLCK
DATA, DOUT, EMPH, FLGA, FLGB, FLGC, FLGD, HSO , IO0, IO1,
(3) Terminal
(4) Terminal
IO2 IO3, IPF, MONIT, MBOV, SBOK, SBSY, SEL, SFSY, SPCK, UHSO
PDO, TMAXS, TMAX, RFGC, TEBC, FMO, DMO, FVO
V
OH
V
OH/2
V
SS
t
t
of
or
12
2001-11-05
TC9462F
Analog Circuit Characteristics
1. A/D Converter
Characteristics
Test Condition
Min
Typ.
Max
Unit
Resolution
¾
¾
¾
8
¾
¾
bit
FE
TE
176.4
176.4
88.2
KHz
KHz
KHz
KHz
¾
¾
Sampling frequency
XI = 16.9344 MHz
SBAD
RFRP
¾
¾
¾
176.4
¾
0.15 ´
0.85 ´
Conversion input range
Ex. V = 0 V, 2V
= 4.2 V
REF
¾
V
SS
2V
2V
REF
REF
2. D/A Converter (focus, tracking equalizer output)
Characteristics
Test Condition
Min
Typ.
Max
Unit
Bit number
¾
¾
¾
¾
¾
5
¾
¾
bit
MHz
V
Sampling frequency
Output signal range
2.8
¾
AV
2V
REF
SS
3. PLL Filter Amp.
Characteristics
Test Condition
Min
Typ.
Max
2V
Unit
Input/output signal range
Frequency characteristics
¾
V
¾
V
SS
REF
-3 dB point, RNF = 15 kW
2
4
¾
MHz
4. VCO (PLL)
Characteristics
Test Condition
Min
Typ.
34.6
±50
±40
Max
Unit
LPFO = V
,
¾
¾
REF
Center oscillation frequency
Frequency variation range
MHz
VCOREF = V
REF
VCOREF = V
,
REF
±40
¾
¾
VCOGSL = “H”
%
V
VCOREF = V
,
REF
¾
VCOGSL = “L”
upper limit
lower limit
¾
¾
¾
1.0
VCOREF terminal
input voltage range
V
reference
REF
-0.5
¾
5. TEZI Signal Comparator
Characteristics
Test Condition
Min
Typ.
Max
Unit
V
Input range
¾
¾
V
¾
¾
2V
REF
SS
Input amplitude
1.0
3.5
V
p-p
Hysteresis voltage
V
reference
¾
100
¾
mV
REF
13
2001-11-05
TC9462F
6. RFZI Signal Comparator
Characteristics
Test Condition
Min
Typ.
Max
2V
Unit
Input range
¾
V
¾
¾
V
SS
REF
Input amplitude
¾
1.0
3.5
Vp-p
V
reference (no external
REF
Hysteresis voltage
¾
100
¾
mV
register to RFCT terminal)
7. Data Slicer Circuit
Characteristics
Test Condition
Min
Typ.
Max
Unit
(comparator)
Input amplitude
Response time
(R-2R DAC)
V
reference
¾
1.2
60
2.0
90
V
p-p
REF
RFI = 0.6 V , f = 700 kHz
30
ns
p-p
Output conversion range
Output impedance
¾
¾
1.58
¾
2.59
V
¾
2.5
¾
kW
8. PWM Converter Output (RFGC, TEBC, FMO, FVO, DMO)
Characteristics
PWM accuracy
Test Condition
Min
Typ.
Max
Unit
¾
¾
¾
¾
¾
8
¾
¾
bit
kHz
V
Sampling frequency
Output signal range
88.2
¾
AV
2V
REF
SS
14
2001-11-05
TC9462F
DAC Characteristics
Test
Circuit
Characteristics
Symbol
Test Condition
1 kHz sine wave,
Min
Typ.
Max
Unit
Total harmonic
distortion + noise
THD + N
1
1
¾
-85
-80
dB
dB
full scale input, PXI = “L”
S/N ratio
S/N
PXI = “L”
90
100
¾
1 kHz sine wave,
-60dB input conversion,
PXI = “L”
Dynamic range
DR
1
85
90
¾
dB
dB
1 kHz sine wave,
full scale input, PXI = “L”
Cross talk
CT
1
1
¾
-90
-85
1 kHz sine wave,
full scale input, PXI = “L”
Analog output amplitude
DAC out
1.12
1.20
1.28
V
rms
Test Circuit 1: Application Circuit is Used.
TC9462F
Lout
Rout
20 kHz
ideal LPF
Distortion
meter
Application circuit
LPF: SHIBASOKU
725C (built-in filter)
Distortion meter: SHIBASOKU 725C (corresponding)
Distortion Filter Setting:
Characteristics
A-wait
OFF
ON
THD + N, CT
S/N, DR
A-WAIT: IEC-A (corresponding)
Application Circuit
TC9462F
5 V
DV
SR
R-ch Analog out
270 W
3.3 mF
XV
XI
RO
DD
5 V
16.9344 MHz
DV
DD
XO
XV
100 mF
DVR
SS
L-ch Analog out
0.1 mF
270 W
3.3 mF
LO
PXI
DV
SL
15
2001-11-05
TC9462F
Package Dimensions
Weight: 1.6 g (typ.)
16
2001-11-05
TC9462F
RESTRICTIONS ON PRODUCT USE
000707EBA
· TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
· The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
· The products described in this document are subject to the foreign exchange and foreign trade laws.
· The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
rights of the third parties which may result from its use. No license is granted by implication or otherwise under
any intellectual property or other rights of TOSHIBA CORPORATION or others.
· The information contained herein is subject to change without notice.
17
2001-11-05
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