TC9470FN [TOSHIBA]
?-? Modulation DA Converter with Built-in 8-Times Oversampling Digital Filter/Dynamic Digital Bass Boost/Analog Filter; ？ - ？调制DA转换器，内置8倍过采样数字滤波器/数字动态低音增强/模拟滤波器
| 型号： | TC9470FN |
| 厂家： | 
TOSHIBA |
| 描述： | ?-? Modulation DA Converter with Built-in 8-Times Oversampling Digital Filter/Dynamic Digital Bass Boost/Analog Filter |
| 文件： | 总20页 (文件大小：267K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TC9470FN
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC9470FN
Σ-∆ Modulation DA Converter with Built-in 8-Times Oversampling Digital Filter/Dynamic
Digital Bass Boost/Analog Filter
The TC9470FN is a second-order Σ-∆ modulation system
1-bit DA converter incorporating an 8-times oversampling digital
filter, dynamic digital bass boost function for use with compressor
operations and an analog filter developed for digital audio
equipment.
Because the IC includes an analog filter, it can output a direct
analog waveform, thus reducing the size and cost of the DA
converter.
Features
Weight: 0.14 g (typ.)
·
·
·
·
·
·
·
·
·
·
·
·
·
Built-in 8-times oversampling digital filter
Low-voltage operations (2.4 V) possible
Built-in digital de-emphasis filter
Built-in dynamic digital bass boost function
In serial control mode, output amplitude can be set in 4096 steps of resolution using microcontroller commands
In parallel control mode, soft mute can be set for the output signal in 64 steps in 23 ms
Built-in LR common digital zero detection output circuit
Sampling frequency: 44.1 kHz
Supports 384 fs/256 fs (automatic switching)
DA converter oversampling ratio (OSR): 192 fs (at 384 fs)
Stereo/monaural output selection possible
Built-in third-order analog filter
The digital filter and DA converter characteristics are shown on the next page
Digital Filter
Transient
Digital Filter
8 fs
Passband Ripple
±0.11dB
Attenuation
Bandwidth
Standard operation
20 k to 24.1 kHz
−26dB or less
DA Converter (V = 2.7 V)
DD
OSR
Noise Distortion
S/N Ratio
Standard operation
192 fs
−82dB (typ.)
90dB (typ.)
1
2002-02-27
TC9470FN
Pin Connection
V
1
24
23
22
21
20
19
18
17
16
15
14
13
LRCK
DD
T1
2
BCK
DATA
P/S
3
4
V
DBB2
DA
RO
GNDA
VR
5
6
ATT (DBB1)
SHIFT (EMP)
LATCH (SM)
7
GNDA
LO
8
9
V
DX
XO
V
10
11
12
XI
DA
ZD
GNDD
GNDX
MCK
Block Diagram
(DBB1)(EMP) (SM)
ATT SHIFT LATCH
LRCK BCK DATA DBB2
24 23 22
21
V
XO
16
XI GNDX MCK
15 14 13
DX
20
19
18
17
Data interface
circuit
Microcontroller
interface circuit
Oscillator circuit
Timing generator
Dynamic bus
boost circuit
Digital filter circuit,
de-emphasis filter circuit,
attenuator circuit
+
Σ-∆ modulator circuit
Output
Output
circuit
Test
circuit
circuit
Analog
filter
Analog
filter
1
2
3
4
5
6
7
8
9
10
11
12
V
T1
P/S
V
RO GNDA VR GNDA LO
V
DA
ZD GNDD
DD
DA
2
2002-02-27
TC9470FN
Pin Function
Pin No.
Symbol
I/O
Function
Remarks
1
2
V
―
I
Digital block power supply pin
Test pin. Always set to “Low” level.
Parallel/serial mode select pin
Analog power supply pin
DD
T1
3
P/S
I
4
V
―
O
―
―
―
O
―
O
―
O
―
DA
5
RO
Right channel analog signal output pin
Analog GND pin
6
GNDA
VR
7
Reference voltage pin
8
GNDA
LO
Analog GND pin
9
Left channel analog signal output pin
Analog power supply pin
10
11
12
13
14
V
DA
ZD
Zero data detection output pin common to left and right channels
Digital GND pin
GNDD
MCK
GNDX
System clock output pin
Crystal oscillator GND pin
15
16
XI
I
Crystal oscillator connecting pins.
Generate the clock required by the system.
XI
XO
XO
O
17
18
V
―
Crystal oscillator power supply pin
In serial mode, data latch signal input pin
In parallel mode, soft mute control pin
In serial mode, shift clock input pin
In parallel mode, de-emphasis filter control pin
In serial mode, data input pin
DX
LATCH
(SM)
I
Schmidt input
Schmidt input
Schmidt input
SHIFT
(EMP)
19
20
I
I
ATT
(DBB1)
In parallel mode, dynamic bass boost control pin 1
In parallel mode, dynamic bass boost control pin 2
Audio data input pin
21
22
23
24
DBB2
DATA
BCK
I
I
I
I
Schmidt input
Schmidt input
Schmidt input
Bit clock input pin
LRCK
LR clock input pin
3
2002-02-27
TC9470FN
Description of Block Operations
1. Crystal Oscillator Circuit and Timing Generator
The clock required for internal operations is generated by connecting a crystal and condensers as shown
in the diagram below.
The IC will also operate when a system clock is input from an external source through the XI pin (pin 15).
However, in this situation, due consideration must be given to the fact that waveform characteristics, such
as jitter and rising/falling characteristics of the system clock, significantly affect the DA converter’s noise
distortion and the S/N ratio.
To internal circuit
GNDX
XI
X’tal
XO
V
MCK
DX
16.9344 MHz
C
L
C
L
C = 10 to 33 pF
L
Use a crystal with a low CI value and favorable start-up characteristics.
Figure 1 Crystal Oscillator Circuit Configuration (when in the 384 fs mode)
The timing generator generates the clocks and process timing signals required for such functions as
digital filtering and de-emphasis filtering.
4
2002-02-27
TC9470FN
3. Digital Filter
The 8-times oversampling IIR digital filter eliminates the noise returned from outside the bandwidth
during standard operations.
Table 1 Basic Characteristics of Digital Filter
Set Mode
Passband Ripple
±0.11dB
Transient Bandwidth
20 k to 24.1 kHz
Attenuation
Standard operations
−26dB or less
The characteristics of the digital filter frequencies are shown below.
0.000
−10.00
−20.00
−0.00
−0.10
−0.20
−0.30
−0.40
−0.50
−0.60
−0.70
−0.80
−0.90
−1.00
−30.00
−40.00
−50.00
−60.00
−70.00
0.65dB
−80.00
−90.00
−100.0
0
44.1
88.2
132.3
176.4
0
2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0 22.0 24.0
Frequency (kHz)
Frequency (kHz)
Figure 3 Digital Filter Frequency Characteristics
4. De-Emphasis Filter
ON/OFF is controlled in the parallel mode ( P/S = “H”) with the SHIFT (EMP) pin (pin 19).
This is set in the serial mode ( P/S = “L”) with a microcontroller or other equipment. (refer to 10.2
microcontroller setting mode for further details on serial mode settings.)
Table 2 De-Emphasis Filter Settings (when in the parallel mode)
Shift (EMP) Pin
De-emphasis filter
H
L
ON
OFF
6
2002-02-27
TC9470FN
The digitalization of the de-emphasis filter eliminates the need for such external components as resistors,
condensers and analog switches. In addition to this, the coefficients are aligned to reduce error in the
de-emphasis filter characteristics.
The filter structure and characteristics are shown below.
Input data
+
+
b
0
|G (j )|
ω
−1
Z
a
1
b
1
1
1
/T
2
/T
1
-1
(b + b Z
)
0
1
T = 50 µs, T = 15 µs
Transfer function : H(Z) =
1
2
-1
(1- a Z
)
1
Figure 4 IIR Digital De-Emphasis Filter
5. Dynamic Digital Bass Boost Circuit
Figure 5 Filter Characteristics
ON/OFF for the dynamic digital bass boost is controlled in the parallel mode ( P/S = “H”) with the DBB1
pin (pin 20) and the DBB2 pin (pin 21).
This is set in the serial mode ( P/S = “L”) with a microcontroller or other equipment. (refer to 10.2
microcontroller setting mode for further details on serial mode settings.)
A block diagram for the dynamic bass boost circuit is shown in Figure 6.
INPUT
OUTPUT
+
L.P.F
SERIAL
ATTENUATOR
Coefficient length: 7 bits
COMPRESSOR BLOCK
Figure 6 Dynamic Digital Bass Boost Circuit Block
The compressor’s compression ratio when in the control mode for the parallel mode is shown below.
Table 3 Compressor Compression Ratio (when in the parallel mode)
DBB max
DBB MID
18dB
12dB
The compressor’s compression characteristics are as follows:
Table 4 Compressor Compression Characteristics (when in the parallel mode)
DBB max
DBB MID
−36dB
−24dB
7
2002-02-27
TC9470FN
The compressor I/O characteristics for the dynamic digital bass boost are shown in Figure 7.
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
EFS = “L”
EFS = “H”
−100 −90 −80 −70 −60 −50 −40 −30 −20 −10
0
Input level (dB)
Figure 7 Dynamic Digital Bass Boost Compressor I/O Characteristics
The bass boost settings when in the parallel mode are shown below.
Table 5 Bass Boost Mode Settings
MODE 1
MODE 2
MODE 3
MODE 4
DBB1 (pin 20)
DBB2 (pin 21)
L
L
L
H
L
H
H
H
MODE 1: DBB OFF
MODE 2: DBB MID
MODE 3: DBB max
MODE 4: DBB max + HB
8
2002-02-27
TC9470FN
The bus boost characteristics are shown in Figure 8.
30
25
20
15
10
5
30
25
20
15
10
5
0
0
−5
−10
−5
−10
0.01
0.1
1
10
100
0.01
0.1
1
10
100
Frequency (kHz)
Frequency (kHz)
b) Vin = −20dB input, DBB OFF, 1 kHz = 0dB.
Compressor characteristics
a) Vin = −36dB input, DBB OFF, 1 kHz = 0dB.
MID: EFS = “L” (−24dB)
max: EFS = “H” (−36dB)
MAGA: EFS = “H” (−36dB)
30
25
20
15
10
5
OFF
MID
0
max + HB
MEGA + HB
−5
−10
0.01
0.1
1
10
100
Frequency (kHz)
c) Vin = 0dB input, DBB OFF, 1 kHz = 0dB.
Compressor’s compression characteristics
MID: EFS = “L” (−24dB)
max: EFS = “H” (−36dB)
MAGA: EFS = “H” (−36dB)
Figure 8 Dynamic Bass Boost Frequency Characteristics (V = 2.7 V)
DD
9
2002-02-27
TC9470FN
6. DA Conversion Circuit
The IC incorporates a second-order Σ-∆ modulation DA converter for two channels (simultaneous output
type). The internal structure of this is shown in Figure 9.
X (Z)
Y (Z)
Data
+
Output data
Q
(bit-stream 1-bit DA conversion data)
−1
+
2
+
Z
−
−
Limiter
−1
Z
−1
Second-order Σ-∆ converter: Y (Z) = X (Z) + (1 − Z )2 Q (Z)
Figure 9 Σ-∆ Modulation DA Converter
The Σ-∆ modulation clock has been designed to operate at 192 fs (when 384 fs). The noise shaping
characteristics are shown in Figure 10.
10dB
0
500 k
1 M
Frequency (Hz)
Figure 10 Noise Shaping Characteristics
7. Data Output Circuit
The output circuit is equipped with a third-order analog low-pass filter. This enables direct analog
signals to be acquired from the IC’s RO (pin 5) and LO (pin 9) output pins.
PDM signals
RO (LO)
VR
Figure 11 Analog Filter Circuit
10
2002-02-27
TC9470FN
8. Soft Mute Circuit
The IC is equipped with a soft mute function, and this enables a soft mute to be set for the DA converter
output by switching the SM pin (pin 18) from the “L” level to the “H” level when in the parallel mode
( P/S = “H”). The soft mute’s ON/OFF function and the DA converter output are shown in Figure 12.
The Soft mute ON/OFF control function is disabled during level transition.
SM Pin Input
Off
On
Off
DA Converter
Output Level
1
64
1
64
Approximately 23 ms
Approximately 23 ms
Figure 12 Changes in the Soft Mute DA Converter Output Level
9. Common Left Channel/Right Channel Digital Zero Data Detection Output Circuit
The IC is equipped with a common left channel/right channel digital zero data detection output circuit,
and the ZD pin (pin 11) is switched from “L” to “H” when data for both the left channel and the right
channel becomes zero data for approximately 350 ms or longer.
This is fixed at “L” when the data for the left channel and right channel is not zero data.
10. Description of Internal Control Signals
The P/S pin can be used to switch between the parallel mode ( P/S pin = “H” in DC setting mode) and
the serial mode ( P/S pin = “L” with the microcontroller interface function).
10.1 Parallel Mode (
= “H”: DC setting mode)
P/S
Pins 18, 19, 20 and 21 are used as the mode setting pins shown in the table below when in the
parallel mode.
Table 6 Pin Names at the Parallel Mode
Pin No.
Pin Name
Pin Description
18
19
20
21
SM
Soft mute control pin
EMP
DBB1
DBB2
De-emphasis control pin
Digital bass boost mode control pin 1
Digital bass boost mode control pin 2
11
2002-02-27
TC9470FN
10.2 Serial Mode (
= “L”: microcontroller setting mode)
P/S
It is possible to make the various settings with a microcontroller when in the serial mode.
Pins 18, 19 and 20 are used as the command input pins shown in the table below when in the serial
mode.
Table 7 Pin Names at the Serial Mode
Pin No.
Pin Name
Pin Description
18
19
20
LATCH
SHIFT
ATT
Data latch signal input pin
Shift clock signal input pin
Data input pin
The LATCH signals and ATT signals are loaded to the LSI internal shift registers on the SHIFT
signal rising edge. It is consequently necessary for the data input from the ATT pin on the shift signal
rising edge to be valid as indicated in the timing example in Figure 13. It is also necessary for the
LATCH pulse to rise at least 1.5 µs after the final clock rising edge input from the SHIFT pin.
Operating the shift clock with LATCH low destabilizes the internal state, which may lead to
malfunctions, so it must therefore be set to the low level after loading D7 to the register.
LATCH
SHIFT
ATT
D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12
A = 1.5 µs or higher, B = 1.5 µs or higher
Figure 13 Example of Data Setting Timing in the Serial Mode
The various control settings when in the serial mode are shown in the table below.
Ensure that all control bits are set when the power supply is turned on.
Table 8 Serial Mode Control Settings
Control Signals
Serial Input Data
MODE 1 MODE 2 MODE 3
D12
D11
D10
D09
D08
D07
D06
D05
D04
D03
D02
D01
0
1
0
1
1
AT11
AT10
AT09
AT08
AT07
AT06
AT05
AT04
AT03
AT02
AT01
EMP
MONO
CHS
RLS
EFS
DOFF
―
DBB1
DBB2
DBB3
BMUTE
TCA
TCR
―
AT11 to AT00: Attenuation level setting
EMP: De-emphasis ON/OFF switch
MONO, CHS: Stereo/monaural switch
RLS: LRCK polarity switch
EFS: Dynamic circuit compression characteristics switch
DOFF: Dynamic circuit ON/OFF switch
DBB1, DBB2: Digtal bass boost mode setting
DBB3: DBB MEGA max setting
―
―
―
―
BMUTE: Bass boost mute
―
―
TCA: Attack time switch
D00
AT00
―
―
TCR: Recovery time switch
12
2002-02-27
TC9470FN
10.2.1 Setting Mode 1
Serial setting mode 1 is enabled when D12 = “L”.
(1)
Digital attenuator
The digital attenuation command is enabled when D12 = L. The attenuation data can be set in
4096 different ways (coefficient: 12 bit, maximum attenuation: −72.245dB). The relationship with
the command’s output is shown below.
Table 9 Attenuation Data/Audio Data Output
Attenuation Data
Audio Output
AT [11:00]
FFFH
FFEH
FFBH
···
−0.000dB
−0.002dB
−0.004dB
···
C80H
···
−2.142dB
···
640H
···
−8.163dB
···
002H
001H
000H
−66.224dB
−72.245dB
−∞
001 (HEX) to FFE (HEX): The attenuation value is obtained with the following equation.
ATT = 20 ℓog (input data/4095) dB
Example: When the attenuation data is EA0H
ATT = 20 ℓog (4000/4095) dB = −0.204dB
If an input level is set to −48dB or less when it is set as the amount (−72.245dB) of the maximum
attenuation, the target effective attenuation data of digital attenuator of TC9470FN will be lost. The
output data is set to “0” when an input level is set to −48dB or less. An effective input level is
decided by the following formula.
Effective input data = −[120dB + Attenuation level (dB)]
10.2.2 Setting Mode 2
Serial setting mode 2 is enabled when D12 = “H” and D11 = “L”.
(1)
Digital de-emphasis filter
Controlled with EMP.
Table 10 Digital De-Emphasis Filter Setting
EMP
De-emphasis filter
L
H
OFF
ON
13
2002-02-27
TC9470FN
(2)
Stereo/monaural output channel settings
Set with MONO and CHS.
Table 11 Stereo, Monaural and Channel Select Settings
MONO
L
H
H
CHS
(Note)
Stereo output
L
H
L, R-ch output
L-ch monaural output R-ch monaural output
Note: “H” or “L”
(3)
(4)
LRCH (channel clock) polarity switch settings
Set with RLS.
Table 12 LRCK Polarity Switch Settings
RLS
L
H
Data input
R-ch data when LRCK = “L”
L-ch data when LRCK = “L”
Compressor’s compression characteristics switch settings
Set with EFS.
Table 13 Compressor Compression Characteristics
(compression ratio) Settings
EFS
L
H
Compressor’s compression
characteristics
−24dB
12dB
−36dB
18dB
Compressor compression
ratio
Compressor’s compression characteristics and compression ratio are shown in Figure 7.
(5)
Dynamic circuit ON/OFF switch settings
Set with DOFF.
Table 14 Dynamic Circuit ON/OFF Switch Settings
DOFF
L
H
Dynamic circuit
ON
OFF
The dynamic circuit’s ON/OFF switch settings become invalid when DBB3 is set to “H” in the
following mode 2 settings. The amount of boost when the dynamic circuit is OFF is shown in
table 15.
Table 15 Amount of Boost when the
Dynamic Circuit is OFF
Amount of Boost
MID
max
10.6dB
15.2dB
14
2002-02-27
TC9470FN
10.2.3 Setting Mode 3
Serial setting mode 3 is enabled when D7 = “H” and D6 = “H”.
(1)
Digital bass boost mode settings
Set with DBB1, DBB2 and DBB3.
Table 16 Bass Boost Mode Settings
MODE 1
MODE 2
MODE 3
MODE 4
DBB1
DBB2
DBB3
L
L
L
H
H
L
H
H
L or H
L or H
L or H
L or H
The DBB3 settings are as follows.
DBB3 = “L”
DBB3 = “H”
MODE 1: DBB OFF
MODE 2: DBB MID
MODE 3: DBB max
MODE 4: DBB max + HB
MODE 1’: DBB OFF
MODE 2’: DBB max
MODE 3’: DBB MEGA max
MODE 4’: DBB MEGA max + HB
(2)
Bass boost mute setting
Set with BMUTE. The bass boost mute to be set for bass boost signal by switching the BMUTE
from the “L” level to the “H” level.
Table 17 Bass Boost Mute Setting
BMUTE
L
H
Bass boost mute
OFF
ON
Time constant of bass boost mute: Approximately 3.8 ms
(3)
Attack time/recovery time switch settings
Set with TCA for attack time and TCR for recovery time.
Table 18 Attack Time Settings
TCA
L
H
Attack time
6.3 ms
24.3 ms
Table 19 Recovery Time Settings
TCA
L
H
Recovery time
12.3 s
24.6 s
15
2002-02-27
TC9470FN
Maximum Ratings (Ta = 25°C)
Characteristics
Symbol
Rating
Unit
V
V
DD
V
DA
V
DX
−0.3 to 6.0
−0.3 to 6.0
−0.3 to 6.0
Power supply voltage
Input voltage
V
−0.3 to V
+ 0.3
DD
V
mW
°C
in
D
Power dissipation
Operating temperature
Storage temperature
P
200
T
−15 to 50
opr
T
−55 to 150
°C
stg
Electrical Characteristics
(unless otherwise specified, Ta = 25°C, V = V = V = 2.7 V)
DD
DX
DA
DC Characteristics
Test
Characteristics
Symbol
Test Condition
Min
Typ.
Max
Unit
V
Circuit
V
DD
V
DX
V
DA
2.4
2.4
2.4
2.7
2.7
2.7
3.5
3.5
3.5
Operating power supply voltage
Current consumption
―
Ta = −15 to 50°C
XI = 16.9344 MHz
I
―ꢀ
―ꢀ
―
4.0
―
5.5
mA
V
DD
V
= V = 2.4 V
DX
DD
V
×
DD
“H” level
Input voltage
V
V
DD
IH
0.7
V
×
DD
“L” level
V
0
―
IL
0.3
“H” level
Input current
I
IH
―ꢀ
−10
―
10
µA
“L” level
I
IL
AC Characteristics (oversampling ratio = 192 fs)
Test
Circuit
Characteristics
Symbol
Test Condition
Min
Typ.
Max
Unit
1 kHz sine wave, full-scale input
Noise distortion
THD + N
S/N
1
―
85
85
―
―
−82
90
−77
―
dB
dB
dB
dB
V
V
= V = V = 2.7 V
DX DA
DD
S/N ratio
1ꢀ
= V = V = 2.7 V
DX DA
DD
1 kHz sine wave, −60dB input
Dynamic range
Crosstalk
DR
1ꢀ
90
―
conversion
CT
1ꢀ
1 kHz sine wave, full-scale input
1 kHz sine wave, full-scale input
−90
685
−80
―
Analog output level
Operating frequency
Aout
1ꢀ
mV
rms
V
V
= V = V = 2.7 V
DX DA
DD
f
―ꢀ
= V = V ≥ 2.4 V
11
―
16.9344
44.1
2.1168
―
―
―
MHz
kHz
MHz
ns
opr
DD
DX
DA
f
LRCK duty cycle = 50%
BCK duty cycle = 50%
LR
Input frequency
―ꢀ
f
1.4
―
2.9
15
15
50
BCK
Rise time
Fall time
t
r
t
f
―ꢀ
―ꢀ
LRCK, BCK pins (10% to 90%)
―
―
ns
Delay time
t
―ꢀ BCK
edge → LRCK, DATA
―
―
ns
d
16
2002-02-27
TC9470FN
·
Test circuit 1: With the use of a sample application circuit
DATA
LOUT
20 kHz
Distortion
factor
gauge
S G
BCK Application circuit example
LRCK
ROUT
Ideal LPF
MCK
SG: Anritsu: MG-22A or equivalent
LPF: Shibasoku: Built-in 725C distortion factor gauge filter
Distortion: Shibasoku: 725C or equivalent
Distortion Factor Gauge
Parameter
Filter Setting
Measured
A weight: IEC-A or equivalent
A Weight
OFF
THD + N, CT
S/N, DR
ON
·
AC characteristics stipulated point (input signal stipulation: LRCK, BCK, DATA)
10% 90%
10% 90%
50%
50%
BCK
t
f
t
f
t
t
d
d
DATA
LRCK
50%
Application Circuit
The following diagram is for reference purposes only and does not guarantee operations.
MCK
GNDX
XI
GNDD
ZD
ZD
30 pF
2.7 V
V
DA
16.9344 M
30 pF
220 Ω
L-ch Analog OUT
XO
LO
2.7 V
2.7 V
V
GNDA
VR
DX
LATCH
(SM)
22 µF
SHIFT
GNDA
RO
(EMP)
XI
EMPH
ATT
220 Ω
(DBB1)
R-ch Analog OUT
(DBB2)
DATA
BCX
V
DA
TC9236AF
Single-chip processor
for CD players
2.7 V
Aout
BCK
P/S
T1
CHCK
LRCK
V
2.7 V
DD
17
2002-02-27
TC9470FN
Package Dimensions
Weight: 0.14 g (typ.)
18
2002-02-27
TC9470FN
RESTRICTIONS ON PRODUCT USE
000707EBA
· TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
· The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
· The products described in this document are subject to the foreign exchange and foreign trade laws.
· The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
rights of the third parties which may result from its use. No license is granted by implication or otherwise under
any intellectual property or other rights of TOSHIBA CORPORATION or others.
· The information contained herein is subject to change without notice.
19
2002-02-27
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.
相关型号：
TC9472F
IC SPECIALTY CONSUMER CIRCUIT, PQFP100, 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100, Consumer IC:Other
TOSHIBA
©2020 ICPDF网 联系我们和版权申明