THNCF192MBA_技术文档

THNCFxxxMBA/BAI Series

Preliminary

TENTATIVE

TOSHIBA SMALL FORM FACTOR CARD

CompactFlash™ Card

DESCRIPTION

The THNCFxxxMBA/BAI series CompactFlash™ card is a flash technology based with ATA interface flash

memory card. It is constructed with flash disk controller chip and NAND-type （Toshiba） flash memory device.

The CompactFlash™ card operates in both 5-Volt and 3.3-Volt power supplies. It comes in capacity of 8, 16, 32, 48,

64, 96, 128, 160, 192, 256, 320, 384 and up to 512 MB unformatted for type-I card. Emulating IDE hard disk drives

and being certified in accordance with the CompactFlash™ Certification Plan it is a perfect choice of solid-state

mass-storage cards for battery backup handheld devices such as Digital Camera, Audio Player, PDA, or the

applications that require high environment tolerance with high performance sustained write speed.

FEATURES

• CompactFlash™ Compatibility

•

Certified in accordance with the CompactFlash™ Certification Plan

Substantially compatible with PC Card standard and PC Card ATA

Support for CIS implemented with 256 bytes of attribute memory

• ATA/IDE interface

•

ATA command set compatible

Support for 8- or 16-bit host transfers

Programmable and auto-wait-state generation for compatibility with any host speed using IORDY

• High performance

•

Supports PIO mode 4, both at 16.6 Mbytes/second theoretically

Sustained write : max 1.5 Mbytes/second (8MB to 48MB), 3.2 Mbytes/second (64MB to 512MB)

Sustained read : max 6.5Mbytes/second

Single +5 Volt or 3.3 Volt power supply and very low power consumption with automatic power

management.

Notes: CompactFlash™ is a trademark of SanDisk Corporation and is licensed royalty-free to the CFA, which in turn will license it

royal-free to CFA members.

CFA: CompactFlash™ Association.

Products Models

unformatted

8MB

Cylinder

248

496

744

978

733

978

611

Head

2

Sector

32

Model No.

THNCF008MBA / BAI

THNCF016MBA / BAI

THNCF032MBA / BAI

THNCF048MBA / BAI

THNCF064MBA / BAI

THNCF096MBA / BAI

THNCF128MBA / BAI

THNCF160MBA / BAI

THNCF192MBA / BAI

THNCF256MBA / BAI

THNCF320MBA / BAI

THNCF384MBA / BAI

THNCF512MBA / BAI

16MB

4

32

32MB

4

32

48MB

4

32

64MB

4

32

96MB

8

32

128MB

160MB

192MB

256MB

320MB

384MB

512MB

8

32

16

32

733

978

814

977

993

32

48

63

2002-10-20 1/48

THNCFxxxMBA/BAI Series

Preliminary

Products Specifications

• Dimensions:

Type I card :

36.4mm(L) x 42.8mm (W) x 3.3mm (H)

• Storage Capacities:

8,16, 32, 48, 64, 96,128, 160, 192, 256, 320, 384 and up to 512 MB (unformatted)

• System Compatibility:

Please refer to the compatibility list.

• Performance:

Supports PIO mode 4, both at 16.6 Mbytes/second theoretically

Sustained write max 1.5 Mbyte/sec (max) in ATA PIO mode 4 (8MB to 48MB)

Sustained write max 3.2 Mbyte/sec (max) in ATA PIO mode 4 (64MB to 512MB)

Sustained read max 6.5 Mbyte/sec (max ) in ATA PIO mode 4

• Operating Voltage:

3.3V 0.3V

5.0V 0.5V

• Power consumption:

•

5V operation

Active mode:

Write operation

:

43 mA (Typ.)

35 mA (Typ.)

1.2mA (Typ) *1

Read operation

Sleep mode

2.0mA (max.)

1.5mA (max.)

•

3.3V operation

Active mode:

Write operation

:

38 mA (Typ.)

30 mA (Typ.)

1.0mA (Typ) *1

Read operation

Sleep mode

• Environment conditions:

•

Operating temperature:

0°C to 70°C (THNCFxxxMBA Series)  Commercial grade 

−40°C to 85°C (THNCFxxxMBAI Series)  Industrial grade 

−20°C to 85°C (THNCFxxxMBA Series)  Commercial grade 

−45°C to 90°C (THNCFxxxMBAI Series)  Industrial grade 

•

Storage temperature:

2002-10-20 2/48

THNCFxxxMBA/BAI Series

Preliminary

Electrical Interface

• Physical Description:

The host is connected to the CompactFlash™ Storage Card using a standard 50-pin connector. The

connector in the host consists of two rows of 25 male contacts each on 50 mil (1.27 mm) centers.

• Pin Assignments and Pin Type:

The signal/pin assignments are listed in Table 4. Low active signals have a “ “ prefix. Pin types are Input,

Output or Input/Output. Section “Electrical specification” and “DC characteristics” defines the all input and

output type structures.

• Electrical Description:

The CompactFlash™ Storage Card functions in three basic modes: 1) PC Card ATA using I/O Mode, 2) PC

Card ATA using Memory Mode and 3) True IDE Mode, which is compatible with most disk drives.

CompactFlash™ Storage Cards are required to support all three modes. The CF Cards normally function in

the first and second modes, however they can optionally function in True IDE mode. The configuration of the

CompactFlash™ Card will be controlled using the standard PCMCIA configuration registers starting at

address 200h in the Attribute Memory space of the storage card. Or for True IDE Mode, pin 9 being grounded.

The configuration of the CF Card will be controlled using configuration registers. The configuration registers

are starting at the address defined in the Configuration Tuple (CISTPL_CONFIG) in the Attribute Memory

space of the CF Card. Signals, whose source is the host, is designated as inputs while signals that the

CompactFlash™ Storage Card sources are outputs. The CompactFlash™ Storage Card logic levels conform to

those specified in the PC Card Standard Release 8. Each signal has three possible operating modes:

1) PC Card Memory mode

2) PC Card I/O mode

3) True IDE mode

True IDE mode is required for CompactFlash™ Storage cards. All outputs from the card are totem pole

except the data bus signals that are bi-directional tri-state

2002-10-20 3/48

THNCFxxxMBA/BAI Series

Preliminary

Pin Assignments and Pin Type

True IDE Mode⁴

PC Card Memory Mode

PC Card I/O Mode

Signal

Name

In, Out

Type

Signal

Name

In, Out

Type

Signal

Name

In, Out

Type

Pin Type

1

2

3

GND

D03

D04

Ground

I4Z,OZ1

1

2

3

GND

D03

D04

Ground

I4Z,OZ1

1

2

3

GND

D03

D04

Ground

I4Z,OZ1

I/O

4

D05

D06

D07

−CE1

A10

−OE

A09

A08

A07

VCC

A06

A05

A04

A03

A02

A01

A00

D00

D01

D02

WP

I/O

I4Z,OZ1

I3U

4

D05

D06

I/O

I4Z,OZ1

I3U

4

D05

D06

I/O

I4Z,OZ1

I3U

5

I/O

5

I/O

5

I/O

6

I/O

6

D07

I/O

6

D07

I/O

7

I

7

−CE1

A10

I

7

−CS0

I

2

8

I3Z

8

I3Z

8

A10

I3Z

9

I4U

9

−OE

A09

I4U

9

−ATA SEL

I4U

2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

I3Z

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

I3Z

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

A09

I3Z

2

I3Z

A08

I3Z

A08

I3Z

2

I3Z

A07

I3Z

A07

I3Z

Power

I3Z

VCC

A06

Power

I3Z

VCC

Power

I3Z

2

I

A06

I

2

I3Z

A05

I3Z

A05

I3Z

2

I

I3Z

A04

I

I3Z

A04

I

I3Z

2

I

I3Z

A03

I

I3Z

A03

I

I3Z

I

I3Z

A02

I

I3Z

A02

A01

I

I3Z

I

I3Z

A01

I

I3Z

I

I3Z

I

I3Z

A00

I

I3Z

A00

I

I3Z

I/O

O

I/O

I

I4Z,OZ1

OT1

D00

I/O

O

I/O

I

I4Z,OZ1

OT1

D00

I/O

O

I/O

I

I4Z,OZ1

ON1

D01

D02

−IOIS16

−CD2

−CD1

−IOCS16

-CD2

-CD1

−CD2

−CD1

Ground

I4Z,OZ1

I3U

Ground

I4Z,OZ1

I3U

Ground

I4Z,OZ1

I3U

1

D11

1

D12

1

D13

1

D14

1

D15

1

−CE2

−VS1

−IORD

−CE2

−CS1

O

I

Ground

I4U

−VS1

O

I

Ground

I4U

−VS1

O

I

Ground

I4U

−IORD

35

36

37

38

39

40

41

−IOWR

−WE

I

I4U

35

36

37

38

39

40

41

−IOWR

−WE

I

I4U

35

36

37

38

39

40

41

−IOWR

I

I4U

3

−WE

RDY/BSY

VCC

O

OT1

Power

I1U

IREQ

O

OT1

Power

I1U

INTRQ

VCC

O

OZ1

Power

I1U

VCC

−^CSEL

−VS2

I

O

I

−CSEL

−VS2

RESET

I

O

I

−CSEL

−VS2

I

O

I

OPEN

I3U

OPEN

I3U

OPEN

I3U

RESET

−RESET

2002-10-20 4/48

THNCFxxxMBA/BAI Series

Preliminary

True IDE Mode⁴

PC Card Memory Mode

PC Card I/O Mode

Signal

Name

In, Out

Type

Signal

Name

In, Out

Type

Signal

Name

In, Out

Type

Pin Type

42

43

44

45

46

47

−WAIT

−INPACK

−REG

O

OT1

42

43

44

45

46

47

−WAIT

−INPACK

−REG

O

OT1

42

43

44

45

46

47

IORDY

O

ON1

OZ1

OT1

−INPACK

3

I

I3U

I

I3U

−REG

I

I3U

BVD2

I/O

I4U,OT1

I4Z,OZ1

−SPKR

I/O

I4U,OT1

I4Z,OZ1

−DASP

I/O

I4U,ON1

I4Z,OZ1

BVD1

−STSCHG

−PDIAG

1

D08

1

D09

48

I/O

I4Z,OZ1

48

I/O

I4Z,OZ1

48

I/O

I4Z,OZ1

1

49

50

D10

I4Z,OZ1

Ground

49

50

D10

I4Z,OZ1

Ground

49

50

D10

I4Z,OZ1

Ground

GND

Notes: 1. These signals are required only for 16 bit access and not required when installed in 8 bit systems. Devices should allow

for 3-state signals not to consume current.

2. Should be grounded by the host.

3. Should be tied to VCC by the host.

2002-10-20 5/48

THNCFxxxMBA/BAI Series

Preliminary

Signal Description

Signal Name

Dir

Pin No.

Description

A10 to A0

These address lines along with the-REG signal are used to select

the following: The I/O port address registers within the

CompactFlash Storage Card, the memory mapped port address

registers within the CompactFlash Storage Card, a byte in the

card’s information structure and its configuration control and status

registers.

(PC Card Memory Mode)

8,10,11,12,1

4,15,16,17,1

8,19,20

A10 to A0

I

(PC Card I/O Mode)

In True IDE Mode only A [2 : 0] are used to select the one of eight

registers in the Task File, the remaining address lines should be

grounded by the host.

A2 to A0

18,19,20

(True IDE Mode)

BVD1

This signal is asserted high as BVD1 is not supported

(PC Card Memory Mode)

This signal is asserted low to alert the host to changes in the

RDY/−BSY and Write Protect states; while the I/O interface is

configured .Its use is controlled by the Card Config and Status

Register.

−STSCHG

(PC Card I/O Mode)

I/O

46

−PDIAG

(True IDE Mode)

In the True IDE Mode, this input/output is the Pass Diagnostic

signal in the Master/Slave handshake protocol

BVD2

This signal is asserted high, as BVD2 is not supported.

(PC Card Memory Mode)

This line is the Binary Audio output from the card .If the Card does

not support the Binary Audio function, this line should be held

negated.

−SPKR

(PC Card I/O Mode)

I/O

45

−DASP

(True IDE Mode)

In the True IDE Mode, this input/output is the Disk Active/Slave

Present signal in the Master/Slave handshake protocol.

−CD1, −CD2

(PC Card Memory Mode)

These Card Detect pins are connected to ground on the

CompactFlash Storage Card. They are used by the host to

determine that the CompactFlash Storage Card is fully inserted into

its socket.

−CD1, −CD2

(PC Card I/O Mode)

O

26,25

−CD1, −CD2

(True IDE Mode)

−CE1, −CE2

These input signals are used both to select the card and to indicate

to the card whether

a byte or a word operation is being

(PC Card Memory Mode)

performed. −CE2 always accesses the odd byte of the word. −CE1

accesses the even byte or the Odd byte of the word depending on

A0 and −CE2.A multiplexing scheme based on A0, −CE1, −CE2

allows 8 bit hosts to access all data on D0~D7.

−CE1, −CE2

(PC Card I/O Mode)

I

7,32

See Access specification below.

In the True IDE Mode CS0 is the chip select for the task file

registers while CS1 is used to select the Alternate Status Register

and the Device Control Register.

−CS0, −CS1

(True IDE Mode)

−CSEL

(PC Card Memory Mode)

This signal is not used for this mode.

−CSEL

(PC Card I/O Mode)

I

39

This internally pulled up signal is used to configure this device as a

Master or a Slave when configured in the True IDE Mode.

When this pin is grounded, this device is configured as a Master.

When the pin is open, this device is configured as a Slave.

−CSEL

(True IDE Mode)

D15 to D00

These lines carry the Data, Commands and Status information

between the host and the controller. D00 is the LSB of the Even

Byte of the Word.D08 is the LSB of the Odd Byte of the Word.

(PC Card Memory Mode)

D15 to D00

31,30,29,28,

27,49,48,47,

6,5,4,3,2,

I/O

(PC Card I/O Mode)

True IDE Mode, all Task File operations occur in byte mode on the

low order bus D00 to D07 while all data transfers are 16 bit using

D00 to D15.

23,22,21

D15 to D00

(True IDE Mode)

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THNCFxxxMBA/BAI Series

Preliminary

Signal Name

Dir

Pin No.

Description

GND

(PC Card Memory Mode)

GND



1,50

Ground

(PC Card I/O Mode)

GND

(True IDE Mode)

−INPACK

This signal is not used in this mode.

(PC Card Memory Mode)

The Input Acknowledge signal is asserted by the CompactFlash

Storage Card when the card is selected and responding to an I/O

read cycle at the address that is on the address bus. This signal is

used by the host to control the enable of any input data buffers

between the CompactFlash Storage Card and the CPU.

−INPACK

O

43

(PC Card I/O Mode)

−INPACK

In True IDE Mode this output signal is not used and should not be

connected at the host.

(True IDE Mode)

−IORD

This signal is not used in this mode.

(PC Card Memory Mode)

This is an I/O Read strobe generated by the host. This signal gates

I/O data onto the bus from the CompcatFlash Storage Card when

the card is configured to use the I/O interface.

−IORD

I

34

35

9

(PC Card I/O Mode)

−IORD

In True IDE Mode, this signal has same function as in PC Card I/O

Mode.

(True IDE Mode)

−IOWR

This signal is not used in this mode.

(PC Card Memory Mode)

The I/O Write strobe pulse is used to clock I/O data on the Card

Data bus into the CompactFlash Storage Card controller registers

when the CompactFlash Storage Card is configured to use the I/O

interface.

−IOWR

I

(PC Card I/O Mode)

The clocking will occur on the negative to positive edge of the

signal (trailing edge)

−IOWR

In True IDE Mode, this signal has the same function as in PC Card

I/O Mode.

(True IDE Mode)

This is an Output Enable strobe generated by the host interface .It

is used to read data from the CompactFlash Storage Card in

Memory Mode and to read the CIS and configuration registers.

−OE

(PC Card Memory Mode)

−OE

I

In PC Card I/O Mode, this signal is used to read the CIS and

configuration registers.

(PC Card I/O Mode)

−ATA SEL

To enable True IDE Mode this input should be grounded by the

host.

(True IDE Mode)

2002-10-20 7/48

THNCFxxxMBA/BAI Series

Preliminary

Signal Name

Dir

Pin No.

Description

In Memory Mode this signal is set high when the CompactFlash

Storage Card is ready to accept a new data transfer operation and

held low when the card is busy .The Host memory card socket

must provide a pull-up resistor.

At power up and at Reset the RDY/−BSY signal is held low (busy)

until the CompactFlash Storage Card has completed its power up

or reset function. No access of any type should be made to the

CompactFlash Storage Card during this time .The RDY/-BSY

signal is held high (disabled from being busy) whenever the

following condition is true. The CompactFlash Storage Card has

been powered up with + RESET continuously disconnected or

asserted.

RDY/-BSY

(PC Card Memory Mode)

O

37

Operation-After the CompactFlash Storage Card has been

configured for I/O operation; this signal is used as interrupt

Request. This line is strobe low to generate a pulse mode interrupt

or held low for a level mode interrupt

−IREQ

(PC Card I/O Mode)

INTRQ

In True IDE Mode signal is the active high interrupt Request to the

host.

(True IDE Mode)

This signal is used during Memory Cycles to distinguish between

Common Memory and Register (Attribute) Memory accesses. High

for Common Memory, Low for Attribute Memory.

−REG

(PC Card Memory Mode)

−REG

(PC Card I/O Mode)

I

44

The signal must also be active (low) during I/O Cycles when the I/O

address is on the Bus.

−REG

(True IDE Mode)

In True IDE Mode this input signal is not used and should be

connected to VCC by the host.

RESET

When the pin is high, this signal Resets the CompactFlash Storage

Card. The CompactFlash Storage Card is Reset only at power up if

this pin is left high or open from power-up .The CompactFlash

Storage Card is also Reset when the Soft Reset bit in the Card

Configuration Option Register is set.

(PC Card Memory Mode)

RESET

I

41

(PC Card I/O Mode)

−RESET

(True IDE Mode)

In the True IDE Mode this input pin is the active low hardware reset

from the host.

VCC

(PC Card Memory Mode)

(PC Card I/O Mode)

(True IDE Mode)

−VS1 / −VS2

(PC Card Memory Mode)

(PC Card I/O Mode)

(True IDE Mode)



13,38

33,40

+5V +3.3V power

Voltage Sense Signals. -VS1 is grounded so that the

CompactFlash Storage Card CIS can be read at 3.3 volts and

−VS2 is reserved by PCMCIA for a secondary voltage.

O

−WAIT

(PC Card Memory Mode)

The −WAIT signal is driven low by the CompactFlash Storage Card

to signal the host to delay completion of a memory or I/O cycle that

is in progress.

−WAIT

(PC Card I/O Mode)

O

42

36

IORDY

In True IDE Mode this output signal may be used as IORDY

(True IDE Mode)

This is a signal driven by the host and used for strobing memory

write data to the registers of the CompactFlash Storage Card when

the card is configured I the memory interface mode. It is also used

for writing the configuration registers.

−WE

I

(PC Card Memory Mode)

−WE

(PC Card I/O Mode)

In PC Card I/O Mode, this signal is used for writing the

configuration registers.

2002-10-20 8/48

THNCFxxxMBA/BAI Series

Preliminary

Signal Name

Dir

Pin No.

Description

−WE

(True IDE Mode)

In True IDE Mode this input signal is not used and should be

connected to VCC by the host.

Memory Mode-The CompactFlash Storage Card does not have a

write protect switch. This signal is held low after the completion of

the reset initialization sequence.

WP

(PC Card Memory Mode )

I/O Operation-When the CompactFlash Storage Card is configured

for I/O Operation Pin 24 is used for the −I/O Selected is 16 Bit Port

(−IOIS16) function. A Low signal indicates that a 16 bit or odd byte

only operation can be performed at the addressed port.

−IOIS16

(PC Card I/O Mode)

O

24

−IOIS16

(True IDE Mode)

In True IDE Mode this output signal is asserted low when this

device is expecting a word data transfer cycle.

2002-10-20 9/48

THNCFxxxMBA/BAI Series

Preliminary

Access Specifications

1. Attribute access specifications

When CIS-ROM region or Configuration register region is accessed, read and write operations are executed

under the condition of –REG=”L” as follows. That region can be accessed by Byte/World/Old-byte modes, which

are defined by PC card standard specifications.

• Attribute Read Access Mode

Mode

Standby mode

−REG

−CE2

−CE1

A0

−OE

−WE

D8 to D15 D0 to D7

X

L

H

L

H

L

X

L

X

L

X

H

High-Z

invalid

High-Z

even byte

invalid

Byte access (8bit)

L

H

X

Word access (16bit)

L

even byte

High-Z

Odd byte access (8bit)

L

H

Note:

X → L or H

• Attribute Write Access Mode

Mode

Standby mode

−REG

−CE2

−CE1

A0

−OE

−WE

D8 to D15 D0 to D7

X

L

H

L

H

L

X

L

X

H

X

L

Don’t care Don’t care

Don’t care even byte

Don’t care Don’t care

Don’t care even byte

Don’t care Don’t care

Byte access (8bit)

L

H

X

Word access (16bit)

L

Odd byte access (8bit)

L

H

Note:

X → L or H

Write CIS-ROM region is invalid.

• Attribute Write Timing Example

A0~A10

−REG

−CE2/−CE1

−OE

−WE

Dout

D0~D15

Din

Read cycle

Write cycle

2002-10-20 10/48

THNCFxxxMBA/BAI Series

Preliminary

2. Task File register access specifications

There are two cases of Task File register mapping, one is mapped I/O address area, the other is mapped

Memory address area. Each case of Task File registers read and write operations is executed under the

condition as follows. That area can be accessed by Byte/World/Odd Byte modes, which are defined by PC card

standard specifications.

(1) I/O address map

•

Task File Register Read Access Mode (1)

Mode

−REG

−CE2

−CE1

A0

−IORD −IOWR

−OE

−WE

D8 to D15 D0 to D7

Standby mode

X

L

H

L

H

L

X

L

X

L

X

H

X

H

X

H

High-Z

even byte

odd byte

Byte access (8bit)

L

H

X

Word access (16bit)

L

odd byte even byte

odd byte High-Z

Odd byte access (8bit)

L

H

Note:

X → L or H

• Task File Register Write Access Mode (1)

Mode

−REG

−CE2

−CE1

A0

−IORD −IOWR

−OE

−WE

D8 to D15 D0 to D7

Standby mode

X

L

H

L

H

L

X

L

X

H

X

L

X

H

X

H

Don’t care Don’t care

Don’t care even byte

Don’t care odd byte

odd byte even byte

odd byte Don’t care

Byte access (8bit)

L

H

X

Word access (16bit)

L

Odd byte access (8bit)

L

H

Note:

X → L or H

• Task File Register Access Timing Example (1)

A0~A10

−REG

−CE2/−CE1

−IORD

−IOWR

Dout

D0~D15

Din

Read cycle

Write cycle

2002-10-20 11/48

THNCFxxxMBA/BAI Series

Preliminary

(2) Memory address map

Task File Register Read Access Mode (2)

•

Mode

−REG

−CE2

−CE1

A0

−OE

−WE

−IORD −IOWR D8 to D15 D0 to D7

Standby mode

X

H

L

H

L

X

L

X

L

X

H

X

H

X

H

High-Z

even byte

odd byte

Byte access (8bit)

L

H

X

Word access (16bit)

L

odd byte even byte

odd byte High-Z

Odd byte access (8bit)

L

H

Note:

X → L or H

• Task File Register Write Access Mode (2)

Mode

−REG

−CE2

−CE1

A0

−OE

−WE

−IORD −IOWR D8 to D15 D0 to D7

Standby mode

X

H

L

H

L

X

L

X

H

X

L

X

H

X

H

Don’t care Don’t care

Don’t care even byte

Don’t care odd byte

odd byte even byte

odd byte Don’t care

Byte access (8bit)

L

H

X

Word access (16bit)

L

Odd byte access (8bit)

L

H

Note:

X → L or H

• Task File Register Access Timing Example (2)

A0~A10

−REG

−CE2/−CE1

−OE

−WE

Dout

D0~D15

Din

Read cycle

Write cycle

2002-10-20 12/48

THNCFxxxMBA/BAI Series

Preliminary

3. True IDE Mode

The card can be configured in a True IDE This card is configured in this mode only when the-OE input signal

is asserted GND by the host. In this True IDE mode Attribute Registers are not accessible from the host.

Only I/O operation to the task file and data register is allowed. If this card is configured during power on

sequence, data register is accessed in word (16-bit). The card permits 8-bit accessed if the user issues a Set

Feature Command to put the device in 8-bit mode.

• True IDE Mode Read I/O Function

Mode

Invalid mode

−CE2

−CE1

A0~A2

−IORD

−IOWR

D8 to D15

D0 to D7

L

H

L

H

L

X

L

X

H

High-Z

odd byte

High-Z

Standby mode

Data register access

Alternate status access

Other task file access

0

even byte

Status out

Data

H

L

6H

1~7H

H

Note:

X → L or H

• True IDE Mode Write I/O Function

Mode

Invalid mode

−CE2

−CE1

A0~A2

−IORD

−IOWR

D8 to D15

D0 to D7

L

H

L

H

L

X

H

X

L

Don’t care

odd byte

Don’t care

even byte

Don’t care

Control in

Data

Standby mode

Data register access

Control register access

Other task file access

0

H

L

6H

1~7H

Don’t care

odd byte

H

Note:

X → L or H

• True IDE Mode I/O Access Timing Example

A0~A2

−CE

−IORD

−IOWR

−IOIS16

Dout

D0~D15

Din

Read cycle

Write cycle

2002-10-20 13/48

THNCFxxxMBA/BAI Series

Preliminary

Configuration register specifications

This card supports four Configuration registers for the purpose of the configuration and observation of this card.

These registers can be used in memory card mode and I/O card mode. In True IDE mode, these registers cannot be

used.

1. Configuration Option register (Address 200h)

This register is used for the configuration of the card configuration status and for the issuing soft reset to the

card.

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

SRESET

LevIREQ

INDEX

Note:

initial value → 00H

Name

R/W

Function

Setting this bit to “1”, places the card in the reset state (Card Hard Reset). This operation is equal

to Hard Reset, except this bit is not cleared. Then this bit set to “0”, places the card in the reset

state of Hard Reset (This bit is set to “0” by Hard Reset). Card configuration status is reset and

the card internal initialized operation starts when Card Hard Reset is executed, so next access to

the card should be the same sequence as the power on sequence.

SRESET

LevlREQ

(HOST->)

This bit sets to “0” when pulse mode interrupt is selected, and “1” when level mode interrupt is

selected.

R/W

This bits is used for select operation mode of the card as follows.

INDEX

When Power on, Card Hard Reset and Soft Reset, this data is “000000” for the purpose of

Memory card interface recognition.

(HOST->)

Note:

initial value → 00H

• INDEX bit assignment

INDEX bit

5

4

3

2

1

0

Card mode

Task file register address

Mapping mode

0

1

0

1

0

1

Memory card

I/O card

0H to FH, 400H to 7FFH

xx0H to xxFH

Memory mapped

Contiguous I/O mapped

Primary I/O mapped

Secondary I/O mapped

I/O card

1F0H to 1F7H, 3F6H to 3F7H

170H to 177H, 376H to 377H

I/O card

2002-10-20 14/48

THNCFxxxMBA/BAI Series

Preliminary

2. Configuration and Status register (Address 202h)

This register is used for observing the state of the card.

bit7

bit6

bit5

bit4

0

bit3

0

bit2

bit1

bit0

0

CHGED

SIGCHG

IOIS8

PWD

INTR

Note:

initial value → 00H

Name

R/W

R

Function

CHGED

This bit indicates that CRDY/−BSY bit on Pin Replacement register is set to “1”. When CHGED bit

is set to “1”, −STSCHG pin is held “L” at the condition of SIGCHG bit set to “1” and the card

configured for the I/O interface.

(CARD->)

SIGCHG

This bit is set or reset by the host for enabling and disabling the status-change signal (−STSCHG

pin). When the card is configured I/O card interface and this bit is set “1”, −STSCHG pin is

controlled by CHGED bit. If this bit is set to “0”, −STSCHG pin is kept “H”.

(HOST->)

R/W

IOIS8

The host sets this field to “1” when it can provide I/O cycles only with on 8 bit data bus (D7 to D0).

(HOST->)

PWD

When this bit is set to “1”, the card enters sleep state (Power Down mode). When this bit is reset

to “0”, the card transfers to idle state (active mode). RRDY/BSY bit on Pin Replacement Register

becomes BUSY when this bit is changed. RRDY/BSY will not become Ready until the power state

requested has been entered. This card automatically powers down when it is idle and powers

back up when it receives a command.

(HOST->)

R/W

INTR

This bit indicates the internal state of the interrupt request. This bit state is available whether I/O

card interface has been configured or not. This signal remains true until the condition, which

caused the interrupt request, has been serviced. If the −IEN bit in the Device Control Register

disables interrupts, this bit is a zero.

(CARD->)

R

2002-10-20 15/48

THNCFxxxMBA/BAI Series

Preliminary

3. Pin Replacement register (Address 204h)

This register is used for providing the state of −IREQ signal when the card configured I/O card interface.

bit7

0

bit6

0

bit5

bit4

0

bit3

1

bit2

1

bit1

bit0

0

CRDY/−BSY

RRDY/−BSY

Note:

initial value → 0CH

Name

R/W

R

Function

CRDY/−BSY

(HOST->)

This bit is set to “1” when the RRDY/−BSY bit changes state. The host may also write this bit.

RRDY/−BSY

(HOST->)

When read, this bit indicates +READY pin states. When written, this bit is used for CRDY/−BSY

bit masking.

4. Socket and Copy register (Address 206h)

This register is used for identification of the card from the other cards. Host can read and write this register.

Host should set this register before this card’s Configuration Option register set.

bit7

0

bit6

0

bit5

0

bit4

bit3

0

bit2

0

bit1

0

bit0

0

DRV#

Note:

initial value → 00H

Name

R/W

Function

These fields are used for the configuration of the plural cards. When host configures the plural

cards, written the card’s copy number in this field. In this way, host can perform the card’s

master/slave organization.

DRV#

(HOST->)

2002-10-20 16/48

THNCFxxxMBA/BAI Series

Preliminary

CIS information

CIS information of Compact Flash card is defined as follows.

Address

Data

Description of contents

CIS function

Tuple code

000H

002H

004H

006H

008H

00AH

00CH

00EH

010H

012H

014H

016H

018H

01AH

01CH

01EH

020H

022H

024H

026H

028H

02AH

02CH

02EH

030H

032H

034H

036H

038H

03AH

03CH

03EH

040H

042H

044H

046H

048H

04AH

04CH

04EH

050H

052H

054H

056H

01H

03H

D9H

01H

FFH

1CH

04H

03H

D9H

01H

FFH

18H

02H

DFH

01H

20H

04H

98H

00H

15H

20H

04H

01H

54H

4FH

53H

48H

49H

42H

41H

20H

54H

48H

4EH

43H

46H

30H

4DH

42H

41H

CISTPL_DEVICE

TPL_LINK

Tuple link

Device information

Tuple data

End of Tuple

Tuple code

Tuple link

Device information

END MARKER

CISTPL_DEVICE_OC

TPL_LINK

Conditions information

Device information

Tuple data

End of Tuple

Tuple code

Tuple link

Device information

END MARKER

CISTPL_JEDEC_C

TPL_LINK

PCMCIA’s manufacture’s JEDEC ID code

PCMCIA’s JEDEC device code

CISTPL_MANFID

Tuple data

Tuple code

Tuple link

TPL_LINK

Low byte of manufacturer’s ID code

High byte of manufacturer’s ID code

Low byte of product code

High byte of product code

CISTPL_VERS_1

Tuple data

Tuple code

Tuple link

TPL_LINK

TPLLV1_MAJOR

Tuple data

TPLLV1_MINOR

‘ T ’ (Vender Specific Strings)

‘ O ’ (Vender Specific Strings)

‘ S ’ (Vender Specific Strings)

‘ H ’ (Vender Specific Strings)

‘ I ’ (Vender Specific Strings)

‘ B ’ (Vender Specific Strings)

‘ A ’ (Vender Specific Strings)

‘

’ (Vender Specific Strings)

‘ T ’ (Vender Specific Strings)

‘ H ’ (Vender Specific Strings)

‘ N ’ (Vender Specific Strings)

‘ C ’ (Vender Specific Strings)

‘ F ’ (Vender Specific Strings)

‘ 0 ’ (Card capacity dependent strings)

‘ M ’ (Card capacity dependent strings)

‘ B ’ (Vender Specific Strings)

‘ A ’ (Vender Specific Strings)

2002-10-20 17/48

THNCFxxxMBA/BAI Series

Preliminary

Address

Data

Description of contents

CIS function

Tuple data

058H

05AH

05CH

05EH

060H

062H

064H

066H

068H

06AH

06CH

06EH

070H

072H

074H

076H

078H

07AH

07CH

07EH

080H

082H

084H

086H

088H

08AH

08CH

08EH

090H

092H

094H

096H

098H

09AH

09CH

09EH

0A0H

0A2H

0A4H

0A6H

0A8H

0AAH

0ACH

0AEH

0B0H

0B2H

0B4H

20H

00H

FFH

21H

02H

04H

01H

22H

02H

01H

22H

03H

02H

0CH

0FH

1AH

05H

01H

03H

00H

02H

0FH

1BH

08H

C0H

A1H

01H

55H

08H

00H

20H

1BH

06H

00H

01H

21H

B5H

‘

’

Null Terminator

Tuple data

End of Tuple

Tuple code

Tuple link

Reserved (Vender Specific Strings)

END MARKER

CISTPL_FUNCID

TPL_LINK

IC Card function code

System initialization bit mask

CISTPL_FUNCE

Tuple data

Tuple code

Tuple link

TPL_LINK

Type of extended data

Function information

Tuple data

Tuple code

Tuple link

CISTPL_FUNCE

TPL_LINK

Type of extended data

Function information

Tuple data

Tuple code

Tuple link

Function information

CISTPL_CONFIG

TPL_LINK

Size field

Tuple data

Tuple code

Tuple link

Index number of last entry

Configuration register base address (Low)

Configuration register base address (High)

Configuration register present mask

CISTPL_CFTABLE_ENTRY

TPL_LINK

Configuration Index Byte

Interface Descriptor

Tuple data

Tuple code

Tuple link

Feature Select

Vcc Selection Byte

Nom V Parameter

Memory length (256 byte pages)

Misc features

CISTPL_CFTABLE_ENTRY

TPL_LINK

Configuration Index Byte

Feature Select

Tuple data

Vcc Selection Byte

Nom V Parameter

2002-10-20 18/48

THNCFxxxMBA/BAI Series

Preliminary

Address

Data

Description of contents

CIS function

Tuple data

0B6H

0B8H

0BAH

0BCH

0BEH

0C0H

0C2H

0C4H

0C6H

0C8H

0CAH

0CCH

0CEH

0D0H

0D2H

0D4H

0D6H

0D8H

0DAH

0DCH

0DEH

0E0H

0E2H

0E4H

0E6H

0E8H

0EAH

0ECH

0EEH

0F0H

0F2H

0F4H

0F6H

0F8H

0FAH

0FCH

0FEH

100H

102H

104H

106H

108H

10AH

10CH

10EH

110H

112H

1EH

4DH

1BH

0AH

C1H

41H

99H

01H

55H

64H

F0H

FFH

20H

1BH

06H

01H

21H

B5H

1EH

4DH

1BH

0FH

C2H

41H

99H

01H

55H

EAH

61H

F0H

01H

07H

F6H

03H

01H

EEH

20H

1BH

06H

02H

01H

21H

B5H

1EH

4DH

Nom V Parameter

Peak I Parameter

CISTPL_CFTABLE_ENTRY

TPL_LINK

Tuple data

Tuple code

Tuple link

Configuration Index Byte

Interface Descriptor

Feature Select

Tuple data

Tuple code

Tuple link

Vcc Selection Byte

Nom V Parameter

I/O Parameter

IRQ parameter

IRQ request mask

Misc features

CISTPL_CFTABLE_ENTRY

TPL_LINK

Configuration Index Byte

Feature Select

Tuple data

Tuple code

Tuple link

Vcc Selection Byte

Nom V Parameter

Peak I Parameter

CISTPL_CFTABLE_ENTRY

TPL_LINK

Configuration Index Byte

Interface Descriptor

Feature Select

Tuple data

Tuple code

Tuple link

Vcc Selection Byte

Nom V Parameter

I/O parameter

I/O range length and size

Base address

Address length

Base address

Address length

IRQ parameter

Misc features

CISTPL_CFTABLE_ENTRY

TPL_LINK

Configuration Index Byte

Feature Select

Tuple data

Vcc Selection Byte

Nom V Parameter

Peak I Parameter

2002-10-20 19/48

THNCFxxxMBA/BAI Series

Preliminary

Address

Data

Description of contents

CIS function

Tuple code

114H

116H

118H

11AH

11CH

11EH

120H

122H

124H

126H

128H

12AH

12CH

12EH

130H

132H

134H

136H

138H

13AH

13CH

13EH

140H

142H

144H

146H

148H

14AH

1BH

0FH

C3H

41H

99H

01H

55H

EAH

61H

70H

01H

07H

76H

03H

01H

EEH

20H

1BH

06H

03H

01H

21H

B5H

1EH

4DH

14H

00H

FFH

CISTPL_CFTABLE_ENTRY

TPL_LINK

Tuple link

Configuration Index Byte

Interface Descriptor

Feature Select

Tuple data

Tuple code

Tuple link

Vcc Selection Byte

Nom V Parameter

I/O parameter

I/O range length and size

Base address

Address length

Base address

Address length

IRQ parameter

Misc features

CISTPL_CFTABLE_ENTRY

TPL_LINK

Configuration Index Byte

Feature Select

Tuple data

Tuple code

Tuple link

Vcc Selection Byte

Nom V Parameter

Peak I Parameter

CISTPL_NO_LINK

TPL_LINK

CISTPL_END

End of Tuple

2002-10-20 20/48

THNCFxxxMBA/BAI Series

Preliminary

Task File Register specification

These registers are used for reading and writing the storage data in this card. These registers are mapped five

types by the configuration of INDEX in Configuration Option register. The decoded addresses are shown as

follows.

Memory map (INDEX=0)

−REG

A10

A9~A4

A3

A2

A1

A0

Offset

−OE=L

Data register

−WE=L

Data register

1

0

1

X

0

1

X

0

1

0

1

X

0

1

0

1

0

1

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0H

1H

2H

3H

4H

5H

6H

7H

8H

9H

DH

EH

FH

8H

9H

Error register

Feature register

Sector count register

Sector number register

Cylinder low register

Cylinder high register

Drive head register

Status register

Sector count register

Sector number register

Cylinder low register

Cylinder high register

Drive head register

Command register

Dup. even data register

Dup.odd data register

Dup.feature register

Device control register

Reserved

Dup. Even data register

Dup.odd data register

Dup.error register

Alt. status register

Drive address register

Even data register

Odd data register

Even data register

Odd data register

Contiguous I/O map (INDEX=1)

−REG

A10~A4

A3

A2

A1

A0

Offset

−OE=L

−WE=L

0

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0H

1H

2H

3H

4H

5H

6H

7H

8H

9H

DH

EH

FH

Data register

Error register

Feature register

Sector count register

Sector number register

Cylinder low register

Cylinder high register

Drive head register

Status register

Sector count register

Sector number register

Cylinder low register

Cylinder high register

Drive head register

Command register

Dup. even data register

Dup.odd data register

Dup.feature register

Device control register

Reserved

Dup. even data register

Dup.odd data register

Dup.error register

Alt. status register

Drive address register

2002-10-20 21/48

THNCFxxxMBA/BAI Series

Preliminary

Primary I/O map (INDEX=2)

−REG

A10

A9~A4

A3

A2

A1

A0

−IORD=L

Data register

−IOWR=L

Data register

0

X

1FH

3FH

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Error register

Feature register

Sector count register

Sector number register

Cylinder low register

Cylinder high register

Drive head register

Status register

Sector count register

Sector number register

Cylinder low register

Cylinder high register

Drive head register

Command register

Device control register

Reserved

Alt. status register

Drive address register

Secondary I/O map (INDEX=3)

−REG

A10

A9~A4

A3

A2

A1

A0

−IORD=L

−IOWR=L

0

X

17H

37H

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Data register

Error register

Feature register

Sector count register

Sector number register

Cylinder low register

Cylinder high register

Drive head register

Status register

Sector count register

Sector number register

Cylinder low register

Cylinder high register

Drive head register

Command register

Device control register

Reserved

Alt. status register

Drive address register

True IDE Mode I/O map

−CE2

−CE1

A2

A1

A0

−IORD=L

−IOWR=L

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Data register

Error register

Feature register

Sector count register

Sector number register

Cylinder low register

Cylinder high register

Drive head register

Status register

Sector count register

Sector number register

Cylinder low register

Cylinder high register

Drive head register

Command register

Device control register

Reserved

Alt. status register

Drive address register

2002-10-20 22/48

THNCFxxxMBA/BAI Series

Preliminary

1. Data register

This register is a 16-bit register that has read/write ability, and it is used for transferring 1 sector data

between the card and the host. This register can be accessed in word mode and byte mode. This register

overlaps the Error or Feature register.

bit15 bit14 bit13 bit12

bit11

bit10

bit9

bit8

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

D0 to D15

2. Error register

This register is a read only register, and it is used for analyzing the error content at the card accessing. This

register is valid when the BSY bit in Status register and Alternate Status register are set to “0”(Ready).

bit7

bit6

bit5

0

bit4

bit3

0

bit2

bit1

0

bit0

BBK

UNC

IDNF

ABRT

AMNF

bit

Name

Function

7

6

4

BBK(Bad Block detected)

UNC(Data ECC error)

IDNF(ID Not Found)

This bit is set when a Bad Block is detected in requester ID field.

This bit is set when Uncorrectable error is occurred at reading the card.

The requested sector ID is in error or cannot be found.

This bit is set if the command has been aborted because of the card status

condition.(Not ready, Write fault, Invalid command, etc.)

2

0

ABRT(ABoRTed command)

AMNF(Address Mark Not Found) This bit is set in case of a general error.

3. Feature register

This register is write-only register, and provides information regarding features of the drive that the host

wishes to utilize.

bit7

bit6

bit5

bit4

bit3

Feature byte

bit2

bit1

bit0

4. Sector count register

This register contains the numbers of sectors of data requested to be transferred on a read or write operation

between the host and the card. If the value of this register is zero, a count of 256 sectors is specified. In

plural sector transfer, if not successfully completed, the register contains the number of sectors, which need to

be transferred in order to complete, the request.

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

Sector count byte

5. Sector number register

This register contains the starting sector number, which is started by following sector transfer command.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

Sector number byte

2002-10-20 23/48

THNCFxxxMBA/BAI Series

Preliminary

6. Cylinder low register

This register contains the low 8-bit of the starting cylinder address, which is started by following sector

transfer command.

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

Cylinder low byte

7. Cylinder high register

This register contains the high 8-bit of the starting cylinder address, which is started by following sector

transfer command.

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

Cylinder high byte

8. Drive head register

This register is used for selecting the Drive number and Head number for the following command.

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

Obsolete

LBA

Obsolete

DRV

Head number

bit

Name

Function

7

6

Obsolete

This bit is normally set to “1”.

LBA is a flag to select either Cylinder/Head/Sector (CHS) or Logical Block Address

(LBA) mode. When LBA = 0, CHS mode is selected. When LBA=1, LBA mode is

selected. In LBA mode, the Logical Block Address is interrupted as follows:

LBA07~LBA00：Sector Number Register D7 to D0.

LBA

LBA15~LBA08：Cylinder Low Register D7 to D0.

LBA23~LBA16：Cylinder High Register D7 to D0.

LBA27~LBA24：Drive / Head Register bits HS3 to HS0.

5

4

Obsolete

This bit is normally set to “1”.

This bit is used for selecting the Master (Card 0) and Slave (Card 1) in

Master/Slave organization. The card is set to be Card 0 or 1 by using DRV# of the

Socket and Copy register.

DRV (Drive select)

Head number

This bit is used for selecting the Head number for the following command. Bit 3 is

MSB.

3

2002-10-20 24/48

THNCFxxxMBA/BAI Series

Preliminary

9. Status register

This register is read only register, and it indicates the card status of command execution. When this register

is read in configured I/O card mode (INDEX=1,2,3) and level interrupt mode, −IREQ is negated.

bit7

bit6

bit5

bit4

bit3

bit2

bit1

IDX

bit0

BSY

DRDY

DWF

DSC

DRQ

CORR

ERR

bit

Name

Function

This bit is set when the card internal operation is executing. When this bit is set to

“1”, other bits in this register are invalid.

7

6

BSY (BuSY)

If this bit and DSC bit are set to “1”, the card is capable of receiving the read or

write or seek requests. If this bit is set to “0”, the card prohibits these requests.

DRDY (Drive ReaDY)

5

4

DWF (Drive Write Fault)

This bit is set if this card indicates the write fault status.

This bit is set when the drive seeks complete.

DSC (Drive Seek Complete)

DRQ (Data ReQuest)

This bit is set when the information can be transferred between the host and Data

register. This bit is cleared when the card receives the other command.

3

This bit is set when a correctable data error has been occurred and the data has

been corrected.

2

1

CORR (CORRected data)

IDX (InDeX)

This bit is always set to “0”.

This bit is set when the previous command has ended in some type of error. The

error information is set in the error register. This bit is cleared by the next

command.

0

ERR (ERRor)

10. Alternate status register

This register is the same as Status register in physically, so the bit assignment refers to previous item of

Status register. But this register is different from Status register that –IREQ is not negated when data read.

11. Command register

This register is write only register, and it is used for writing the command to execute the requested operation.

The command code is written in the command register, after the parameter is written in the Task File when

the card is in Ready state.

2002-10-20 25/48

THNCFxxxMBA/BAI Series

Preliminary

Used parameter

Command

Command code

FR

SC

SN

CY

DR

HD

LBA

Check power mode

Execute drive diagnostic

Erase sector

E5H or 98H

90H

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

C0H

Format track

50H

Identify Drive

ECH

Idle

E3H or 97H

E1h or 95h

91H

Idle immediate

Initialize drive parameters

Read buffer

E4H

Read multiple

Read long sector

Read sector

C4H

22H or 23H

20H or 21H

40h or 41h

1Xh

Read verify sector

Recalibrate

Request sense

Seek

03H

7XH

Set features

EFH

Set multiple mode

Set sleep mode

Stand by

C6H

E6h or 99h

E2h or 96h

E0h or 94h

87H

Stand by immediate

Translate sector

Wear level

F5H

Write buffer

E8H

Write long sector

Write multiple

Write multiple w/o erase

Write sector

32h or 33h

C5H

CDH

30H or 31H

38H

Write sector w/o erase

Write verify

3CH

Notes: FR: Feature register

SC: Sector Count register

SN: Sector Number register

CY: Cylinder register

DR: DRV bit of Drive Head register

HD: Head Number of Drive Head Supported

Y: The register contains a valid parameter for this command.

N: The register does not contain a valid parameter for this command.

2002-10-20 26/48

THNCFxxxMBA/BAI Series

Preliminary

12. Device control register

This register is write only register, and it is used for controlling the card interrupt request and issuing an

ATA soft reset to the card.

bit7

X

bit6

X

bit5

X

bit4

X

bit3

1

bit2

bit1

bit0

0

SRST

nIEN

bit

Name

Function

7 to 4

3

X

1

Don’t care

This bit is set to “1”.

This bit is set to “1” in order to force the card to perform Task File Reset operation.

This does not change the Card Configuration registers as a Hardware Reset does.

The card remains in Reset until this bit is reset to “0”.

2

SRST(Software ReSeT)

This bit is used for enabling −IREQ. When this bit is set to “0”, −IREQ is enabled.

When this bit is set to “1”, −IREQ is disabled.

1

0

nIEN(Interrupt Enable)

0

This bit is set to “0”.

13. Drive Address register

This register is read only register, and it is used for confirming the drive status. This register is provides for

compatibility with the AT disk drive interface. It is recommended that this register is not mapped into the

host’s I/O space because of potential conflicts on bit7.

bit7

X

bit6

bit5

bit4

bit3

bit2

bit1

bit0

nWTG

nHS3

nHS2

nHS1

nHS0

nDS1

nDS0

bit

Name

Function

7

6

X

This bit remains tri-state when host read access.

This bit is set as 0

nWTG (WriTing Gate)

These bits are the negative value of Head Select bits (bit3 to 0) in Drive/Head

register.

5 to 2

nHS3 to nHS0 (Head Select3-0)

1

0

nDS1 (Idrive Select1)

nDS0 (Idrive Select0)

This bit is 0 when drive 1 is active and selected.

This bit is 0 when drive 0 is active and selected.

2002-10-20 27/48

THNCFxxxMBA/BAI Series

Preliminary

ATA Command specifications

This table summarizes the ATA command set with the paragraphs. Following shows the supported commands

and command codes, which are written in command registers.

ATA Command Set

No.

Command set

Code

FR

SC

SN

CY

DR

HD

LBA

1

2

3

4

5

6

7

8

9

Check power mode

Execute drive diagnostic

Erase sector(s)

Format track

E5h or 98h

90H



Y



Y



Y



Y



Y



Y

C0H

50H

Y



Y

Identify Drive

ECH



Y



Y



Y



Y

Idle

E3h or 97h

E1h or 95h

91H

Idle immediate

Initialize drive parameters

Read buffer



Y

E4H



Y



Y

10 Read multiple

11 Read long sector

12 Read sector (s)

13 Read verify sector (s)

14 Recalibrate

C4H

22H or 23H

20H or 21H

40H or 41H

1XH



Y



Y



Y



Y



Y



Y

15 Request sense

16 Seek

03H

7XH

17 Set features

EFH



Y



Y



Y



Y

18 Set multiple mode

19 Set sleep mode

20 Stand by

C6H



E6h or 99h

E2h or 96h

E0h or 94h

87H



Y

21 Stand by immediate

22 Translate sector

23 Wear level

F5H



Y



Y



Y



Y

24 Write buffer

E8H



Y

25 Write long sector

26 Write multiple

27 Write multiple w/o erase

28 Write sector

32H or 33H

C5H

Y

CDH

Y

30H or 31H

38H

Y

29 Write sector w/o erase

30 Write verify

Y

3CH

Y

Notes: FR: Feature register

SC: Sector Count register (00H~FFH)

SN: Sector Number register (01H~20H)

CY: Cylinder Low / High register

DR: Drive bit of Drive / Head register

HD: Head No.(0~3) of Drive / Head register

LBA: Logical Block Address Mode supported

Y: Set up

: Not set up

2002-10-20 28/48

THNCFxxxMBA/BAI Series

Preliminary

(1)

(2)

Check Power Mode (code: E5h or 98h): This command checks the power mode.

Execute Drive Diagnostic (code: 90h): This command performs the internal diagnostic tests implemented

by the Card.

(3)

(4)

Erase Sector(s)(code: C0h): This command is used to erase data sectors.

Format Track (code: 50h): This command writes the desired head and cylinder of the selected drive with a

vendor unique data pattern (typically FFh or 00h). To remain host backward compatible, the card expects

one sector (512Bytes) of data from the host to follow the command with same protocol as the Write Sector

Command.

(5)

Identify Drive (code: ECh): This command enables the host to receive parameter information from the

Card.

Identify Drive Information

Word address Default value

Total bytes

Data field type information

0

848AH

XXXX

0000H

00XXH

0000H

XXXX

0000H

XXXX

0001H

0004H

XXXX

0001H

0000H

0200H

0000H

0200H

0000H

XXXX

0101H

XXXX

0000H

2

General configuration bit-significant information

Default number of cylinders

1

2

Reserved

3

2

Default number of heads

4

2

Number of unformatted bytes per track

Number of unformatted bytes per sector

Default number of sectors per track

Number of sectors per card(Word7=MSW,Words=LSW)

Reserved

5

6

2

7 to 8

9

4

2

10 to 19

20

2

Serial number in ASCII

Buffer type (single ported)

21

2

Buffer size in 512 byte increments

# of ECC bytes passed on Read/Write Long Commands

Firmware revision in ASCII etc.

Maximum of 1 sector on Read/Write Multiple command

Double Word not supported

22

2

23 to 46

47

48

2

48

2

49

2

Capabilities: DMA NOT Supported(bit 8), LBA supported (bit9)

Reserved

50

2

51

2

PIO data transfer cycle timing mode 2

DMA data transfer cycle timing mode not Supported

Reserved

52

2

53 to 58

59

12

2

Multiple sector setting is valid

60 to 61

62 to 255

4

Total number of sectors addressable in LBA Mode

Reserved

388

(6)

Idle (code: E3h or 97h): This command causes the Card to set BSY, enter the Idle mode, clear BSY and

generate an interrupt. If sector count is non-zero, the automatic power down mode is enabled. If the

sector count is zero, the automatic power mode is disabled.

(7)

(8)

Idle Immediate (code: E1h or 95h): This command causes the Card to set BSY, enter the Idle(Read) mode,

clear BSY and generate an interrupt.

Initialize Drive Parameters (code: 91h): This command enables the host to set the number of sectors per

track and the number of heads per cylinder.

(9)

Read Buffer (code: E4h): This command enables the host to read the current contents of the card’s sector

buffer.

(10)

Read Multiple (code: C4h): This command performs similarly to the Read Sectors command.

Interrupts are not generated on each sector, but on the transfer of a block, which contains the number of

sectors defined by a Set Multiple command.

2002-10-20 29/48

THNCFxxxMBA/BAI Series

Preliminary

(11)

(12)

Read Long Sector (code 22h or 23h): This command performs similarly to the Read Sector(s) command

except that it returns 516 bytes of data instead of 512 bytes.

Read Sector(s) (code 20h or 21h): This command reads from 1 to 256 sectors as specified in the Sector

Count register. A sector count of 0 requests 256 sectors. The transfer beings specified in the Sector

Number register.

(13)

(14)

(15)

(16)

(17)

Read Verify Sector(s) (code: 40h or 41h): This command is identical to the Read Sectors command, except

that DRQ is never set and no data is transferred to the host.

Recalibrate (code: 1Xh): This command is effectively a NOP command to the Card and is provided for

compatibility purposes.

Request Sense (code: 03h): This command requests an extended error code after command ends with an

error.

Seek (code: 7Xh): This command is effectively a NOP command to the Card although it does perform a

range check.

Set Features (code: EFh): This command is used by the host to establish or select certain features.

Features

01H

Operation

Enable 8-bit data transfers.

Disable Read Look Ahead.

55H

66H

81H

BBH

CCH

Disable Power on Reset (POR) establishment of defaults at Soft Reset.

Disable 8-bit data transfers.

4 bytes of data apply on Read/Write Long commands.

Enable Power on Reset (POR) establishment of defaults at Soft Reset.

(18)

(19)

(20)

(21)

(22)

(23)

Set Multiple Mode (code: C6h): This command enables the Card to perform Read and Write Multiple

operations and establishes the block count for these commands.

Set Sleep Mode (code: E6h or 99h): This command causes the Card to set BSY, enter the Sleep mode,

clear BSY and generate an interrupt.

Stand By (code: E2h or 96h): This command causes the Card to set BSY, enter the Sleep mode (which

corresponds to the ATA “Standby” Mode), clear BSY and return the interrupt immediately.

Stand By Immediate (code: E0h or 94h): This command causes the Card to set BSY, enter the Sleep mode

(which corresponds to the ATA “Standby” Mode), clear BSY and return the interrupt immediately.

Translate Sector (code: 87h): This command allows the host a method of determining the exact number of

times a use sector has been erased and programmed.

Wear Level (code: F5h): This command effectively a NOP command and only implemented for backward

compatibility. The Sector Count Register will always be returned with a 00h indicating Wear Level is

not needed.

(24)

(25)

(26)

Write Buffer (code: E8h): This command enables the host to overwrite contents of the Card’s sector buffer

with any data pattern desired.

Write Long Sector (code: 32h or 33h): This command is provided for compatibility purposes and is

similar to the Write Sector(s) command except that it writes 516 bytes instead of 512 bytes.

Write Multiple (code: C5h): This command is similar to the Write Sectors command. Interrupts are not

presented on each sector, but on the transfer of a block which contains the number of sectors defined by

Set Multiple command.

(27)

(28)

Write Multiple without Erase (code: CDh): This command is similar to the Write Multiple command with

the exception that an implied erase before write operation is not performed.

Write Sector(s): (code: 30h or 31h): This command writes from 1 to 256 sectors as specified in the Sector

Count register. A sector count of zero requests 256 sectors. The transfer begins at the sector specified

in the Sector Number register.

(29)

(30)

Write Sector(s) without Erase (code: 38h): This command is similar to the Write Sector(s) command with

the exception that an implied erase before write operation is not performed.

Write Verify (code: 3Ch): This command is similar to the Write Sector(s) command, except each sector is

verified immediately after being written.

2002-10-20 30/48

THNCFxxxMBA/BAI Series

Preliminary

Sector Transfer Protocol

1. Sector read: Sector read procedure after the card configured I/O interface is shown as follows.

start

I/O Access, INDEX=1

Set the cylinder low/high register

Set the head No. of drive head register

Set the sector number register

Set in sector count register

(1) Set the logical sector number

Set “20h” in command register

Read the status register

(2) Set read sector command

N

(3) Polling until ready

“51h”?

Y

“58h”?

Y

Read 256 times the data register

(512 bytes)

(4) Burst data transfer

(5) Read more sectors?

error handle

N

Get all data

Y

Wait the command input

(1)

(2)

(3)

(4)

(5)

A0~A10

−CE1

4H 5H 6H 3H 2H 7H

7H

0H

7H

−CE2

−IOWR

−IORD

D0~D15

01H 20H

D0H→58H (Data transfer)

D0H→50H

−IREQ

2002-10-20 31/48

THNCFxxxMBA/BAI Series

Preliminary

2. Sector write: write sector procedure after the card configured I/O interface is shown as follows.

start

I/O Access, INDEX=1

Set the cylinder low/high register

Set the head No. of drive head register

Set the sector number register

Set in sector count register

(1) Set the logical sector number

(2) Set write sector command

Set “30h” in command register

Read the status register

N

(3) Polling until ready

(4) Burst data transfer

“51h”?

“58h”?

Y

Read 256 times the data register

(512 bytes)

N

Y

all data

Y

Read the status register

(5) Read the Status Register

N

“51h”?

“50h”?

Y

Wait the command input

Error handle

(1)

(2)

(3)

(4)

(5)

A0~A10

−CE1

4H 5H 6H 3H 2H 7H

7H

0H

7H

−CE2

−IOWR

−IORD

D0~D15

01H 30H

D0H→58H (Data transfer)

D0H→50H

−IREQ

2002-10-20 32/48

THNCFxxxMBA/BAI Series

Preliminary

Card System performance

ITEM

Performance

Set up times (Reset to Ready)

Set up times (Sleep to Idle)

400 ms (max.) *1

100µs (max.)

Set up times (Deep Power Down to Idle)

Data transfer rate to / from host

Sustained read transfer rate

Sustained write transfer rate

Controller overhead (Command to DRQ)

Data transfer cycle end to ready (Sector write)

Notes:

4 ms (max.)

16.6 M byte / s burst (max.), theoretically

6.5 M byte / s (max.), actually *2

1.5 M byte / s (max.) <8MB~48MB>, actually *2

3.2 M byte / s (max.) <64MB~512MB>, actually *2

4 ms (max.)

500µs (typ.), 50ms (max.)

1. This parameter will be changed for different capacity and NAND type flash memory, the typical set up time for 2 Giga Bytes

flash card is 325ms

2. The actual transfer rate is measured under ATA PIO mode 4 with single cycle time as 120ns.

ELECTRICAL SPECIFICATION

SYMBOL

PARAMETER

MIN

MAX

+ 0.3

TYP

UNIT

V

NOTES

V

, V

All input / output voltage

−0.3

V



IN

OUT

CC

Power Supply Voltage

−0.6

6.0



V

CC

(Absolute Maximum Ratings)

4.5

3.0

0

5.5

3.6

70

85

90

5.0

3.3

25



V

Power Supply Voltage

V

(Recommended Operation Condition)

V

°C

Commercial grade *1

Industrial grade *2

Commercial grade *1

Industrial grade *2

T

Operating Temperature

Storage Temperature

opr

stg

−40

−20

−45



Notes:

1. THNCFxxxMBA Series (Commercial grade)

2. THNCFxxxMBAI Series (Industrial grade)

2002-10-20 33/48

THNCFxxxMBA/BAI Series

Preliminary

Input Leakage Current

Type

SYMBOL

PARAMETER

CONDIDTION

MIN

MAX

TYP

UNIT NOTES

IxZ

IL

Input leakage current

Pull Up Resistor

V

=Vcc / V =GND

-1

50

1



uA

*1

IH

IL

RPU1

RPD1

IxU

IxD

Vcc = 5.0V

500

kΩ

Pull Down Resister

Notes:

1. x refers to the characteristics described in section “DC Characteristics ( Input Characteristics)”. For example, I1U indicates a

pull up resister with a type 1 input characteristics.

Output Drive Type

Type

OUTPUT TYPE

VALID CONDITIONS

NOTES

OTx

OZx

OPx

ONx

Totempole

I

& I

*1

OH

OL

Tri-State N-P Channel

P-Channel only

I

Only

OH

N-Channel only

I

OL

Notes:

1. x refers to the characteristics described in section “DC Characteristics ( Output Drive Characteristics)”. For example, OT1

refers to Totempole output with a type 1 Output drive characteristics.

2002-10-20 34/48

THNCFxxxMBA/BAI Series

Preliminary

DC CHARACTERISTICS (V = 3.3 V 0.3V, V = 5 V 0.5V)

CC

Ta = 0°C~70°C for THNCFxxxMBA (Commercial grade)

Ta = -40°C~85°C for THNCFxxxMBAI (Industrial grade)

SYMBOL

PARAMETER

MIN

MAX

TYP.

UNIT

TEST CONDITIONS

I

Input leakage current

Output leakage current



1



µA



LI

V

= high

OUT

LO

impedance

= 3.3V

FORCE

−I

Pull-up current (Resistivity)



43 (75)

−48 / (206)

1.0

µA (kΩ)

V

PU

PD

Pull-down current (Resistivity)

V

= 0V

FORCE

1.5

2.0

V

= 3.3V

CC

I

Sleep mode current

mA

CCS

CCO

1.2

V

= 5V

CC

Operating current @ 3.3V

Write operation



38

30

mA

V

= 3.3V operation

CC

Read operation

Operating current @ 5V

Write operation



43

35

mA

V

= 5V operation

CC

Read operation

Input Characteristics

Type

SYMBOL

PARAMETER

MIN

MAX

TYP

UNIT

CONDITION

V

Input High Voltage CMOS

2.0

V

= 3.3 V

IH

IL

CC



(5V Tolerance)

V

= 5 V

CC

1

V

Input Low Voltage CMOS

(5V Tolerance)

1.0

V

= 3.3 V

= 5 V



V

CC

Input High Voltage

2.0

V

= 3.3 V

= 5 V

IH

IL



(3.3V : CMOS 5V: TTL)

V

CC

2

3

4

Input Low Voltage CMOS

(3.3V : CMOS 5V: TTL)

1.0

0.8

V

= 3.3 V

= 5 V



V

CC

V

Input High Voltage CMOS with Schmitt trigger

(5V Tolerance)

2.5

2.1

V

= 3.3 V

= 5 V

V

T+

T-

V

CC

Input Low Voltage CMOS with Schmitt trigger

(5V Tolerance)

0.9

1.2

V

= 3.3 V

= 5 V



V

CC

Input High Voltage with Schmitt trigger

(3.3V : CMOS 5V: TTL)

2.3

2.0

2.1

1.8

V

= 3.3 V

= 5 V



T+

T-

V

CC

Input Low Voltage with Schmitt trigger

(3.3V : CMOS 5V: TTL)

1.0

0.8

1.2

1.1

V

= 3.3 V

= 5 V



V

CC

Output Drive Characteristics

Type

1

SYMBOL

PARAMETER

MIN

MAX

TYP

UNIT

V

CONDITION

V

Output High Voltage

Output Low Voltage

V

− 0.8



I

= −4mA

= 4mA

OH

OL

CC

OH

I

V



Gnd + 0.4

OL

2002-10-20 35/48

THNCFxxxMBA/BAI Series

Preliminary

AC CHARACTERISTICS (V = 3.3 V 0.3V, V = 5 V 0.5V)

CC

Ta = 0°C~70°C for THNCFxxxMBA (Commercial grade)

Ta = -40°C~85°C for THNCFxxxMBAI (Industrial grade)

Attribute Memory Read AC Characteristics

SYMBOL

PARAMETER

MIN

MAX

TYP

UNIT

NOTES

t

Read cycle time

250



5



250

125

100



CR

(A)

Address access time

−CE access time

A

(CE)

(OE)

−OE access time

(CE)

(OE)

(CE)

(OE)

Output disable time (−CE)

Output disable time (−OE)

Output enable time (−CE)

Output enable time (−OE)

Data valid time (A)

DIS

EN

ns

5



(A)

0



V

(A)

Address setup time

30



SU

Attribute Memory Read Timing

t

(R)

C

An

t

(A)

A

−REG

−CE

t

(A)

SU

t (A)

V

t (CE)

A

t

(CE)

EN

t

(CE)

(OE)

DIS

t (OE)

A

−OE

t

DIS

t

(OE)

EN

D

OUT

2002-10-20 36/48

THNCFxxxMBA/BAI Series

Preliminary

Attribute Memory Write AC Characteristics

SYMBOL

PARAMETER

MIN

MAX

TYP

UNIT

NOTES

t

Write cycle time

250

150

30



CW

(WE)

Write pulse time

W

(A)

Address setup time

SU

H

ns

(D-WEH) Data setup time (−WE)

80

(D)

Data hold time

30

(WE)

Write recover time

30

REC

Attribute Memory Read Timing

t

(W)

C

An

−REG

t

(A)

SU

t

(WE)

REC

t

W

(WE)

−WE

−CE

−OE

t (D)

H

t

(D-WEH)

SU

D

IN

Data in Valid

2002-10-20 37/48

THNCFxxxMBA/BAI Series

Preliminary

I/O Access Read AC Characteristics

SYMBOL

PARAMETER

MIN

MAX

TYP

UNIT

NOTES

t

(IORD)

Data delay after −IORD

Data hold following −IORD

−IORD pulse width



0

100



45

35



D

H

(IORD)

165

70

W

A (IORD)

Address setup before −IORD

SU

t A (IORD)

Address hold following −IORD

−CE setup before −IORD

−CE hold following −IORD

−REG setup before −IORD

−REG hold following −IORD

20

5

H

t

CE (IORD)

SU

ns

t CE (IORD)

20

5

H

t

REG (IORD)

SU

t REG (IORD)

0

H

t

INPACK (IORD) −INPACK delay failing from −IORD

0

DF

DR

INPACK (IORD) −INPACK delay rising from −IORD



IOIS16 (ADR)

−IOIS16 delay failing from address

−IOIS16 delay rising from address

DF

DR

IOIS16 (ADR)

I/O Access Read Timing

An

t

A(IORD)

t A(IORD)

H

SU

t

REG(IORD)

t REG(IORD)

H

SU

−REG

t

CE(IORD)

t CE(IORD)

H

SU

−CE

t

W

(IORD)

−IORD

t

INPACK(IORD)

DR

−INPACK

−IOIS16

t

IOIS16(ADR)

t

INPACK(IORD)

DR

DF

t

(IORD)

D

t

IOIS16(ADR)

DF

D

OUT

2002-10-20 38/48

THNCFxxxMBA/BAI Series

Preliminary

I/O Access Write AC Characteristics

SYMBOL

(IOWR)

PARAMETER

MIN

MAX

TYP

UNIT

NOTES

t

Data setup before −IOWR

Data hold following −IOWR

−IOWR pulse width

60

30



35



SU

(IOWR)

H

165

W

A (IOWR)

Address setup before −IOWR

Address hold following −IOWR

−CE setup before −IOWR

70

20

5

SU

t A (IOWR)

H

ns

t

CE (IOWR)

SU

t CE (IOWR)

−CE hold following −IOWR

20

5

H

t

REG (IORD)

−REG setup before −IOWR

−REG hold following −IOWR

−IOIS16 delay failing from address

−IOIS16 delay rising from address

SU

t REG (IOWR)

0

H

t

IOIS16 (ADR)



DF

DR

IOIS16 (ADR)

I/O Access Write Timing

An

t

A(IOWR)

t A(IOWR)

H

SU

t REG(IOWR)

H

t

REG(IOWR)

SU

−REG

t

CE(IORD)

t CE(IOWR)

H

SU

−CE

t

W

(IOWR)

−IOWR

t

IOIS16(ADR)

DR

t

(IOWR)

D

t (IOWR)

H

SU

−IOIS16

t

IOIS16(ADR)

DF

Valid

D

IN

2002-10-20 39/48

THNCFxxxMBA/BAI Series

Preliminary

Common Memory Access Read AC Characteristics

SYMBOL

PARAMETER

MIN

MAX

TYP

UNIT

NOTES

t

(OE)

−OE access time



30

20

0

125

100



A

(OE)

(A)

Output disable time (−OE)

Address setup time

Address hold time

−CE setup time

DIS

SU

ns

(A)



H

(CE)



SU

(CE)

−OE hold time

20



H

Common Memory Access Read Timing

An

t

(A)

t

t (A)

H

SU

−REG

(CE)

t

(CE)

SU

H

−CE

−OE

t (OE)

A

t

(OE)

DIS

D

OUT

2002-10-20 40/48

THNCFxxxMBA/BAI Series

Preliminary

Common Memory Access Write AC Characteristics

SYMBOL

PARAMETER

MIN

MAX

TYP

UNIT

NOTES

t

(D−WEH)

Data setup time (−WE)

Data hold time

80

30

150

20

30

0



SU

(D)

H

(WE)

(A)

Write pulse time

W

Address hold time

Address setup time

−CE setup time

H

ns

(A)

SU

(CE)

(WE)

Write recover time

−CE hold following −WE

30

20

REC

(CE)

H

Common Memory Access Write Timing

An

t

(A)

t

(A)

SU

H

−REG

−CE

t

(CE)

t

(CE)

SU

H

t

(WE)

REC

t

W

(WE)

−WE

t

(D)

H

D

IN

D

IN

Valid

2002-10-20 41/48

THNCFxxxMBA/BAI Series

Preliminary

True IDE Mode Access Read AC Characteristics

SYMBOL

PARAMETER

MIN

MAX

TYP

UNIT

NOTES

t

(IORD)

Data delay after −IORD



0

100



35



D

H

(IORD)

Data hold following −IORD

−ΙORD width time

165

70

20

5

W

A (IORD)

Address setup before −IORD

Address hold following −IORD

−CE setup before −IORD

−CE hold following −IORD

−IOIS16 delay falling from address

−IOIS16 delay rising from address

SU

ns

t A (IORD)

H

t

CE (IORD)

SU

t CE (IORD)

20



H

t

IOIS16 (ADR)

DF

IOIS16 (ADR)

SF

True IDE Mode Access Read Timing

An

t

A (IORD)

t A (IORD)

H

SU

t CE (IORD)

H

t

CE (IORD)

SU

−CE

t

W

(IORD)

−IORD

t

IOIS16 (ADR)

DR

t (IORD)

D

−IOIS16

t

(IORD)

H

t

IOIS16 (ADR)

DF

D

OUT

2002-10-20 42/48

THNCFxxxMBA/BAI Series

Preliminary

True IDE Mode Access Write AC Characteristics

SYMBOL

(IOWR)

PARAMETER

MIN

MAX

TYP

UNIT

NOTES

t

Data setup before −IOWR

Data hold following− IOWR

−IOWR width time

60

30

165

70

20

5



35



SU

(IOWR)

H

W

A (IOWR)

Address setup before −IOWR

Address hold following −IOWR

−CE setup before −IOWR

−CE hold following −IOWR

−IOIS16 delay falling from address

−IOIS16 delay rising from address

SU

ns

t A (IOWR)

H

t

CE (IOWR)

SU

t CE (IOWR)

20



H

t

IOIS16 (ADR)

DF

SF



True IDE Mode Access Write Timing

An

t

A (IOWR)

t A (IOWR)

H

SU

t CE (IOWR)

H

t

CE (IOWR)

SU

−CE

t

W

(IOWR)

−IORD

t

IOIS16 (ADR)

DR

−IOIS16

t

(IOWR)

t (IOWR)

H

SU

t

IOIS16 (ADR)

DF

D

OUT

2002-10-20 43/48

THNCFxxxMBA/BAI Series

Preliminary

Reset Characteristics (only Memory Card Mode or I/O Card Mode)

SYMBOL

(RESET)

PARAMETER

MIN

MAX

TYP

UNIT

NOTES

t

Reset setup time

100

1



ms

µs

SU

(VCC)

−CE recover time

REC

PR

VCC rising up time

VCC falling down time

0.1

3

100

300



ms

µs

PF

(RESET)

10

1

W

H

S

Reset pulse width

(Hi-ZRESET)



ms

0



Hardware Reset Timing

t

PF

PR

90%

V

CC

10%

t

(V

)

REC CC

−CE1,−CE2

t

(RESET)

SU

t (Hi-ZRESET)

H

t

W

(RESET)

t (Hi-ZRESET)

S

High-Z

RESET

Low

2002-10-20 44/48

THNCFxxxMBA/BAI Series

Preliminary

Power on Reset Characteristics

Power on reset sequence must need by −PORST at the rising of V

.

CC

SYMBOL

(VCC)

PARAMETER

MIN

MAX

TYP

UNIT

NOTES

t

−CE setup time

VCC rising up time

100

0.1



ms

SU

PR

100

Power on Reset Timing

t

PR

V

CC

−PORST

t

(VCC)

SU

−CE1,−CE2

2002-10-20 45/48

THNCFxxxMBA/BAI Series

Preliminary

Package Dimensions

1.60mm .05

(.063 in .002)

.99mm .05

(.039 in. . 002)

50

25

26

2.44mm .07

(.096 in . 003)

1

3.30mm .10

(.130 in .004 )

1.01mm 0.7 (.039 in .003)

1.01mm 0.7( .039 in .003)

TOP

41.66mm .13(1.640 in . 005)

42.80mm .10(1.685 in . 004)

0.76mm .07(0.30 in .003)

0.63mm .07(.025 in . 003)

4XR 0.5mm .1

(4XR.020 in . 004)

±

Note:

The optional notched configuration was shown in the CF Specification Rev.1.0. In

Specification Rev. 1.2. The notch was removed for ease of tooling.

This optional configuration can be used but it is not recommended.

Type Ⅰ CompactFlash Storage Card Dimensions

2002-10-20 46/48

THNCFxxxMBA/BAI Series

Preliminary

Attention for Card Use

•

In the reset or power off, the information of all registers is cleared.

Notice that the card insertion/removal should not be executed during host is active, if the card is used in True

IDE mode.

•

After the card hard reset, soft reset, or power on reset, ATA reset, command applied the card cannot access

during +RDY / −BSY pin is “low” level. Flash card can’t be operated in this case.

Before the card insertion V_CCcannot be supplied to the card. After confirmation that −CD1, −CD2 pins are

inseted, supply V_CCto the card.

−OE must be kept at the V_CClevel during power on reset in memory card mode and I/O card mode. OE must be

kept constantly at the GND level in True IDE mode.

Do not turn off the power or remove THNCFxxxMBA/BAI Series from the slot before read/write operation is

complete. Avoid using THNCFxxxMBA/BAI Series when the battery is low. Power shortage, power failure and/or

removal of THNCFxxxMBA/BAI Series from the slot before read/write operation is complete may cause

malfunction of THNCFxxxMBA/BAI Series, data loss and/or damage to data.

•

Routine performance of backing-up data (or taking back-up of data) is strongly recommended.

2002-10-20 47/48

THNCFxxxMBA/BAI Series

Preliminary

RESTRICTIONS ON PRODUCT USE

000707EBA

• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor

devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical

stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of

safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of

such TOSHIBA products could cause loss of human life, bodily injury or damage to property.

In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as

set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and

conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability

Handbook” etc..

• The TOSHIBA products listed in this document are intended for usage in general electronics applications

(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,

etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires

extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or

bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or

spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,

medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this

document shall be made at the customer’s own risk.

• The products described in this document are subject to the foreign exchange and foreign trade laws.

• The information contained herein is presented only as a guide for the applications of our products. No

responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other

rights of the third parties which may result from its use. No license is granted by implication or otherwise under

any intellectual property or other rights of TOSHIBA CORPORATION or others.

• The information contained herein is subject to change without notice.

2002-10-20 48/48


型号：	THNCF192MBA
厂家：	TOSHIBA
描述：	The THNCFxxxMBA/BAI series CompactFlash card is a flash technology based with ATA interface flash memory card. 该THNCFxxxMBA / BAI系列CompactFlash卡是基于与ATA接口闪存卡闪存技术。闪存
文件：	总48页 (文件大小：523K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

THNCF192MBA [TOSHIBA]

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