TMPR3904AF [TOSHIBA]
IC 32-BIT, RISC MICROCONTROLLER, PQFP208, 28 X 28 MM, PLASTIC, QFP-208, Microcontroller;
| 型号： | TMPR3904AF |
| 厂家： | 
TOSHIBA |
| 描述： | IC 32-BIT, RISC MICROCONTROLLER, PQFP208, 28 X 28 MM, PLASTIC, QFP-208, Microcontroller 时钟 微控制器 外围集成电路 |
| 文件： | 总28页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUIT
TECHNICAL DATA
TMPR3904AF
(32 bit TX System RISC)
1. GENERAL DESCRIPTION
The TMPR3904AF (to be called TX3904A hereinafter) is a standard micro controller of the 32-
bit RISC Microprocessor TX39 family. The TX3904A uses the TX39 Processor Core as the CPU.
The TX39 Processor Core is a RISC CPU core Toshiba developed based on the R3000A
architecture of MIPS Technologies, Inc. As micro-controllers that can be embedded, besides the
TX39 Processor Core, the TX3904A has built-in peripheral circuits such as memory controllers,
DMA controllers, serial ports, and timers/counters.
2. FEATURES
n Built-in TX39 Processor Core
· Toshiba has uniquely developed this on the basis of the R3000A architecture of the MIPS.
· Instruction cache 4KB/Data cache 1KB
· Built-in debug support unit
n DRAM Controller
· Four-bank x two-channel configuration
· Fast page mode/Hyper page (EDO) mode support
n ROM Controller
· Two-bank x two-channel configuration
· Mask ROM, EPROM, E2PROM, Flash Memory, SRAM support
· Page mode ROM support
n DMA Controller
· Independent four channels
· Single address mode/Dual address mode
n Interrupt Controller
· Internal nine sources, external eight sources
· Non-maskable interrupt (NMI)
TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA
product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA
products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind
the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook.
The products described in this document are subject to foreign exchange and foreign trade control laws.
The information contained herein is subject to change without notice.
The information contained herein is presented only as a guide for the application of our
products. No responsibility is assumed by TOSHIBA for any infringements of patents or
other rights of the third parties which may result from its use. No license is granted by
EJC-TMPR3904AF-1
14-Dec-1998
implication or otherwise under any patent or patent rights of TOSHIBA or others.
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TECHNICAL DATA
TOSIBA RISC PROCESSOR
TMPR3904AF
n Timer/Counter
· 24-bit up counter three channels
· Watchdog timer mode support
n Serial I/O
· Two-channel UART
n I/O Ports
· Exclusive port: one channel; shared port: two channels
· 16-bit Bus Support
n Power Supply Voltage: 3.3V
n Power Consumption: 900mW (3.3V, at 66 MHz operation, Typ)
n Maximum Operation Frequency: 66 MHz
n Package: 208 pin plastic QFP
R3000A is a trademark of MIPS Group, a division of Silicon Graphics, Inc.
EJC-TMPR3904AF-2
14-Dec-1998
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TECHNICAL DATA
TOSIBA RISC PROCESSOR
TMPR3904AF
3. SYSTEM CONFIGURATION
3.1 TMPR3904AF BLOCK DIAGRAM
TX39 Processor Core
I-Cache
TX39
D-Cache
Debug[7:0]
D R E Q [1:0]
DACK[1:0]
D O N E *
D R E Q [3:2]/PIO1[7:6]
DACK[3:2]/PIO1[5:4]
W B U
D S U
G-Bus I/F
SYSCLK
A[31:24]/PIO2[7:0]
A[23:1]
DMAC0(2ch.)
DMAC1(2ch.)
B E [3:0]*
D[31:0]
R /W*
BSTART
LAST*
ACK*
RAS1,0[3:0]*
CAS[3:0]*
W E *
E B I F
DRAMC
B U S E R R *
R E S E T *
OE1*,OE0*
B U S R E Q */PIO1[1]
B U S G N T * /PIO1[0]
B U S R E L */PIO1[3]
HAVEIT*/PIO1[2]
N M I *
CE1,0[1:0]*
SWE1*,SWE0*
R O M C
IRC
INT[7:0]
HALF*
S C S [3:0]*
BOOT16
XIN
XOUT
G to IM Bridge
C G
TEST*
E N D I A N
C L K E N
PLLOFF*
S I N 0
S O U T 0
CTS0*
RTS0*
SIO0
PIO0[7:0]
P I O
SCLK
S I N 1
TMR0
TMR1
TMR2
S O U T 1
CTS1*
RTS1*
SIO1
TIMOUT1
TIMIN1
TIMOUT2
TIMIN2
EJC-TMPR3904AF-3
14-Dec-1998
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TECHNICAL DATA
TOSIBA RISC PROCESSOR
TMPR3904AF
4. PINS
4.1 PIN ASSIGNMENT
Pin No. Signal Pin No. Signal Pin No. Signal Pin No. Signal
1
XIN
VDD
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
VSS
TOUT[2]
TOUT[3]
WE*
A[1]
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
A[19]
A[20]
A[21]
VSS
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
TSTO2
BOOT16
HALF*
2
3
LAST*
R/W*
4
ENDIAN
BUSGNT*
BUSREL*
DACK[0]
DACK[1]
DACK[2]
DACK[3]
DONE*
5
BE[3]*
VDD
6
BE[2]*
VDD
A[2]
A[22]
A[23]
A[24]
A[25]
A[26]
A[27]
VSS
7
BE[1]*
8
BE[0]*
A[3]
9
VSS
A[4]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VDD
VSS
RAS0[0]*
RAS0[1]*
RAS0[2]*
VDD
A[5]
A[6]
VSS
A[7]
VDD
VDD
A[8]
A[28]
A[29]
A[30]
A[31]
CE0[0]*
CE0[1]*
CE1[0]*
CE1[1]*
OE1*
VSS
DREQ[0]
DREQ[1]
DREQ[2]
DREQ[3]
HAVEIT*
VSS
VDD
VSS
RAS0[3]*
RAS1[0]*
RAS1[1]*
VSS
A[9]
A[10]
A[11]
A[12]
A[13]
A[14]
A[15]
VDD
VSS
103 BUSREQ*
RAS1[2]*
RAS1[3]*
CAS[0]*
CAS[1]*
VDD
104
105
106
107
108
109
110
111
112
VDD
SCS[3]*
SCS[2]*
SCS[1]*
SCS[0]*
VSS
VDD
CAS[2]*
CAS[3]*
TOUT[0]
TOUT[1]
OE0*
SWE0*
SWE1*
TSTO1
A[16]
A[17]
A[18]
PIO0[0]
PIO0[1]
PIO0[2]
EJC-TMPR3904AF-4
14-Dec-1998
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TECHNICAL DATA
TOSIBA RISC PROCESSOR
TMPR3904AF
Pin No. Signal Pin No. Signal Pin No. Signal Pin No. Signal
113
114
115
116
117
118
119
PIO0[3]
VDD
137
138
139
140
141
142
143
VDD
D[28]
D[27]
D[26]
D[25]
VSS
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
D[10]
D[9]
185
186
187
188
189
190
191
192
193
INT[7]
VSS
PIO0[4]
PIO0[5]
PIO0[6]
PIO0[7]
VSS
D[8]
PCST[2]
PCST[1]
PCST[0]
DCLK
VSS
VDD
D[7]
D[24]
D[23]
D[22]
D[21]
VDD
D[6]
SDAO
DBGE*
SDI*
120 TIMOUT2 144
121 TIMOUT1 145
D[5]
D[4]
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
TIMIN2
TIMIN1
SCLK
SIN1
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
D[3]
194 DRESET*
D[2]
195
196
197
TEST*
RESET*
ACK*
VSS
VSS
D[20]
D[19]
D[18]
D[17]
D[16]
D[15]
D[14]
VDD
VDD
D[1]
SIN0
198 BUSERR*
CTS1*
CTS0*
VDD
D[0]
199
200
201
202
203
204
205
206
207
208
BSTART*
VSS
NMI*
INT[0]
INT[1]
INT[2]
VDD
INT[3]
INT[4]
INT[5]
INT[6]
VDD
SOUT1
SOUT0
RTS1*
RTS0*
D[31]
SYSCLK
PLLOFF*
CLKEN
VDDP
VSSP
VSS
D[13]
D[12]
D[11]
D[30]
VSS
D[29]
XOUT
* Active-low signal
EJC-TMPR3904AF-5
14-Dec-1998
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TECHNICAL DATA
TOSIBA RISC PROCESSOR
TMPR3904AF
4.2 PIN FUNCTIONS
5V tolerant
Name
I/O input
Function
System Interface
SYSCLK
O -
System Clock
Outputs a clock with frequency either equal to or half of that
of the TX39 Processor Core.
Address bus. It is an output when the TX3904A is a bus
A[31:1]
I/O A
master, an input in otherwise.
(PIO2[7:0]) I/O A
A[31:24] are shared with PIO2.
I/O A
BE[3:0]*
Byte Enable
Indicates valid data positions on the data bus D[31:0]. It is an
output when the TX3904A is a bus master, an input in
otherwise.
BE[3]* : D[31:24]
BE[2]* : D[23:16]
BE[1]* : D[15:8]
BE[0]* : D[7:0]
I/O A
O -
D[31:0]
Data bus.
D[15:0] is used in 16-bit bus mode.
System Chip Select
SCS[3:0]*
Asserts when accessing the address range that is set by the
internal register.
I/O A
R/W*
Read/Write
Indicates the bus operation being executed is either read or
write. It is an output when the TX3904A is a bus master, an
input in otherwise.
High: Read
Low: Write
I/O A
BSTART*
Bus Start
Asserts during the first clock period of the bus operation. It is
an output when the TX3904A is a bus master, an input in
otherwise.
I/O A
I/O A
LAST*
ACK*
Last
Indicates that it is the last of the bus operation. It is an output
when the TX3904A is a bus master, an input in otherwise.
Acknowledge
Slave devices inform the bus master that the bus operation
may be finished. It is an input when the TX3904A is a bus
master, an output in otherwise.
5V tolerant input : A = Available, N.A = Not Available
EJC-TMPR3904AF-6
14-Dec-1998
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TECHNICAL DATA
TOSIBA RISC PROCESSOR
TMPR3904AF
5V
Name
I/O tolerant
input
Function
Bus Error
A
BUSERR* I/O
Informs of bus errors. It is an input when the TX3904A is a
bus master, an output in otherwise.
RESET*
I
N.A
Reset
Initializes the TX3904A by setting this signal low for 12
SYSCLK or more.
Clock
XIN
I
N.A
Crystal Input
Connect a crystal oscillator.
Crystal Output
Connect a crystal oscillator.
PLL OFF
A signal to halt the PLL oscillation of the TX3904A built-in
clock generator.
Clock Enable
XOUT
O
I
PLLOFF*
N.A
N.A
CLKEN
I
A signal to enable the TX3904A internal clock.
External Bus Master Interface
BUSREQ* I
A
Bus Request
Changes to low when the external bus master requests for
the bus ownership of the TX39 Processor Core.
A pin that is shared with the PIO1.
(PIO1[1]) I/O A
BUSGNT* O -
(PIO1[0]) I/O A
Bus Grant
Asserted when the TX39 Processor Core informs that it is
releasing the bus ownership in response to BUSREQ*.
A pin that is shared with the PIO1.
Have It
HAVEIT*
I
A
Indicates to the TX3904A that the external bus master has
the bus ownership.
A pin that is shared with the PIO1.
(PIO1[2]) I/O A
BUSREL* O -
(PIO1[3]) I/O A
Interrupt Signals
Bus Release
Asserted when TX39 processor core requests the external
bus master to release the bus ownership.
A pin that is shared with the PIO1.
NMI*
I
A
Non Maskable Interrupt
Non-maskable interrupt input.
5V tolerant input : A = Available, N.A = Not Available
EJC-TMPR3904AF-7
14-Dec-1998
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TECHNICAL DATA
TOSIBA RISC PROCESSOR
TMPR3904AF
5V
Name
INT[7:0]
I/O tolerant
input
Function
Interrupt Request
I
A
External interrupt request signals. An active level and level
sensed/edge triggered are designated by the chip
configuration register.
Memory Interface
RAS0[3:0]* O -
RAS1[3:0]*
CAS[3:0]* O -
Row Address Strobe
RAS signals for a DRAM.
Column Address Strobe
CAS signals for a DRAM.
Write Enable
Write enable signal for a DRAM.
Output Enable
Output enable signals of a ROM.
Chip Enable
Chip select signals of a ROM.
WE*
O -
O -
OE0*
OE1*
CE0[1:0]* O -
CE1[1:0]*
SWE0*
SWE1*
O -
SRAM Write Enable
Write enable signals of an SRAM and Flash ROM.
DMA Interface
DREQ[3:0] I
A
DMA Request
The external I/O device requests a DMA transfer.
DREQ[3:2] are shared with the PIO1.
DMA Acknowledge
(PIO1[7:6]) I/O A
DACK[3:0] O -
Acknowledge signals to DMA transfer request through the
DREQ.
(PIO1[5:4]) I/O A
DACK[3:2] are shared with the PIO1.
DONE*
I
A
Done
Input: LOW is input to terminate data transfer.
Output: Notification that transfer ended.
This signal is
asserted during one SYSCLK period when DMA transfer ends.
5V tolerant input : A = Available, N.A = Not Available
EJC-TMPR3904AF-8
14-Dec-1998
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TECHNICAL DATA
TOSIBA RISC PROCESSOR
TMPR3904AF
5V
Name
I/O tolerant Function
input
Timer/Counter
TIMOUT2
TIMOUT1
TIMIN2
O
-
Timer Output
Output signals of the timer.
Timer Input
I
N.A
TIMIN1
External signals for the timer s count.
Serial Port
SIN1
SIN0
I
A
-
Serial Input
Data input signals of the serial I/O.
Serial Output
Data output signals of the serial I/O.
Clear To Send
Control signals of the serial I/O.
Request To Send
SOUT1
SOUT0
CTS1*
CTS0*
RTS1*
RTS0*
SCLK
O
I
A
-
O
I
Control signals of the serial I/O.
Serial Clock Input
A
Clock input of the serial I/O.
IO Port
PIO0[7:0]
I/O A
I/O Port0
A signal for I/O Port0. Input/Output can be set in each
bit.
Debug Interface
PCST[2:0]
DCLK
SDAO
O
-
Debug
A signal for the external real time debug system.
DBGE*, SDI*, and DRESET* are pulled up internally.
DBGE*
SDI*
I
N.A
DRESET*
Others
BOOT16
I
N.A
Boot 16-bit
Sets the memory bus width of the channel-0 of ROM
controller. Fix to either high or low according to the bus
width of the boot ROM.
High: 16 bits
Low: 32 bits
5V tolerant input : A = Available, N.A = Not Available
EJC-TMPR3904AF-9
14-Dec-1998
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TECHNICAL DATA
TOSIBA RISC PROCESSOR
TMPR3904AF
5V
Name
I/O tolerant Function
input
N.A
HALF*
I
Half Speed Bus Mode
Designates the half speed bus mode. At low, the
TX3904A becomes the half speed bus mode so that the
frequency of the bus operation becomes a half of the
operation frequency of the TX39 Processor Core. Fix to
either high or low.
ENDIAN
TEST*
I
N.A
Sets the Endian immediately after reset. Fix to either
high or low.
High: Big Endian
Low: Little Endian
Test
A signal for tests. Fix to high.
Test output
A signal for tests. Leave open.
I
N.A
-
TOUT[3:0],
TSTO1,
O
TSTO2
5V tolerant input : A = Available, N.A = Not Available
EJC-TMPR3904AF-10
14-Dec-1998
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TECHNICAL DATA
TOSIBA RISC PROCESSOR
TMPR3904AF
5. ELECTRICAL SPECIFICATIONS
5.1 ABSOLUTE MAXMUM RATINGS
Parameter
Symbol
Rating
Unit
V
V
DD
Supply voltage
-0.3 ~ 5.0
Input voltage
V
IN1
-0.3 ~ V + 0.3V
XIN, PLLOFF*, CLKEN, DBGE*,
SDI*, DRESET*, TEST*, RESET*,
BOOT16, HALF*, ENDIAN, TIMIN
V
DD
V
IN2
Other inputs
-0.3 ~ 5.3V
V
T
Storage temperature
-40 ~ 125
°C
STG
P
D
Maximum power dissipation
1.2
W
Note: Using the LSI at specifications higher than the maximum ratings can cause permanent
damage to the LSI device. For normal operation, use under the recommended
operating conditions. Exceeding the recommended operating conditions may affect the
reliability of the LSI device.
5.2 RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Condition
Min. Max. Unit
V
T
Supply voltage
Operating
3.0
0
3.6
70
V
°C
DD
a
temperature
EJC-TMPR3904AF-11
14-Dec-1998
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TECHNICAL DATA
TOSIBA RISC PROCESSOR
TMPR3904AF
5.3 DC CHARACTERISTICS
(T = 0 ~ 70°C, V = 3.3V ± 0.3V, V = 0V)
a
DD
SS
Parameter
Symbol
Condition
Min.
Max.
V ´ 0.2
DD
Unit
V
Low-level input voltage
V
V
XIN
-
-
IL1
except XIN
XIN
0.8
IL2
High-level input
voltage
V
V
V
´ 0.8
-
-
V
IH1
DD
except XIN
2.0
4.0
8.0
16.0
-
IH2
Low-level output
current
I
I
I
V
OL
V
OL
V
OL
V
OH
V
OH
V
OH
= 0.4V (1)
= 0.4V (2)
= 0.4V (3)
= 2.4V (1)
= 2.4V (2)
= 2.4V (3)
-
mA
mA
mA
mA
mA
mA
mA
OL1
OL2
OL3
-
-
High-level output
current
I
I
I
-4.0
-8.0
-16.0
10
20
10
10
330
OH1
OH2
OH3
-
-
Input leakage current
I
I
(6)
-10
-10
-10
-320
-
IH1
IH2
(7),(8)
(6),(8)
(7)
mA
I
I
mA
IL1
IL2
DD
mA
Operating current
I
V
DD
= 3.6V, 66MHz
mA
(1) PCST[2:0], DCLK, SDAO, SYSCLK, SCS[3:0]*, SOUT0, SOUT1, CTS0*, CTS1*,
(2) BE[3:0]*, BSTART*, BUSERR*, ACK*, LAST*, R/W*, BUSGNT*, BUSREL*,
BUSREQ*, HAVEIT*, DREQ[3:2], DACK[3:2], PIO0[7:0], DONE*, RTS0*, RTS1*,
TIMOUT1, TIMOUT2, RAS0[3:0]*, RAS1[3:0]*, CAS[3:0]*, OE0*, OE1*,
CE0[1:0]*, CE1[1:0]*, SWE0*, SWE1*
(3) D[31:0], A[31:1], WE*
(6) Input pins except (7) and (8) below
(7) DBGE*, SDI*, DRESET*, TEST*
(8) XIN
EJC-TMPR3904AF-12
14-Dec-1998
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TECHNICAL DATA
TOSIBA RISC PROCESSOR
TMPR3904AF
5.4 CRYSTAL OSCILLATOR CHARACTERISTICS
5.4.1 Crystal Oscillator Conditions
TMPR3904AF
XIN
XOUT
R
C
OUT
X’tal
C
IN
OUT
Parameter
Symbol
Recommended value
Unit
Crystal Oscillator
frequency
Output register
External condenser
Clock generator
Rising time
f
4.125 ~ 8.25
MHz
kW
pF
IN
R
OUT
3.3
10
C ,C
IN OUT
(1)
t
5
ns
ns
r
(1)
t
f
Falling time
5
For a reference. Ask clock generator manufacture.
5.4.2 Electrical Specifications
(T = 0 ~ 70°C, V = 3.3V ± 0.3V, V = 0V)
a
DD
SS
Parameter
Symbol
Condition
MIN. TYP. MAX. Unit
500ms 10ms
t
Oscillation start time
f=4.125~8.25MHz
-
-
STA
EJC-TMPR3904AF-13
14-Dec-1998
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TECHNICAL DATA
TOSIBA RISC PROCESSOR
TMPR3904AF
5.5 AC CHARACTERISTICS
(T = 0 ~ 70°C, V = 3.3V ± 0.3V, V = 0V, C = 50pF)
a
DD
SS
L
Symbol
Signal
Description
Min. Max. Unit
t
SYSCLK
Full speed bus mode
Half speed bus mode
High Level
15
30
5
-
-
-
-
-
-
22
10
ns
ns
ns
ns
ns
ns
ns
ns
sys
t
t
t
t
t
t
SYSCLK
SYSCLK
SYSCLK
SYSCLK
A[31:1]
BE[3:0]*, R/W*,
BSTART*, LAST*
BE[3:0], R/W*,
BSTART*, LAST*
D[31:0]
1
2
3
4
5
6
Low Level
5
High Level (Half speed mode)
Low Level (Half speed mode)
Delay
12
12
-
Delay (High to Low)
-
t
Delay (Low to High)
-
10
ns
7
t
t
t
t
t
t
t
t
t
t
t
t
Setup
Hold
Setup
Hold
Delay
Setup
Hold
Delay
Delay
Setup
Hold
8
0
8
0
-
8
0
-
-
-
-
-
12
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
D[31:0]
9
ACK*, BUSERR*
ACK*, BUSERR*
D[31:0]
BUSREQ*
BUSREQ*
BUSGNT*
ACK*
HAVEIT*
HAVEIT*
BUSREL*
A[31:1], BE[3:0], R/W*, Active to Hi-Z
BSTART*, LAST*
A[31:1], BE[3:0], R/W*, Hi-Z to active
BSTART*, LAST*
A[31:1], BE[3:0], R/W*, Setup (Full speed bus mode)
BSTART*, LAST*
A[31:1], BE[3:0], R/W*, Hold (Full speed bus mode)
BSTART*, LAST*
RESET*, INT[7:0]*,
NMI*
10
11
12
13
14
15
16
17
18
19
-
10
10
-
-
10
17
-
8
0
-
Delay
t
t
t
-
20
-
17
-
ns
ns
ns
ns
21
8
0
8
22
23
24
t
t
-
Setup
-
EJC-TMPR3904AF-14
14-Dec-1998
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TECHNICAL DATA
TOSIBA RISC PROCESSOR
TMPR3904AF
(T = 0 ~ 70°C, V = 3.3V ± 0.3V, V = 0V, C = 50pF)
a
DD
SS
L
Symbol
Signal
RESET*, INT[7:0]*,NMI* Hold
Description
Min. Max.
Unit
ns
t
t
t
t
t
t
0
12
-
-
25
t
RESET*
CLKEN
Reset time
PLL stabilization time upon reset 500(2)
26
27
28
29
30
sys
-
ms
t
SYSCLK
PLLOFF*
RAS1[3:0]*, RAS0[3:0]* Delay
CAS[3:0]*
2
-
sys
250
-
ms
ns
-
10
t
t
WE*
Delay
Delay
-
-
10
10
ns
ns
31
32
CE1[3:0]*, CE0[3:0]*
OE1*, OE0*
SWE1*, SWE0*
DREQ[3:0]
DREQ[3:0]
DACK[3:0]
TIMIN1, TIMIN2
TIMOUT1,TIMOUT2
SCLK
PIO0[7:0]
PIO0[7:0]
PIO0[7:0]
SCS[3:0]*
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Delay
Setup
Hold
Delay
-
8
0
-
45
-
80
-
8
0
-
10
-
-
10
-
10
-
10
-
-
10
15
15
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
33
34
35
36
37
38
39
40
41
42
43
44
45
46
External timer clock
Timer output
External baud rate clock
Delay
Setup
Hold
Delay
A[13:1]
A[13:1]
BSTART*
Row address output delay
Column address output delay
Low width driven by an external
bus master(1)
-
-
1
t
sys
t
t
t
t
sys/2
SYSCLK-BSTART*
SYSCLK-BSTART* delay
(Half speed bus mode)
0
0
-
ns
ns
ns
47
48
49
-t
49
A[31:1], BE[3:0], R/W*, Hold (Half speed bus mode)
BSTART*, LAST*
GCLK-SYSCLK
-
GCLK-SYSCLK delay
(Half speed bus mode)
8
(1) Both this specification and setup/hold time must be satisfied at the same time when the
external bus master drives the BSTART*.
(2) This specification does not include X tal oscillation start time (tSTA).
Note: Load capacitance(C ) for A[31:1], D[31:0] is 100pF.
L
EJC-TMPR3904AF-15
14-Dec-1998
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TECHNICAL DATA
TOSIBA RISC PROCESSOR
TMPR3904AF
5.5.1 Definition of AC characteristics
t
sys
t , t
t , t
2 4
1
3
2.0V
0.8V
SYSCLK
Output
t
d
t
vz
t
zv
2.0V
0.8V
SYSCLK
Input
t
t
hd
su
2.2V
0.8V
2.2V
0.8V
t
t
t
t
t
: Output delay
d
: Output off (active to Hi-Z)
: Output on (Hi-Z to active)
: Input setup
vz
zv
su
hd
: Input hold
EJC-TMPR3904AF-16
14-Dec-1998
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TECHNICAL DATA
TOSIBA RISC PROCESSOR
TMPR3904AF
5.5.2 Timing diagram
SYSCLK
A[31:1]
BE[3:0]*
BSTART*
LAST*
t
5
t
5
t
t
6
6
t
6
t
7
t
6
t
7
R/W*
t
43
t
43
SCS[3:0]*
ACK*
t
10
t
11
t
8
t
9
D[31:0]
Read operation
Note: SCS[3:0]* are asserted only when a bus master accessed SCS area.
EJC-TMPR3904AF-17
14-Dec-1998
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TECHNICAL DATA
TOSIBA RISC PROCESSOR
TMPR3904AF
SYSCLK
t
5
t
5
A[31:1]
BE[3:0]*
BSTART*
LAST*
t
t
6
6
t
6
t
7
t
6
t
7
t
6
t
7
R/W*
T
43
t
43
SCS[3:0]*
ACK*
t
10
t
11
t
12
t
12
D[31:0]
Write operation
Note: SCS[3:0]* are asserted only when a bus master accessed SCS area.
EJC-TMPR3904AF-18
14-Dec-1998
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TECHNICAL DATA
TOSIBA RISC PROCESSOR
TMPR3904AF
SYSCLK
t
44
t
45
t
5
ROW
A[31:1]
BE3:0]*
BSTART
LAST*
RASnm*
CASn*
WE*
COLUMN
t
t
6
6
t
6
t
7
t
6
t
7
t
30
t
30
t
30
t
30
t
8
t
9
D[31:0]
Read operation from DRAM
EJC-TMPR3904AF-19
14-Dec-1998
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TECHNICAL DATA
TOSIBA RISC PROCESSOR
TMPR3904AF
SYSCLK
t
44
t
45
t
5
ROW
A[31:1]
BE3:0]*
BSTART
LAST*
RASnm*
CASn*
WE*
COLUMN
t
t
6
6
t
6
t
7
t
6
t
7
t
30
t
30
t
30
t
30
t
31
t
31
t
12
t
12
D[31:0]
Write operation to DRAM
EJC-TMPR3904AF-20
14-Dec-1998
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TECHNICAL DATA
TOSIBA RISC PROCESSOR
TMPR3904AF
SYSCLK
t
5
A[31:1]
BE[3:0]*
BSTART
LAST*
CEnm*
OEn*
t
6
t
6
t
7
t
6
t
7
t
32
t
32
SWE*
t
8
t
9
D[31:0]
Read operation from ROM/FLASH/SRAM
EJC-TMPR3904AF-21
14-Dec-1998
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TECHNICAL DATA
TOSIBA RISC PROCESSOR
TMPR3904AF
SYSCLK
t
5
A[31:1]
BE[3:0]*
BSTART
LAST*
CEnm*
OEn*
t
6
t
6
t
7
t
6
t
7
t
32
t
33
t
33
SWE*
t
12
t
12
D[31:0]
Write operation to FLASH/SRAM
EJC-TMPR3904AF-22
14-Dec-1998
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TECHNICAL DATA
TOSIBA RISC PROCESSOR
TMPR3904AF
SYSCLK
t
13
BUSREQ*
BUSGNT*
HAVEIT*
A[31:1]
t
15
t
17
t
20
t
20
t
20
t
20
t
22
t
22
t
22
t
22
t
22
t
t
23
Hi-Z
Hi-Z
Hi-Z *2
Hi-Z *2
23
BE[3:0]*
BSTART*
LAST*
t
t
23
Hi-Z
Hi-Z
Hi-Z
45
t
t
23
t
20
23
R/W*
TX3904A cycle
External bus master cycle
Note 1: A period from asserting BUSREQ* to replying BUSGNT* varies by the status of the TX3904A.
Note 2: When the external bus master uses on-chip DRAMC or ROMC, the external bus master must
stop driving A[31:1] and BE[3:0]* at a rising of BSTART*.
Release of bus ownership and External bus master cycle (Full speed bus mode)
EJC-TMPR3904AF-23
14-Dec-1998
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TECHNICAL DATA
TOSIBA RISC PROCESSOR
TMPR3904AF
SYSCLK
BUSREQ
BUSGNT*
HAVEIT*
A[31:1]
t
13
t
t
17
t
t
t
t
21
21
21
Hi-Z
Hi-Z
Hi-Z
BE[3:0]*
BSTART*
LAST*
Hi-Z
t
Hi-Z
R/W*
External bus master cycle
TX3904A cycle
Regaining of bus ownership
EJC-TMPR3904AF-24
14-Dec-1998
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TECHNICAL DATA
TOSIBA RISC PROCESSOR
TMPR3904AF
SYSCLK
t
sys
t
49
GCLK
(Int. clock)
GCLKH
(Int. clock)
t
47
t
t
t
48
BSTART*
A[31:1]
BE[3:0]*
LAST*
48
Hi-Z
Hi-Z
Hi-Z *1
48
Hi-Z *1
R/W*
Note 1: When the external bus master uses on-chip DRAMC or ROMC, the
external bus master must stop driving A[31:1] and BE[3:0]* at a rising of
BSTART*.
External bus master cycle (Half speed bus mode 1)
EJC-TMPR3904AF-25
14-Dec-1998
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TECHNICAL DATA
TOSIBA RISC PROCESSOR
TMPR3904AF
SYSCLK
t
sys
t
49
GCLK
(Int. clock)
GCLKH
(Int. clock)
t
47
t
48
t
48
t
48
BSTART*
A[31:1]
BE[3:0]*
LAST*
Hi-Z
Hi-Z
Hi-Z *1
Hi-Z *1
R/W*
Note 1: When the external bus master uses on-chip DRAMC or ROMC, the external
bus master must stop driving A[31:1] and BE[3:0]* at a falling of BSTART*.
External bus master cycle (Half speed bus mode 2)
EJC-TMPR3904AF-26
14-Dec-1998
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TECHNICAL DATA
TOSIBA RISC PROCESSOR
TMPR3904AF
SYSCLK
t
26
RESET*
Reset
V
DD
t
27
SYSCLK
CLKEN
RESET*
t
28
t
26
t
’
27 is not include X tal oscilation start time (tsta)
Power-on Reset
EJC-TMPR3904AF-27
14-Dec-1998
TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TECHNICAL DATA
TOSIBA RISC PROCESSOR
TMPR3904AF
6. PACKAGE DIMENSION
QFP208-P-2828
Unit: mm
EJC-TMPR3904AF-28E
27-Mar-1998
TOSHIBA CORPORATION
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