TPD7106F [TOSHIBA]
MOSFET Driver;
| 型号： | TPD7106F |
| 厂家： | 
TOSHIBA |
| 描述： | MOSFET Driver |
| 文件： | 总22页 (文件大小：622K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPD7106F
TOSHIBA Intelligent Power Device Silicon Power MOS Integrated Circuit
TPD7106F
1 channel High-Side N channel Power MOSFET Gate Driver
1. Description
TPD7106F is a 1channel high-side N channel power MOSFET gate
driver. This IC contains a charge pump circuit, allowing easy
configuration of a high-side switch for large-current applications.
TPD7106F
SSOP16-P-225-0.65B
2. Applications
●
●
●
Junction Boxes for Automotive.
Power distribution modules for Automotive.
Semiconductor relays.
3. Features
●
●
●
AEC-Q100 qualified.
Built in the charge pump circuit (Charge pump capacitor is external).
Output current is -10mA / +400mA, and the drive by parallel use of N channel power MOSFET is
possible.
●
●
●
Built in the protection for reverse connection of power supply.
Built in the diagnosis output for under voltage of Charge pump circuit.
SSOP16 package for surface mounting.
Note: Due to its MOS structure. This product is sensitive to static electricity.
Start of commercial production
2020-03
© 2019
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TPD7106F
4. Block Diagram
VDD1
VDD1
Logic
Logic
CP1-
OSC
CP2-
CP_GND
CP_GND
Logic
CP1
VDD
CP2
CPV
VDD1
VREG
STBY
IN1
OUT1
OUT2
DIAG
OSC
Logic
IN2
CP_GND
GND1
GND2
TPD7106F
Note: Some of the functional blocks, circuits or constants labels in the block diagram may have been
omitted or simplified for clarity.
Figure 4.1 Block Diagram
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5. Pin Assignments (top view)
CP1-
TEST
CP1
CP2-
N.C.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
CP2
VDD
CPV
STBY
IN1
OUT1
OUT2
IN2
10 DIAG
GND1
9
GND2
Figure 5.1 Pin Assignments
6. Pin Description
Table 6.1 Pin Description
Pin No
Symbol
Description
1
2
CP1-
The terminal for charge pump capacitor connection.
The terminal for and internal circuit test. Normal operation = connect to
Ground.
TEST
3
4
CP1
VDD
The terminal for charge pump capacitor connection.
Power supply pin.
5
STBY
IN1
Standby mode control pin.
6
Input pin. Built in pull down resistor.(for Normal operation)
Input pin. Built in pull down resistor.(for rapid off)
Ground pin.
7
IN2
8
GND1
GND2
DIAG
OUT2
9
Ground pin.
10
11
Diagnostic output (Open drain).
Output pin for an external N channel power MOSFET drive( for rapid off)
Output pin for an external N channel power MOSFET drive( for Normal
switching)
12
OUT1
13
14
15
16
CPV
CP2
N.C
Output of charge pump voltage.
The terminal for charge pump capacitor connection.
No-Connect pin.
CP2-
The terminal for charge pump capacitor connection.
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7. Operational Description
7.1. Gate drive of Power MOSFET
7.1.1. On driver
In response to FET turn-on instructions (VIN1=VIH), a charge pump circuit and the drive circuit operate
from input terminal IN1, and it drives N channel power MOSFET of a high side with sufficient gate voltage.
(VOUT1=VDD+12V (typ.))
VIN1: IN1 pin input voltage
VIH: High level input voltage
VOUT1: OUT1 pin output voltage
7.1.2. Off driver (Normal Off)
The OFF operation in normal turns off external FET by M2 in Figure 7.1 in response to FET drive
instructions (VIN1=VIL) from input terminal IN1 (drive on resistance = 630Ω (typ.)).
VIL: Low level input voltage
7.1.3. Off driver (Rapid Off)
Abnormalities, such as external FET and short circuits which occurred around load, are detected, and
when it is required to make external FET turn off for a short time, in response to FET rapid OFF instructions
(VIN2=VIH), the following figure M3 operates from input terminal IN2, and it turns off external FET quickly
(Driver on resistance = 5Ω (typ.)). In addition, although rapid off-driver operating time (tO2ON) is a maximum
of 200μs.
VIN2: IN2 pin input voltage
CP drive
CPV
VDD
M1
OUT1
OUT2
M2
M3
M4
GND2
Figure 7.1 Output driver part.
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TPD7106F
Table 7.2 Truth table (1)
IN1
IN2
STBY
OUT1
OUT2
state
X
L
X
L
L
Hiz
L
Hiz
Hiz
Hiz
L
Stand-by mode
H
H
H
H
Normal operation
H
L
L
H
L
H
H
Rapid off mode
H
L
L
7.2. Protection for reverse connection of power supply
When a power supply is connected by reverse polarity, the current from a GND terminal is intercepted by
M4 and M5, and external FET is turned off.
CPV
VDD
M1
M2
OUT1
OUT2
M3
M5
M4
GND1
GND 2
Figure 7.3 Protection for reverse connection.
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7.3. Detection for under voltage of charge pump
CPV terminal voltage is supervised and a charge pump voltage fall is detected. If it becomes below the
charge pump fall judging voltage VCPL, a DIAG terminal will serve as L State. Output terminal OUT1 and
OUT2 maintain operation. In addition, when STBY is L State, a charge pump circuit stops.
STBY
VCPL
CPV
IN1
IN2
VCPV
OUT1
Hiz
OUT2
Hiz
DIAG
Hiz
Under
voltage.
Under
voltage.
Rapid off.
(100μs typ.)
Figure 7.4 Timing chart.
Note: When STBY is momentarily made into L State from H State and it returns to H State again, even
if CPV terminal voltage holds more than VCPL, a DIAG terminal may serve as L State.
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7.4. Truth Table (protect function and diagnosis output)
Table 7.5 Truth table (2)
Charge pump
Boost
OUT1
OUT2
M3 Note3
DIAG
Rapd off
drive
IN1
IN2
STBY
M1 Note3 M2 Note3
M6 Note3
VCPV
operation
H
X
X
L
V
CPV＝L
stop
Disable
Hiz
OFF
OFF
Hiz
OFF
OFF
(pull up)
L
L
H
L
L
L
H
VCPV≦VCPL Operation
Disable
Disable
Enable
Disable
Enable
Disable
Disable
Disable
Enable
Disable
Enable
Disable
L
H
L
L
L
L
L
H
L
L
L
L
OFF
ON
ON
OFF
ON
ON
ON
ON
ON
OFF
ON
ON
ON
ON
Hiz
Hiz
L
OFF
OFF
ON
ON
HNote1
HNote2
HNote1
HNote2
L
OFF
OFF
OFF
OFF
OFF
ON
Hiz
L
OFF
ON
H
Hiz
Hiz
Hiz
L
OFF
OFF
OFF
ON
L
H
L
VCPV＞VCPL
H
OFF
L
(pull up)
HNote1
HNote2
HNote1
HNote2
OFF
OFF
OFF
OFF
Hiz
L
OFF
ON
H
Hiz
OFF
Note1: Rapid off drive operation time (100μs typ.)
Note2: After Rapid off drive.
Note3: Refer to the following figure of the device name.
CPV
VDD
M1
OUT1
OUT2
DIAG
M6
M2
M3
M5
M4
GND1
GND2
Figure 7.6 TPD7106F Output part.
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8. Absolute Maximum Ratings
Table 8.1 Absolute Maximum Ratings
(Ta = 25°C unless otherwise specified)
Characteristics
Symbol
Rating
Unit
Note
DC
VDD (1)
VDD (2)
VSTBY
–18 to 27
40
V
V
-
Supply voltage
Pulse
t≤500ms
-
-
-
-
-
-
-
-
-
-
-
-
-
Input voltage(1)
–0.3 to 40.0
–0.3 to 6.0
40
V
Input voltage(2)
VIN1,VIN2
VCPV
V
CPV voltage
V
TEST pin voltage
Output source current
Output sink current
Output sink current
DIAG Output voltage
DIAG Output current
Power dissipation
Operating temperature
Junction temperature
Strage temperature
VTEST
40
V
IOUT1
–10
mA
mA
mA
V
(1)
(2)
IOUT1
+10
IOUT2
+400
VDIAG
IDIAG
PD
–0.3 to 40.0
5
mA
W
°C
°C
°C
1.16
Topr
Tj
–40 to 150
150
Tstg
–55 to 150
Note1: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage
and the significant change in temperature, etc.) may cause this product to decrease in the
reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage,
etc.) are within the absolute maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability
Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability
data (i.e. reliability test report and estimated failure rate, etc.)
8.1. Thermal Resistance
Table 8.2 Thermal resistance
Charateristics
Symbol
Rth (j–a)
Rating
108
unit
Thermal resistance(junction-to-
ambient)
°C / W
Note2: Glass epoxy board
Material: FR-4(4 layer) Board size: 76.2mmx114.3mmx1.6mm
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9. Operating Ranges
Table 9.1 Operating Ranges
Characteristics
Symbol
VDD
Condition
Min
Typ.
Max
Unit
Operating supply voltage
Tj = -40 to 150°C
4.5
12.0
27.0
V
10. Electrical Characteristics
Table 10.1 Electrical Characteristics
(Unless otherwise specified, Tj = -40 to 150°C, VDD = 4.5 to 27.0V)
Characteristics
Symbol
Pin
Test Condition
Min
Typ.
Max
Unit
IDD(1)
IDD(2)
VDD
VDD
VDD = 12V, VSTBY = VIL, Tj = 25°C
-
-
-
5.0
6.0
μA
VIN1,2 = VIL, VSTBY = VIH, C1,C2 = 0.01μF
3.2
mA
Supply current
V
IN1 = VIH, VSTBY = VIH, C1,C2 = 0.01μF,
IDD(3)
VDD
-
-
6.0
mA
V
OUT1,OUT2 = open.
High level input voltage
Low level input voltage
VIH
VIL
IIH
-
2.0
-
-
-
-
IN1,IN2,
STBY
-
0.8
100
1
VIN = 5V, Note1
VIN = 0V
-
50
-
IN1,IN2,
STBY
Input current
μA
IIL
-1
VDD = 18 to 27V, C1,C2 = 0.01μF,
VIN1 = VIH, VSTBY = VIH, IOUT1 = -0.1mA
VDD
+7.0
VOH1
VOH2
VOH3
VOCL
VOL1
VOL2
OUT1
OUT1
OUT1
OUT1
OUT1
OUT2
-
40.0
VDD
VDD = 8 to 18V, C1,C2 = 0.01μF,
VDD
VDD
High level output voltage
V
VIN1 = VIH, VSTBY = VIH, IOUT1 = -0.1mA
+10.0 +12.0 +14.0
VDD = 4.5 to 8V, VIN1 = VIH,
VDD
+5.4
VDD
+7.0
VDD
+14.0
VSTBY = VIH, IOUT1 = -0.1mA
VIN1 = VIH, VSTBY = VIH,
C1,C2 = 0.01μF, IOUT1 = +0.1mA
Output clamp voltage
34
-
37
-
40
0.1
1.3
V
V
VIN1 = VIL, VSTBY = VIH,
C1,C2 = 0.01μF, IOUT1 = +0.1mA
Low level output voltage
VIN2 = VIH, VSTBY = VIH,
C1,C2 = 0.01μF, IOUT2 = +0.1A
-
0.5
Diagnosis output leakage
current
IDIAGH
VDIAGL
fOSC
DIAG VIN1=VIL, VDIAG=5V
-
-
-
1
μA
V
Diagnosis output voltage
Charge pump frequency
DIAG VSTBY = VIH, IDIAG = 500μA
0.22
55
0.40
80
CP1,
VSTBY = VIH
CP2
30
kHz
VDD
+4.0
VDD
+4.7
VDD
+5.4
Charge pump under voltage
detection voltage
VCPL
CPV
V
V
VIN1 = VIH, VSTBY = VIH
Charge pump under voltage
Hysteresis
ΔVCPL
CPV
0.25
0.50
1.00
RONH
RONL1
RONL2
OUT1 VIN1 = VIH, VSTBY = VIH,IOUT1 = -5mA
OUT1 VIN1 = VIL, VSTBY = VIH,IOUT1 = +5mA
OUT2 VIN2 = VIH, VSTBY = VIH,IOUT2 = +0.1A
-
-
-
16
630
5
40
800
13
Output driver on resistance
Ω
（Continued on next page）
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（Continued from previous page）
Characteristics
Symbol
Pin
Test Condition
Min
Typ.
Max
Unit
tON
-
-
0.1
0.4
0.5
0.5
IN1,
Refer to test circuit 1, Tj=25°C
Refer to test circuit 2, Tj=25°C
ms
OUT1
tOFF1
Switching time
IN2,
OUT2
tOFF2
tO2ON
-
10
15
μs
μs
IN2,
OUT2
Rapid off drive operation time
Tj=25°C
50
100
200
IREV1
IREV2
OUT1
OUT2
-10
-10
-
-
-
-
μA
μA
Refer to test circuit 3
Output current in reverse
connection
V
DD=-4.5 to -18V
Note1: Built in pull down resistance 100kΩ(typ.).
Note2: Typical value is VDD=12V and Tj=25°C condition.
11. Test Circuit
11.1. Test circuit 1
12V
24V
VIN1
1
2
3
4
5
6
7
8
CP1-
TEST
CP1
VDD
CP2- 16
N.C. 15
VDD+4V
1.4V
VOUT1
14
CP2
13
12
CPV
tON
tOFF1
STBY
IN1
OUT1
1kΩ
VIN1
OUT2 11
VOUT1
IN2
DIAG
VM
10
9
GND1
GND2
Figure 11.1 Switching time measurement circuit (1)
11.2. Test circuit 2
12V
24V
VIN2
1
2
3
4
5
6
7
8
CP1-
TEST
CP1
VDD
CP2- 16
N.C. 15
≒VCPV
14
CP2
1.4V
VOUT2
13
12
CPV
1kΩ
10Ω
STBY
IN1
tOFF2
OUT1
OUT2 11
VOUT2
VIN2
IN2
DIAG
VM
10
9
GND1
GND2
Figure 11.2 Switching time measurement circuit (2)
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11.3. Test circuit 3
0.1μF
-4.5 to -18V
1
2
3
4
5
6
7
8
CP1-
TEST
CP1
VDD
CP2- 16
N.C. 15
14
VM
CP2
VM
13
12
CPV
STBY
IN1
OUT1
VOUT1
VOUT2
OUT2 11
IN2
IREV*=VOUT*/100kΩ
DIAG
10
9
GND1
GND2
Figure 11.3 Output current in reverse connection measurement circuit
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12. Characteristic curves
The below characteristics curves are presented for reference only and not guaranteed by production test,
unless otherwise noted.
5
VDD=12V
4
3
2
1
0
-80
-40
0
40
80 120 160
Junction temperature T [℃]
ｊ
Figure 12.1 IDD(1) - Tj
5
4
3
2
1
0
5
4
3
2
1
0
IDD(3)
IDD(3)
IDD(2)
IDD(2)
VDD=12V
Tj=25°C
-80
-40
0
40
80
120 160
0
10
20
30
Junction temperature Tｊ [℃]
Supply voltage VDD [V]
Figure 12.2 IDD - VDD
Figure 12.3 IDD - Tj
5
4
3
2
1
0
5
VDD=12V, STBY
Tj=25°C, STBY
4
3
2
1
0
VIH
VIH
VIL
VIL
-80
-40
0
40
80
120 160
0
10
20
30
Junction temperature Tｊ [℃]
Supply Power VDD [V]
Figure 12.4 VIH,VIL - VDD
Figure 12.5 VIH,VIL - Tj
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5
4
3
2
1
0
5
4
3
2
1
0
Tj=25°C
VDD=12V
V
V
IH
IL
VIH
VIL
-80
-40
0
40
80
120 160
0
10
20
30
Junction temperature Tｊ [℃]
Supply voltage VDD [V]
Figure 12.6 VIH,VIL - VDD
Figure 12.7 VIH,VIL - Tj
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
Tj=25°C
VDD=12V
VSTBY=5V
VSTBY=5V
-80
-40
0
40
80
120 160
0
10
20
30
Junction temperature Tｊ [℃]
Supply voltage VDD [V]
Figure 12.8 IIH - VDD
Figure 12.9 IIH - Tj
80
80
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
VDD=12V
VIN1=5V
Tj=25°C
VIN1=5V
-80
-40
0
40
80
120 160
0
10
20
30
Junction temperature Tｊ [℃]
Supply voltage VDD [V]
Figure 12.10 IIH - VDD
Figure 12.11 IIH - Tj
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50
40
30
20
10
0
50
40
30
20
10
0
VDD=12V
VIN1=VIH, IOUT1=-0.1mA
Tj=25℃
VIN1=VIH, IOUT1=-0.1mA
0
10
20
30
-80
-40
0
40
80
120 160
Supply voltage VDD [V]
Junction temperature Tj [℃]
Figure 12.12 VOUT1 - VDD
Figure 12.13 VOUT1 - Tj
50
VDD=27V
45
40
35
30
-80
-40
0
40
80
120 160
Junction temperature Tj [℃]
Figure 12.14 VOCL - Tj
0.1
0.08
0.06
0.04
0.02
0
0.1
0.08
0.06
0.04
0.02
0
VDD=12V
VIN1=VIL, IOUT1=+0.1mA
Tj=25°C, VIN1=VIL, VSTBY=VIH,
IOUT1=+0.1mA
-80 -40
0
40
80 120 160
0
10
20
30
Supply voltage VDD [V]
Junction temperature Tj [℃]
Figure 12.15 VOL1 - VDD
Figure 12.16 VOL1 - Tj
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2
1.5
1
2
1.5
1
VDD=12V, VIN2=VIH, VSTBY=VIH
Tj=25°C, VIN2=VIH, VSTBY=VIH
,
,
IOUT2=+0.1A
IOUT2=+0.1A
0.5
0
0.5
0
0
10
20
30
-80
-40
0
40
80
120 160
Supply voltage VDD [V]
Junction temperature Tj [℃]
Figure 12.17 VOL2 - VDD
Figure 12.18 VOL2 - Tj
1
1
VDD=12V
Tj=25°C
VSTBY=VIL, VDIAG=5V
VSTBY=VIL, VDIAG=5V
0.1
0.1
0.01
0.01
0.001
0.001
0.0001
0.0001
0
10
20
30
-80 -40
0
40
80 120 160
Supply voltage VDD [V]
Junction temperature Tｊ [℃]
Figure 12.19 IDIAGH - VDD
Figure 12.20 IDIAGH - Tj
0.5
0.4
0.3
0.2
0.1
0.5
0.4
0.3
0.2
0.1
0
Tj=25°C
VDD=12V
VSTBY=VIH, IDIAG=500μA
V
STBY=VIH, IDIAG=500μA
0
0
-80 -40
0
40
80 120 160
10
20
30
Junction temperature Tｊ [℃]
Supply voltage VDD [V]
Figure 12.21 IDIAGL - VDD
Figure 12.22 IDIAGL - Tj
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80
70
60
50
40
30
80
70
60
50
40
30
VDD=12V, VSTBY=VIH
Tj=25°C, VSTBY=VIH
-80
-40
0
40
80
120 160
0
10
20
30
Junction temperature Tj [℃]
Supply voltage VDD [V]
Figure 12.23 fOSC - VDD
Figure 12.24 fOSC - Tj
7
7
VDD=12V, VIN1=VIH
V
STBY=VIH
,
Tj=25°C, VIN1=VIH
V
STBY=VIH
,
6
5
4
3
6
5
4
3
-80 -40
0
40
80
120 160
0
10
20
30
Junction temperature Tj [℃]
Supply voltage VDD [V]
Figure 12.25 VCPL - VDD
Figure 12.26 VCPL - Tj
1
1
VDD=12V, VIN1=VIH
V
STBY=VIH
Tj=25°C, VIN1=VIH
V
STBY=VIH
,
,
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
-80 -40
0
40
80 120 160
0
10
20
30
Junction temperature Tj [℃]
Supply voltage VDD [V]
Figure 12.27 ΔVCPL - VDD
Figure 12.28 ΔVCPL - Tj
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40
30
20
10
0
40
30
20
10
0
Tj=25°C, VIN1=VIH, VSTBY=VIH,
IOUT1=-5mA
VDD=12V, VIN1=VIH, VSTBY=VIH,
IOUT1=-5mA
0
10
20
30
-80
-40
0
40
80
120 160
Supply voltage VDD [V]
Junction temperature Tj [℃]
Figure 12.29 RONH - VDD
Figure 12.30 RONH - Tj
800
600
400
200
0
800
600
400
200
0
Tj=25°C, VIN1=VIL, VSTBY=VIH,
IOUT1=+5mA
VDD=12V, VIN1=VIL, VSTBY=VIH,
I
OUT1=+5mA
-80 -40
0
40
80
120 160
0
10
20
30
Junction temperature Tj [℃]
Supply voltage VDD [V]
Figure 12.31 RONL1 - VDD
Figure 12.32 RONL1 - Tj
20
15
10
5
20
15
10
5
VDD=12V, VIN2=VIH, VSTBY=VIH,
IOUT2=+0.1A
Tj=25°C, VIN2=VIH, VSTBY=VIH,
IOUT2=+0.1A
0
0
-80
-40
0
40
80
120 160
0
10
20
30
Junction temperature Tj [℃]
Supply voltage VDD [V]
Figure 12.33 RONL2 - VDD
Figure 12.34 RONL2 - Tj
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Toshiba Electronic Devices & Storage Corporation
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TPD7106F
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
VDD=12V
VDD=12V
-80
-40
0
40
80
120 160
-80
-40
0
40
80
120 160
Junction temperature Tj [℃]
Junction temperature Tj [℃]
Figure 12.35 tON - Tj
Figure 12.36 tOFF1 - Tj
200
20
15
10
5
VDD=12V
VDD=12V
150
100
50
0
0
-80 -40
0
40
80
120 160
-80
-40
0
40
80
120 160
Junction temperature Tj [℃]
Junction temperature Tj [℃]
Figure 12.37 tOFF2 - Tj
Figure 12.38 tO2ON - Tj
5
4
3
2
1
0
5
4
3
2
1
0
VDD=12V
Tj=25℃
IREV2
IREV1
IREV2
IREV1
80 120 160
-20
-15
-10
-5
0
-80 -40
0
40
Supply voltage VDD [V]
Junction temperature Tj [℃]
Figure 12.39 IREV1, IREV2 - VDD
Figure 12.40 IREV1, IREV2 - Tj
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Toshiba Electronic Devices & Storage Corporation
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TPD7106F
13. Package Information
13.1. Package Dimensions
Unit: mm
Weight: 0.074 g (typ.)
Figure 13.1 Package Dimensions
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Toshiba Electronic Devices & Storage Corporation
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TPD7106F
13.2. Marking
Part No.
Lot No.
(Last digit of the year and weekly code.)
Assembly code (2digits)
The lower left marking is shown No. 1 terminal.
Figure 13.2 Marking
13.3. Land Pattern Dimensions for Reference only
Unit: mm
Figure 13.3 Land Pattern Dimensions for Reference only
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Toshiba Electronic Devices & Storage Corporation
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TPD7106F
14. IC Usage Considerations
14.1. Notes on Handling of ICs
(1) The absolute maximum ratings of a semiconductor device are a set of ratings that must not be
exceeded, even for a moment.
(2) Immediately after power activation, by the constant of external elements, since a pulse may occur
in a DIAG output signal, please do not use the DIAG output signal immediately after power
activation for diagnosis of operation of a product.
15. Application Circuit Example
+Battery
C1
U1
CP2-
CP1-
TEST
CP1
Q3
Q4
Q1
Q2
C2
C3
C4
N.C
CP2
R4
CPV
VDD
MCU
R1
R2
D1,D2
OUT1
OUT2
DIAG
GND2
STBY
IN1
IN2
R3
+5V
GND1
▪ U1: TPD7106F
▪ Q1,Q2,Q3,Q4: N channel power MOSFET/40V
▪ D1,D2: CRZ16
▪ R1: 1kΩ
▪ R2: 10Ω
▪ R3: 10kΩ
▪ R4: 200kΩ
▪ C1: 10μF/50V
▪ C2,C3: 0.1μF/50V
▪ C4: 1μF/50V
Figure 15.1 Application Circuit Example
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TPD7106F
RESTRICTIONS ON PRODUCT USE
Toshiba Corporation and its subsidiaries and affiliates are collectively referred to as “TOSHIBA”.
Hardware, software and systems described in this document are collectively referred to as “Product”.
• TOSHIBA reserves the right to make changes to the information in this document and related Product without notice.
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written permission, reproduction is permissible only if reproduction is without alteration/omission.
• Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are responsible for
complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which
minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily injury or damage to
property, including data loss or corruption. Before customers use the Product, create designs including the Product, or incorporate the
Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA information,
including without limitation, this document, the specifications, the data sheets and application notes for Product and the precautions and
conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application with which the Product
will be used with or for. Customers are solely responsible for all aspects of their own product design or applications, including but not limited
to (a) determining the appropriateness of the use of this Product in such design or applications; (b) evaluating and determining the
applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any
other referenced documents; and (c) validating all operating parameters for such designs and applications. TOSHIBA ASSUMES NO
LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR APPLICATIONS.
•
PRODUCT IS NEITHER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE
EXTRAORDINARILY HIGH LEVELS OF QUALITY AND/OR RELIABILITY, AND/OR A MALFUNCTION OR FAILURE OF WHICH MAY
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("UNINTENDED USE"). Except for specific applications as expressly stated in this document, Unintended Use includes, without limitation,
equipment used in nuclear facilities, equipment used in the aerospace industry, lifesaving and/or life supporting medical equipment,
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•
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INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES OR LOSS, INCLUDING
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OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS.
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