PMV117EN [TYSEMI]
uTrenchMOS enhanced logic level FET Very fast switching; uTrenchMOS增强逻辑电平FET的快速切换
| 型号： | PMV117EN |
| 厂家： | 
TY Semiconductor Co., Ltd |
| 描述： | uTrenchMOS enhanced logic level FET Very fast switching |
| 文件： | 总3页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Product specification
PMV117EN
µTrenchMOS™ enhanced logic level FET
Rev. 02 — 7 April 2005
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS™ technology.
1.2 Features
■ Logic level threshold
■ Very fast switching
■ Subminiature surface-mounted
package
1.3 Applications
■ Battery management
■ High-speed switch
■ Low power DC-to-DC converter
1.4 Quick reference data
■ VDS ≤ 30 V
■ ID ≤ 2.5 A
■ RDSon ≤ 117 mΩ (VGS = 10 V)
■ Ptot ≤ 0.83 W
2. Pinning information
Table 1:
Pinning
Pin
1
Description
gate (G)
Simplified outline
Symbol
D
S
3
2
source (S)
drain (D)
3
G
1
2
mbb076
SOT23
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Product specification
PMV117EN
µTrenchMOS™ enhanced logic level FET
3. Ordering information
Table 2:
Ordering information
Type number
Package
Name
Description
Version
PMV117EN
TO-236AB plastic surface mounted package; 3 leads
SOT23
4. Limiting values
Table 3:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
30
Unit
V
VDS
VDGR
VGS
ID
drain-source voltage (DC)
25 °C ≤ Tj ≤ 150 °C
-
drain-gate voltage (DC)
gate-source voltage (DC)
drain current (DC)
25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ
-
30
V
-
±20
2.5
V
Tsp = 25 °C; VGS = 10 V; Figure 2 and 3
Tsp = 100 °C; VGS = 10 V; Figure 2
Tsp = 25 °C; pulsed; tp ≤ 10 µs; Figure 3
Tsp = 25 °C; Figure 1
-
A
-
1.6
A
IDM
Ptot
Tstg
Tj
peak drain current
-
10
A
total power dissipation
storage temperature
junction temperature
-
0.83
+150
+150
W
°C
°C
−65
−65
Source-drain diode
IS
source (diode forward) current (DC) Tsp = 25 °C
-
-
0.8
3.3
A
A
ISM
peak source (diode forward) current Tsp = 25 °C; pulsed; tp ≤ 10 µs
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Product specification
PMV117EN
µTrenchMOS™ enhanced logic level FET
5. Characteristics
Table 4:
Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max Unit
Static characteristics
V(BR)DSS drain-source breakdown voltage
ID = 10 µA; VGS = 0 V
Tj = 25 °C
30
27
37
-
-
-
V
V
Tj = −55 °C
VGS(th)
gate-source threshold voltage
drain-source leakage current
ID = 1 mA; VDS = VGS; Figure 9 and 10
Tj = 25 °C
1.5
1.1
-
2
-
-
V
V
V
Tj = 150 °C
-
Tj = −55 °C
-
2.7
IDSS
VDS = 24 V; VGS = 0 V
Tj = 25 °C
-
-
-
0.01 0.5
µA
µA
nA
Tj = 150 °C
-
10
IGSS
gate-source leakage current
VGS = ±20 V; VDS = 0 V
VGS = 10 V; ID = 500 mA; Figure 6 and 8
Tj = 25 °C
10
100
RDSon
drain-source on-state resistance
-
-
-
74
117
mΩ
VGS = 4.5 V; ID = 500 mA; Figure 6 and 8
Tj = 25 °C
117
188
190
300
mΩ
mΩ
Tj = 150 °C
Dynamic characteristics
Qg(tot)
Qgs
Qgd
Ciss
Coss
Crss
td(on)
tr
total gate charge
gate-source charge
gate-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
ID = 0.5 A; VDD = 15 V; VGS = 10 V;
Figure 11
-
-
-
-
-
-
-
-
-
-
4.6
0.6
1.35
147
65
-
-
-
-
-
-
-
-
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
VGS = 0 V; VDS = 10 V; f = 1 MHz;
Figure 13
41
VDD = 15 V; RL = 15 Ω; VGS = 10 V
4
7.5
18
td(off)
tf
turn-off delay time
fall time
13
Source-drain diode
VSD
trr
source-drain (diode forward) voltage IS = 0.83 A; VGS = 0 V; Figure 12
reverse recovery time IS = 1 A; dIS/dt = −100 A/µs; VGS = 0 V;
-
-
0.7
69
1.2
-
V
ns
VDS = 25 V
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