UP1566PQKF [UPI]

Complete DDR3/ DDR4 Memory Power Solution Controller;


型号：	UP1566PQKF
厂家：	uPI Semiconductor Corp.
描述：	Complete DDR3/ DDR4 Memory Power Solution Controller 双倍数据速率
文件：	总14页 (文件大小：208K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

uP1566

Complete DDR3/ DDR4 Memory Power Solution Controller

Features

General Description

The uP1566 is a high performance synchronous buck Synchronous Buck Controller (VDDQ)

controller with 1.5Asource/sink LDO for memory system

Wide Input Voltage Range from 4.5V to 26V

Fast Load Transient Response

RCOT^TMControl Topology

power. It also provides a buffered low noise reference

VTTREF. The uP1566 has wide operation range from 4.5V

to 26V for input voltage and 0.75V to 3.3V for memory

output voltage.

Soft-Off in S4/S5 States

The synchronous buck of the uP1566 adopts uPI

proprietary robust constant on-time (RCOT^TM) PWM

scheme that features easy-to-use, low external component

count, fast transient response and quasi-constant

frequency operation over the operation range.

Lossless R_DS(ON)Current Sensing for Inductor

Current Limit

Fixed 1.5V (DDR3), 1.8V (DDR2) Output or

Adjustable from 0.75V to 3.3V

The 1.5A source/sink LDO for VTT has fast transient

response, requiring only two 10uF of ceramic output

capacitors. In addition, the LDO supply input is available

externally to significantly reduce the total power losses.

The uP1566 supports all the sleep state controls, in S3

state (suspend to RAM) VTT is disable and in S4/S5

(suspend to disk) VDDQ, VTT and VTTREF are soft off.

POK, OVP, UVP and Thermal Shutdown

LDO (VTT)

1.5A Source/Sink Capability

Requires Only Two 10uF Ceramic Output

Capacitors

Disable in S3 and Soft-Off in S4/S5

Thermal Shutdown

The uP1566 has complete functions including under

voltage protection, over current protection, over voltage

protection, power-up sequencing, power OK output, and

thermal shutdown. The uP1566 is available in WQFN3x3-

20L package.

20mV Accuracy

Reference Voltage (VTTREF)

20mV Accuracy

Low Noise 10mA Output

Applications

Desktop PCs, Notebooks, and Workstations

Pin Configuration

Microprocessor and Chipset Supplies

DDR3/DDR3L/DDR4 Memory Power Supplies

SSTL-2 SSTL-18 and HSTL Bus Termination

20 19 18 17 16

VTTGND

VTTSNS

GND

15 LGATE

14 PGND

13 CS

Ordering Information

GND

Order Number

uP1566PQKF

Package Type

WQFN3x3-20L

Top Marking

u1566P

VTTREF

VDDQ

12 PVCC

11 VCC

Note: uPI products are compatible with the current IPC/

JEDEC J-STD-020 requirement. They are halogen-free,

RoHS compliant and 100% matte tin (Sn) plating that are

suitable for use in SnPb or Pb-free soldering processes.

WQFN3x3 – 20L

uP1566-DS-P0000, Jan. 2013

www.upi-semi.com

uP1566

Typical Application Circuit

V_IN

TON

BOOT

PVCC

UGATE

PHASE

V_VDDQ

VCC

LGATE

POK

VTTIN

VDDQ

VTTREF

GND

VTT

V_VTT

PGND

VTTGND VTTSNS

Exposed Pad

Adjustable Output Voltage Regulator for VDDQ

V_IN

TON

BOOT

PVCC

UGATE

PHASE

V_VDDQ

1.8V/1.5V

VCC

LGATE

To 5V for DDRII

To GND for DDRIII

POK

VTTIN

VDDQ

VTTREF

VTT

V_VTT

0.9V/0.75V

GND

VTTSNS

PGND

VTTGND

Exposed Pad

Fixed Output Voltage Regulator for VDDQ

uP1566-DS-P0000, Jan. 2013

www.upi-semi.com

uP1566

Functional Pin Description

Pin No. Pin Name Pin Function

Power Ground for the VTT LDO.

VTTGND

VTTSNS

GND

VTT LDO Output Voltage Sense. Connect this pin to the VTT LDO output capacitors for

VTT output voltage sensing.

Signal Ground for the IC. All voltage levels are measured with respect to this pin.

Buffered Reference Output. Bypass this pin with a 33nF ceramic capacitor to GND. This

pin is capable of sourcing up to 10mA current for external loads.

VTTREF

Reference Input for VTT and VTTREF. Connect this pin to the VDDQ output. This pin is

the discharge current sinking terminal of VDDQ output inS4/S5 states. WhenVDDQ regulator

is in fixed output configuration (FB pin is tied to VCC or GND), this pin is the output voltage

feedback input.

VDDQ

VDDQ Voltage Feedback Input. This pinis the inverting input of the error amplifier. Aresistor

divider from output to GND is used to set the regulator output voltage. For fixed output voltage

application, connect this pin to VCC for DDR2 power supply, or connect this pin to GND for

DDR3 power supply.

S3 Signal Input. Connect this pin to the computer system's SLP_S3 signal. This pin

companied withS5 switches the IC's operating state from active (S0, S1/S2) to S3 and S4/S5

sleep states.

S5 Signal Input. Connect this pin to the computer system's SLP_S5 signal. This pin

companied withS3 switches the IC's operating state from active (S0, S1/S2) to S3 and S4/S5

sleep states.

On-Time Setting Pin. Connect a resistor from this pin to V_INto set the on-time for the upper

MOSFET.

TON

Power OK Indication. POK is the open-drain architecture that indicates the output voltage

is ready or not. This pin is set to high impedance when the output voltage is within regulation

and the soft-start ends. POK is pulled low immediately when either output is in soft-start,

standby, shutdown or fault protection.

POK

5V Power Supply Input. This pin provides power for internal circuit. Bypass this pin with a

1uF ceramic capacitor to GND.

VCC

PVCC

Supply Voltage for the Gate Drivers. Connect this pin to 5V voltage source and bypass it

to GND with at least 1uF ceramic capacitor.

Current Limit Threshold Setting. Connect this pin through the setting resistor to VCC for

inductor current limit threshold setting.

Power Ground. This pin is dedicated for lower MOSFET gate driver and should be directly

connected to the source of the lower MOSFET with an isolated path.

PGND

Lower MOSFET Gate Driver Output. This pin is monitored by the shoot-through protection

circuitry to determine when the lower MOSFET has turned off. Connect this pin to the gate of

lower MOSFET.

LGATE

PHASE

Switch Node. This pin is used as the sink for the upper MOSFET gate driver. This pin is

also monitored bythe shoot-throughprotectioncircuitryto determine whenthe upper MOSFET

has turned off. Connect this pin to the source of the upper MOSFET and the drain of the lower

MOSFET.

Upper MOSFET Gate Driver Output. This pin is monitored by the shoot-through protection

UGATE circuitry to determine when the upper MOSFET has turned off. Connect this pin to the gate of

upper MOSFET.

uP1566-DS-P0000, Jan. 2013

www.upi-semi.com

uP1566

Functional Pin Description

Pin No. Pin Name Pin Function

Bootstrap Supply for the Floating Upper MOSFET Gate Driver. The bootstrap capacitor

provides the charge to turn on the upper MOSFET. Connect this bootstrap capacitor between

BOOT pin and the PHASE pin to form a bootstrap circuit.

BOOT

VTTIN

VTT

Input for the VTT LDO. This is the drain input to the power device that supplies current to

the VTT pin.

Output for the VTT LDO. This pin is the output of VTT. Typical value of two 10uF ceramic

capacitors is recommended to reduce the effects of current transients on VOUT. A pull low

resistance exists when the device is disabled.

Exposed

Pad

Ground. The exposed pad dominates heat conduction path and should be well soldered to

PCB for optimal thermal performance.

Functional Block Diagram

Output Enable

and Discharge

Enable

POR

VCC

POK

V_POK

V_OV

VTTREF

VTTIN

PVCC

V_UV

BOOT

UGATE

VTT

Control

Logic

PHASE

LGATE

PGND

VTTGND

VTTSNS

VDDQ

Zero Cross

Detection

Current

Limit

Ramp

Generator

Soft-Start

On-time

Calculator

Reference

Voltage

GND

TON

uP1566-DS-P0000, Jan. 2013

www.upi-semi.com

uP1566

Functional Description

The uP1566 is a high performance synchronous buck

controller with 1.5A source/sink VTT LDO for memory

system power. It also provides the buffered low noise

reference with 10mA capability.

BOOT

V_IN

UGATE

PHASE

V_VDDQ

The buck controller adopts RCOT^TMPWM scheme that

features easy-to-use, low external component count, fast

transient response and quasi-constant frequency operation

over the operation range.

LGATE

R_FB1

R_FB2

The 1.5Asource/sink VTT LDO has fast transient response

that only requires two 10uF of ceramic output capacitors.

GND

VDDQ

The reference voltage tracks VDDQ/2 within 1% of VDDQ.

The VTT tracks VTTREF within 20mV at no load condition

and within 40mV over all load conditions.

Figure 1. VDDQ Output Voltage Setting

On-Time Setting

The uP1566 supports all the sleep state controls, and also

has complete functions including over current protection,

over voltage protection, thermal shutdown, power-up

sequencing, power OK output, and thermal shutdown. The

uP1566 is available in space-saving WQFN3x3-20L

package.

The uP1566 adopts a compensated constant-on-time

control scheme. A resistor R_TONconnected to T_ONpin

programs the constant on time according to equation:

3.8×10⁻¹²× VDDQ×R_TON

T_ON

VIN − 0.5V

Output Voltage Selection

where RTON is in kΩ, VIN is the supply input voltage and

VDDQ is the sensed output voltage.

As shown in Table 1, uP1566 can support DDR2, DDR3,

DDR3L,DDR4 power supply or adjustable output voltage

by connecting resistor divider to the FB pin.

700

600

500

400

300

200

Table 1. Output Voltage Selection

VTTREF

and VTT

VDDQ

Application

Connection

VCC

GND

1.8 V

1.5 V

VDDQ / 2

DDR2

DDR3

DDR3L, DDR4

0.75V < V_VDDQ

< 3.3V

Resistor

Divider

Adjustable VDDQ / 2

The uP1566 can adjust output voltage by connecting a

resistive voltage divider between VDDQ and GND as

shown in Figure 1. Choose R_FB2to be approximately 10kΩ

and solve R_FB1using the equation as below:

400

500

600

700

800

900 1000

R_TON(kohm)

Figure 2. Switching Frequency vs. R_TON

Soft Start and POK

R_FB1

V_DDQ= V_REF×(1+

)

R_FB2

The soft-start function of the uP1566 for VDDQ is achieved

by ramping up reference as shown in Figure 3. After S5 is

set high, the VREF is rising. There is a time delay between

VREF ramping up and VDDQ rising.After that, the uP1566

initiates soft-start operation.

where V_REFis 0.75V (typ.).

The POK is an open-drain output. The uP1566 asserts

POK high impedance output if the output voltage is within

regulation with a time delay after soft-start end. Anytime

the fault protection is triggered, the POK signal will go low

immediately.

uP1566-DS-P0000, Jan. 2013

www.upi-semi.com

uP1566

Functional Description

level is higher than V_OCSET. When triggered, the over current

limit will keep upper MOSFET off even the voltage loop

commands it to turn on.

V_S5

The output voltage will decrease if the load continuously

demands more current than current limit level. Further

increase in load current higher than the current limit level

will eventually let V_VDDQdecrease to trip UVP to shut down

the uP1566.

V_VREF

V_VDDQ

V_POK

The current limit threshold is set by connecting a resistor

from CS to VCC. The CS pin will sink a 10uA current

Figure 3. VDDQ Soft Start and POK Timing

source and create a voltage drop across R_CSas the V_OCSET

VDDQ Light Load Operation

V_OCSET= 10uA x R_CS.

The uP1566 automatically reduces switching frequency

at light load to maintain high efficiency. As the output

current decreases from heavy-load condition, the inductor

current will also be reduced, and eventually comes to the

point that its valley touches zero current, which is the

boundary between continuous conduction and

discontinuous conduction modes. By emulating the

behavior of diodes, the lower MOSFET allows only partial

of negative current when the inductor freewheeling current

reaches negative.As the load current is further decreased,

it takes longer time to discharge the output capacitor to

the level than requires the next ON cycle.

When the voltage drop across the lower MOSFET equals

the voltage across the setting resistor, the current limit

will be activated.

The voltage across PHASE and PGND pins is compared

with V_OCSETfor current limit. The current limit level is

calculated as:

V_OCSETI_RIPPlE

I_LIM

R_DS(ON)

where I_RIPPLEis the peak-to-peak inductor ripple current at

steady state.

Outputs Control by S3, S5

Over Voltage/Under Voltage Protection

The uP1566 provides the output management for the

sleep-mode signals such as SLP_S3 and SLP_S5 in the

notebook PC system by monitoring S3, S5 status, the

output control table is as shown in Table 2 below.

The uP1566 monitors FB voltage to detect overvoltage

and undervoltage condition of VDDQ output.

When the FB voltage becomes higher than 115% of the

target voltage, the OVP is triggered. Then, upper

MOSFET is off and lower MOSFET is on. When the FB

voltage is lower than 70% of the target voltage, the UVP

is triggered after 30us fault detection. Then, upper

MOSFET and lower MOSFET are latched off. This function

is enabled 5ms after S5 go high to ensure startup.

Table 2. S0, S3 and S5 State

State

S5 VDDQSNS VTTREF

VTT

High High

Off

Low

High

Low

Off (Hi-Z)

Off

VCC UVLO

(discharge) (discharge) (discharge)

The VCC has under voltage lockout protection (UVLO).

When the VCC voltage is lower than UVLO threshold

voltage, all functions are turned off. This is non-latch

protection.

Ouput Discharge Control

The uP1566 is in non-tracking discharge mode when it

enters S4/S5 state. In this non-tracking discharge mode,

the uP1566 discharges the VDDQ and VTT outputs

through the internal MOSFETs with 15Ω R_DS(on)which are

connected from VDDQ toGND, and from VTT to VTTGND,

respectively.

Thermal Protection

The uP1566 monitors the temperature of itself. If the

temperature exceeds typical 165^OC, the uP1566 will be

turned off. This is non-latch protection.

Output Current Limit

The synchronous buck VDDQ monitors the inductor valley

current by lower MOSFET R_DS(ON)when it turns on. The

over current limit is triggered once the sensing current

uP1566-DS-P0000, Jan. 2013

www.upi-semi.com

uP1566

Absolute Maximum Rating

(Note 1)

VCC, PVCC to GND ----------------------------------------------------------------------------------------------------------- -0.3V to +6V

BOOT to PHASE ------------------------------------------------------------------------------------------------------------- -0.3V to +6V

PHASE to GND

DC ------------------------------------------------------------------------------------------------------------------------- -0.3V to +30V

< 200ns -------------------------------------------------------------------------------------------------------------------- -5V to +38V

UGATE to PHASE

DC---------------------------------------------------------------------------------------------------------------------- -0.3V to +6V

< 200ns ---------------------------------------------------------------------------------------------------------------- -5V to +7V

LGATE to GND

DC ------------------------------------------------------------------------------------------------------------------------ -0.3V to +6V

< 200ns ----------------------------------------------------------------------------------------------------------------- -2V to +7V

Other Pins ----------------------------------------------------------------------------------------------------------------------- -0.3V to +6V

Storage Temperature Range ----------------------------------------------------------------------------------- -65^OC to +150^OC

Junction Temperature ------------------------------------------------------------------------------------------------------- 150^OC

Lead Temperature Range(Soldering 10sec) ------------------------------------------------------------------------------------------- 260^OC

ESD Rating (Note 2)

HBM(Human Body Mode)---------------------------------------------------------------------------------------------------------------2KV

MM(Mechine Mode)-----------------------------------------------------------------------------------------------------------------------200V

Thermal Information

Package Thermal Resistance (Note 3)

WQFN3x3-20L θ_JA------------------------------------------------------------------------------------------------------- 68°C/W

WQFN3x3-20L θ_JC---------------------------------------------------------------------------------------------------------- 6°C/W

Power Dissipation, P_D@ T_A= 25°C

WQFN3x3-20L ------------------------------------------------------------------------------------------------------------------ 1.47W

Recommended Operation Conditions

(Note 4)

Supply Input Voltage, V_IN------------------------------------------------------------------------------------------------------- 4.5V to 26V

Control Voltage, VCC, PVCC ----------------------------------------------------------------------------------------------- 4.5V to 5.5V

Operating Junction Temperature Range -------------------------------------------------------------------- -40^OC to +125^OC

Operating Ambient Temperature Range -------------------------------------------------------------------------------- -40^OC to +85^OC

Note 1. Stresses listed as the above Absolute Maximum Ratings may cause permanent damage to the device.

These are for stress ratings. Functional operation of the device at these or any other conditions beyond

those indicated in the operational sections of the specifications is not implied. Exposure to absolute

maximum rating conditions for extended periods may remain possibility to affect device reliability.

Note 2. Devices are ESD sensitive. Handling precaution recommended.

Note 3. θ_JAis measured in the natural convection at T_A= 25°C on a high effective thermal conductivity test board of

JEDEC 51-7 thermal measurement standard.

Note 4. The device is not guaranteed to function outside its operating conditions.

Note 5. Guarantee by design.

uP1566-DS-P0000, Jan. 2013

www.upi-semi.com

uP1566

Electrical Characteristics

(V_IN= 15V, V_PVCC= V_VCC= 5V, VTTIN is connected to VDDQ output, T_A= +25^OC unless otherwise specified.)

Parameter

Symbol Test Conditions

Min

Typ Max Unit

Supply Current

Supply current, V_S3= 0V, V_S5= 5V, force

FB above regulation level (no switching).

470 1000

VCC, PVCC Current

VTTIN Current

I_VCC+PVCC

Shutdown current, V_S3= V_S5= 0V

0.1

Standby current, V_S3= 0V, V_S5= 5V. No

load at VTT pin

I_VTTIN

Shutdown current, V_S3= V_S5= 0V

Bias current, V_S3= V_S5= 5V, no load at

VTT pin.

Operating current, R_TON= 1MΩ

TON Current

I_TON

Shutdown current, V_S3= V_S5= 0V

0.1

Reference Voltage

V_VCC= 4.5V to 5.5V

Connect FB pin to VCC.

Connect FB pin to GND.

V_FB= 0.75V.

0.742 0.75 0.758

FB Reference Voltage

V_REF

1.8

1.5

0.1

FB Input Bias Current

I_FB

-1

VTTREF Output

Connect FB pin to VCC.

0.9

0.75

VTTREF Output Voltage

V_VTTREF

Connect FB pin to GND.

V_VDDQ= V_VTTIN= 1.8V , | I_VTTREF| <10mA

-18

-15

VTTREF Output Voltage

Tolerance

V_VTTREFTO

_VDDQ= V_VTTIN= 1.5V , | I_VTTREF| <10mA

I_VTTREFOCLSRC

VTTREF Source Current Limit

V_VTTREF= 0V

VTT Output

V_VDDQ= V_VTTIN= 1.2V/ 1.35V /1.5V/ 1.8V,

I_VTT= 0A

-20

-30

_VDDQ= V_VTTIN= 1.2V/ 1.35V/ 1.5V /1.8V,

VTT Output Voltage Tolerance

V_VTTTO

| I_VTT| < 1A

V_VDDQ= V_VTTIN= 1.2V/ 1.35V, | I_VTT| < 1.2A -40

3.6

_VDDQ= V_VTTIN= 1.5V/ 1.8V, | I_VTT| < 1.5A

-40

1.6

V_VTT= (V_VDDQ/ 2) x 0.95

2.6

1.3

2.6

1.3

VTT Source Current Limit

VTT Sink Current Limit

I_VTTTOCLSRC

_VTT= 0V

V_VTT= (V_VDDQ/ 2) x 1.05

V_VTT= V_VDDQ

1.6

3.6

I_VTTTOCLSNK

VTTSNS Leakage Current

VTT Discharge Current

I_VTTSNSLKSink current = 1mA

I_VTTDisV_S3= V_S5= 0V, V_VDDQ= 0V, V_VTT= 0.5V

- 1

uP1566-DS-P0000, Jan. 2013

www.upi-semi.com

uP1566

Electrical Characteristics

Parameter

Symbol Test Conditions

Min

Typ Max Unit

VDDQ

VDDQ Input Resistance

VDDQ Discharge Resistance

On Time

R_VDDQ

100

kΩ

I_VDDQDisV_S5= 0V

On-Time

T_ON

R_TON= 1MΩ, V_VDDQ= 1.25V

267

334

401

Minimum On-Time

Minimum Off-Time

Power OK

T_ONMIN

T_OFFMIN

250

400

550

Measured at FB, with respect to

reference voltage.

POK Rising Threshold

V_THPOKH

Hysteresis

From FB forced below POK falling

threshold to POK go low.

POK Propagation Delay

T_POK

2.5

POK Leakage Current

I_{LK_POK}High state, POK = 5V

V_{POK_L}Sink current = 1mA

POK Output Low Voltage

Logic Input Threshold

High Level Input Voltage

Low Level Input Voltage

Logic Input Leakage Current

Internal Bootstrap Switch

0.4

V_IH

V_IL

S3, S5 High

S3, S5 Low

0.8

V_INLEAKS3, S5 = 5V/0V

-1

Internal Boost Charging Switch

On-Resistance

R_BOOTPVCC to BOOT, I_BOOT= 10mA

Output Drivers

Source, V_BOOT-V_UGATE= 100mV

R_UGATE

2.5

1.5

2.5

0.8

UGATE Resistance

Sink, V_UGATE-V_PHASE= 100mV

Source, V_PVCC-V_LGATE= 100mV

R_LGATE

LGATE Resistance

Sink, V_LGATE= 100mV

1.6

Dead Time

T_D

V_UGATE< 1V to V_LGATE> 1V

Protection: Current Limit

CS Sink Current

I_CS

V_CS> 4.5V

ppm/-

^OC

CS Current Temp. Coefficient

OCP Comparator Offset

T_CICS

On the basis of 25^OC (Note 5)

4700

V_OCLoffGND - V_PHASE, R_CS= 5kΩ

-15

200

GND - V_PHASE, R_CS= 5kΩ

V_OCL

Current Limit Threshold

Zero Current Threshold

GND - V_PHASE, R_CS= 20kΩ

170

-5

230

V_ZC

GND - V_PHASE

uP1566-DS-P0000, Jan. 2013

www.upi-semi.com

uP1566

Electrical Characteristics

Parameter

Symbol Test Conditions

Min

Typ Max Unit

Protection: UVP & OVP

Measured at FB, with respect to

reference voltage.

OVP Trip Threshold

OVP Propagation Delay

UVP Trip Threshold

V_OVP

110

115

120

T_OVPDELForce FB above OVP trip threshold.

Measured at FB, with respect to

reference voltage.

V_UVP

UVP Propagation Delay

UVP Enable Delay

Protection: UVLO

T_UVPDELForce FB below UVP trip threshold.

T_UVPENFrom S5 signal go high

Rising edge

V_UVLO

3.9

4.2

4.5

VCC UVLO Threshold

Hysteresis

0.12

Protection: Thermal Shutdown

Thermal Shutdown Threshold

Shutdown temperature

165

T_SDN

^OC

Hysteresis

uP1566-DS-P0000, Jan. 2013

www.upi-semi.com

uP1566

Typical Operation Characteristics

This page is intentionally left blank and will be updated later.

uP1566-DS-P0000, Jan. 2013

www.upi-semi.com

uP1566

Application Information

PCB Layout Considerations

Place the output capacitor for VTT should close to

the pin with short and wide trace to avoid additional ESR

and/or ESL of the trace.

High speed switching and relatively large peak currents

in a synchronous-rectified buck converter make the PCB

layout a very important part of design. Fast current

switching from one device to another in a synchronous-

rectified buck converter causes voltage spikes across the

interconnecting impedances and parasitic circuit elements.

The voltage spikes can degrade efficiency and radiate

noise that result in overvoltage stress on devices. Careful

component placement layout and printed circuit board

design minimizes the voltage spikes induced in the

converter.

Connect VTT to the positive of VTT output capacitors

with a separate trace.

VDDQ can be connected separately from VTTIN.

Remember that this sensing potential is the reference

voltage of VTTREF. Avoid any noise generative lines.

Negative node of VTT output capacitor(s) and

VTTREF capacitor should be tied together by avoiding

common impedance to the high current path of the VTT

source/sink current.

Follow the layout guidelines for optimal performance of

uP1566.

GND(SignalGND) pin node represents the reference

potential for VTTREF and VTT outputs. Connect GND to

Keep the PCB trace PHASE node as short and wide negative nodes of VTT capacitor(s), VTTREF capacitor

as possible.

and VDDQ capacitor(s) with care to avoid additional ESR

and/or ESL. GND and PGND (power ground) should be

connected together at a single point.

Add a sunbber circuit between PHASE and PGND to

eliminate the high frequency voltage spike at PHASE node.

Keep sensitive analog circuits such as VDDQ,

VTTSNS and CS away from high voltage switching node

such PHASE, UGATE and LGATE.

Connect VDDQ output to VTTIN with short and wide

trace. If other power source is used as VTTIN, a bypass

input capacitor should be placed as close to VTTIN as

possible.

uP1566-DS-P0000, Jan. 2013

www.upi-semi.com

uP1566

Package Information

WQFN3x3-20L

0.30 - 0.50

1.40 - 1.80

0.15 - 0.25

2.90 - 3.10

Bottom View - Exposed Pad

Pin 1 mark

0.70 - 0.80

0.00 - 0.05

0.20 REF

Note

1.Package Outline Unit Description:

BSC: Basic. Represents theoretical exact dimension or dimension target

MIN: Minimum dimension specified.

MAX: Maximum dimension specified.

REF: Reference. Represents dimension for reference use only. This value is not a device specification.

TYP. Typical. Provided as a general value. This value is not a device specification.

2.Dimensions in Millimeters.

3.Drawing not to scale.

4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm.

uP1566-DS-P0000, Jan. 2013

www.upi-semi.com

uP1566

Important Notice

uPI and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products

and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information

before placing orders and should verify that such information is current and complete.

uPI products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment. However, no responsibility is

assumed by uPI or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use.

No license is granted by implication or otherwise under any patent or patent rights of uPI or its subsidiaries.

uPI Semiconductor Corp.

Sales Branch Office

uPI Semiconductor Corp.

Headquarter

12F-5, No. 408, Ruiguang Rd. Neihu District,

Taipei Taiwan, R.O.C.

TEL : 886.2.8751.2062 FAX : 886.2.8751.5064

9F.,No.5, Taiyuan 1st St. Zhubei City,

Hsinchu Taiwan, R.O.C.

TEL : 886.3.560.1666 FAX : 886.3.560.1888

uP1566-DS-P0000, Jan. 2013

www.upi-semi.com

UP1566PQKF [UPI]

相关型号：

UP1586

UP1586PQAG

UP1586QQAG

UP1586RQAG

UP1590

UP1590PQKF

UP1590QQKF

UP1590RQKF

UP159A

UP1620

UP1620G-O-T3P-T

UP1620G-P-T3P-T