UP1664 [UPI]
2-Phase 1-Phase PWM Controller;
| 型号： | UP1664 |
| 厂家： | 
uPI Semiconductor Corp. |
| 描述： | 2-Phase 1-Phase PWM Controller |
| 文件： | 总31页 (文件大小：408K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
uP1664
2-Phase + 1-Phase PWM Controller
with I2C Digital Interface for VR12 CPUs
Features
General Description
The uP1664 is a VR12 compliant CPU voltage regulator
controller supports 2-phase for VCORE and 1-phase for VGT.
The 2-phase VCORE regulator controller has integrated 12V
MOSFET drivers, and the 1-phase VGT regulator controller
has a logic level PWM output. This part adopts uPI
proprietary RCOTTM (Robust Constant On-Time) topology
to have fast transient response and smooth mode
transition. The uP1664 features I2C digital interface. The
integrated I2C interface programmability makes the uP1664
high performance and easy design. Similar to digital based
PWM controller, this device provides many VR parameters
that are programmable by I2C interface to achieve design
flexibility. Platform designer can define different power
scenario for different current states to optimize the VR
performance and efficiency. The uP1664 combines true
differential remote voltage sensing, inductorDCR current
sensing and adaptive voltage positioning to provide
accurately regulated power for desktop CPUs. This device
provides VROK indicator and complete fault protection
functions, including over voltage, under voltage, over current,
and under voltage lockout. The uP1664 is available in
VQFN5X5-40Lpackage.
Intel VR12 Compliant
2-Phase for VCORE with Integrated 12V MOSFET
Drivers
1-Phase for VGT with Logic Level PWM Output
RCOTTM Control Topology
Easy Setting
Smooth Mode Transient
Fast Transient Response
Differential Remote Voltage Sense
Inductor DCR Current Sense for Droop
MOSFET RDS(ON) Current Sense for Current
Balance
Programmable Vboot
I2C Interface for Performance and Effciency
Optimization
Dynamic Programmable VR Parameters
Programmable Protection Thresholds
VR Reporting
Ordering Information
OVP, UVP, OCP, UVLO
RoHS Compliant and Halogen Free
Order Number
uP1664PQGJ
Package
Remark
VQFN5x5 - 40L
Applications
Note:
(1) Please check the sample/production availability with
uPI representatives.
(2) uPI products are compatible with the current IPC/JEDEC
J-STD-020 requirements. They are halogen-free, RoHS
compliant and 100% matte tin (Sn) plating that are suit-
able for use in SnPb or Pb-free soldering processes.
Desktop PC CPU Power Supplies
Pin Configuration
31
32
33
34
35
36
37
38
39
40
20
19
18
17
16
15
14
13
12
11
STM
VRHOT#
BOOT2
SDAC
SCSN
SCSP
SPWM
SDAT
ALERT#
SCLK
VBOOT
DAC
UGATE2
PHASE2
LGATE2
VCC12
41
GND
LGATE1
PHASE1
UGATE1
EAP
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1
uP1664
Typical Application Circuit
12V
VCC12
GND
BOOT1
UGATE1
PHASE1
VCORE
LGATE1
BOOT PWM
SPWM
UGATE OD#
PHASE VCC
VGT
BOOT2
LGATE GND
uP1959
UGATE2
PHASE2
SCSP
SCSN
LGATE2
ISEN1
ISEN2
SEAP
SDAC
CSP
CSN
VGTSS_SENSE
VGTCC_SENSE
SFBRTN
SFB
1Ω
1Ω
SCOMP
SIMON
VCC5
EAP
DAC
5V
FBRTN
FB
VSS_SENSE
VCC_SENSE
VBOOT
TM
COMP
IMON
STM
VRHOT#
SDAT
SCLK
ALERT#
VROK
EN
SDA
SCL
2
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uP1664
Functional Pin Description
No.
Name
Pin Function
BOOT for Phase 1. Connect a capacitor from this pin to PHASE1, and also connect a
bootstrap diode from 12V power supply to this pin to form a bootstrap circuit for upper
gate driver of the phase 1.
1
BOOT1
Current Sensing for Phase 1. Connect a resistor from this pin to phase1 switching
node for current sensing.
2
3
ISEN1
ISEN2
Current Sensing for Phase 2. Connect a resistor from this pin to phase2 switching
node for current sensing.
VCORE Total Current Sense Positive Input.
VCORE Total Current Sense Negative Input.
4
5
CSP
CSN
VCORE Output Current Monitor. The output current of IMON pin is proportional to the total
load current. Connect a resistor from this pin to GND. The IMON voltage is decoded by
ADC for current reporting. The IMON voltage is also used for over current protection.
6
IMON
VGT Output Current Monitor. The output current of SIMON pin is proportional to the total
load current. Connect a resistor from this pin to GND. The SIMON voltage is decoded by
ADC for current reporting. The SIMON voltage is also used for over current protection.
7
8
SIMON
FBRTN
VCORE Feedback Return. VCORE VID DAC and error amplifier reference for remote
sensing of the output voltage.
VCORE Feedback Pin. Error amplifier inverting input for remote sensing of the VCORE output
voltage.
9
FB
VCORE Compensation Output. Error amplifier output and compensation point.
10
11
COMP
EAP
VCORE Non-Inverting Input of the Error Amplifier. A resistor between EAP and the
DAC sets the load line.
VCORE DAC Output. Connect a capacitor from this pin to FBRTN to program the slew rate
during soft start and dynamic VID transition.
12
13
DAC
Boot Voltage Setting. Connect a voltage divider from VCC5 to this pin to set boot-up
voltage for VCORE and VGT regulators.
VBOOT
SVID Clock.
SVID Alert#.
SVID Data.
14
15
16
SCLK
ALERT#
SDAT
VGT PWM Output. Connect this pin to the PWM input of external MOSFET driver for VGT
voltage regulator.
17
SPWM
VGT Total Current Sense Positive Input.
VGT Total Current Sense Negative Input.
18
19
SCSP
SCSN
V
GT DAC Output. Connect a capacitor from this pin to SFBRTN to program the slew rate
20
SDAC
during soft start and dynamic VID transition.
VGT Non-Inverting Input of the Error Amplifier. A resistor between SEAP and the
SDAC sets the load line.
21
22
SEAP
VGT Compensation Output. Error amplifier output and compensation point.
SCOMP
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uP1664
Functional Pin Description
No.
Name
Pin Function
V
GT Feedback Pin. Error amplifier inverting input for remote sensing of the VGT output
23
SFB
voltage.
VGT Feedback Return. VGT VID DAC and error amplifier reference for remote sensing of
the output voltage.
24
25
SFBRTN
VROK
VCORE Power Good Indication. This pin is an open-drain output that indicates the VCORE
soft start process is complete and no fault happens.
SMBUS Clock Input. This pin receives serial bus clock signal.
26
27
SCL
SDA
SMBUS Data Input. This pin is input or output of serial bus data signal.
VCORE Thermal Monitoring Input. Connect a NTC network from VCC5 to this pin for
sensing VCORE VR temperature. uP1664 uses specific nonlinear A/D converter in thermal
reporting. The recommended NTC thermistor is 10kΩ, and the recommended lower
dividing resistor is 6kΩ.
28
TM
Enable Control. Voltage of this pin higher than 0.8V enables both of the VCORE and VGT
VR. If it is lower than 0.4V, both of the VCORE and VGT VR outputs will be disabled.
29
30
EN
Supply Input for the IC Control Logic. Connect this pin to a 5V voltage source with an
RC filter.
VCC5
VGT Thermal Monitoring Input. Connect a NTC network from VCC5 to this pin for
sensing VGT VR temperature. uP1664 uses specific nonlinear A/D converter in thermal
reporting. The recommended NTC thermistor is 10kΩ, and the recommended lower
dividing resistor is 6kΩ.
31
32
STM
V
CORE and VGT VRHOT Output. This pin is an open-drain output. When the VTM or VSTM
VRHOT#
reaches the level that the decoded temperature reaches Temp_Max (SVID Reg. 22h)
setting, it will trigger VRHOT#.
BOOT for Phase 2. Connect a capacitor from this pin to PHASE2, and also connect a
bootstrap diode from 12V power supply to this pin to form a bootstrap circuit for upper
gate driver of the phase 2.
33
34
35
BOOT2
Upper Gate Driver for Phase 2. Connect this pin to the gate of phase 2 upper
MOSFET.
UGATE2
Phase Pin for Phase 2. This pin is the return path of upper gate driver for phase 2.
PHASE2 Connect a capacitor from this pin to BOOT2 to form a bootstrap circuit for upper gate
driver of the phase 2.
Lower Gate Driver for Phase 2. Connect this pin to the gate of phase 2 lower MOSFET.
36
37
38
LGATE2
VCC12
LGATE1
Supply Input for Embedded MOSFET Drivers. Connect this pin to a 12V voltage
source with an RC filter.
Lower Gate Driver for Phase 1. Connect this pin to the gate of phase 1 lower MOSFET.
Phase Pin for Phase 1. This pin is the return path of upper gate driver for phase 1.
39
40
PHASE1 Connect a capacitor from this pin to BOOT1 to form a bootstrap circuit for upper gate
driver of the phase 1.
Upper Gate Driver for Phase 1. Connect this pin to the gate of phase 1 upper
UGATE1
MOSFET.
Ground. The exposed pad must be soldered to a large PCB and connected to GND.
Exposed Pad
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uP1664
Functional Block Diagram
SDAC
DAC
Soft Start
&
Power OK
SVID/I2C
VCC12
BOOT1
POR
VROK
ICSN
ISCSN
UGATE1
PHASE1
Ramp
Generator
Gate
Control
Logic
COMP
EAP
FB
LGATE1
On Time
Generation
and
ICSN
Current
Balance
IMON
CSN
CSP
OCP
BOOT2
UGATE2
3.4V
Gate
Control
Logic
PHASE2
LGATE2
UVP
OVP
EAP - 300mV
EAP + 300mV
SEAP - 300mV
SEAP + 300mV
UVP
OVP
ISEN1
ISEN2
S/H
S/H
SFB
SEAP
Ramp
Generator
SCOMP
SCSP
On Time
Generation
ISCSN
SCSN
GND
SIMON
OCP
3.4V
SPWM
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uP1664
Functional Description
The uP1664 is a VR12 compliant CPU voltage regulator
controller supports 2-phase for VCORE and 1-phase for VGT.
Table 1. Boot-up Voltage Setting
Boot-up Voltage, Vboot (V)
BOOT Pin Voltage
(% of VCC5)
Control Loop
The uP1664 adopts the uPI proprietary RCOTTM control
technology. The RCOTTM uses the constant on-time
modulator. The output voltage is sensed to compare with
the internal high accurate DAC. The DAC is commanded
by CPU through the SVIDinterface. The amplified error signal,
VCOMP, is compared to the internal ramp to initiate an on-
time to PWM. The RCOT features easy design, fast transient
response and smooth mode transition and especially suits
for powering the microprocessor.
VCORE
0
VGT
0
0
9.375
0
0.9
1
15.625
0
21.875
0
1.1
0
28.125
0.9
0.9
0.9
0.9
1
Power Input and Power On Reset
34.375
0.9
1
Figure 1 shows the power ready detection of the uP1664.
The uP1664 receives supply input from VCC12 pin to provide
current to gate drivers. The VCC12 pin is monitored for
power on reset, the POR level is typically 4.2V at VCC12
rising.An RC filter is required for locally bypassing the supply
input pin. Place a 1uF ceramic capacitor physically near
the VCC12 pin for locally bypassing the VCC12 voltage.
The VCC5 pin receives a well-decoupled 5V voltage source
to power the internal control circuit. Place a 0.1uF ceramic
capacitor physically near the VCC5 pin for locally bypassing
the VCC5 voltage. The VCC5 voltage is continuously
monitored for power on reset. The POR level is typical 4.3V
at VCC5 rising.
40.625
46.875
1.1
0
53.125
59.375
1
0.9
1
65.625
1
71.875
1
1.1
0
78.125
1.1
1.1
1.1
1.1
84.375
0.9
1
90.625
VCC5
4.3V
100
1.1
I2C Device Address
VCC12
4.2V
The I2C device address of uP1664 is 40h.
Reference Voltage VDAC Generator
The uP1664 embeds precise bandgap reference circuit for
VCORE and VGT regulators as shown in Figure 2. The output
voltage of bandgap reference is 2.1V with respective to
FBRTN. The uP1664 uses plural resistors to generate
precise reference voltages ranging from 0.0V to 2.1V, with
5mV increments. All the voltages connect to a multiplexer
(MUX). The multiplexer outputs VDAC according to the SVID
inputs. Please note that all the voltage values in Figure 2
are referred to FBRTN. The VDAC generator for VGT is
identical to that of VCORE except that its voltage values are
referred to SFBRTN. The VDAC voltage is expressed as:
Figure 1. Circuit for Power ReadyDetection
Phase Number of Operation
The VCORE controller only supports 2-phase configuration,
and it cannot be hardwarely configured as a single-phase
controller.
Initial Parameters Setting
The VBOOT pin sets the initial boot-up voltage for VCORE
and VGT regulator. ICCMAX in SVID register 0x21 of VCORE
VR is fixed at 96A and ICCMAX in SVID register 0x21 of
VGT VR is fixed at 48A. The VCORE and VGT regulator boot-up
voltage is shown in Table 1.
VDAC = VID + Offset
where VIDand Offset can be programmed by SVIDor I2C
interface. Table 2 illustrates the VIDvoltages according to
VID code.
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uP1664
Functional Description
Soft Start
2.1V
SVID
Interface
VBG
The uP1664 has programmable soft start function. The soft
start function limits the output voltage slew rate during both
soft start and VIDon the fly (VID_OTF) periods. Take VCORE
regulator as an example. As shown in Figure 4, the soft
start buffer is a current limited buffer whose output current
ISS is used to charge/discharge the soft start capacitor CSS
when VDAC transition during soft start and VID_OTF. This
limits the slew rate of VDAC. Consequently EAP and FB pin
voltages will follow the slew rate of VDAC. The VGT regulator
has similar mechanism and it works in the same way. The
VDAC voltage level can be dynamically programmed by SVID/
I2C interfaces.
R1
2.1V
R2
0V to 2.1V
Step = 5mV
FBRTN
SMBUS
Interface
VDAC
RN
0V
FBRTN
Figure 2. VDAC Generation Circuit for VCORE
State Transition
FB
VCOMP
EAP
Figure 3 illustrates the state diagram. The soft start cycle
is initiated when POR transits from Low to High. VROK is
set high when soft start cycle completes and no fault occurs.
If any fault occurs, the uP1664 shutdown both power rails
and latches off. The latch state can only be reset by POR.
RDRP
VDAC
DAC
SS
Buffer
CSS
FBRTN
Controller
POR
Calibrate
and
Initialize
Figure 4. Circuit for Soft Start and Dynamic VID
Power Sequence
POR = L
to reset
VBOOT not 0V
VBOOT = 0V
The initial boot-up voltage Vboot can be set to 0V, 0.9V,
1V or 1.1V. Take VCORE controller as an example, the power
sequence of each case is described as follows. Figure 5
Soft Start
Ramp I
Soft Start
Ramp I
shows a typical soft start waveforms of Vboot 0V. When
EN= Low, theDAC pin is held atGND. The uP1664 takes
about 2ms (T1) for initialization before the VDAC begins to
rise to Vboot. The ramping up period T2 is decided byVboot,
CSS and ISS, and it is calculated as:
VDAC = VBOOT
VDAC = VID + Offset
POR = L
to reset
VROK = High VROK = High
VDAC = VID + Offset
Soft Start
Ramp II
V
BOOT × CSS
T2 =
,
ISS = 50uA
ISS
Protection
The VROK is asserted with an extra 650us time delay T3.
When the SetVID command is acknowledged, the VDAC
starts to ramp to the new target level with a typical 600ns
delay time. The ramping periodT4 is decided byVDAC, Vboot,
CSS and ISS, and it is calculated as:
Figure 3. StateDiagram
(
VDAC − Vboot × CSS
)
T4 =
ISS
For SetVID_fast command, typical ISS = 200uA, and for
SetVID_slow command, typical ISS = 50uA.
The uP1664 asserts soft start end when VDAC is within 10mV
of the target level and setsALERT# low.
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uP1664
Functional Description
VID_OTF may occur under either light or heavy load
conditions. This voltage change can be upward or
downward. During a VID_OTF, the internal VDAC is a
staircase waveform, and CSS is being charged/ discharged
as a timing capcitor to filter the VDAC and also controls the
slew rate.
ENABLE
SVID
SetVID PKG
VBOOT
VCORE VR Controller:
VOUT
=
Output Voltage Differential Sensing
VDAC
The uP1664 uses output voltage differential sensing by a
high-gain low-offset error amplifier as shown in Figure 7.
The CPU voltage is sensed between the FB and FBRTN
pins.Aresistor RFB connects FB pin and the positive remote
sense pin of the CPU VCCP. FBRTN pin connects to the
negative remote sense pin of CPU VCCN directly. The error
ALERT#
T3
VROK
T1
T2
T4
amplifier compares the VFB with VEAP (= VDAC - ISUM x RDRP
to regulate the output voltage.
)
Figure 5. Soft Start Waveforms of Vboot 0V
CFB
Figure 6 shows a typical soft start waveforms of Vboot =
0V. When EN = Low, the DAC pin is held at GND. The
uP1664 takes about 2ms (T1) for initialization. When the
SetVIDcommand is acknowledged, the VDAC starts to ramp
to the new target level with a typical 600ns delay. The
ramping period T2 is decided by the target VDAC, CSS and
VCCP
FB
COMP
Positive
remote sense
pin of CPU
gm
RFB
EAP
ISUM
ISS, and it is calculated as:
RDRP
DAC
VDAC
V
DAC × CSS
Nagative
remote sense
pin of CPU
T2 =
,
ISS = 50uA
CSS
FBRTN
ISS
The uP1664 asserts soft start end when VDAC is within 10mV
of its target level and sets ALERT# low. The VROK is
asserted with an extra 800us time delay T3.
VCCN
Figure 7. Circuit for VOUT Differential Sensing
Channel Current Sensing
As shown in Figure 8, the uP1664 extracts phase currents
for current balance and per phase over current protection
by the on-resistance of the low side MOSFET when it is
on. The ISEN1 pin and ISEN2 pin sense the corresponding
phase current when the low side MOSFETs are turned on.
ENABLE
SetVID PKG
SVID
ISENX = ((IPHASEX x RDS(ON)) + VDC) / RSENX
VOUT
VDAC/SS
=
where ISENX is the sample and hold phase current signal,
IPHASEX is phase current, RDS(ON) is the on-resistance of the
low side MOSFET, andVDC is an offset voltage for the current
balance circuit. The current balance circuit increases the
duty cycle of the phase whose phase current is smaller
than others and decrease the duty cycle of the phase whose
phase current is larger than others.
ALERT#
VROK
T1
T2
T3
PHASE1 PHASE2
Figure 6. Soft Start Waveforms of Vboot = 0V
ISEN1
ISEN1
Dynamic VID Transition
S/H
Current
Balance
&
Per Phase
OCP
RSEN1
The controller accepts SetVIDcommand input during normal
operation. This allows theVR output voltage to change while
the VR is running and supplying current to the load. This is
commonly referred to as VID on-the-fly (VID_OTF). A
ISEN2
ISEN2
S/H
RSEN2
VDC
Figure 8. Phase Current Sensing and Current Balance
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uP1664
Functional Description
Total Load Current Sensing
The IMONpin voltage is also decoded by the internalADC
for digital output current reporting via SVIDinterface. When
IMONpin voltage reaches 2.56V, the controller reports FFh
and assert ICCMAX alert.
The uP1664 provides low input offset current sense amplifier
(CSA) to monitor the total load current flowing through
inductor as shown in Figure 9. Output current of CSA(ISUM
)
is used for adaptive voltage positioning (AVP), load current Output Over Current Protection
monitoring and total load over current protection. In this
inductor current sensing topology, RSW and CSUM must be
selected according to the equation below:
The VIMON pin voltage is continuously monitored for total
load over current protection (OCP). If VIMON is higher than
3.4V, OCP is triggered and both high side and low side
MOSFET are turned off. VROK will go low immediately.
The total load current protection has 20us delay time. The
total load OCP is latch-off type and can be reset only by
POR toggling.
RSW × CSUM
L
k ×
=
RDC
2
where RDC is theDCR of the output inductor, 2 is the phase
number of operation . Theoretically, k should be equal to 1 Over Voltage Protection (OVP)
to sense the instantaneous total load current. But in real
application usually 1.2 ~ 1.8 is better for transient response.
The over voltage protection monitors the output voltage via
the FB pin. Once VFB exceeds VEAP + 300mV, OVP is
triggered and latched. The controller will try to turn on low
side MOSFET and turn off high side MOSFET to protect
CPU. VROK will go low immediately. A20us delay is used
in OVP detection circuit to prevent false trigger. Only re-
start up can release OVP latch.
I
OUT ×RDC
RSUM
2
ISUM
=
RSW1
RSW2
Under Voltage Protection (UVP)
PHASE1
PHASE2
The under voltage protection monitors the output voltage
via the FB pin. After starting up and VCORE ramping up to
Vboot, the controller initiates UVP function. Once VFB is
lower than VEAP - 300mV, UVP is triggered and latched.
The controller will try to turn off both high side and low side
MOSFETs. VROK will go low immediately. A 5us delay is
used in UVP detection circuit to prevent false trigger. Only
re-start up can release UVP latch.
CSP
CSN
ISUM
CSUM
1ohm
1ohm
VCORE
VCORE
RSUM
Figure 9. Total Load Current Sensing
Droop (Load Line) Tuning
VGT VR Controller:
The ISUM is mirrored to EAP pin as shown in Figure 7.
This creates voltage drop across RDRP and makes VEAP as:
Output Voltage Differential Sensing
The controller uses output voltage differential sensing by a
high-gain low-offset error amplifier as shown in Figure 10.
The CPU voltage is sensed between the SFB and SFBRTN
pins. A resistor RFB connects SFB pin and the positive
remote sense pin of the CPU VGT. FBRTNpin connects to
the negative remote sense pin of CPU VGTN directly. The
error amplifier compares the VSFB with VSEAP (= VSDAC - ISSUM
x RDRP) to regulate the output voltage.
I
OUT ×RDC ×RDRP
VEAP = VDAC −ISUM ×RDRP = VDAC
−
R
CSN × 2
In steady state, output voltage is equal to VEAP. Thus, the
output voltage decreasing linearly with IOUT is obtained. The
loadline is defined as:
∆VOUT
∆IOUT
R
DC ×RDRP
SUM × 2
LoadLine =
=
CFB
R
Output Current Monitoring
VGT
SFB
SCOMP
The ISUM is mirrored to IMON pin for ourput current monitoring
and over current protection. The VIMON voltage is created
that is proportional to the output current as:
Positive
remote sense
pin of CPU
gm
RFB
SEAP
ISSUM
I
MAX ×RDC
2.56V
RIMON
RDRP
=
SDAC
VDAC
R
SUM × 2
Nagative
remote sense
pin of CPU
CSS
SFBRTN
, where IMAX is maximum supported current of VCORE
regulator.
VGTN
Figure 10. Circuit for VGT Differential Sensing
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9
uP1664
Functional Description
Phase Current Sensing
Output Current Monitoring
The controller senses the phase current by DCR current The ISSUM is mirrored to SIMON pin for ourput current
sensing technique for droop tuning, load current monitoring, monitoring and over current protection. The VSIMON voltage
over current protection as shown in Figure 11. A RCSP/CCS is created that is proportional to the output current as:
nework is paralleled with the output inductor. The time
I
SIMAX ×RDC
2.56V
constants can be express as:
=
RSIMON
RSUM
L
R
CSP × CCS = k ×
, where ISMAX is maximum supported current of VGT
regulator.
RDC
where L is the output inductor, RDC is its parasitic resistance
and k is a constant. Theoretically, if k = 1, the sensed
current signal ISSUM can be expressed as:
The SIMON pin voltage is also decoded by the internal
ADC for digital output current reporting via SVIDinterface.
When SIMON pin voltage reaches 2.56V, the controller
reports FFh and assert ICCMAX alert.
IL ×RDC
ISSUM
=
Output Over Current Protection
RCSN
The VSIMON pin voltage is continuously monitored for total
load over current protection (OCP). If VSIMON is higher than
3.4V, OCP is triggered and SPWM output is set to high
impedance state to turn off both high side and low side
MOSFET. VROK will go low immediately. The over current
protection has 20us delay time. The OCP is latch-off type
and can be reset only by POR toggling.
, where IL is the phase current. In real application, k =
1.2~1.8 is recommended for better transient response.
VIN
L
RDC
VGT
Over Voltage Protection (OVP)
The over voltage protection monitors the output voltage via
the SFB pin. Once VSFB exceeds VSEAP + 300mV, OVP is
triggered and latched. The SPWM output will go low to
turn on low side MOSFET and turn off high side MOSFET
to protect CPU. VROK will go low immediately. A 20us
delay is used in OVP detection circuit to prevent false
trigger. Only re-start up can release OVP latch.
RCSP
SCSP
CSA
CCS
ISSUM
RCSN
SCSN
Under Voltage Protection (UVP)
The under voltage protection monitors the output voltage
via the SFB pin. After starting up and VGT ramping up to
Vboot, the controller initiates UVP function. Once VSFB is
lower than VSEAP - 300mV, UVP is triggered and latched.
The SPWM output is set to high impedance state to turn
off both high side and low side MOSFET. VROK will go
low immediately. A 5us delay is used in UVP detection
circuit to prevent false trigger. Only re-start up can release
UVP latch.
Figure 11. Channel Current Sensing
Droop (Load Line) Tuning
The controller senses the inductor current to get the current
ISSUM as:
I
OUT ×RDC
ISSUM
=
RCSN
The current ISSUM is mirrored to SEAP pin as shown in Figure Serial VID (SVID)
10. This creates voltage drop across RDRP and makes VSEAP
as:
Serial VID is a three wire (SCLK, SDAT, Alert#) serial
synchronous interface used to transfer power management
information between a micoprocessor and a VRM. The
link is between one microprocessor and multiple VR
controller on the same bus. The standard SVIDcommands
are listed in Table 3. The supported data and configuration
registers are listed in Table 4.
I
OUT ×RDC ×RDRP
VSEAP = VSDAC −ISSUM ×RDRP = VSDAC −
RCSN
In steady state, output voltage is equal to VSEAP. Thus, the
output voltage decreasing linearly with IOUT is obtained. The
loadline is defined as:
∆VOUT
∆IOUT
R
DC ×RDRP
LoadLine =
=
RSUM
10
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uP1664
Functional Description
Table 2. Intel SVIDTable
SVID
HEX
VDAC
(V)
SVID
HEX
VDAC
(V)
SVID
HEX
VDAC
(V)
SVID
HEX
VDAC
(V)
SVID
HEX
VDAC
(V)
SVID
HEX
VDAC
(V)
SVID
HEX
VDAC
(V)
0x00 0.000 0x25 0.430 0x4A 0.615 0x6F 0.800 0x94 0.985 0xB8 1.165 0xDC 1.345
0x01 0.250 0x26 0.435 0x4B 0.620 0x70 0.805 0x95 0.990 0xB9 1.170 0xDD 1.350
0x02 0.255 0x27 0.440 0x4C 0.625 0x71 0.810 0x96 0.995 0xBA 1.175 0xDE 1.355
0x03 0.260 0x28 0.445 0x4D 0.630 0x72 0.815 0x97 1.000 0xBB 1.180 0xDF 1.360
0x04 0.265 0x29 0.450 0x4E 0.635 0x73 0.820 0x98 1.005 0xBC 1.185 0xE0 1.365
0x05 0.270 0x2A 0.455 0x4F 0.640 0x74 0.825 0x99 1.010 0xBD 1.190 0xE1 1.370
0x06 0.275 0x2B 0.460 0x50 0.645 0x75 0.830 0x9A 1.015 0xBE 1.195 0xE2 1.375
0x07 0.280 0x2C 0.465 0x51 0.650 0x76 0.835 0x9B 1.020 0xBF 1.200 0xE3 1.380
0x08 0.285 0x2D 0.470 0x52 0.655 0x77 0.840 0x9C 1.025 0xC0 1.205 0xE4 1.385
0x09 0.290 0x2E 0.475 0x53 0.660 0x78 0.845 0x9D 1.030 0xC1 1.210 0xE5 1.390
0x0A 0.295 0x2F 0.480 0x54 0.665 0x79 0.850 0x9E 1.035 0xC2 1.215 0xE6 1.395
0x0B 0.300 0x30 0.485 0x55 0.670 0x7A 0.855 0x9F 1.040 0xC3 1.220 0xE7 1.400
0x0C 0.305 0x31 0.490 0x56 0.675 0x7B 0.860 0xA0 1.045 0xC4 1.225 0xE8 1.405
0x0D 0.310 0x32 0.495 0x57 0.680 0x7C 0.865 0xA1 1.050 0xC5 1.230 0xE9 1.410
0x0E 0.315 0x33 0.500 0x58 0.685 0x7D 0.870 0xA2 1.055 0xC6 1.235 0xEA 1.415
0x0F 0.320 0x34 0.505 0x59 0.690 0x7E 0.875 0xA3 1.060 0xC7 1.240 0xEB 1.420
0x10 0.325 0x35 0.510 0x5A 0.695 0x7F 0.880 0xA4 1.065 0xC8 1.245 0xEC 1.425
0x11 0.330 0x36 0.515 0x5B 0.700 0x80 0.885 0xA5 1.070 0xC9 1.250 0xED 1.430
0x12 0.335 0x37 0.520 0x5C 0.705 0x81 0.890 0xA6 1.075 0xCA 1.255 0xEE 1.435
0x13 0.340 0x38 0.525 0x5D 0.710 0x82 0.895 0xA7 1.080 0xCB 1.260 0xEF 1.440
0x14 0.345 0x39 0.530 0x5E 0.715 0x83 0.900 0xA8 1.085 0xCC 1.265 0xF0 1.445
0x15 0.350 0x3A 0.535 0x5F 0.720 0x84 0.905 0xA9 1.090 0xCD 1.270 0xF1 1.450
0x16 0.355 0x3B 0.540 0x60 0.725 0x85 0.910 0xAA 1.095 0xCE 1.275 0xF2 1.455
0x17 0.360 0x3C 0.545 0x61 0.730 0x86 0.915 0xAB 1.100 0xCF 1.280 0xF3 1.460
0x18 0.365 0x3D 0.550 0x62 0.735 0x87 0.920 0xAC 1.105 0xD0 1.285 0xF4 1.465
0x19 0.370 0x3E 0.555 0x63 0.740 0x88 0.925 0xAD 1.110 0xD1 1.290 0xF5 1.470
0x1A 0.375 0x3F 0.560 0x64 0.745 0x89 0.930 0xAE 1.115 0xD2 1.295 0xF6 1.475
0x1B 0.380 0x40 0.565 0x65 0.750 0x8A 0.935 0xAF 1.120 0xD3 1.300 0xF7 1.480
0x1C 0.385 0x41 0.570 0x66 0.755 0x8B 0.940 0xB0 1.125 0xD4 1.305 0xF8 1.485
0x1D 0.390 0x42 0.575 0x67 0.760 0x8C 0.945 0xB1 1.130 0xD5 1.310 0xF9 1.490
0x1E 0.395 0x43 0.580 0x68 0.765 0x8D 0.950 0xB2 1.135 0xD6 1.315 0xFA 1.495
0x1F 0.400 0x44 0.585 0x69 0.770 0x8E 0.955 0xB3 1.140 0xD7 1.320 0xFB 1.500
0x20 0.405 0x45 0.590 0x6A 0.775 0x8F 0.960 0xB4 1.145 0xD8 1.325 0xFC 1.505
0x21 0.410 0x46 0.595 0x6B 0.780 0x90 0.965 0xB5 1.150 0xD9 1.330 0xFD 1.510
0x22 0.415 0x47 0.600 0x6C 0.785 0x91 0.970 0xB6 1.155 0xDA 1.335 0xFE 1.515
0x23 0.420 0x48 0.605 0x6D 0.790 0x92 0.975 0xB7 1.160 0xDB 1.340 0xFF 1.520
0x24 0.425 0x49 0.610 0x6E 0.795 0x93 0.980
uP1664-DS-F00A0, Apr. 2018
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11
uP1664
Functional Description
Table 3. Stanstard SVIDCommands
Master Payload Slave Payload
Pre-
emptive Call
All
Code
Command
Description
Contents
Contents
00h not supported
01h SetVID_Fast
NA
NA
NA
NA
NA
Set the target VID code, VR jumps to new
VID target with controlled default fast slew
rate 10mV/us.
VID Code
VID Code
NA
NA
Yes
Yes
Set the target VID code, VR jumps to new
VID target with controlled default slow slew
rate 2.5mV/us.
02h SetVID_Slow
03h SetVID_Decay
Yes
Yes
Yes
Yes
Set the target VID code, VR jumps to new
VID target but does not control the slew
rate. The output voltage decays at a rate
proportional to the load current.
VID Code
NA
Byte indicating
power states
04h
05h
06h
07h
SetPS
NA
NA
NA
Set power state
No
No
No
No
Yes
No
No
No
Pointer of
registers in
data table
SetRegADR
SetRegDAT
GetReg
Set the pointer of the data register
Write the contents to the data register
New data
register content
Pointer of
register in data
table
Specified
Register
Contents
Slave returns the contents of the specified
register as the payload.
08h
~
not supported
NA
NA
NA
NA
No
1Fh
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uP1664
Functional Description
Table 4. SVID Data and Configuration Registers
Reg
Addr
Register Name
Access
Default
Description
00h
01h
02h
05h
Vender_ID
Product_ID
RO
RO
RO
RO
26h Vender ID
14h Product ID
Product_Revision
Protocol_Version
08h Product Revision
01h SVID Protocol Version
Bit mapped register, identifies the SVID VR capability
and which of the optional telemetry are supported.
06h
VR_Capability
RO
81h
10h
11h
Status_1
Status_2
R-M, W-PWM
R-M, W-PWM
00h Data register containing the status of VR.
00h Data register containing the status of transmission.
Data register showing temperature zone that have been
entered.
12h
Temperature_Zone R-M, W-PWM
Output_Current R-M, W-PWM
Status_2_LastRead R-M, W-PWM
00h
Data register showing the output current that have been
entered.
15h
1Ch
21h
--
00h This register contains a copy of the Status_2.
Data register containing the maximum current the
platform supports.
ICC_Max
RO Platform
RO Platform
--
Data register containing the maximum temperature the
64h platform supports.
22h
24h
25h
Temp_Max
Binary format in OC, i.e. 64h = 100OC.
Data register containing the capability of fast slew rate
0Ah the platform can sustain. Binary format in mV/us, i.e. 0Ah
= 10mV/us
SR_Fast
SR_Slow
RO
RO
Data register containing the capability of slow slew rate
the platform can sustain. Binary format in mV/us, i.e. 03h
= 3mV/us
02h
26h
30h
VBOOT
RO Platform
RW Master
--
Data register containing Vboot voltage in VID steps.
This register is programmed by master and sets the
maximum VID.
VOUT_Max
FBh
31h
32h
33h
VID_Setting
Power_State
Offset
RW Master
RW Master
RW Master
00h Data register containing currently programmed VID.
00h Register containing the programmed power state.
00h Set offset in VID steps.
Bit mapped data register which configures multiple VRs
behavior on the same bus.
34h
35h
Multi_VR_Config
SetRegADR
RW Master
RW Master
00h
Scratch pad register for temporary storage of the
SetRegADR pointer register.
--
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13
uP1664
Functional Description
I2C Interface
IICF0~3
The uP1664 includes an I2C interface to adjust output Frequency adjust of the 4 load current states: IICF0~3
voltage, switching frequency and operating phase number define the frequency in load current states LCS0~3
of VR controller according to the total load current respectively as show in Table 6.
dynamically. We call itAuto Phase. The target ofAuto Phase
is an optimal VR design for both power conversion efficiency
and CPU performance. Operating parameters that can be
adjusted through the I2C are summarized as Table 10.
Table 6. IICF Setting Table
IICF0~3
000
001
010
011
Freq(Hz)
150K
VM0~2: Define the 4 load current states (LCS0~3)
200K (Default)
250K
Voltage at IMON pin VIMON is converted to an 8-bit digital
value as IMONAD[7:0] = VIMON/10mV. IMONAD[7:0] is
compared with three I2C programmable registers VM0~2
to determine the load current states LCS0~3 as:
300K
LCS0: VIMON > VM0, highest load current.
LCS1: VM0 > VIMON > VM1
LCS2: VM1 > VIMON > VM2
LCS3: VM2 > VIMON, lowest load current.
VM_Hys
100
101
110
350K
400K
450K
111
500K
Define the VM0~2 and SVM0 state hysteresis VMx_Hys
as shown in Table 5.
IICP0~3
Table 5. VHYS Setting Table
Operating phase number of the 4 load current states: 4
I2C programmable registers IICP0~3 define the operating
phase number in load current states LCS0~3 respectively.
VM0~2_Hys;
VM0~2_Hys
SVM0_Hys
SVM0_Hys
000
IICPn[1:0] = [00] => 2-phase
60mV (Default) 120mV (Default)
IICPn[1:0] = [01] => 2-phase
IICPn[1:0] = [10] => 2-phase
001
80mV
100mV
120mV
140mV
160mV
180mV
200mV
160mV
200mV
240mV
280mV
320mV
360mV
400mV
IICPn[1:0] = [11] => 1-phase
010
Misc2[7:0]
Register Misc2[7:0] enables/disables the I2C functions as:
Misc[7]=[1]=> enables VCORE Auto Phase function
Misc[7]=[0]=> disables VCORE Auto Phase function
Misc[6]=[1]=> enables VGT Auto Phase function
Misc[6]=[0]=> disables VGT Auto Phase function
Misc[5]=[1]=> enables VCORE PSM operation
Misc[5]=[0]=> disables VCORE PSM operation
Misc[4]=[1]=> enables VGT PSM operation
Misc[4]=[0]=> disables VGT PSM operation
Misc[3]=[1]=> enables VCORE load line
Misc[3]=[0]=> disables VCORE load line
Misc[2]=[1]=> enables VGT load line
011
100
101
110
111
VOFS0~3
Define voltage offset of the 4 load current states: 4 I2C
programmable registers VOFS0~3 define the voltage offset
in load current status LCS0~3 respectively. See Table 11
for the voltage offset table.
Misc[2]=[0]=> disables VGT load line
Misc[1]=[1]=> enables VCORE voltage offset
Misc[1]=[0]=> disables VCORE voltage offset
Misc[0]=[1]=> enables VGT voltage offset
Misc[0]=[0]=> disables VGT voltage offset
14
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uP1664
Functional Description
RCOMP[3:0]
The register OCP[3:2] is used to adjust VCORE Per Phase
OCP Level as:
RCOMP is the internal compensation resistor. It can be
programmed by 0x13/0x1F Register as shown in Table 7. OCP[3:2] = [00] => 60uA
OCP[3:2] = [01] => 100uA
I2C
EAP
OCP[3:2] = [10] => 140uA
GM
FB
OCP[3:2] = [11] => 180uA
The register OCP[1:0] is used to adjust VGT Total Current
RCOMP
OCP Level as:
OCP[1:0] = [00] => 120%
OCP[1:0] = [01] => 133%
OCP[1:0] = [10] => 150%
OCP[1:0] = [11] => 171%
UV/OV[7:0]: VR UV/OV Protection Setting
Table 7. RCOMP Setting Table
Bit[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
RCOMP(ohm)
5K
The register OV/UV[7:6] is used to adjust VCORE UVP
Level as:
10K
UV/OV[7:6] = [00] => 200mV
UV/OV[7:6] = [01] => 300mV
UV/OV[7:6] = [10] => 400mV
UV/OV[7:6] = [11] => 500mV
15K
20K (Default)
25K
The register OV/UV[5:4] is used to adjust VCORE OVP
Level as:
30K
UV/OV[5:4] = [00] => 200mV
UV/OV[5:4] = [01] => 300mV
UV/OV[5:4] = [10] => 400mV
UV/OV[5:4] = [11] => 500mV
35K
40K
45K
The register OV/UV[3:2] is used to adjust VGT UVP Level
as:
50K
UV/OV[3:2] = [00] => 200mV
UV/OV[3:2] = [01] => 300mV
UV/OV[3:2] = [10] => 400mV
UV/OV[3:2] = [11] => 500mV
55K
60K
65K
The register OV/UV[1:0] is used to adjust VGT OVP Level
as:
70K
UV/OV[1:0] = [00] => 200mV
UV/OV[1:0] = [01] => 300mV
UV/OV[1:0] = [10] => 400mV
UV/OV[1:0] = [11] => 500mV
TEMP_SHIFT[7:0]: TEMPMAX Shift
75K
80K
LCHVID[7:0]:Latch VID
The register LCHVID stores the 8 bits VID Code of user
defined, when enable this function, VR will ignore CPU The register TEMP_SHIFT is used to shift SVID TEMPMAX
SETVIDCommand.
and achieve to adjust VRHOT# trigger point.
OCP[5:0]: VR Over Current Protection Setting
TEMP_SHIFT[7]: VCORE’s VRHOT#
The register OCP[5:4] is used to adjust VCORE Total 0: Enable
Current OCP Level as:
1:Disable VCORE VRHOT# and force SVID0x12 = 00h
TEMP_SHIFT[6]: VGT’s VRHOT#
OCP[5:4] = [00] => 120%
OCP[5:4] = [01] => 133%
OCP[5:4] = [10] => 150%
OCP[5:4] = [11] => 171%
0: Enable
1:Disable VGT VRHOT# and force SVID0x12 = 00h
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15
uP1664
Functional Description
TEMP_SHIFT[5:3]:VCORE SVID 0X12 Shift left by LSB:
IICLL0~3
000: No Shift 001: Shift 1LSB 010: Shift 2LSB 011: Shift Load line adjust of 4 load current state: IICLL0~3 define
3LSB 100:Shift 4LSB 101:Shift 5LSB 110:Shift 6LSB the DC load line slope in load current state LCS0~3
111:Shift 7 LSB
respectively as shown in Table 9.
TEMP_SHIFT[2:0]:VCORE SVID 0X12 Shift left by LSB:
Table 9. IICLL0~3
000: No Shift 001: Shift 1LSB 010: Shift 2LSB 011: Shift
3LSB 100:Shift 4LSB 101:Shift 5LSB 110:Shift 6LSB
111:Shift 7 LSB
IICL0~3
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Load Line
0%
GCOMP[3:0]: OTA Transconductance Gain Setting
12.5%
25%
The register GCOMP[3:0] is used to adjust error amp
Gm(uA/V) for loop gain as show in Table 8.
GCOMP[3] = [0] => 2020uA/V(default value)
37.5%
50%
I2C
EAP
GM
FB
62.5%
75%
RCOMP
87.5%
100% (Default)
112.5%
125%
Table 8. GCOMP Setting Table
Bit[3] = 1, Bit[2:0]
GCOMP(uA / V)
X1 (Default)
X1.17
137.5%
150%
000
001
010
011
100
101
110
111
162.5%
175%
X1.31
X1.45
187.5%
X1.69
X0.81
X0.6
X0.33
16
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uP1664
Functional Description
Table 10. I2C Configuration Registers
Access Default
Reg
Addr
Register Name
Description
Set IMON voltage level 0,VIMON > level 0 => LCS0 (highest current
state)
0x01
0x02
0x03
VM0[7:0]
VM1[7:0]
VM2[7:0]
R/W
R/W
R/W
00h
00h Set IMON voltage level 1,VIMON > level 1 => LCS1
Set IMON voltage level 2,VIMON > level 2 => LCS2, VIMON < level 2
=> LCS3 (lowest current state).
00h
Bit[2:0] :Set VCORE VM0 Hysteresis
000:60mV ; 001=80mV ;010=100mV; 011=120mV ;
VM0_Hys[2:0]
VM1_Hys[6:4]
100=140mV;101=160mV;110=180 mV;111=200mV
Bit[6:4] : Set VCORE VM1 Hysteresis
000:60mV ; 001=80mV ;010=100mV; 011=120mV ;
100=140mV;101=160mV;110=180 mV;111=200mV
0x04
0x05
0x06
R/W
R/W
R/W
00h
Bit[6:4] :Set VGT SVM0 Hystersis
000:120mV ; 001=160mV ;010=200mV; 011=240mV ;
100=280mV;101=320mV;110=360 mV;111=400mV
Bit[2:0] :Set Vcore VM2 Hysteresis
000:60mV ; 001=80mV ;010=100mV; 011=120mV ;
100=140mV;101=160mV;110=180 mV;111=200mV
SVM0_Hys[6:4]
VM2_Hys[2:0]
00h
VCORE Operation Phase Number Setting
Bit[7:6] : Phase Number of LCS3
Bit[5:4] : Phase Number of LCS2
IICP3[7:6];IICP2[5:4]
IICP1[3:2];IICP0[1:0]
00h
Bit[3:2] : Phase Number of LCS1
Bit[1:0] : Phase Number of LCS0
00: 2 phase 01: 2 phase,10: 2 phase 11:1 phase
0x07
0x08
0x09
0x0A
VOFS0[7:0]
VOFS1[7:0]
VOFS2[7:0]
VOFS3[7:0]
R/W
R/W
R/W
R/W
00h VCORE Voltage offset of LCS0. 5mV/ step.
00h VCORE Voltage offset of LCS1. 5mV/ step.
00h VCORE Voltage offset of LCS2. 5mV/ step.
00h VCORE Voltage offset of LCS3. 5mV/ step.
IICF0[6:4]: freq of LCS0; IICF1[2:0]: freq of LCS1;
11h 000: 150K; 001:200K;010:250K;011:300K;100:350K;101:400K;
110:450K;111:500K
0x0B IICF0[6:4]; IICF1[2:0]
0x0C IICF2[6:4]; IICF3[2:0]
R/W
R/W
IICF2[6:4]: freq of LCS2; IICF3[2:0]: freq of LCS3
11h 000: 150K; 001:200K;010:250K;011:300K;100:350K;101:400K;
110:450K;111:500K
IICLL0[7:4] load line setting of LCS0 (default 100%, min 0%, max
IICLL0[7:4]
0x0D
187.5% ,12.5%/step)
IICLL1[3:0] load line setting of LCS1 (default 100%, min 0%, max
187.5% ,12.5%/step)
R/W
R/W
88h
IICLL1[3:0]
IICLL2[7:4] load line setting of LCS2 (default 100%, min 0%, max
187.5% ,12.5%/step)
IICLL3[3:0] load line setting of LCS3 (default 100%, min 0%, max
IICLL2[7:4]
0x0E
88h
IICLL3[3:0]
187.5% ,12.5%/step)
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17
uP1664
Functional Description
Table 10. I2C Configuration Registers
Access Default
Reg
Addr
Register Name
Description
VCORE PHASE1 Current Balance Gain Adjust
PH1_IGAIN[7]: 0:Disable 1:Enable
Bit[6:4]:
000:50%; 001:62.5%; 010:75%; 011:87.5%; 100:100%;
101:112.5%; 110:125%; 111:137.5%
VCORE PHASE2 Current Balance Gain Adjust
PH2_IGAIN[3]: 0:Disable 1:Enable
Bit[2:0]:
PH1_IGAIN[7:4]
PH2_IGAIN[3:0]
0x0F
R/W
00h
000:50%; 001:62.5%; 010:75%; 011:87.5%; 100:100%;
101:112.5%; 110:125%; 111:137.5%
VCORE PHASE1 Current Balance Offset Adjust
Bit[7]: "1" => Offset enable, "0" => Offset disable
Bit[6:4]:
000:0mV ; 001:3mV; 010:6mV; 011:9mV; 100:12mV; 101:15mV;
110:18mV; 111:21mV
VCORE PHASE2 Current Balance Offset Adjust
Bit[3]: "1" => Offset enable, "0" =>Offset disable
Bit[2:0]:
PH1_IOS[7:4]
PH2_IOS[3:0]
0x11
R/W
00h
03h
000:0mV ; 001:3mV; 010:6mV; 011:9mV; 100:12mV; 101:15mV;
110:18mV; 111:21mV
VCORE RCOMP Resistor
RCOMP=5K(1+[3:0])
0x13
0x14
RCOMP[3:0]
GCOMP[3:0]
R/W
R/W
VCORE OTA Gm
00h Bit3:0 is default 2020 uA / V
GCOMP[3:0]
0x15
0x16
LCHVID[7:0]
IOUT[7:0]
R/W
R
00h VCORE Latch VID Register.
--
--
VCORE SVID 0x15 Reading.
VCORE Voltage Reading.
0x17 VCORE_VOUT[7:0]
0x19 VCORE_OC[7:0]
R
Bit[7]: "1" Enable "0" Disable
Bit[6:0]: Mapping to SVID 0x15 Register.
R/W
00h
18
uP1664-DS-F00A0, Apr. 2018
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uP1664
Functional Description
Table 10. I2C Configuration Registers
Access Default
Reg
Addr
Register Name
SVM0[7:0]
Description
Set SIMON voltage level 0, SIMON > level 0 => SLCS0(highest
load current state), SIMON < level 0 => SLCS1
0x1A
R/W
00h
0x1B
0x1C
VSOFS0[7:0]
VSOFS1[7:0]
R/W
R/W
00h VGT Voltage Offset of SLCS0. 5mV/step
00h VGT Voltage Offset of SLCS1. 5mV/step
IICSF0[6:4]: freq of SLCS0 IICSF1[2:0]: freq of SLCS1
11h 000: 150K; 001: 200K; 010: 250K; 011: 300K; 100: 350K;
101: 400K; 110: 450K; 111: 500K
IICSF0[6:4]
IICSF1[2:0]
0x1D
0x1E
R/W
R/W
IICSLL0[7:4] load line setting of SLCS0 (default 100%, min 0%,
IICSLL0[7:4]
IICSLL1[3:0]
max 187.5%, 12.5%/step)
IICSLL1[3:0] load line setting of SLCS1 (default 100%, min 0%,
88h
max 187.5%, 12.5%/step)
VGT RSCOMP Register
03h
0x1F
0x20
VGT_RCOMP[3:0]
VGT_GCOMP[3:0]
R/W
R/W
RSCOMP = 5K (1+[3:0])
VGT OTA Gm
00h Bit3:0 is default 2020 uA / V
GCOMP[3:0]
0x21
0x22
0x23
VGT_LCHVID[7:0]
VGT_IOUT[7:0]
VGT_VOUT[7:0]
R/W
R
00h VGT Latch VID Register.
--
--
VGT SVID 0X15 Reading.
VGT Voltage Reading.
R/W
Bit[7]: "1" Enable "0" Disable
Bit[6:0]: Mapping to SVID 0x15 Register.
0x24
VGT_OC[7:0]
R/W
00h
VCORE Total Current OCP:
Bit[5:4]:
00: 120%, 01: 133%, 10: 150%, 11: 171%
VCORE Per Phase OCP:
0x25
OCP[5:0]
R/W
11h Bit[3:2]:
000: 60uA, 01: 100uA, 10: 140uA, 11: 180uA
VGT: Total Current OCP:
Bit[1:0]:
000: 120%, 01: 133%, 10: 150%, 11: 171%
UVP Setting:
Bit [7:6] : VCORE
00:200mV 01:300mV 10:400mV 11:500mV
Bit [3:2] : VGT
00:200mV 01:300mV 10:400mV 11:500mV
OVP Setting:
0x26
UV/OV[7:0]
R/W
55h
Bit [5:4] : VCORE
00:200mV 01:300mV 10:400mV 11:500mV
Bit [1:0] : VGT
00:200mV 01:300mV 10:400mV 11:500mV
uP1664-DS-F00A0, Apr. 2018
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19
uP1664
Functional Description
Table 10. I2C Configuration Registers
Access Default
Reg
Addr
Register Name
Description
Bit[7]: "0" Disable immediately asserting ALERT#
after +/- 2VID command is received
"1" Enable immediately asserting ALERT#
after +/- 2VID command is received
Bit[6]: "0" VGT Power Enable
"1" VGT Power Disable
Bit[5]: "0" VCORE SVID 0x31 V DAC follow SVID
"1" VCORE SVID 0x31 V DAC ignore SVID
Bit[4]: "0" VCORE SVID 0x32 Power state follow SVID
"1" VCORE SVID 0x32 Power state ignore SVID
Bit[3]: "0" VCORE SVID 0x33 Offset follow SVID
"1" VCORE SVID 0x33 Offset ignore SVID
Bit[2]: "0" VGT SVID 0x31 V DAC follow SVID
"1" VGT SVID 0x31 V DAC ignore SVID
Bit[1]: "0" VGT SVID 0x32 Power state follow SVID
"1" VGT SVID 0x32 Power state ignore SVID
Bit[0]: "0" VGT SVID 0x33 Offset follow SVID
"1" VGT SVID 0x33 Offset ignore SVID
0x27
Misc1[7:0]
R/W
00h
Bit[7]: "0" Disable VCORE Auto Phase
"1" Enable VCORE Auto Phase
Bit[6]: "0" Disable VGT Auto Phase
"1" Enable VGT Auto Phase
Bit[5]: "0" Disable VCORE PSM
"1" Enable VCORE PSM
Bit[4]: "0" Disable VGT PSM
"1" Enable VGT PSM
Bit[3]: "0" Disable VCORE Load line
"1" Enable VCORE Load line
Bit[2]: "0" Disable VGT Load line
"1" Enable VGT Load line
0x28
Misc2[7:0]
R/W
0Ch
Bit[1]: "0" Disable VCORE Offset
"1" Enable VCORE Offset
Bit[0]: "0" Disable VGT Offset
"1" Enable VGT Offset
Bit[7]: "0" Enable VCORE's VRHOT#
"1" Disable VCORE's VRHOT#
Bit[6]: "0" Enable VGT's VRHOT#
"1" Disable VGT's VRHOT#
0x2C
Bit[5:3]: VCORE SVID 0x12 Shift left by LSB
000: No Shift 001: Shift 1LSB 010: Shift 2LSB 011: Shift 3LSB
100: Shift 4LSB 101: Shift 5LSB 110: Shift 6LSB 111: Shift 7LSB
Bit[2:0]: VGT SVID 0x12 Shift left by LSB
TEMP_SHIFT[7:0]
R/W
00h
000: No Shift 001: Shift 1LSB 010: Shift 2LSB 011: Shift 3LSB
100: Shift 4LSB 101: Shift 5LSB 110: Shift 6LSB 111: Shift 7LSB
20
uP1664-DS-F00A0, Apr. 2018
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uP1664
Functional Description
Table 10. I2C Configuration Registers
Access Default
Reg
Addr
Register Name
Description
VCORE TB In PS0
Bit[7]: "0" Disable "1" Enable
Bit[6:4]:
000: 0mV 001: 10mV 010: 20mV 011: 30mV 100: 40mV
101: 50mV 100: 60mV 111: 70mV
VCORE TB In PS1/2
0x2D
VCORE_TB[7:0]
R/W
00h
Bit[3]: "0" Disable "1" Enable
Bit[2:0]:
000: 0mV 001: 10mV 010: 20mV 011: 30mV 100: 40mV
101: 50mV 100: 60mV 111: 70mV
VCORE TB Vtrig Limit in PS0
Bit[7]: "0" Disable "1" Enable
Bit[6:4]:
000: 1.25V 001: 1.35V 010: 1.45V 011: 1.55V 100: 1.65V
101: 1.75V 110: 1.85V 111: 1.95V
VCORE TB Vtrig Limit in PS1/2
Bit[3]: "0" Disable "1" Enable
Bit[2:0]:
0x2E VCORE_TRIG[7:0]
R/W
R/W
R/W
00h
000: 1.25V 001: 1.35V 010: 1.45V 011: 1.55V 100: 1.65V
101: 1.75V 110: 1.85V 111: 1.95V
VCORE TB ON Time
Bit[5:3] PS0 TB ON Time
000: 200nS 001: 300nS 010: 400nS 011: 500nS 100: 600nS
0x2F
VCORE_TON[5:0]
00h 101: 700nS 110: 800nS 111: 900nS
Bit[2:0] PS1/2 TB ON Time
000: 200nS 001: 300nS 010: 400nS 011: 500nS 100: 600nS
101: 700nS 110: 800nS 111: 900nS
VGT TB In PS0
Bit[7]: "0" Disable "1" Enable
Bit[6:4]:
000: 0mV 001: 10mV 010: 20mV 011: 30mV 100: 40mV
101: 50mV 100: 60mV 111: 70mV
VGT TB In PS1/2
0x30
VGT_TB[7:0]
00h
Bit[3] "0" Disable "1" Enable
Bit[2:0]:
000: 0mV 001: 10mV 010: 20mV 011: 30mV 100: 40mV
101: 50mV 100: 60mV 111: 70mV
uP1664-DS-F00A0, Apr. 2018
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21
uP1664
Functional Description
Table 10. I2C Configuration Registers
Access Default
Reg
Addr
Register Name
VGT_TRIG[7:0]
Description
VGT TB Vtrig Limit in PS0
Bit[7]: "0" Disable "1" Enable
Bit[6:4]:
000: 1.25V 001: 1.35V 010: 1.45V 011: 1.55V 100: 1.65V
101: 1.75V 110: 1.85V 111: 1.95V
VGT TB Vtrig Limit in PS1/2
0x31
R/W
00h
Bit[3]: "0" Disable "1" Enable
Bit[2:0]:
000: 1.25V 001: 1.35V 010: 1.45V 011: 1.55V 100: 1.65V
101: 1.75V 110: 1.85V 111: 1.95V
VGT TB ON Time
Bit[5:3] PS0 TB ON Time
000: 200nS 001: 300nS 010: 400nS 011: 500nS 100: 600nS
0x32
0x33
VGT_TON[5:0]
ITB[7:0]
R/W
R/W
00h 101: 700nS 110: 800nS 111: 900nS
Bit[2:0] PS1/2 TB ON Time
000: 200nS 001: 300nS 010: 400nS 011: 500nS 100: 600nS
101: 700nS 110: 800nS 111: 900nS
VCORE internal testing bit:
10mV x Bit[7:4]
VGT internal testing bit:
68h
10mV x Bit[3:0]
0x48
0xB2
Version ID
CHIP ID
R
R
08h
20h
22
uP1664-DS-F00A0, Apr. 2018
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uP1664
Functional Description
Table 11. Offset Voltage Table vs. VOFSn[7:0]
VOFSn[7:0] Voffset (mV) VOFSn[7:0] Voffset (mV) VOFSn[7:0] Voffset (mV) VOFSn[7:0] Voffset (mV)
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
160
165
170
175
180
185
190
195
200
205
210
215
220
225
230
235
240
245
250
255
260
265
270
275
280
285
290
295
300
305
310
315
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
320
325
330
335
340
345
350
355
360
365
370
375
380
385
390
395
400
405
410
415
420
425
430
435
440
445
450
455
460
465
470
475
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
480
485
490
495
500
505
510
515
520
525
530
535
540
545
550
555
560
565
570
575
580
585
590
595
600
605
610
615
620
625
630
635
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
105
110
115
120
125
130
135
140
145
150
155
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23
uP1664
Functional Description
Table 11. Offset Voltage Table vs. VOFSn[7:0]
VOFSn[7:0] Voffset (mV) VOFSn[7:0] Voffset (mV) VOFSn[7:0] Voffset (mV) VOFSn[7:0] Voffset (mV)
0x80
0x81
0x82
0x83
0x84
0x85
0x86
0x87
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x8F
0x90
0x91
0x92
0x93
0x94
0x95
0x96
0x97
0x98
0x99
0x9A
0x9B
0x9C
0x9D
0x9E
0x9F
-640
-635
-630
-625
-620
-615
-610
-605
-600
-595
-590
-585
-580
-575
-570
-565
-560
-555
-550
-545
-540
-535
-530
-525
-520
-515
-510
-505
-500
-495
-490
-485
0xA0
0xA1
0xA2
0xA3
0xA4
0xA5
0xA6
0xA7
0xA8
0xA9
0xAA
0xAB
0xAC
0xAD
0xAE
0xAF
0xB0
0xB1
0xB2
0xB3
0xB4
0xB5
0xB6
0xB7
0xB8
0xB9
0xBA
0xBB
0xBC
0xBD
0xBE
0xBF
-480
-475
-470
-465
-460
-455
-450
-445
-440
-435
-430
-425
-420
-415
-410
-405
-400
-395
-390
-385
-380
-375
-370
-365
-360
-355
-350
-345
-340
-335
-330
-325
0xC0
0xC1
0xC2
0xC3
0xC4
0xC5
0xC6
0xC7
0xC8
0xC9
0xCA
0xCB
0xCC
0xCD
0xCE
0xCF
0xD0
0xD1
0xD2
0xD3
0xD4
0xD5
0xD6
0xD7
0xD8
0xD9
0xDA
0xDB
0xDC
0xDD
0xDE
0xDF
-320
-315
-310
-305
-300
-295
-290
-285
-280
-275
-270
-265
-260
-255
-250
-245
-240
-235
-230
-225
-220
-215
-210
-205
-200
-195
-190
-185
-180
-175
-170
-165
0xE0
0xE1
0xE2
0xE3
0xE4
0xE5
0xE6
0xE7
0xE8
0xE9
0xEA
0xEB
0xEC
0xED
0xEE
0xEF
0xF0
0xF1
0xF2
0xF3
0xF4
0xF5
0xF6
0xF7
0xF8
0xF9
0xFA
0xFB
0xFC
0xFD
0xFE
0xFF
-160
-155
-150
-145
-140
-135
-130
-125
-120
-115
-110
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
24
uP1664-DS-F00A0, Apr. 2018
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uP1664
Absolute Maximum Rating
(Note 1)
Supply InputVoltage, VCC12 ------------------------------------------------------------------------------------------------------------ -0.3Vto +15V
BOOTx to PHASEx -------------------------------------------------------------------------------------------------------------------------- -0.3V to +15V
PHASEx to GND
DC --------------------------------------------------------------------------------------------------------------------------------------- -0.7V to 15V
< 200ns ---------------------------------------------------------------------------------------------------------------------------------- -8V to 30V
BOOTx toGND
DC ----------------------------------------------------------------------------------------------------------------------- -0.3V to VCC12 + 15V
< 200ns ------------------------------------------------------------------------------------------------------------------------------- -0.3V to 42V
UGATEx to PHASEx
DC --------------------------------------------------------------------------------------------------------------- -0.3V to (BOOTx - PHx +0.3V)
<200ns -------------------------------------------------------------------------------------------------------- -5V to (BOOTx - PHx + 0.3V)
LGATEx toGND
DC ------------------------------------------------------------------------------------------------------------------- -0.3V to + (VCC12 + 0.3V)
<200ns -------------------------------------------------------------------------------------------------------------------- -5V to VCC12 + 0.3V
Other Pins --------------------------------------------------------------------------------------------------------------------------------------- -0.3V to +6V
StorageTemperatureRange -------------------------------------------------------------------------------------------------------------- -65OCto+150OC
JunctionTemperature --------------------------------------------------------------------------------------------------------------------------------------- 150OC
LeadTemperature (Soldering, 10 sec) -------------------------------------------------------------------------------------------------------------- 260OC
ESD Rating (Note 2)
HBM (Human Body Mode) ----------------------------------------------------------------------------------------------------------------------- 2kV
MM(MachineMode) -------------------------------------------------------------------------------------------------------------------------------- 200V
Thermal Information
Package Thermal Resistance (Note 3)
VQFN5x5 - 40LθJA ------------------------------------------------------------------------------------------------------------------------ 36OC/W
VQFN5x5 - 40LθJC ------------------------------------------------------------------------------------------------------------------------- 3OC/W
PowerDissipation, PD @ TA = 25OC
VQFN5x5-40L --------------------------------------------------------------------------------------------------------------------------------------- 2.78W
Recommended Operation Conditions
(Note 4)
Operating JunctionTemperature Range --------------------------------------------------------------------------------------------- -40OC to +125OC
OperatingAmbientTemperature Range ---------------------------------------------------------------------------------------------- -40OC to +85OC
Supply InputVoltage, VCC5 ----------------------------------------------------------------------------------------------------------------- 4.5Vto 5.5V
Supply InputVoltage, VCC12 -------------------------------------------------------------------------------------------------------------- 10.8Vto 13.2V
Note 1. Stresses listed as the above Absolute Maximum Ratings may cause permanent damage to the device.
These are for stress ratings. Functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may remain possibility to affect device reliability.
Note 2. Devices are ESDsensitive. Handling precaution recommended.
Note 3. θJA is measured in the natural convection at TA = 25OC on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
Note 4. The device is not guaranteed to function outside its operating conditions.
uP1664-DS-F00A0, Apr. 2018
www.upi-semi.com
25
uP1664
Electrical Characteristics
(VCC5 = 5V, VCC12 = 12V, TA = 25OC, unless otherwise specified)
Parameter
Supply Input (VCC5, VCC12)
VCC5 POR Threshold
VCC5 POR Hysteresis
Supply Input Current
Symbol
Test Conditions
Min
Typ Max Units
VVCC5_POR
4
--
--
4
4.3
0.2
9
4.5
--
V
V
VVCC5_HYS VCC5 falling
IVCC5
--
mA
V
VCC12 POR Threshold
VCC12 POR Hysteresis
Supply Input Current
VVCC12_POR
4.2
0.2
0.15
4.5
--
VVCC12_HYS VCC12 falling
--
--
V
IVCC12
EN = 0V, No Switching
--
mA
Error Amplifier (VCORE and VGT)
Offset Voltage
VOS(EA)
-1
--
--
1
--
--
mV
uA/V
MHz
Trans-Conductance
GM
2020
10
Gain Bandwidth Product
GBWEA Guarantee by Design
--
DAC Voltage Accuracy (DAC, SDAC)
1.0V to 1.52V
0.8V to 1.0V
0.25V to 0.8V
-0.5
-5
--
--
--
0.5
5
%
mV
mV
DAC Output Accuracy
VDAC
-8
8
Soft Start (VCORE and VGT)
SetVID_Fast
SetVID_Slow
180
45
200
50
240
58
uA
uA
Soft Start Current
ISS
EN Input
Input Low
Input High
Input Current
VIL
VIH
--
0.8
-1
--
--
--
0.4
--
V
V
1
uA
PWM On-Time Setting (VCORE and VGT)
On Time Accuracy
TON
VIN = 12V, VID = 1.2V, default setting
--
500
--
ns
Current Sense Amplifier (VCORE and VGT)
Offset Voltage
VOS(CSA) No Load, Guarantee by Design
-1
-10
--
--
--
1
10
--
mV
nA
Input Bias Current
Gain Bandwidth Product
GBW(CSA) Guarantee by Design
10
MHz
26
uP1664-DS-F00A0, Apr. 2018
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uP1664
Electrical Characteristics
Parameter
PWM Output (SPWM)
Symbol
Test Conditions
Min
Typ Max Units
Output Low Voltage
VOL(PWM) ISINK = 4mA
--
4.7
-1
--
--
--
0.2
--
V
V
Output High Voltage
VOH(PWM) ISOURCE = 4mA
High Impedance State Leakage
VR Ready Output (VROK)
Output Low Voltage
V
PWM = 0V to 5V
1
uA
VOL
ISINK = 4mA
VROK = 5V
--
--
--
--
0.2
1
V
Output High Leakage
V
uA
Current Monitoring (IMON, SIMON)
IMON Current Mirror Accuracy
SIMON Current Mirror Accuracy
Droop
I
MON to ICSN ratio
95
95
100
100
105
105
%
%
ISIMON to ISCSN ratio
Current Mirror Ratio for VCORE
Current Mirror Ratio for VGT
Thermal Monitoring (TM, STM)
I
EAP /ICSN
95
95
100
100
105
105
%
%
ISEAP /ISCSN
VTM = 4.097V to 4.307V
-3
-3
--
--
3
3
OC
OC
A/D Accuracy
V
STM = 4.097V to 4.307V
Gate Drivers
Upper Gate Source
Upper Gate Sink
RUG_SRC IUG = -80mA
RUG_SNK IUG = 80mA
RLG_SRC ILG = -80mA
RLG_SNK ILG = 80mA
TDT
--
--
--
--
--
2
4
3
Ω
Ω
Ω
Ω
ns
1.5
2
Lower Gate Source
Lower Gate Sink
4
0.8
30
1.6
--
Dead Time
Protection (VCORE and VGT)
OVP Threshold
VOVP
TOVP
VUVP
TUVP
VOCP
TOCP
IOCP
VFB - VEAP, VSFB - VSEAP
250
--
300
20
300
5
350
--
mV
us
mV
us
V
OVP Delay Time
UVP Threshold
VEAP - VFB, VSEAP - VSFB
250
--
350
--
UVP Delay Time
Total Current OCP Threshold
Total Current OCP Delay Time
Channel Current OCP Threshold
Channel Current OCP Delay Time
VIMON, VSIMON
3.35
--
3.4
20
60
20
3.45
--
us
uA
us
Measure IISEN1, I
--
--
ISEN2
TOCP2
--
--
uP1664-DS-F00A0, Apr. 2018
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27
uP1664
Typical Operation Characteristics
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Application Information
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uP1664
Package Information
VQFN5x5 - 40L
0.30 - 0.50
3.20 - 3.80
4.90 - 5.10
0.15 - 0.25
Bottom View - Exposed Pad
Pin 1 mark
0.80 - 1.00
0.0 - 0.05
0.20 REF
Note
1.Package Outline UnitDescription:
BSC: Basic. Represents theoretical exact dimension or dimension target
MIN: Minimum dimension specified.
MAX: Maximum dimension specified.
REF: Reference. Represents dimension for reference use only. This value is not a device specification.
TYP. Typical. Provided as a general value. This value is not a device specification.
2.Dimensions in Millimeters.
3.Drawing not to scale.
4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm.
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ImportantNotice
uPI and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products
and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information
before placing orders and should verify that such information is current and complete.
uPI products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment. However, no responsibility
is assumed by uPI or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its
use. No license is granted by implication or otherwise under any patent or patent rights of uPI or its subsidiaries.
COPYRIGHT (C) 2013, UPI SEMICONDUCTOR CORP.
uPI Semiconductor Corp.
Headquarter
uPI Semiconductor Corp.
Sales Branch Office
9F.,No.5, Taiyuan 1st St. Zhubei City,
Hsinchu Taiwan, R.O.C.
12F-5, No. 408, Ruiguang Rd. NeihuDistrict,
Taipei Taiwan, R.O.C.
TEL : 886.3.560.1666 FAX : 886.3.560.1888
TEL : 886.2.8751.2062 FAX : 886.2.8751.5064
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