8565G-S08-R [UTC]

HIGH PERFORMANCE POWER FACTOR CORRECTION; 高性能功率因数校正


型号：	8565G-S08-R
厂家：	Unisonic Technologies
描述：	HIGH PERFORMANCE POWER FACTOR CORRECTION 高性能功率因数校正功率因数校正
文件：	总13页 (文件大小：363K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UNISONIC TECHNOLOGIES CO., LTD

8565

Preliminary

LINEAR INTEGRATED CIRCUIT

HIGH PERFORMANCE POWER

FACTOR CORRECTION

CONTROLLER IN CONTINUOUS

CONDUCTION MODE

DESCRIPTION

The UTC 8565 is a wide input range controller integrated circuit for

active power factor correction. The circuit is designed for boost PFC

application, and requires reduced external component count. Its power

supply is recommended to be provided by an external auxiliary supply

which will switch on and off the IC.

The circuit operates in the continuous conduction mode under average

current, and in discontinuous conduction mode only in light load

condition. The switching frequency can be set with the external resistor at

pin 4. Both current and voltage loop compensations are done externally

to allow full user control.

There are many kinds of protection features incorporated to make sure of safe system operation conditions, such as

brown-out protection, output under voltage detection and peak current limitation. The inside reference is adjusted

(5V±2%) to make sure control level and precise protection. There is a particular soft-start function to limit the start up

current and thus reduces the stress on the boost diode.

FEATURES

* Supports wide input range

* Under voltage lockout

* Average current control

* Cycle by cycle peak current limiting

* Over-voltage protection

* Open loop detection

* Output under-voltage detection

* Brown-out protection

* Soft Over current Protection

* Enhanced dynamic response

* Ease of use with few external components

* External current and voltage loop compensation

* Trimmed internal reference voltage (5V±2%)

* Programmable operating/switching frequency

* (50kHz ~ 250kHz)

* Max duty cycle of 95% (typ) at 125kHz

ORDERING INFORMATION

Ordering Number

Lead Free

Package

Packing

Halogen Free

8565G-S08-R

8565G-S08-T

8565L-S08-R

SOP-8

Tape Reel

Tube

8565L-S08-T

8565L-S08-R

(1) R: Tape Reel, T: Tube

(2) S08: SOP-8

(1)Packing Type

(2)Package Type

(3)Lead Free

(3) G: Halogen Free, L: Lead Free

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8565

Preliminary

LINEAR INTEGRATED CIRCUIT

PIN CONFIGURATION

V_CC

GND

I_COMP

GATE

V_SENSE

V_COMP

I_SENSE

FREQ

PIN DESCRIPTION

PIN NO.

PIN NAME

V_SENSE

DESCRIPTION

The output bus voltage of the boost converter is sensed at this pin via a resistive divider.

The reference voltage for this pin is 5V.

This VCOMP Pin provides the compensation of the output voltage loop with a

compensation network to ground (see Fig. 2). This also gives the soft start function which

controls an increasing AC input current during start-up.

V_COMP

At this pin the compensation components of the current loop are connected. The

capacitor which is connected at this pin integrates the output current of OTA2 and

averages the current sense signal.

I_COMP

A resistor connected to this pin sets the fixed switching frequency. The frequency range

is from 50kHz to 250kHz.

FREQ

The pin senses the negative voltage drop at the external sense resistor (R1). This is the

input signal for the average current regulation in the current loop. It is also fed to the

peak current limitation block. During power up time, high inrush currents cause high

voltage drop at R1, driving currents into pin 5 which could be beyond the absolute

maximum ratings. Therefore a series resistor (R2) of around 220Ω is recommended in

order to limit this current into the IC.

I_SENSE

GND

This is the Ground pin.

The GATE pin is the output of the internal driver stage, which has a capability of 1.5A

source and sink current. Its gate drive voltage is clamped at 11.5V (typically).

The V_CCpin is the positive supply of the IC and should be connected to an external

auxiliary supply. The operating range is between 10V and 21V. The turn-on threshold is

at 11.2V and under voltage occurs at 10.2V.

GATE

V_CC

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Preliminary

LINEAR INTEGRATED CIRCUIT

BLOCK DIAGRAM

RFI Filter

D2...D5

V_OUT

Vin

85...265 VAC

auxiliary supply

V_CC

GND

GATE

UTC 8565

Variable Oscillator

PWM Logic

Gate Driver

2.5V

OTA3

OSC CLK

FREQ

250ns

Toff min

Protection Block

V_CC

Peak Current Limit

Current Sense

Ramp Generator

PWM Comp

UV lockout

OUP

Opamp -1.43x

Protection

Logic

OP1

2.5V

0.8V

V_SENSE

Over-current

Comp

Fault

300ns

1.5V

I_SENSE

Deglitcher

OLP

Fault

Voltage Loop

0.73V

Current Loop

+/-30μA, 42μS

Current Loop Comp

OTA1

I_COMP

-ve

OTA2

Soft Over

Current Control

Nonlinear

Gain

1.1mS

+/-50μA linear range

Soft Start

4.0V

4.75V

+ve

5.25V

V_COMP

4.0V

-ve

Fault

Window Detect

Representative Block diagram

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8565

Preliminary

LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

PARAMETER

SYMBOL

V_CC

RATINGS

-0.3 ~ 22

-0.3 ~ 7

-24 ~ 7

±1

UNIT

V_CCSupply Voltage

FREQ Voltage

V_FREQ

V_ICOMP

V_ISENSE

I_ISENSE

V_VSENSE

I_VSENSE

V_VCOMP

V_GATE

V_ESD

ICOMP Voltage

ISENSE Voltage

ISENSE Current

VSENSE Voltage

VSENSE Current

VCOMP Voltage

GATE Voltage

-0.3 ~ 7

±1

-0.3 ~ 7

-0.3 ~ 22

ESD Protection (Note 2)

Junction Temperature

Storage Temperature

°C

T_J

-40 ~ 150

-55 ~ 150

T_STG

Notes: 1. Absolute maximum ratings are those values beyond which the device could be permanently damaged.

Absolute maximum ratings are stress ratings only and functional device operation is not implied.

2. According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kΩ series resistor)

THERMAL DATA

PARAMETER

SYMBOL

RATINGS

UNIT

K/W

Junction to Ambient

θ_JA

ELECTRICAL CHARACTERISTICS

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX UNIT

OPERATING RANGE (Note 1)

V_CCSupply Voltage

V_CC

V_CCUVLO

-40

Junction Temperature

T_J(CON)

125

°C

SUPPLY SECTION (Note 2)

V_CCTurn-On Threshold

V_CCTurn-Off Threshold/

Under Voltage Lock Out

V_CCTurn-On/Off Hysteresis

Start Up Current Before V_CCON

Operating Current With Active

GATE

V_CCON

V_CCUVLO

V_CCHY

10.5

9.4

11.2

10.2

11.9

10.8

0.8

1.3

I_CCSTARTV_VCC=V_VCC(ON)-0.1V

100

200

µA

I_CCHGR5=33kΩ, C_L=4.7nF

13.5

2.0

22.5

3.2

Operating Current During Standby I_CCSTDBYR5 = 33kΩ, V_VSENSE=0.5V

2.6

VARIABLE FREQUENCY SECTION

Switching Frequency (Typical)

Switching Frequency (Min.)

Switching Frequency (Max.)

Voltage At FREQ Pin

PWM SECTION

F_SWNOMR5=33kΩ

F_SW(MIN)R5=82kΩ

F_SW(MAX)R5=15kΩ

V_FREQ

106

133

161

kHz

200

2.40

250

2.50

320

2.60

Max. Duty Cycle

D_MAX

D_MIN

F_SW=F_SWNOM(R5=33kΩ)

V_VCOMP=0V, V_VSENSE=5V, V_ICOMP=6.4V

Min. Duty Cycle

Min. Off Time

T_OFF(MIN)V_VCOMP=5V, V_VSENSE=5V, V_ISENSE=0.1V 150

250

350

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8565

Preliminary

LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS(Cont.)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN TYP MAX UNIT

SYSTEM PROTECTION SECTION

Open Loop Protection (OLP)

V_OLP

V_PCL

V_SOC

0.77 0.81 0.86

-1.15 -1.08 -1.00

-0.79 -0.73 -0.66

_SENSEThreshold

Peak Current Limitation (PCL)

_SENSEThreshold

Soft Over Current Control (SOC) I_SENSE

Threshold

Output Under Voltage Detection (OUV)

V_OUV

V_OVP

2.45 2.55 2.65

5.12 5.25 5.38

V_SENSEThreshold

Output Over-Voltage Protection (OVP)

CURRENT LOOP SECTION

OTA2 Transconductance Gain

OTA2 Output Linear Range

I_COMPVoltage during OLP

VOLTAGE LOOP SECTION

OTA1 Reference Voltage

OTA1 Transconductance Gain

OTA1 Max. Source Current Under

Normal Operation

Gm_OTA2At Temp=25°C

0.9

3.6

1.1

±50

4.0

1.3 mS

I_OTA2

Guaranteed by design

µA

V_ICOMPFV_VSENSE=0.5V

V_OTA1

4.90 5.00 5.10

Gm_OTA1

31.5 42 52.5 µS

I_OTA1SOV_VSENSE=4.25V, V_VCOMP=4V

µA

OTA1 Max. Sink Current Under

Normal Operation

I_OTA1SKV_VSENSE=6V, V_VCOMP=4V

V_SOFT

µA

Soft Start End

3.80 4.00 4.20

OTA1 Source Current Under Soft Start I_OTA1SSV_VSENSE=2V, V_VCOMP=0V

8.0 10.8 13.4 µA

V_SENSEHigh

V_SENSELow

V_Hi

5.12 5.25 5.38

4.63 4.75 4.87

Enhanced Dynamic

Response

V_Lo

V_SENSEInput Bias Current At 5V

V_SENSEInput Bias Current at 1V

V_COMPVoltage during OLP

DRIVER SECTION

I_VSEN5VV_VSENSE=5V

I_VSEN1VV_VSENSE=1V

V_VCOMPFV_VSENSE= 0.5V, I_VCOMP=0.5mA

1.5

µA

0.2

0.4

V_CC=5V, I_GATE=5mA

V_CC=5V, I_GATE=20mA

V_GATELI_GATE=0A

1.2

1.5

GATE Low Voltage

GATE High Voltage

0.8

1.6

I_GATE=20mA

2.0

I_GATE=-20mA

-0.2 0.2

11.5

10.5

7.5

V_CC=20V, C_L=4.7nF

V_GATEHV_CC=11V, C_L=4.7nF

V_CC=V_VCC(OFF)+0.2V, C_L=4.7nF

GATE Rise Time

t_R

V_GATE=2V...9V, C_L=4.7nF

V_GATE=9V...2V, C_L=4.7nF

C_L=4.7nF (Note 3)

GATE Fall Time

t_F

GATE Current, Peak, Rising Edge

GATE Current, Peak, Falling Edge

I_GATE

-1.5

C_L=4.7nF (Note 3)

1.5

Notes: 1. Within the operating range the IC operates as described in the functional description.

2. The electrical characteristics involve the spread of values within the specified supply voltage and junction

temperature range T_Jfrom -40°C to 125°C. Typical values represent the median values, which are related

to 25°C. If not otherwise stated, a supply voltage of V_CC=15V is assumed for test condition.

3. Design characteristics (not meant for production testing)

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8565

Preliminary

LINEAR INTEGRATED CIRCUIT

FUNCTIONAL DESCRIPTION

1. General

The UTC 8565 is an active power factor correction controller for boost PFC application. The IC comes in DIP

package and is suitable for wide input range applications from 85 to 265 V_AC. The IC is usually realized with boost

converters and it operates in continuous conduction mode with average current control.

The UTC 8565 operates with a cascaded control; the inner current loop and the outer voltage loop. The inner

current loop of the IC controls the sinusoidal profile for the average input current. It uses the dependency of the

PWM duty cycle on the line input voltage to determine the corresponding input current. This means the average

input current follows the input voltage as long as the device operates in CCM. Under light load condition, depending

on the choke inductance, the system may enter into discontinuous conduction mode (DCM). In DCM, the average

current waveform will be distorted but the resultant harmonics are still low enough to meet the Class D requirement

of IEC 1000-3-2. The outer loop controls the output voltage. Depending on the load condition, OTA1 establishes an

appropriate voltage at V_COMPpin which controls the amplitude of the average input current.

The UTC 8565 provides several protection features to ensure safe operating condition for both the system and

device. Important protection features are namely Brown-out protection, Current Limitation and Output Under-voltage

Protection.

2. Power Supply

The operating voltage range of the V_CCis from 10V to 21V. An internal under voltage lockout (UVLO) block

monitors the V_CCpower supply. As soon as it exceeds 11.2V and the voltage at pin 1 (V_SENSE) is >0.8V, the IC

begins operating its gate drive and performs its Soft-Start as shown in Fig. 3.

If V_CCdrops below 10.2V, the IC is off. The IC will then be consuming typically 200µA, whereas consuming 18mA

during normal operation.

The IC can be turned off and forced into standby mode by pulling down the voltage at pin 1 (V_SENSE) to lower than

0.8V. The current consumption is reduced to 3mA in this mode.

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8565

Preliminary

LINEAR INTEGRATED CIRCUIT

FUNCTIONAL DESCRIPTION(Cont.)

3. Start-up (Soft-Start)

The operation of OTA1 during startup is shown in Fig. 4 and 5.

V_SENSE

R3+R4

)

×V_OUT

(

Soft Start

_OUT<80% rated

Normal Operation

V_OUT>80% rated

4.0V

Soft Start

10.8μA during

Soft Start

OTA1

V_COMP

Open-Loop

Protect

av(I_IN)

0.8V

(OLP)

UTC 8565

Fig. 4 Soft Start Circuit

Fig. 5 Soft Start With Controlled Current

It sources a constant 10.8µA into the compensation network at pin 2 (V_COMP). The voltage at this pin rises

linearly and so does the amplitude of the input current. As soon as the output voltage V_OUTreaches 80% of its rated

level, the startup procedure is finished and the normal voltage control takes over. In normal operation, the IC

operates with a higher maximum current at OTA1 and therefore with a higher voltage loop gain in order to improve

the dynamic behavior of the device.

The advantage of this technique is a soft-start function with lower stress for the boost diode but without the risk of

audible noise.

4. System Protection

The IC is equipped with various protection features to ensure the PFC system in safe operating range. Depending

on the input line voltage (V_IN) and output bus voltage (V_OUT), When these protections are active the conditions are

shown in Fig. 6 and 7.

The following sections describe the functionality of these protection features.

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8565

Preliminary

LINEAR INTEGRATED CIRCUIT

FUNCTIONAL DESCRIPTION(Cont.)

4.1 Brown-Out Protection (BOP)

Input Brown-out occurs if the input voltage V_INfalls below the minimum input voltage of the design (i.e. 85V for

universal input voltage range) and the V_CChas not entered into the V_CCunder voltage lockout level yet. For a system

without BOP, the boost converter will increasingly draw a higher current from the mains at a given output power

which may exceed the maximum design values of the input current. The UTC 8565 limits internally the current drawn

from the mains and therefore also limits the input power. The difference of input and output power will result in

decreasing output voltage. If the condition prolongs, the decreasing V_OUTwill terminate in output under voltage

condition (OUV, 50% of rated), and the IC will be shut down (See section 4.5).

Fig. 8 shows the occurrence of BOP in respect to the I_SENSEvoltage.

The V_INthreshold for BOP to occur is dependent on the voltage at I_SENSEand thus the output power. The rated

output power with a minimum V_IN(V_IN(MIN)) is

0.6

P_OUT(rated) = V

R1×

INMIN

Due to the internal parameter tolerance, the maximum power with V_IN(MIN)before BOP occurs is

0.73

P_OUT(max) = V

R1×

INMIN

And the BOP takes over the normal operation under rated output power latest at an input voltage of

0.73

V_BOPMAX= P_OUT(rated)× ^R1×

4.2 Soft Over Current Control (SOC)

The UTC 8565 is designed not to support any output power that corresponds to a voltage lower than -0.73V at the

_SENSEpin. A further increase in the inductor current, which results in a lower I_SENSEvoltage, will activate the Soft Over

Current Control (SOC). This is a soft control as it does not directly switch off the gate drive like the PCL. It acts on

the nonlinear gain block to result in a reduced PWM duty cycle.

4.3 Peak Current Limit (PCL)

The UTC 8565 is equipped with a cycle by cycle peak current protection feature. It is active when the voltage at

pin 5 (I_SENSE) reaches -1.08V. This voltage is amplified by OP1 with a factor of -1.43 and connected to comparator

C2 with a reference voltage of 1.5V as shown in Fig. 9. A deglitcher with 300ns after the comparator improves noise

immunity to the activation of this protection.

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8565

Preliminary

LINEAR INTEGRATED CIRCUIT

FUNCTIONAL DESCRIPTION(Cont.)

4.4 Open Loop Protection / Input Under Voltage Protect (OLP)

Whenever V_SENSEvoltage falls below 0.8V, or equivalently V_OUTfalls below 16% of its rated value, it indicates an

open loop condition (i.e. V_SENSEpin not connected) or an insufficient input voltage V_INfor normal operation. In this

case, most of the blocks within the IC will be shutdown. The function is implemented using comparator C3 with a

threshold of 0.8V as shown in the IC block diagram in Fig. 2.

4.5 Output Under Voltage Detection (OUV)

In the event of main interrupt or brown-out condition, the PFC system is not able to deliver the rated output power.

This will cause the output voltage V_OUTto drop below its rated value. The IC provides an output under voltage

detection that checks if V_OUTis falling below 50% of its rated value. Comparator C4 as shown in the device block

diagram (Fig. 2) senses the voltage at pin 1 (V_SENSE) with a reference of 2.5V. If comparator C4 trips, the IC will be

shut down as in OLP. The IC will be ready to restart if there is sufficient V_INto pull V_OUTout of OLP.

4.6 Over-Voltage Protection (OVP)

Whenever V_OUTexceeds the rated value by 5%, the over-voltage protection OVP is active as shown in Fig. 7. This

is implemented by sensing the voltage at pin V_SENSEwith respect to a reference voltage of 5.25V. A V_SENSEvoltage

higher than 5.25V will immediately reduce the output duty cycle, bypassing the normal voltage loop control. This

results in a lower input power to reduce the output voltage V_OUT

5. Frequency Setting

The switching frequency of the PFC controller is fixed and can be set by an external resistor R5 at FREQ pin. The

pin voltage V_FREQis typically 2.5V. The corresponding capacitor for the oscillator is integrated in the device and the

R5/frequency relationship is given at the “Electrical Characteristic” section. The recommended operating frequency

range is from 50kHz to 250kHz. As an example, a R5 of 33kΩ at pin FREQ will set a switching frequency F_SWof

133kHz typically.

6. Average Current Control

6.1 Complete Current Loop

Fig. 10 show the complete system current loop. It consists of the current loop block which averages the voltage at

pin I_SENSE, resulted from the inductor current flowing across R1. The averaged waveform is compared with an

internal ramp in the ramp generator and PWM block. Once the ramp crosses the average waveform, the comparator

C1 turns on the driver stage through the PWM logic block. The Nonlinear Gain block defines the amplitude of the

inductor current. The following sections describe the functionality of each individual blocks.

V_OUT

From

Full-wave

Retifier

GATE

voltage

Current Loop

I_SENSE

proportional to

averaged

Gate

Inductor current

Driver

Current Loop

Compensation

PWM

Comparator

I_COMP

OTA2

PWM Logic

1.1mS +/-50μA

(linear range)

Input From

Voltage Loop

Nonlinear

Gain

Fault

UTC 8565

Fig. 10 Complete System Current Loop

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Preliminary

LINEAR INTEGRATED CIRCUIT

FUNCTIONAL DESCRIPTION(Cont.)

6.2 Current Loop Compensation

The compensation of the current loop is done at the ICOMP pin. This is the OTA2 output and a capacitor C3 has

to be installed at this node to ground (see Fig. 10). Under normal mode of operation, this pin gives a voltage which is

proportional to the averaged inductor current. This pin is internally shorted to 5V in the event of IC shuts down when

OLP and UVLO occur.

6.3 Pulse Width Modulation (PWM)

The IC employs an average current control scheme in continuous conduction mode (CCM) to achieve the power

factor correction.

Assuming the voltage loop is working and output voltage is kept constant, the off duty cycle D_OFFfor a CCM PFC

system is given as

D_OFF

OUT

From the above equation, D_OFFis proportional to V_IN. The objective of the current loop is to regulate the average

inductor current such that it is proportional to the off duty cycle D_OFF, and thus to the input voltage V_IN. Fig. 11 shows

the scheme to achieve the objective.

The PWM is performed by the intersection of a ramp signal with the averaged inductor current at pin 3 (I_COMP). The

PWM cycle starts with the Gate turn off for a duration of T_OFF(MIN)(250ns typ.) and the ramp is kept discharged. The

ramp is then allowed to rise after T_OFF(MIN)expires. The off time of the boost transistor ends at the intersection of the

ramp signal and the averaged current waveform. This results in the proportional relationship between the average

current and the off duty cycle D_OFF

Fig. 12 shows the timing diagrams of T_OFF(MIN)and the PWM waveforms.

6.4 Nonlinear Gain Block

The nonlinear gain block controls the amplitude of the regulated inductor current. The input of this block is the

voltage at pin V_COMP. This block has been designed to support the wide input voltage range (85-265V_AC).

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Preliminary

LINEAR INTEGRATED CIRCUIT

FUNCTIONAL DESCRIPTION(Cont.)

7. PWM Logic

The PWM logic block prioritizes the control input signals and generates the final logic signal to turn on the driver

stage. The speed of the logic gates in this block, together with the width of the reset pulse T_OFF(MIN), are designed to

meet a maximum duty cycle D_MAXof 95% at the GATE output under 133kHz of operation.

In case of high input currents which result in Peak Current Limitation, the GATE will be turned off immediately and

maintained in off state for the current PWM cycle. The signal T_OFFMINresets (highest priority, overriding other input

signals) both the current limit latch and the PWM on latch as illustrated in Fig. 13.

8. Voltage Loop

The voltage loop is the outer loop of the cascaded control scheme which controls the PFC output bus voltage V_OUT

This loop is closed by the feedback sensing voltage at V_SENSEwhich is a resistive divider tapping from V_OUT. The pin

V_SENSEis the input of OTA1 which has an internal reference of 5V. Fig. 14 shows the important blocks of this voltage

loop.

8.1 Voltage Loop Compensation

The compensation of the voltage loop is installed at the V_COMPpin (see Fig. 14). This is the output of OTA1 and the

compensation must be connected at this pin to ground. The compensation is also responsible for the soft start

function which controls an increasing AC input current during start-up.

V_OUT

From

Full-wave

Retifier

Gate Driver

Current Loop

PWM Generation

V_IN

GATE

V_SENSE

OTA1

Nonlinear

Gain

Av(I_IN)

V_COMP

UTC 8565

Fig. 14 Voltage Loop

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Preliminary

LINEAR INTEGRATED CIRCUIT

FUNCTIONAL DESCRIPTION(Cont.)

8.2 Enhanced Dynamic Response

Due to the low frequency bandwidth of the voltage loop, the dynamic response is slow and in the range of about

several 10ms. This may cause additional stress to the bus capacitor and the switching transistor of the PFC in the

event of heavy load changes.

The IC provides therefore a “window detector” for the feedback voltage V_VSENSEat pin 1 (V_SENSE). Whenever

V_VSENSEexceeds the reference value (5V) by ±5%, it will act on the nonlinear gain block which in turn affect the gate

drive duty cycle directly. This change in duty cycle is bypassing the slow changing V_COMPvoltage, thus results in a

fast dynamic response of V_OUT

9. Output Gate Driver

The output gate driver is a fast totem pole gate drive. It has an in-built cross conduction currents protection and a

Zener diode Z1 (see Fig. 15) to protect the external transistor switch against undesirable over voltages. The

maximum voltage at pin 7 (GATE) is typically clamped at 11.5V.

The output is active HIGH and at V_CCvoltages below the under voltage lockout threshold V_CCUVLO, the gate drive is

internally pull low to maintain the off state.

TYPICAL APPLICATION CIRCUIT

V_OUT

Auxiliary Supply

PFC-Controller

V_CC

85...265VAC EMI-Filter

SWITCH

UTC 8565

Protection Unit

V_SENSE

Voltage Loop

Compensation

PWM Logic

Driver

GATE

FREQ

Variable

Ramp

Oscillator

Generator

V_COMP

I_COMP

Nonlinear

Gain

Current Loop

Compensation

I_SENSE

GND

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Preliminary

LINEAR INTEGRATED CIRCUIT

UTC assumes no responsibility for equipment failures that result from using products at values that

exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or

other parameters) listed in products specifications of any and all UTC products described or contained

herein. UTC products are not designed for use in life support appliances, devices or systems where

malfunction of these products can be reasonably expected to result in personal injury. Reproduction in

whole or in part is prohibited without the prior written consent of the copyright owner. The information

presented in this document does not form part of any quotation or contract, is believed to be accurate

and reliable and may be changed without notice.

UNISONIC TECHNOLOGIES CO., LTD

13 of 13

QW-R114-004.b

www.unisonic.com.tw

8565G-S08-R [UTC]

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